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[PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmlada...
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
73cd51e5
AV		 178 MVE_NONE
179};
180
181enum mve_unpredictable
182{
183 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
184 */
143275ea
AV		 185 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
186 fcB = 1 (vpt). */
187 UNPRED_R13, /* Unpredictable because r13 (sp) or
188 r15 (sp) used. */
9743db03 189 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 190 UNPRED_Q_GT_4, /* Unpredictable because
191 vec reg start > 4 (vld4/st4). */
192 UNPRED_Q_GT_6, /* Unpredictable because
193 vec reg start > 6 (vld2/st2). */
194 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
195 and WB bit = 1. */
ef1576a1
AV		 196 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
197 equal. */
198 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 199 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
200 same. */
c507f10b
AV		 201 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
202 size = 1. */
203 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
204 size = 2. */
73cd51e5
AV		 205 UNPRED_NONE /* No unpredictable behavior. */
206};
207
208enum mve_undefined
209{
bf0b396d 210 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 211 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 212 UNDEF_SIZE_3, /* undefined because size == 3. */
213 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
ef1576a1
AV		 214 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
215 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
216 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
217 size == 0. */
218 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
219 size == 1. */
220 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 221 UNDEF_VCVT_IMM6, /* imm6 < 32. */
222 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 223 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
224 op1 == (0 or 1). */
225 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
226 op2 == 0 and op1 == (0 or 1). */
227 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
228 in {0xx1, x0x1}. */
d3b63143 229 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 230 UNDEF_NONE /* no undefined behavior. */
231};
232
6b5d3a4d
ZW		 233struct opcode32
234{
823d2571
TG		 235 arm_feature_set arch; /* Architecture defining this insn. */
236 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 237 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 238 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 239};
240
73cd51e5
AV		 241/* MVE opcodes. */
242
243struct mopcode32
244{
245 arm_feature_set arch; /* Architecture defining this insn. */
246 enum mve_instructions mve_op; /* Specific mve instruction for faster
247 decoding. */
248 unsigned long value; /* If arch is 0 then value is a sentinel. */
249 unsigned long mask; /* Recognise insn if (op & mask) == value. */
250 const char * assembler; /* How to disassemble this insn. */
251};
252
6b0dd094
AV		 253enum isa {
254 ANY,
255 T32,
256 ARM
257};
258
259
260/* Shared (between Arm and Thumb mode) opcode. */
261struct sopcode32
262{
263 enum isa isa; /* Execution mode instruction availability. */
264 arm_feature_set arch; /* Architecture defining this insn. */
265 unsigned long value; /* If arch is 0 then value is a sentinel. */
266 unsigned long mask; /* Recognise insn if (op & mask) == value. */
267 const char * assembler; /* How to disassemble this insn. */
268};
269
6b5d3a4d
ZW		 270struct opcode16
271{
823d2571 272 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 273 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 274 const char *assembler; /* How to disassemble this insn. */
275};
b7693d02 276
8f06b2d8 277/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 278
2fbad815 279 %% %
4a5329c6 280
c22aaad1 281 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 282 %q print shifter argument
e2efe87d
MGD		 283 %u print condition code (unconditional in ARM mode,
284 UNPREDICTABLE if not AL in Thumb)
4a5329c6 285 %A print address for ldc/stc/ldf/stf instruction
16980d0b 286 %B print vstm/vldm register list
efd6b359 287 %C print vscclrm register list
4a5329c6 288 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 289 %J print register for VLDR instruction
290 %K print address for VLDR instruction
4a5329c6
ZW		 291 %F print the COUNT field of a LFM/SFM instruction.
292 %P print floating point precision in arithmetic insn
293 %Q print floating point precision in ldf/stf insn
294 %R print floating point rounding mode
295
33399f07 296 %<bitfield>c print as a condition code (for vsel)
4a5329c6 297 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 298 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
299 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 300 %<bitfield>d print the bitfield in decimal
16980d0b 301 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 302 %<bitfield>x print the bitfield in hex
303 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 304 %<bitfield>f print a floating point constant if >7 else a
305 floating point register
4a5329c6
ZW		 306 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
307 %<bitfield>g print as an iWMMXt 64-bit register
308 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 309 %<bitfield>D print as a NEON D register
310 %<bitfield>Q print as a NEON Q register
c28eeff2 311 %<bitfield>V print as a NEON D or Q register
6f1c2142 312 %<bitfield>E print a quarter-float immediate value
4a5329c6 313
16980d0b 314 %y<code> print a single precision VFP reg.
2fbad815 315 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 316 %z<code> print a double precision VFP reg
2fbad815 317 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 318
16980d0b
JB		 319 %<bitfield>'c print specified char iff bitfield is all ones
320 %<bitfield>`c print specified char iff bitfield is all zeroes
321 %<bitfield>?ab... select from array of values in big endian order
43e65147 322
2fbad815 323 %L print as an iWMMXt N/M width field.
4a5329c6 324 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 325 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 326 versions.
327 %i print 5-bit immediate in bits 8,3..0
328 (print "32" when 0)
fe56b6ce 329 %r print register offset address for wldt/wstr instruction. */
2fbad815 330
21d799b5 331enum opcode_sentinel_enum
05413229
NC		 332{
333 SENTINEL_IWMMXT_START = 1,
334 SENTINEL_IWMMXT_END,
335 SENTINEL_GENERIC_START
336} opcode_sentinels;
337
aefd8a40 338#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 339#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
340#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 341#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 342
8f06b2d8 343/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 344
6b0dd094 345static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 346{
2fbad815 347 /* XScale instructions. */
6b0dd094 348 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 349 0x0e200010, 0x0fff0ff0,
350 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 351 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 352 0x0e280010, 0x0fff0ff0,
353 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 354 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 355 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 356 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 357 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 358 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 359 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 360
2fbad815 361 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 362 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
363 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 364 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 365 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 366 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 367 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 368 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 369 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 370 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 371 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 372 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 373 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 374 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 375 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 376 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 377 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 378 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 379 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 380 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 381 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 382 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 383 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 384 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 385 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 386 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 387 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 388 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 389 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 390 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 391 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 392 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 393 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 394 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 395 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 396 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 397 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 398 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 399 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 400 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 401 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 402 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 403 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 404 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 405 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 406 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 407 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 408 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 409 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 410 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 411 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 412 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 413 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 414 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 415 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 416 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 417 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 418 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 419 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 420 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 421 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 422 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 423 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 424 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 425 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 426 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 427 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 428 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 429 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 430 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 431 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 432 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 433 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 434 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 435 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 436 0x0e800120, 0x0f800ff0,
437 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 438 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 439 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 440 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 441 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 442 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 443 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 444 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 445 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 446 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 447 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 448 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 449 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 450 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 451 0x0e8000a0, 0x0f800ff0,
452 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 453 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 454 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 455 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 456 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 457 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 458 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 459 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 460 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 461 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 462 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 463 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 464 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 466 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 467 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 468 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 470 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 472 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 474 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 476 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 477 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 478 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 479 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 480 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 481 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 482 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 483 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 484 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 485 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 486 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 488 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 490 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 492 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 494 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 496 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 498 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 500 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 501 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 502 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 503 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 504 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 505 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 506 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 508 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 510 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 512 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 514 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 515 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 516 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 517
fe56b6ce 518 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 519 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 520 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 521 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 522 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 523 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 524 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 525 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 526 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 528 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 530 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 532 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 534 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 536 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 538 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 540 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 542 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 544 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 546 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 548 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 550 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 552 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 554 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 556 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 558 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 560 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 562 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 564 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 566 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 568 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 570 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 572 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 574 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 576 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 578 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 580 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 582 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 584 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 586 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 588 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 590 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 592 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 594 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 596 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 598 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 600 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 602 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 604 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 605
efd6b359
AV		 606 /* Armv8.1-M Mainline instructions. */
607 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
608 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
609 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
610 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
611
16a1fa25 612 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 613 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 614 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 615 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 616 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
617
fe56b6ce 618 /* Register load/store. */
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 620 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 622 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 624 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 626 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 628 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 630 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 632 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 633 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 634 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 636 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 638 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 640 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 642 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 644 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 646 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 648 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 650 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 651 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
652 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
653 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
654 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 655
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 657 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 659 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 661 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 663 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 664
fe56b6ce 665 /* Data transfer between ARM and NEON registers. */
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 667 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 669 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 671 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 673 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 675 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 677 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 679 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 681 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 682 /* Half-precision conversion instructions. */
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 684 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 686 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 688 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 690 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 691
fe56b6ce 692 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 694 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 696 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 698 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 700 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 702 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 704 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 706 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 707 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 708 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 709 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 710 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 712 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 714 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 716 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 718 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 720 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 722 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 724 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 726 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 728 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 730 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 732 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 734 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 736 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 738 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 740 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 742 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 744 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 746 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 748 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 750 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 752 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 754 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 756 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 758 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 760 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 762 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 764 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 766 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 768 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 770 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 772 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 774 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 776 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 778 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 780 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 782 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 784 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 786 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 788 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 790 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 792 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 794 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 796 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 798 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 799 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 800 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 802 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 804 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 806 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 808 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 809 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 810 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 812 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 814 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 816 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 818 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 820 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 822 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 824 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 826 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 828 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 830 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 831
832 /* Cirrus coprocessor instructions. */
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 834 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 836 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 838 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 840 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 842 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 843 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 844 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 846 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 847 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 848 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 850 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 852 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 854 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 856 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 858 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 860 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 861 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 862 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 864 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 866 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 868 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 870 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 872 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 874 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 876 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 878 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 880 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 882 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 884 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 886 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 887 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 888 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 889 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 890 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 892 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 894 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 896 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 898 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 900 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 902 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 904 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 906 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 908 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 910 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 912 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 914 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 915 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 916 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 917 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 918 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 920 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 922 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 924 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 926 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 928 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 930 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 932 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 933 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 934 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 935 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 936 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 937 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 938 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 940 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 942 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 944 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 946 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 948 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 950 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 952 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 954 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 956 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 958 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 960 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 962 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 964 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 966 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 968 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 970 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 972 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 974 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 976 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 978 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 980 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 982 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 984 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 986 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 988 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 990 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 992 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 994 0x0e000600, 0x0ff00f10,
995 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 997 0x0e100600, 0x0ff00f10,
998 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1000 0x0e200600, 0x0ff00f10,
1001 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1003 0x0e300600, 0x0ff00f10,
1004 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1005
62f3b8c8 1006 /* VFP Fused multiply add instructions. */
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1008 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1010 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1012 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1014 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1016 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1018 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1020 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1022 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1023
33399f07 1024 /* FP v5. */
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1026 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1028 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1030 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1032 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1034 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1036 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1038 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1040 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1042 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1043 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1044 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1046 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1048 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1049
05413229 1050 /* Generic coprocessor instructions. */
6b0dd094
AV		 1051 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1052 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1053 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1054 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1055 0x0c500000, 0x0ff00000,
1056 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1057 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1058 0x0e000000, 0x0f000010,
1059 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1060 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1061 0x0e10f010, 0x0f10f010,
1062 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1063 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1064 0x0e100010, 0x0f100010,
1065 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1066 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1067 0x0e000010, 0x0f100010,
1068 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1069 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1070 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1071 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1072 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1073
05413229 1074 /* V6 coprocessor instructions. */
6b0dd094 1075 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1076 0xfc500000, 0xfff00000,
1077 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1078 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1079 0xfc400000, 0xfff00000,
1080 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1081
c28eeff2 1082 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1083 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1084 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1085 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1086 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1087 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1088 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1089 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1090 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1091 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1092 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1093 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1094 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1095 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1096 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1097 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1098 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1099 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1100 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1101 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1102 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1103
c604a79a 1104 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1105 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1106 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1107 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1108 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1109
dec41383 1110 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1111 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1112 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1113 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1114 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1115 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1116 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1117 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1118 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1119 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1120 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1121 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1122 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1123 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1124 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1125 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1126 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1127
05413229 1128 /* V5 coprocessor instructions. */
6b0dd094 1129 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1130 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1131 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1132 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1133 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1134 0xfe000000, 0xff000010,
1135 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1136 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1137 0xfe000010, 0xff100010,
1138 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1139 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1140 0xfe100010, 0xff100010,
1141 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1142
b0c11777
RL		 1143 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1144 cp_num: bit <11:8> == 0b1001.
1145 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1146 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1147 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1148 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1149 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1150 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1151 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1152 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1153 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1154 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1155 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1156 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1157 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1158 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1159 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1160 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1161 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1162 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1163 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1164 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1165 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1166 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1167 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1168 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1169 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1170 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1171 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1172 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1173 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1174 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1175 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1176 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1177 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1178 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1179 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1180 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1181 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1183 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1185 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1187 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1189 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1191 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1193 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1195 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1197 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1199 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1201 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1203 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1205 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1207 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1209 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1211 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1213 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1215 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1216
49e8a725 1217 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1218 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1219 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1220
6b0dd094 1221 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1222};
1223
16980d0b
JB		 1224/* Neon opcode table: This does not encode the top byte -- that is
1225 checked by the print_insn_neon routine, as it depends on whether we are
1226 doing thumb32 or arm32 disassembly. */
1227
1228/* print_insn_neon recognizes the following format control codes:
1229
1230 %% %
1231
c22aaad1 1232 %c print condition code
e2efe87d
MGD		 1233 %u print condition code (unconditional in ARM mode,
1234 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1235 %A print v{st,ld}[1234] operands
1236 %B print v{st,ld}[1234] any one operands
1237 %C print v{st,ld}[1234] single->all operands
1238 %D print scalar
1239 %E print vmov, vmvn, vorr, vbic encoded constant
1240 %F print vtbl,vtbx register list
1241
1242 %<bitfield>r print as an ARM register
1243 %<bitfield>d print the bitfield in decimal
1244 %<bitfield>e print the 2^N - bitfield in decimal
1245 %<bitfield>D print as a NEON D register
1246 %<bitfield>Q print as a NEON Q register
1247 %<bitfield>R print as a NEON D or Q register
1248 %<bitfield>Sn print byte scaled width limited by n
1249 %<bitfield>Tn print short scaled width limited by n
1250 %<bitfield>Un print long scaled width limited by n
43e65147 1251
16980d0b
JB		 1252 %<bitfield>'c print specified char iff bitfield is all ones
1253 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1254 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1255
1256static const struct opcode32 neon_opcodes[] =
1257{
fe56b6ce 1258 /* Extract. */
823d2571
TG		 1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260 0xf2b00840, 0xffb00850,
1261 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf2b00000, 0xffb00810,
1264 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1265
9743db03
AV		 1266 /* Data transfer between ARM and NEON registers. */
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1279
fe56b6ce 1280 /* Move data element to all lanes. */
823d2571
TG		 1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1287
fe56b6ce 1288 /* Table lookup. */
823d2571
TG		 1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1293
8e79c3df 1294 /* Half-precision conversions. */
823d2571
TG		 1295 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1296 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1297 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1298 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1299
1300 /* NEON fused multiply add instructions. */
823d2571 1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1302 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1306 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1309
fe56b6ce 1310 /* Two registers, miscellaneous. */
823d2571
TG		 1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1312 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1314 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1316 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1317 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1318 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1319 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1320 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1321 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1322 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1323 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1324 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1325 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1326 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1327 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1328 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1329 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1330 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1331 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1332 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1333 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1334 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf3b20300, 0xffb30fd0,
1355 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1358 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1359 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1363 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1403 0xf3bb0600, 0xffbf0e10,
823d2571 1404 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1405 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1406 0xf3b70600, 0xffbf0e10,
1407 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1408
fe56b6ce 1409 /* Three registers of the same length. */
823d2571
TG		 1410 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1411 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1412 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1413 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1414 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1415 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1416 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1417 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1418 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1419 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1420 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1421 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1422 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1423 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1425 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1427 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1429 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1431 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1449 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1451 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1453 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1455 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1457 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1459 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1461 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1463 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1465 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1467 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1469 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1471 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1473 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1475 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1477 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1479 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1481 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1483 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1485 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1487 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1489 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1491 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1493 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1495 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1497 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1499 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1501 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1503 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1505 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1507 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1509 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1511 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1513 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1515 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1517 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1519 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2000b00, 0xff800f10,
1528 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2000b10, 0xff800f10,
1531 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf3000b00, 0xff800f10,
1540 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf2000000, 0xfe800f10,
1543 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf2000010, 0xfe800f10,
1546 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2000100, 0xfe800f10,
1549 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf2000200, 0xfe800f10,
1552 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2000210, 0xfe800f10,
1555 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2000300, 0xfe800f10,
1558 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2000310, 0xfe800f10,
1561 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf2000400, 0xfe800f10,
1564 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2000410, 0xfe800f10,
1567 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf2000500, 0xfe800f10,
1570 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2000510, 0xfe800f10,
1573 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575 0xf2000600, 0xfe800f10,
1576 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf2000610, 0xfe800f10,
1579 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2000700, 0xfe800f10,
1582 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2000710, 0xfe800f10,
1585 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2000910, 0xfe800f10,
1588 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2000a00, 0xfe800f10,
1591 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2000a10, 0xfe800f10,
1594 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1596 0xf3000b10, 0xff800f10,
1597 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1599 0xf3000c10, 0xff800f10,
1600 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1601
fe56b6ce 1602 /* One register and an immediate value. */
823d2571
TG		 1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1629
fe56b6ce 1630 /* Two registers and a shift amount. */
823d2571
TG		 1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2880950, 0xfeb80fd0,
1643 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf2900950, 0xfeb00fd0,
1666 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf2a00950, 0xfea00fd0,
1711 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1731 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2a00e10, 0xfea00e90,
1750 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1752 0xf2a00c10, 0xfea00e90,
1753 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1754
fe56b6ce 1755 /* Three registers of different lengths. */
823d2571
TG		 1756 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1757 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2800400, 0xff800f50,
1762 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1764 0xf2800600, 0xff800f50,
1765 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf2800900, 0xff800f50,
1768 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1770 0xf2800b00, 0xff800f50,
1771 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2800d00, 0xff800f50,
1774 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776 0xf3800400, 0xff800f50,
1777 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf3800600, 0xff800f50,
1780 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2800000, 0xfe800f50,
1783 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf2800100, 0xfe800f50,
1786 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2800200, 0xfe800f50,
1789 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf2800300, 0xfe800f50,
1792 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2800500, 0xfe800f50,
1795 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2800700, 0xfe800f50,
1798 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2800800, 0xfe800f50,
1801 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2800a00, 0xfe800f50,
1804 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2800c00, 0xfe800f50,
1807 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1808
fe56b6ce 1809 /* Two registers and a scalar. */
823d2571
TG		 1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1813 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1814 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1815 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1821 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1822 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1823 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1829 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1830 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1831 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1841 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1842 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1843 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1847 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1848 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1849 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1853 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1854 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1855 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1857 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1859 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf2800240, 0xfe800f50,
1862 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2800640, 0xfe800f50,
1865 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867 0xf2800a40, 0xfe800f50,
1868 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1870 0xf2800e40, 0xff800f50,
1871 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1873 0xf2800f40, 0xff800f50,
1874 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1876 0xf3800e40, 0xff800f50,
1877 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1879 0xf3800f40, 0xff800f50,
1880 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1881 },
16980d0b 1882
fe56b6ce 1883 /* Element and structure load/store. */
823d2571
TG		 1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1887 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1922
1923 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1924};
1925
73cd51e5
AV		 1926/* mve opcode table. */
1927
1928/* print_insn_mve recognizes the following format control codes:
1929
1930 %% %
1931
ef1576a1
AV		 1932 %a print '+' or '-' or imm offset in vldr[bhwd] and
1933 vstr[bhwd]
9743db03 1934 %c print condition code
aef6d006
AV		 1935 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1936 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 1937 %i print MVE predicate(s) for vpt and vpst
bf0b396d 1938 %m print rounding mode for vcvt and vrint
143275ea 1939 %n print vector comparison code for predicated instruction
bf0b396d 1940 %s print size for various vcvt instructions
143275ea
AV		 1941 %v print vector predicate for instruction in predicated
1942 block
ef1576a1 1943 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 1944 %w print writeback mode for MVE v{st,ld}[24]
1945 %B print v{st,ld}[24] any one operands
c507f10b
AV		 1946 %E print vmov, vmvn, vorr, vbic encoded constant
1947 %N print generic index for vmov
14925797 1948 %T print bottom ('b') or top ('t') of source register
d3b63143 1949 %X print exchange field in vmla* instructions
04d54ace 1950
9743db03 1951 %<bitfield>r print as an ARM register
04d54ace 1952 %<bitfield>d print the bitfield in decimal
d3b63143 1953 %<bitfield>A print accumulate or not
143275ea 1954 %<bitfield>Q print as a MVE Q register
c507f10b 1955 %<bitfield>F print as a MVE S register
143275ea
AV		 1956 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1957 UNPREDICTABLE
1958 %<bitfield>s print size for vector predicate & non VMOV instructions
ef1576a1 1959 %<bitfield>i print immediate for vstr/vldr reg +/- imm
bf0b396d 1960 %<bitfield>k print immediate for vector conversion instruction
c507f10b 1961 %<bitfield>x print the bitfield in hex.
bf0b396d 1962 */
73cd51e5
AV		 1963
1964static const struct mopcode32 mve_opcodes[] =
1965{
143275ea
AV		 1966 /* MVE. */
1967
1968 {ARM_FEATURE_COPROC (FPU_MVE),
1969 MVE_VPST,
1970 0xfe310f4d, 0xffbf1fff,
1971 "vpst%i"
1972 },
1973
1974 /* Floating point VPT T1. */
1975 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1976 MVE_VPT_FP_T1,
1977 0xee310f00, 0xefb10f50,
1978 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1979 /* Floating point VPT T2. */
1980 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1981 MVE_VPT_FP_T2,
1982 0xee310f40, 0xefb10f50,
1983 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1984
1985 /* Vector VPT T1. */
1986 {ARM_FEATURE_COPROC (FPU_MVE),
1987 MVE_VPT_VEC_T1,
1988 0xfe010f00, 0xff811f51,
1989 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1990 /* Vector VPT T2. */
1991 {ARM_FEATURE_COPROC (FPU_MVE),
1992 MVE_VPT_VEC_T2,
1993 0xfe010f01, 0xff811f51,
1994 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1995 /* Vector VPT T3. */
1996 {ARM_FEATURE_COPROC (FPU_MVE),
1997 MVE_VPT_VEC_T3,
1998 0xfe011f00, 0xff811f50,
1999 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2000 /* Vector VPT T4. */
2001 {ARM_FEATURE_COPROC (FPU_MVE),
2002 MVE_VPT_VEC_T4,
2003 0xfe010f40, 0xff811f70,
2004 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2005 /* Vector VPT T5. */
2006 {ARM_FEATURE_COPROC (FPU_MVE),
2007 MVE_VPT_VEC_T5,
2008 0xfe010f60, 0xff811f70,
2009 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2010 /* Vector VPT T6. */
2011 {ARM_FEATURE_COPROC (FPU_MVE),
2012 MVE_VPT_VEC_T6,
2013 0xfe011f40, 0xff811f50,
2014 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2015
c507f10b
AV		 2016 /* Vector VBIC immediate. */
2017 {ARM_FEATURE_COPROC (FPU_MVE),
2018 MVE_VBIC_IMM,
2019 0xef800070, 0xefb81070,
2020 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2021
2022 /* Vector VBIC register. */
2023 {ARM_FEATURE_COPROC (FPU_MVE),
2024 MVE_VBIC_REG,
2025 0xef100150, 0xffb11f51,
2026 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2027
d3b63143
AV		 2028 /* Vector VADDLV. */
2029 {ARM_FEATURE_COPROC (FPU_MVE),
2030 MVE_VADDLV,
2031 0xee890f00, 0xef8f1fd1,
2032 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2033
2034 /* Vector VADDV. */
2035 {ARM_FEATURE_COPROC (FPU_MVE),
2036 MVE_VADDV,
2037 0xeef10f00, 0xeff31fd1,
2038 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2039
143275ea
AV		 2040 /* Vector VCMP floating point T1. */
2041 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2042 MVE_VCMP_FP_T1,
2043 0xee310f00, 0xeff1ef50,
2044 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2045
2046 /* Vector VCMP floating point T2. */
2047 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2048 MVE_VCMP_FP_T2,
2049 0xee310f40, 0xeff1ef50,
2050 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2051
2052 /* Vector VCMP T1. */
2053 {ARM_FEATURE_COPROC (FPU_MVE),
2054 MVE_VCMP_VEC_T1,
2055 0xfe010f00, 0xffc1ff51,
2056 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2057 /* Vector VCMP T2. */
2058 {ARM_FEATURE_COPROC (FPU_MVE),
2059 MVE_VCMP_VEC_T2,
2060 0xfe010f01, 0xffc1ff51,
2061 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2062 /* Vector VCMP T3. */
2063 {ARM_FEATURE_COPROC (FPU_MVE),
2064 MVE_VCMP_VEC_T3,
2065 0xfe011f00, 0xffc1ff50,
2066 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2067 /* Vector VCMP T4. */
2068 {ARM_FEATURE_COPROC (FPU_MVE),
2069 MVE_VCMP_VEC_T4,
2070 0xfe010f40, 0xffc1ff70,
2071 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2072 /* Vector VCMP T5. */
2073 {ARM_FEATURE_COPROC (FPU_MVE),
2074 MVE_VCMP_VEC_T5,
2075 0xfe010f60, 0xffc1ff70,
2076 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2077 /* Vector VCMP T6. */
2078 {ARM_FEATURE_COPROC (FPU_MVE),
2079 MVE_VCMP_VEC_T6,
2080 0xfe011f40, 0xffc1ff50,
2081 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2082
9743db03
AV		 2083 /* Vector VDUP. */
2084 {ARM_FEATURE_COPROC (FPU_MVE),
2085 MVE_VDUP,
2086 0xeea00b10, 0xffb10f5f,
2087 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2088
2089 /* Vector VEOR. */
2090 {ARM_FEATURE_COPROC (FPU_MVE),
2091 MVE_VEOR,
2092 0xff000150, 0xffd11f51,
2093 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2094
2095 /* Vector VFMA, vector * scalar. */
2096 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2097 MVE_VFMA_FP_SCALAR,
2098 0xee310e40, 0xefb11f70,
2099 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2100
2101 /* Vector VFMA floating point. */
2102 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2103 MVE_VFMA_FP,
2104 0xef000c50, 0xffa11f51,
2105 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2106
2107 /* Vector VFMS floating point. */
2108 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2109 MVE_VFMS_FP,
2110 0xef200c50, 0xffa11f51,
2111 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2112
2113 /* Vector VFMAS, vector * scalar. */
2114 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2115 MVE_VFMAS_FP_SCALAR,
2116 0xee311e40, 0xefb11f70,
2117 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2118
2119 /* Vector VHADD T1. */
2120 {ARM_FEATURE_COPROC (FPU_MVE),
2121 MVE_VHADD_T1,
2122 0xef000040, 0xef811f51,
2123 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2124
2125 /* Vector VHADD T2. */
2126 {ARM_FEATURE_COPROC (FPU_MVE),
2127 MVE_VHADD_T2,
2128 0xee000f40, 0xef811f70,
2129 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2130
2131 /* Vector VHSUB T1. */
2132 {ARM_FEATURE_COPROC (FPU_MVE),
2133 MVE_VHSUB_T1,
2134 0xef000240, 0xef811f51,
2135 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2136
2137 /* Vector VHSUB T2. */
2138 {ARM_FEATURE_COPROC (FPU_MVE),
2139 MVE_VHSUB_T2,
2140 0xee001f40, 0xef811f70,
2141 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2142
2143 /* Vector VDUP. */
2144 {ARM_FEATURE_COPROC (FPU_MVE),
2145 MVE_VDUP,
2146 0xeea00b10, 0xffb10f5f,
2147 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2148
2149 /* Vector VRHADD. */
2150 {ARM_FEATURE_COPROC (FPU_MVE),
2151 MVE_VRHADD,
2152 0xef000140, 0xef811f51,
2153 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2154
bf0b396d
AV		 2155 /* Vector VCVT. */
2156 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2157 MVE_VCVT_FP_FIX_VEC,
2158 0xef800c50, 0xef801cd1,
2159 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2160
2161 /* Vector VCVT. */
2162 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2163 MVE_VCVT_BETWEEN_FP_INT,
2164 0xffb30640, 0xffb31e51,
2165 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2166
2167 /* Vector VCVT between single and half-precision float, bottom half. */
2168 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2169 MVE_VCVT_FP_HALF_FP,
2170 0xee3f0e01, 0xefbf1fd1,
2171 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2172
2173 /* Vector VCVT between single and half-precision float, top half. */
2174 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2175 MVE_VCVT_FP_HALF_FP,
2176 0xee3f1e01, 0xefbf1fd1,
2177 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2178
2179 /* Vector VCVT. */
2180 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2181 MVE_VCVT_FROM_FP_TO_INT,
2182 0xffb30040, 0xffb31c51,
2183 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2184
04d54ace
AV		 2185 /* Vector VLD2. */
2186 {ARM_FEATURE_COPROC (FPU_MVE),
2187 MVE_VLD2,
2188 0xfc901e00, 0xff901e5f,
2189 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2190
2191 /* Vector VLD4. */
2192 {ARM_FEATURE_COPROC (FPU_MVE),
2193 MVE_VLD4,
2194 0xfc901e01, 0xff901e1f,
2195 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2196
ef1576a1
AV		 2197 /* Vector VLDRB gather load. */
2198 {ARM_FEATURE_COPROC (FPU_MVE),
2199 MVE_VLDRB_GATHER_T1,
2200 0xec900e00, 0xefb01e50,
2201 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2202
2203 /* Vector VLDRH gather load. */
2204 {ARM_FEATURE_COPROC (FPU_MVE),
2205 MVE_VLDRH_GATHER_T2,
2206 0xec900e10, 0xefb01e50,
2207 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2208
2209 /* Vector VLDRW gather load. */
2210 {ARM_FEATURE_COPROC (FPU_MVE),
2211 MVE_VLDRW_GATHER_T3,
2212 0xfc900f40, 0xffb01fd0,
2213 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2214
2215 /* Vector VLDRD gather load. */
2216 {ARM_FEATURE_COPROC (FPU_MVE),
2217 MVE_VLDRD_GATHER_T4,
2218 0xec900fd0, 0xefb01fd0,
2219 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2220
2221 /* Vector VLDRW gather load. */
2222 {ARM_FEATURE_COPROC (FPU_MVE),
2223 MVE_VLDRW_GATHER_T5,
2224 0xfd101e00, 0xff111f00,
2225 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2226
2227 /* Vector VLDRD gather load, variant T6. */
2228 {ARM_FEATURE_COPROC (FPU_MVE),
2229 MVE_VLDRD_GATHER_T6,
2230 0xfd101f00, 0xff111f00,
2231 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2232
aef6d006
AV		 2233 /* Vector VLDRB. */
2234 {ARM_FEATURE_COPROC (FPU_MVE),
2235 MVE_VLDRB_T1,
2236 0xec100e00, 0xee581e00,
2237 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2238
2239 /* Vector VLDRH. */
2240 {ARM_FEATURE_COPROC (FPU_MVE),
2241 MVE_VLDRH_T2,
2242 0xec180e00, 0xee581e00,
2243 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2244
2245 /* Vector VLDRB unsigned, variant T5. */
2246 {ARM_FEATURE_COPROC (FPU_MVE),
2247 MVE_VLDRB_T5,
2248 0xec101e00, 0xfe101f80,
2249 "vldrb%v.u8\t%13-15,22Q, %d"},
2250
2251 /* Vector VLDRH unsigned, variant T6. */
2252 {ARM_FEATURE_COPROC (FPU_MVE),
2253 MVE_VLDRH_T6,
2254 0xec101e80, 0xfe101f80,
2255 "vldrh%v.u16\t%13-15,22Q, %d"},
2256
2257 /* Vector VLDRW unsigned, variant T7. */
2258 {ARM_FEATURE_COPROC (FPU_MVE),
2259 MVE_VLDRW_T7,
2260 0xec101f00, 0xfe101f80,
2261 "vldrw%v.u32\t%13-15,22Q, %d"},
2262
d3b63143
AV		 2263 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2264 opcode aliasing. */
2265 {ARM_FEATURE_COPROC (FPU_MVE),
2266 MVE_VMLALDAV,
2267 0xee801e00, 0xef801f51,
2268 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2269
2270 {ARM_FEATURE_COPROC (FPU_MVE),
2271 MVE_VMLALDAV,
2272 0xee800e00, 0xef801f51,
2273 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2274
2275 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2276 {ARM_FEATURE_COPROC (FPU_MVE),
2277 MVE_VMLADAV_T1,
2278 0xeef00e00, 0xeff01f51,
2279 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2280
2281 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2282 {ARM_FEATURE_COPROC (FPU_MVE),
2283 MVE_VMLADAV_T2,
2284 0xeef00f00, 0xeff11f51,
2285 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2286
2287 /* Vector VMLADAV T1 variant. */
2288 {ARM_FEATURE_COPROC (FPU_MVE),
2289 MVE_VMLADAV_T1,
2290 0xeef01e00, 0xeff01f51,
2291 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2292
2293 /* Vector VMLADAV T2 variant. */
2294 {ARM_FEATURE_COPROC (FPU_MVE),
2295 MVE_VMLADAV_T2,
2296 0xeef01f00, 0xeff11f51,
2297 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2298
2299 /* Vector VMLAS. */
2300 {ARM_FEATURE_COPROC (FPU_MVE),
2301 MVE_VMLAS,
2302 0xee011e40, 0xef811f70,
2303 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2304
2305 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2306 opcode aliasing. */
2307 {ARM_FEATURE_COPROC (FPU_MVE),
2308 MVE_VRMLSLDAVH,
2309 0xfe800e01, 0xff810f51,
2310 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2311
2312 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2313 opcdoe aliasing. */
2314 {ARM_FEATURE_COPROC (FPU_MVE),
2315 MVE_VMLSLDAV,
2316 0xee800e01, 0xff800f51,
2317 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2318
2319 /* Vector VMLSDAV T1 Variant. */
2320 {ARM_FEATURE_COPROC (FPU_MVE),
2321 MVE_VMLSDAV_T1,
2322 0xeef00e01, 0xfff00f51,
2323 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2324
2325 /* Vector VMLSDAV T2 Variant. */
2326 {ARM_FEATURE_COPROC (FPU_MVE),
2327 MVE_VMLSDAV_T2,
2328 0xfef00e01, 0xfff10f51,
2329 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2330
c507f10b
AV		 2331 /* Vector VMOV between gpr and half precision register, op == 0. */
2332 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2333 MVE_VMOV_HFP_TO_GP,
2334 0xee000910, 0xfff00f7f,
2335 "vmov.f16\t%7,16-19F, %12-15r"},
2336
2337 /* Vector VMOV between gpr and half precision register, op == 1. */
2338 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2339 MVE_VMOV_HFP_TO_GP,
2340 0xee100910, 0xfff00f7f,
2341 "vmov.f16\t%12-15r, %7,16-19F"},
2342
2343 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2344 MVE_VMOV_GP_TO_VEC_LANE,
2345 0xee000b10, 0xff900f1f,
2346 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2347
2348 /* Vector VORR immediate to vector.
2349 NOTE: MVE_VORR_IMM must appear in the table
2350 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2351 {ARM_FEATURE_COPROC (FPU_MVE),
2352 MVE_VORR_IMM,
2353 0xef800050, 0xefb810f0,
2354 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2355
2356 /* Vector VMOV immediate to vector,
2357 cmode == 11x1 -> VMVN which is UNDEFINED
2358 for such a cmode. */
2359 {ARM_FEATURE_COPROC (FPU_MVE),
2360 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2361
2362 /* Vector VMOV immediate to vector. */
2363 {ARM_FEATURE_COPROC (FPU_MVE),
2364 MVE_VMOV_IMM_TO_VEC,
2365 0xef800050, 0xefb810d0,
2366 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2367
2368 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2369 {ARM_FEATURE_COPROC (FPU_MVE),
2370 MVE_VMOV2_VEC_LANE_TO_GP,
2371 0xec000f00, 0xffb01ff0,
2372 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2373
2374 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2375 {ARM_FEATURE_COPROC (FPU_MVE),
2376 MVE_VMOV2_VEC_LANE_TO_GP,
2377 0xec000f10, 0xffb01ff0,
2378 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2379
2380 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2381 {ARM_FEATURE_COPROC (FPU_MVE),
2382 MVE_VMOV2_GP_TO_VEC_LANE,
2383 0xec100f00, 0xffb01ff0,
2384 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2385
2386 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2387 {ARM_FEATURE_COPROC (FPU_MVE),
2388 MVE_VMOV2_GP_TO_VEC_LANE,
2389 0xec100f10, 0xffb01ff0,
2390 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2391
2392 /* Vector VMOV Vector lane to gpr. */
2393 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2394 MVE_VMOV_VEC_LANE_TO_GP,
2395 0xee100b10, 0xff100f1f,
2396 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2397
14925797
AV		 2398 /* Vector VMOVL long. */
2399 {ARM_FEATURE_COPROC (FPU_MVE),
2400 MVE_VMOVL,
2401 0xeea00f40, 0xefa70fd1,
2402 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2403
2404 /* Vector VMOV and narrow. */
2405 {ARM_FEATURE_COPROC (FPU_MVE),
2406 MVE_VMOVN,
2407 0xfe310e81, 0xffb30fd1,
2408 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2409
c507f10b
AV		 2410 /* Floating point move extract. */
2411 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2412 MVE_VMOVX,
2413 0xfeb00a40, 0xffbf0fd0,
2414 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2415
14925797
AV		 2416 /* Vector VMULL integer. */
2417 {ARM_FEATURE_COPROC (FPU_MVE),
2418 MVE_VMULL_INT,
2419 0xee010e00, 0xef810f51,
2420 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2421
2422 /* Vector VMULL polynomial. */
2423 {ARM_FEATURE_COPROC (FPU_MVE),
2424 MVE_VMULL_POLY,
2425 0xee310e00, 0xefb10f51,
2426 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2427
c507f10b
AV		 2428 /* Vector VMVN immediate to vector. */
2429 {ARM_FEATURE_COPROC (FPU_MVE),
2430 MVE_VMVN_IMM,
2431 0xef800070, 0xefb810f0,
2432 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2433
2434 /* Vector VMVN register. */
2435 {ARM_FEATURE_COPROC (FPU_MVE),
2436 MVE_VMVN_REG,
2437 0xffb005c0, 0xffbf1fd1,
2438 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2439
2440 /* Vector VORN, vector bitwise or not. */
2441 {ARM_FEATURE_COPROC (FPU_MVE),
2442 MVE_VORN,
2443 0xef300150, 0xffb11f51,
2444 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2445
2446 /* Vector VORR register. */
2447 {ARM_FEATURE_COPROC (FPU_MVE),
2448 MVE_VORR_REG,
2449 0xef200150, 0xffb11f51,
2450 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2451
14925797
AV		 2452 /* Vector VQDMULL T1 variant. */
2453 {ARM_FEATURE_COPROC (FPU_MVE),
2454 MVE_VQDMULL_T1,
2455 0xee300f01, 0xefb10f51,
2456 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2457
2458 /* Vector VQDMULL T2 variant. */
2459 {ARM_FEATURE_COPROC (FPU_MVE),
2460 MVE_VQDMULL_T2,
2461 0xee300f60, 0xefb10f70,
2462 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2463
2464 /* Vector VQMOVN. */
2465 {ARM_FEATURE_COPROC (FPU_MVE),
2466 MVE_VQMOVN,
2467 0xee330e01, 0xefb30fd1,
2468 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2469
2470 /* Vector VQMOVUN. */
2471 {ARM_FEATURE_COPROC (FPU_MVE),
2472 MVE_VQMOVUN,
2473 0xee310e81, 0xffb30fd1,
2474 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2475
d3b63143
AV		 2476 /* Vector VQDMLADH. */
2477 {ARM_FEATURE_COPROC (FPU_MVE),
2478 MVE_VQDMLADH,
2479 0xee000e00, 0xff810f51,
2480 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2481
2482 /* Vector VQRDMLADH. */
2483 {ARM_FEATURE_COPROC (FPU_MVE),
2484 MVE_VQRDMLADH,
2485 0xee000e01, 0xff810f51,
2486 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2487
2488 /* Vector VQDMLAH. */
2489 {ARM_FEATURE_COPROC (FPU_MVE),
2490 MVE_VQDMLAH,
2491 0xee000e60, 0xef811f70,
2492 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2493
2494 /* Vector VQRDMLAH. */
2495 {ARM_FEATURE_COPROC (FPU_MVE),
2496 MVE_VQRDMLAH,
2497 0xee000e40, 0xef811f70,
2498 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2499
2500 /* Vector VQDMLASH. */
2501 {ARM_FEATURE_COPROC (FPU_MVE),
2502 MVE_VQDMLASH,
2503 0xee001e60, 0xef811f70,
2504 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2505
2506 /* Vector VQRDMLASH. */
2507 {ARM_FEATURE_COPROC (FPU_MVE),
2508 MVE_VQRDMLASH,
2509 0xee001e40, 0xef811f70,
2510 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2511
2512 /* Vector VQDMLSDH. */
2513 {ARM_FEATURE_COPROC (FPU_MVE),
2514 MVE_VQDMLSDH,
2515 0xfe000e00, 0xff810f51,
2516 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2517
2518 /* Vector VQRDMLSDH. */
2519 {ARM_FEATURE_COPROC (FPU_MVE),
2520 MVE_VQRDMLSDH,
2521 0xfe000e01, 0xff810f51,
2522 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2523
2524 /* Vector VQDMULH T1 variant. */
2525 {ARM_FEATURE_COPROC (FPU_MVE),
2526 MVE_VQDMULH_T1,
2527 0xef000b40, 0xff811f51,
2528 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2529
2530 /* Vector VQRDMULH T2 variant. */
2531 {ARM_FEATURE_COPROC (FPU_MVE),
2532 MVE_VQRDMULH_T2,
2533 0xff000b40, 0xff811f51,
2534 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2535
2536 /* Vector VQDMULH T3 variant. */
2537 {ARM_FEATURE_COPROC (FPU_MVE),
2538 MVE_VQDMULH_T3,
2539 0xee010e60, 0xff811f70,
2540 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2541
2542 /* Vector VQRDMULH T4 variant. */
2543 {ARM_FEATURE_COPROC (FPU_MVE),
2544 MVE_VQRDMULH_T4,
2545 0xfe010e60, 0xff811f70,
2546 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2547
bf0b396d
AV		 2548 /* Vector VRINT floating point. */
2549 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2550 MVE_VRINT_FP,
2551 0xffb20440, 0xffb31c51,
2552 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2553
d3b63143
AV		 2554 /* Vector VRMLALDAVH. */
2555 {ARM_FEATURE_COPROC (FPU_MVE),
2556 MVE_VRMLALDAVH,
2557 0xee800f00, 0xef811f51,
2558 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2559
2560 /* Vector VRMLALDAVH. */
2561 {ARM_FEATURE_COPROC (FPU_MVE),
2562 MVE_VRMLALDAVH,
2563 0xee801f00, 0xef811f51,
2564 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2565
04d54ace
AV		 2566 /* Vector VST2 no writeback. */
2567 {ARM_FEATURE_COPROC (FPU_MVE),
2568 MVE_VST2,
2569 0xfc801e00, 0xffb01e5f,
2570 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2571
2572 /* Vector VST2 writeback. */
2573 {ARM_FEATURE_COPROC (FPU_MVE),
2574 MVE_VST2,
2575 0xfca01e00, 0xffb01e5f,
2576 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2577
2578 /* Vector VST4 no writeback. */
2579 {ARM_FEATURE_COPROC (FPU_MVE),
2580 MVE_VST4,
2581 0xfc801e01, 0xffb01e1f,
2582 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2583
2584 /* Vector VST4 writeback. */
2585 {ARM_FEATURE_COPROC (FPU_MVE),
2586 MVE_VST4,
2587 0xfca01e01, 0xffb01e1f,
2588 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2589
ef1576a1
AV		 2590 /* Vector VSTRB scatter store, T1 variant. */
2591 {ARM_FEATURE_COPROC (FPU_MVE),
2592 MVE_VSTRB_SCATTER_T1,
2593 0xec800e00, 0xffb01e50,
2594 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2595
2596 /* Vector VSTRH scatter store, T2 variant. */
2597 {ARM_FEATURE_COPROC (FPU_MVE),
2598 MVE_VSTRH_SCATTER_T2,
2599 0xec800e10, 0xffb01e50,
2600 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2601
2602 /* Vector VSTRW scatter store, T3 variant. */
2603 {ARM_FEATURE_COPROC (FPU_MVE),
2604 MVE_VSTRW_SCATTER_T3,
2605 0xec800e40, 0xffb01e50,
2606 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2607
2608 /* Vector VSTRD scatter store, T4 variant. */
2609 {ARM_FEATURE_COPROC (FPU_MVE),
2610 MVE_VSTRD_SCATTER_T4,
2611 0xec800fd0, 0xffb01fd0,
2612 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2613
2614 /* Vector VSTRW scatter store, T5 variant. */
2615 {ARM_FEATURE_COPROC (FPU_MVE),
2616 MVE_VSTRW_SCATTER_T5,
2617 0xfd001e00, 0xff111f00,
2618 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2619
2620 /* Vector VSTRD scatter store, T6 variant. */
2621 {ARM_FEATURE_COPROC (FPU_MVE),
2622 MVE_VSTRD_SCATTER_T6,
2623 0xfd001f00, 0xff111f00,
2624 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2625
aef6d006
AV		 2626 /* Vector VSTRB. */
2627 {ARM_FEATURE_COPROC (FPU_MVE),
2628 MVE_VSTRB_T1,
2629 0xec000e00, 0xfe581e00,
2630 "vstrb%v.%7-8s\t%13-15Q, %d"},
2631
2632 /* Vector VSTRH. */
2633 {ARM_FEATURE_COPROC (FPU_MVE),
2634 MVE_VSTRH_T2,
2635 0xec080e00, 0xfe581e00,
2636 "vstrh%v.%7-8s\t%13-15Q, %d"},
2637
2638 /* Vector VSTRB variant T5. */
2639 {ARM_FEATURE_COPROC (FPU_MVE),
2640 MVE_VSTRB_T5,
2641 0xec001e00, 0xfe101f80,
2642 "vstrb%v.8\t%13-15,22Q, %d"},
2643
2644 /* Vector VSTRH variant T6. */
2645 {ARM_FEATURE_COPROC (FPU_MVE),
2646 MVE_VSTRH_T6,
2647 0xec001e80, 0xfe101f80,
2648 "vstrh%v.16\t%13-15,22Q, %d"},
2649
2650 /* Vector VSTRW variant T7. */
2651 {ARM_FEATURE_COPROC (FPU_MVE),
2652 MVE_VSTRW_T7,
2653 0xec001f00, 0xfe101f80,
2654 "vstrw%v.32\t%13-15,22Q, %d"},
2655
143275ea
AV		 2656 {ARM_FEATURE_CORE_LOW (0),
2657 MVE_NONE,
2658 0x00000000, 0x00000000, 0}
73cd51e5
AV		 2659};
2660
8f06b2d8
PB		 2661/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2662 ordered: they must be searched linearly from the top to obtain a correct
2663 match. */
2664
2665/* print_insn_arm recognizes the following format control codes:
2666
2667 %% %
2668
2669 %a print address for ldr/str instruction
2670 %s print address for ldr/str halfword/signextend instruction
c1e26897 2671 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 2672 %b print branch destination
2673 %c print condition code (always bits 28-31)
2674 %m print register mask for ldm/stm instruction
2675 %o print operand2 (immediate or register + shift)
2676 %p print 'p' iff bits 12-15 are 15
2677 %t print 't' iff bit 21 set and bit 24 clear
2678 %B print arm BLX(1) destination
2679 %C print the PSR sub type.
62b3e311
PB		 2680 %U print barrier type.
2681 %P print address for pli instruction.
8f06b2d8
PB		 2682
2683 %<bitfield>r print as an ARM register
9eb6c0f1 2684 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 2685 %<bitfield>R as %r but r15 is UNPREDICTABLE
2686 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2687 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 2688 %<bitfield>d print the bitfield in decimal
43e65147 2689 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 2690 %<bitfield>x print the bitfield in hex
2691 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 2692
16980d0b
JB		 2693 %<bitfield>'c print specified char iff bitfield is all ones
2694 %<bitfield>`c print specified char iff bitfield is all zeroes
2695 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 2696
8f06b2d8
PB		 2697 %e print arm SMI operand (bits 0..7,8..19).
2698 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 2699 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2700 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 2701
8f06b2d8
PB		 2702static const struct opcode32 arm_opcodes[] =
2703{
2704 /* ARM instructions. */
823d2571
TG		 2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2706 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2708 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2709
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2711 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2713 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2715 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2717 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2719 0x00800090, 0x0fa000f0,
2720 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2722 0x00a00090, 0x0fa000f0,
2723 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 2724
105bde57 2725 /* V8.2 RAS extension instructions. */
4d1464f2 2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2727 0xe320f010, 0xffffffff, "esb"},
2728
53c4b28b 2729 /* V8 instructions. */
823d2571
TG		 2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2731 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 2732 /* Defined in V8 but is in NOP space so available to all arch. */
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 2734 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 2735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 2736 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2737 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 2738 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2740 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2742 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 2743 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2744 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2745 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2746 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2747 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2748 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2749 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2750 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2751 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2752 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2753 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2754 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2755 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2756 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2757 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2758 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2759 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2760 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2761 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 2762 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 2763 /* CRC32 instructions. */
823d2571
TG		 2764 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2765 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2766 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2767 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2768 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2769 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2770 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2771 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2772 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2773 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2774 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2775 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 2776
ddfded2f
MW		 2777 /* Privileged Access Never extension instructions. */
2778 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
2779 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2780
90ec0d68 2781 /* Virtualization Extension instructions. */
823d2571
TG		 2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 2784
eea54501 2785 /* Integer Divide Extension instructions. */
823d2571
TG		 2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2787 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2789 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 2790
60e5ef9f 2791 /* MP Extension instructions. */
823d2571 2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 2793
c597cc3d
SD		 2794 /* Speculation Barriers. */
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
2798
62b3e311 2799 /* V7 instructions. */
823d2571
TG		 2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2808 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 2809
c19d1205 2810 /* ARM V6T2 instructions. */
823d2571
TG		 2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2812 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2814 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2816 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2818 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2819
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2824
ff8646ee 2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2826 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 2827 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2828 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2832 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 2833
f4c65163 2834 /* ARM Security extension instructions. */
823d2571
TG		 2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
2836 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 2837
8f06b2d8 2838 /* ARM V6K instructions. */
823d2571
TG		 2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2840 0xf57ff01f, 0xffffffff, "clrex"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2842 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2844 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2846 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2848 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2850 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2852 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 2853
7fadb25d
SD		 2854 /* ARMv8.5-A instructions. */
2855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
2856
8f06b2d8 2857 /* ARM V6K NOP hints. */
823d2571
TG		 2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2859 0x0320f001, 0x0fffffff, "yield%c"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2861 0x0320f002, 0x0fffffff, "wfe%c"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2863 0x0320f003, 0x0fffffff, "wfi%c"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2865 0x0320f004, 0x0fffffff, "sev%c"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2867 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 2868
fe56b6ce 2869 /* ARM V6 instructions. */
823d2571
TG		 2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2871 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2873 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2875 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2877 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2879 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2881 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2883 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2885 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2887 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2889 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2891 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2893 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2895 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2897 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2899 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2901 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2903 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2905 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2907 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2909 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2911 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2913 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2915 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2917 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2919 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2921 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2923 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2925 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2927 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2929 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2931 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2933 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2935 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2937 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2939 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2941 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2943 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2945 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2947 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2949 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2951 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2953 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2955 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2957 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2959 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2961 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2963 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2965 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2967 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2969 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2971 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2973 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2975 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2977 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2979 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2981 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2983 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2985 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2987 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2989 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2991 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2993 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2995 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2997 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2999 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3001 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3003 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3005 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3007 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3009 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3011 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3013 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3015 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3017 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3019 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3021 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3023 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3025 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3027 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3029 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3031 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3033 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3035 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3037 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3039 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3041 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3043 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3045 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3047 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3049 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3051 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3053 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3055 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3057 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3059 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3061 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3063 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3065 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3067 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3069 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3071 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3073 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3075 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3077 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3079 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3081 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3083 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3085 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3087 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3089 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3091 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3093 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3095 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3097 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3099 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3101 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3103 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3105 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3107 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3109 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3111 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3113 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3114
8f06b2d8 3115 /* V5J instruction. */
823d2571
TG		 3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3117 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3118
8f06b2d8 3119 /* V5 Instructions. */
823d2571
TG		 3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3121 0xe1200070, 0xfff000f0,
3122 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3124 0xfa000000, 0xfe000000, "blx\t%B"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3126 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3128 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3129
3130 /* V5E "El Segundo" Instructions. */
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3132 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3134 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3136 0xf450f000, 0xfc70f000, "pld\t%a"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3138 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3140 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3142 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3144 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3145
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3147 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3149 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3150
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3152 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3154 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3156 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3158 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3159
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3161 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3163 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3165 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3167 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3168
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3170 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3172 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3173
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3175 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3177 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3179 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3181 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 3182
8f06b2d8 3183 /* ARM Instructions. */
823d2571
TG		 3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3185 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3186
3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3188 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3190 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3192 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3194 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3196 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3198 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3199
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3201 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3203 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3205 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3207 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3208
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3210 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3212 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3214 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3216 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3217
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3219 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3221 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3223 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3224
3225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3226 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3228 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3230 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3231
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3233 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3235 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3237 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3238
3239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3240 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3242 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3244 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3245
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3247 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3249 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3251 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3252
3253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3254 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3256 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3258 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3259
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3261 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3263 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3265 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3266
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3268 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3270 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3272 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3273
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3275 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3277 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3279 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3280
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3282 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3284 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3286 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3287
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3289 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3291 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3293 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 3294
3295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3296 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3298 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3300 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3301
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3303 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3305 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3307 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3308
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3310 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3312 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3314 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3315
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3317 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3319 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3321 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3323 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3325 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3327 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3329 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3330
3331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3332 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3334 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3336 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3337
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3339 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3341 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3343 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3344
3345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3346 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3348 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3349
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3351 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3352
3353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3354 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3356 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3357
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3359 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3361 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3363 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3365 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3367 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3369 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3371 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3373 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3375 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3377 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3379 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3381 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3383 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3385 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3387 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3389 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3391 0x092d0000, 0x0fff0000, "push%c\t%m"},
3392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3393 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3395 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3396
3397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3398 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3400 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3402 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3404 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3406 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3408 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3410 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3412 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3414 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3416 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3418 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3420 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3422 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3424 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3426 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3428 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3430 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3432 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3434 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3435
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3437 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3439 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 3440
3441 /* The rest. */
4ab90a7a
AV		 3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3443 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3445 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3446 {ARM_FEATURE_CORE_LOW (0),
3447 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 3448};
3449
3450/* print_insn_thumb16 recognizes the following format control codes:
3451
3452 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3453 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3454 %<bitfield>I print bitfield as a signed decimal
3455 (top bit of range being the sign bit)
3456 %N print Thumb register mask (with LR)
3457 %O print Thumb register mask (with PC)
3458 %M print Thumb register mask
3459 %b print CZB's 6-bit unsigned branch destination
3460 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 3461 %c print the condition code
3462 %C print the condition code, or "s" if not conditional
3463 %x print warning if conditional an not at end of IT block"
3464 %X print "\t; unpredictable <IT:code>" if conditional
3465 %I print IT instruction suffix and operands
4547cb56 3466 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 3467 %<bitfield>r print bitfield as an ARM register
3468 %<bitfield>d print bitfield as a decimal
3469 %<bitfield>H print (bitfield * 2) as a decimal
3470 %<bitfield>W print (bitfield * 4) as a decimal
3471 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3472 %<bitfield>B print Thumb branch destination (signed displacement)
3473 %<bitfield>c print bitfield as a condition code
3474 %<bitnum>'c print specified char iff bit is one
3475 %<bitnum>?ab print a if bit is one else print b. */
3476
3477static const struct opcode16 thumb_opcodes[] =
3478{
3479 /* Thumb instructions. */
3480
16a1fa25
TP		 3481 /* ARMv8-M Security Extensions instructions. */
3482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 3483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 3484
53c4b28b 3485 /* ARM V8 instructions. */
823d2571
TG		 3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 3488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 3489
8f06b2d8 3490 /* ARM V6K no-argument instructions. */
823d2571
TG		 3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 3497
3498 /* ARM V6T2 instructions. */
ff8646ee
TP		 3499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3500 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3502 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 3503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 3504
3505 /* ARM V6. */
823d2571
TG		 3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 3517
3518 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 3519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3520 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 3521 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3523 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 3524 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 3525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3526 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 3527 /* Format 4. */
823d2571
TG		 3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 3544 /* format 13 */
823d2571
TG		 3545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 3547 /* format 5 */
823d2571
TG		 3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 3552 /* format 14 */
823d2571
TG		 3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 3555 /* format 2 */
823d2571
TG		 3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3557 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3559 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3561 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3563 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 3564 /* format 8 */
823d2571
TG		 3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3566 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3568 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3570 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3571 /* format 7 */
823d2571
TG		 3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3573 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3575 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3576 /* format 1 */
823d2571
TG		 3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3579 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 3582 /* format 3 */
823d2571
TG		 3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 3587 /* format 6 */
823d2571
TG		 3588 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3590 0x4800, 0xF800,
3591 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 3592 /* format 9 */
823d2571
TG		 3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3594 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3596 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3598 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3600 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 3601 /* format 10 */
823d2571
TG		 3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3603 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3605 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 3606 /* format 11 */
823d2571
TG		 3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3608 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3610 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 3611 /* format 12 */
823d2571
TG		 3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3613 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3615 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 3616 /* format 15 */
823d2571
TG		 3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 3619 /* format 17 */
823d2571 3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 3621 /* format 16 */
823d2571
TG		 3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 3625 /* format 18 */
823d2571 3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 3627
3628 /* The E800 .. FFFF range is unconditionally redirected to the
3629 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3630 are processed via that table. Thus, we can never encounter a
3631 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3633 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 3634};
3635
3636/* Thumb32 opcodes use the same table structure as the ARM opcodes.
3637 We adopt the convention that hw1 is the high 16 bits of .value and
3638 .mask, hw2 the low 16 bits.
3639
3640 print_insn_thumb32 recognizes the following format control codes:
3641
3642 %% %
3643
3644 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3645 %M print a modified 12-bit immediate (same location)
3646 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3647 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 3648 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 3649 %S print a possibly-shifted Rm
3650
32a94698 3651 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 3652 %a print the address of a plain load/store
3653 %w print the width and signedness of a core load/store
3654 %m print register mask for ldm/stm
4b5a202f 3655 %n print register mask for clrm
8f06b2d8
PB		 3656
3657 %E print the lsb and width fields of a bfc/bfi instruction
3658 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 3659 %G print a fallback offset for Branch Future instructions
e5d6e09e 3660 %W print an offset for BF instruction
1caf72a5 3661 %Y print an offset for BFL instruction
1889da70 3662 %Z print an offset for BFCSEL instruction
60f993ce
AV		 3663 %Q print an offset for Low Overhead Loop instructions
3664 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 3665 %b print a conditional branch offset
3666 %B print an unconditional branch offset
3667 %s print the shift field of an SSAT instruction
3668 %R print the rotation field of an SXT instruction
62b3e311
PB		 3669 %U print barrier type.
3670 %P print address for pli instruction.
c22aaad1
PB		 3671 %c print the condition code
3672 %x print warning if conditional an not at end of IT block"
3673 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 3674
3675 %<bitfield>d print bitfield in decimal
f0fba320 3676 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 3677 %<bitfield>W print bitfield*4 in decimal
3678 %<bitfield>r print bitfield as an ARM register
dd5181d5 3679 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 3680 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 3681 %<bitfield>c print bitfield as a condition code
3682
16980d0b
JB		 3683 %<bitfield>'c print specified char iff bitfield is all ones
3684 %<bitfield>`c print specified char iff bitfield is all zeroes
3685 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 3686
3687 With one exception at the bottom (done because BL and BLX(1) need
3688 to come dead last), this table was machine-sorted first in
3689 decreasing order of number of bits set in the mask, then in
3690 increasing numeric order of mask, then in increasing numeric order
3691 of opcode. This order is not the clearest for a human reader, but
3692 is guaranteed never to catch a special-case bit pattern with a more
3693 general mask, which is important, because this instruction encoding
3694 makes heavy use of special-case bit patterns. */
3695static const struct opcode32 thumb32_opcodes[] =
3696{
4b5a202f
AV		 3697 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3698 instructions. */
60f993ce
AV		 3699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3700 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3701 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3702 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3704 0xf02fc001, 0xfffff001, "le\t%P"},
3705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3706 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3707
4389b29a
AV		 3708 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3709 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 3710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3711 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 3712 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3713 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 3714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3715 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 3716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3717 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 3718
4b5a202f
AV		 3719 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3720 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 3721
16a1fa25
TP		 3722 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3725 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3727 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3729 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3731 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 3732
105bde57 3733 /* ARM V8.2 RAS extension instructions. */
4d1464f2 3734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3735 0xf3af8010, 0xffffffff, "esb"},
3736
53c4b28b 3737 /* V8 instructions. */
823d2571
TG		 3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3739 0xf3af8005, 0xffffffff, "sevl%c.w"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3741 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3743 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3745 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3747 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3749 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3751 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3753 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3755 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3757 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3759 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3761 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3763 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3765 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3767 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3769 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 3770
dd5181d5 3771 /* CRC32 instructions. */
823d2571 3772 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3773 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 3774 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3775 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 3776 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3777 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 3778 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3779 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 3780 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3781 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 3782 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3783 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 3784
c597cc3d
SD		 3785 /* Speculation Barriers. */
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
3789
62b3e311 3790 /* V7 instructions. */
823d2571
TG		 3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3799 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3801 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 3802
90ec0d68 3803 /* Virtualization Extension instructions. */
823d2571 3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 3805 /* We skip ERET as that is SUBS pc, lr, #0. */
3806
60e5ef9f 3807 /* MP Extension instructions. */
823d2571 3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 3809
f4c65163 3810 /* Security extension instructions. */
823d2571 3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 3812
7fadb25d
SD		 3813 /* ARMv8.5-A instructions. */
3814 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
3815
8f06b2d8 3816 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3823 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3825
ff8646ee 3826 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3827 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3829 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3831 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3833 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3835 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3837 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3839 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3841 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3843 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3845 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3847 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3849 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3851 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3853 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 3854 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3855 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 3856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3857 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3859 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3861 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3863 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3865 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3867 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3869 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3871 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3873 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 3874 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3875 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3877 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3879 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3881 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3883 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3885 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3887 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3889 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3891 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3893 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3895 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3897 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3899 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3901 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3903 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3905 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3907 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3909 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3911 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3913 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3915 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3917 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3919 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3921 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3923 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3925 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3927 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3929 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3931 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3933 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3935 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3937 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3939 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3941 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3943 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3945 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3947 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3949 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3951 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3953 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3955 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3957 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3959 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3961 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3963 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3965 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3967 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3969 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3971 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3973 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3975 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3977 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3979 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3981 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3983 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3985 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3987 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3989 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3991 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3993 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3995 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3997 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3999 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4001 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4003 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4005 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4007 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4009 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4011 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4013 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4015 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4017 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4019 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4021 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4023 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4025 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4027 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4029 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4031 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4033 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4035 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4037 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4039 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4041 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4043 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4045 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4047 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4049 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4051 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4053 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4055 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4057 0xf810f000, 0xff70f000, "pld%c\t%a"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4059 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4061 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4063 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4065 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4067 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4069 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4071 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4073 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4075 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4077 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4079 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4081 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4083 0xfb100000, 0xfff000c0,
4084 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4086 0xfbc00080, 0xfff000c0,
4087 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4089 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4091 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4093 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4095 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4097 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4098 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4099 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4101 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4102 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4103 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4105 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4107 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4109 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4111 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4113 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4115 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4117 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4119 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4121 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4123 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4125 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4127 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4129 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4131 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4133 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4135 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4137 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4139 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4141 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4143 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4145 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4147 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4149 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4151 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4153 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4155 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4157 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4159 0xe9400000, 0xff500000,
4160 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4162 0xe9500000, 0xff500000,
4163 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4165 0xe8600000, 0xff700000,
4166 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4168 0xe8700000, 0xff700000,
4169 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4171 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4173 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 4174
4175 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4177 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4179 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4181 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4183 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 4184
8f06b2d8 4185 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4187 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4189 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 4190
4191 /* Fallback. */
823d2571
TG		 4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4194 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 4195};
ff4a8d2b 4196
8f06b2d8
PB		 4197static const char *const arm_conditional[] =
4198{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 4199 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 4200
4201static const char *const arm_fp_const[] =
4202{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4203
4204static const char *const arm_shift[] =
4205{"lsl", "lsr", "asr", "ror"};
4206
4207typedef struct
4208{
4209 const char *name;
4210 const char *description;
4211 const char *reg_names[16];
4212}
4213arm_regname;
4214
4215static const arm_regname regnames[] =
4216{
65b48a81 4217 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 4218 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 4219 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 4220 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4221 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 4222 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 4223 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4224 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4225 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 4226 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4227 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 4228 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 4229 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4230 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 4231};
4232
4233static const char *const iwmmxt_wwnames[] =
4234{"b", "h", "w", "d"};
4235
4236static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 4237{"b", "bus", "bc", "bss",
4238 "h", "hus", "hc", "hss",
4239 "w", "wus", "wc", "wss",
4240 "d", "dus", "dc", "dss"
8f06b2d8
PB		 4241};
4242
4243static const char *const iwmmxt_regnames[] =
4244{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4245 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4246};
4247
4248static const char *const iwmmxt_cregnames[] =
4249{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4250 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4251};
4252
143275ea
AV		 4253static const char *const vec_condnames[] =
4254{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4255};
4256
4257static const char *const mve_predicatenames[] =
4258{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4259 "eee", "ee", "eet", "e", "ett", "et", "ete"
4260};
4261
4262/* Names for 2-bit size field for mve vector isntructions. */
4263static const char *const mve_vec_sizename[] =
4264 { "8", "16", "32", "64"};
4265
4266/* Indicates whether we are processing a then predicate,
4267 else predicate or none at all. */
4268enum vpt_pred_state
4269{
4270 PRED_NONE,
4271 PRED_THEN,
4272 PRED_ELSE
4273};
4274
4275/* Information used to process a vpt block and subsequent instructions. */
4276struct vpt_block
4277{
4278 /* Are we in a vpt block. */
4279 bfd_boolean in_vpt_block;
4280
4281 /* Next predicate state if in vpt block. */
4282 enum vpt_pred_state next_pred_state;
4283
4284 /* Mask from vpt/vpst instruction. */
4285 long predicate_mask;
4286
4287 /* Instruction number in vpt block. */
4288 long current_insn_num;
4289
4290 /* Number of instructions in vpt block.. */
4291 long num_pred_insn;
4292};
4293
4294static struct vpt_block vpt_block_state =
4295{
4296 FALSE,
4297 PRED_NONE,
4298 0,
4299 0,
4300 0
4301};
4302
8f06b2d8
PB		 4303/* Default to GCC register name set. */
4304static unsigned int regname_selected = 1;
4305
65b48a81 4306#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 4307#define arm_regnames regnames[regname_selected].reg_names
4308
4309static bfd_boolean force_thumb = FALSE;
4310
c22aaad1
PB		 4311/* Current IT instruction state. This contains the same state as the IT
4312 bits in the CPSR. */
4313static unsigned int ifthen_state;
4314/* IT state for the next instruction. */
4315static unsigned int ifthen_next_state;
4316/* The address of the insn for which the IT state is valid. */
4317static bfd_vma ifthen_address;
4318#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 4319/* Indicates that the current Conditional state is unconditional or outside
4320 an IT block. */
4321#define COND_UNCOND 16
c22aaad1 4322
8f06b2d8
PB		 4323\f
4324/* Functions. */
143275ea
AV		 4325/* Extract the predicate mask for a VPT or VPST instruction.
4326 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4327
4328static long
4329mve_extract_pred_mask (long given)
4330{
4331 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4332}
4333
4334/* Return the number of instructions in a MVE predicate block. */
4335static long
4336num_instructions_vpt_block (long given)
4337{
4338 long mask = mve_extract_pred_mask (given);
4339 if (mask == 0)
4340 return 0;
4341
4342 if (mask == 8)
4343 return 1;
4344
4345 if ((mask & 7) == 4)
4346 return 2;
4347
4348 if ((mask & 3) == 2)
4349 return 3;
4350
4351 if ((mask & 1) == 1)
4352 return 4;
4353
4354 return 0;
4355}
4356
4357static void
4358mark_outside_vpt_block (void)
4359{
4360 vpt_block_state.in_vpt_block = FALSE;
4361 vpt_block_state.next_pred_state = PRED_NONE;
4362 vpt_block_state.predicate_mask = 0;
4363 vpt_block_state.current_insn_num = 0;
4364 vpt_block_state.num_pred_insn = 0;
4365}
4366
4367static void
4368mark_inside_vpt_block (long given)
4369{
4370 vpt_block_state.in_vpt_block = TRUE;
4371 vpt_block_state.next_pred_state = PRED_THEN;
4372 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4373 vpt_block_state.current_insn_num = 0;
4374 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4375 assert (vpt_block_state.num_pred_insn >= 1);
4376}
4377
4378static enum vpt_pred_state
4379invert_next_predicate_state (enum vpt_pred_state astate)
4380{
4381 if (astate == PRED_THEN)
4382 return PRED_ELSE;
4383 else if (astate == PRED_ELSE)
4384 return PRED_THEN;
4385 else
4386 return PRED_NONE;
4387}
4388
4389static enum vpt_pred_state
4390update_next_predicate_state (void)
4391{
4392 long pred_mask = vpt_block_state.predicate_mask;
4393 long mask_for_insn = 0;
4394
4395 switch (vpt_block_state.current_insn_num)
4396 {
4397 case 1:
4398 mask_for_insn = 8;
4399 break;
4400
4401 case 2:
4402 mask_for_insn = 4;
4403 break;
4404
4405 case 3:
4406 mask_for_insn = 2;
4407 break;
4408
4409 case 4:
4410 return PRED_NONE;
4411 }
4412
4413 if (pred_mask & mask_for_insn)
4414 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4415 else
4416 return vpt_block_state.next_pred_state;
4417}
4418
4419static void
4420update_vpt_block_state (void)
4421{
4422 vpt_block_state.current_insn_num++;
4423 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4424 {
4425 /* No more instructions to process in vpt block. */
4426 mark_outside_vpt_block ();
4427 return;
4428 }
4429
4430 vpt_block_state.next_pred_state = update_next_predicate_state ();
4431}
8f06b2d8 4432
16980d0b
JB		 4433/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4434 Returns pointer to following character of the format string and
4435 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 4436 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 4437
4438static const char *
fe56b6ce
NC		 4439arm_decode_bitfield (const char *ptr,
4440 unsigned long insn,
4441 unsigned long *valuep,
4442 int *widthp)
16980d0b
JB		 4443{
4444 unsigned long value = 0;
4445 int width = 0;
43e65147
L		 4446
4447 do
16980d0b
JB		 4448 {
4449 int start, end;
4450 int bits;
4451
4452 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4453 start = start * 10 + *ptr - '0';
4454 if (*ptr == '-')
4455 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4456 end = end * 10 + *ptr - '0';
4457 else
4458 end = start;
4459 bits = end - start;
4460 if (bits < 0)
4461 abort ();
4462 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4463 width += bits + 1;
4464 }
4465 while (*ptr++ == ',');
4466 *valuep = value;
4467 if (widthp)
4468 *widthp = width;
4469 return ptr - 1;
4470}
4471
8f06b2d8 4472static void
37b37b2d 4473arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 4474 bfd_boolean print_shift)
8f06b2d8
PB		 4475{
4476 func (stream, "%s", arm_regnames[given & 0xf]);
4477
4478 if ((given & 0xff0) != 0)
4479 {
4480 if ((given & 0x10) == 0)
4481 {
4482 int amount = (given & 0xf80) >> 7;
4483 int shift = (given & 0x60) >> 5;
4484
4485 if (amount == 0)
4486 {
4487 if (shift == 3)
4488 {
4489 func (stream, ", rrx");
4490 return;
4491 }
4492
4493 amount = 32;
4494 }
4495
37b37b2d
RE		 4496 if (print_shift)
4497 func (stream, ", %s #%d", arm_shift[shift], amount);
4498 else
4499 func (stream, ", #%d", amount);
8f06b2d8 4500 }
74bdfecf 4501 else if ((given & 0x80) == 0x80)
aefd8a40 4502 func (stream, "\t; <illegal shifter operand>");
37b37b2d 4503 else if (print_shift)
8f06b2d8
PB		 4504 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4505 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 4506 else
4507 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 4508 }
4509}
4510
73cd51e5
AV		 4511/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4512
4513static bfd_boolean
4514is_mve_okay_in_it (enum mve_instructions matched_insn)
4515{
c507f10b
AV		 4516 switch (matched_insn)
4517 {
4518 case MVE_VMOV_GP_TO_VEC_LANE:
4519 case MVE_VMOV2_VEC_LANE_TO_GP:
4520 case MVE_VMOV2_GP_TO_VEC_LANE:
4521 case MVE_VMOV_VEC_LANE_TO_GP:
4522 return TRUE;
4523 default:
4524 return FALSE;
4525 }
73cd51e5
AV		 4526}
4527
4528static bfd_boolean
4529is_mve_architecture (struct disassemble_info *info)
4530{
4531 struct arm_private_data *private_data = info->private_data;
4532 arm_feature_set allowed_arches = private_data->features;
4533
4534 arm_feature_set arm_ext_v8_1m_main
4535 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4536
4537 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4538 && !ARM_CPU_IS_ANY (allowed_arches))
4539 return TRUE;
4540 else
4541 return FALSE;
4542}
4543
143275ea
AV		 4544static bfd_boolean
4545is_vpt_instruction (long given)
4546{
4547
4548 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4549 if ((given & 0x0040e000) == 0)
4550 return FALSE;
4551
4552 /* VPT floating point T1 variant. */
4553 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4554 /* VPT floating point T2 variant. */
4555 || ((given & 0xefb10f50) == 0xee310f40)
4556 /* VPT vector T1 variant. */
4557 || ((given & 0xff811f51) == 0xfe010f00)
4558 /* VPT vector T2 variant. */
4559 || ((given & 0xff811f51) == 0xfe010f01
4560 && ((given & 0x300000) != 0x300000))
4561 /* VPT vector T3 variant. */
4562 || ((given & 0xff811f50) == 0xfe011f00)
4563 /* VPT vector T4 variant. */
4564 || ((given & 0xff811f70) == 0xfe010f40)
4565 /* VPT vector T5 variant. */
4566 || ((given & 0xff811f70) == 0xfe010f60)
4567 /* VPT vector T6 variant. */
4568 || ((given & 0xff811f50) == 0xfe011f40)
4569 /* VPST vector T variant. */
4570 || ((given & 0xffbf1fff) == 0xfe310f4d))
4571 return TRUE;
4572 else
4573 return FALSE;
4574}
4575
73cd51e5
AV		 4576/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4577 and ending bitfield = END. END must be greater than START. */
4578
4579static unsigned long
4580arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4581{
4582 int bits = end - start;
4583
4584 if (bits < 0)
4585 abort ();
4586
4587 return ((given >> start) & ((2ul << bits) - 1));
4588}
4589
4590/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4591 START:END and START2:END2. END/END2 must be greater than
4592 START/START2. */
4593
4594static unsigned long
4595arm_decode_field_multiple (unsigned long given, unsigned int start,
4596 unsigned int end, unsigned int start2,
4597 unsigned int end2)
4598{
4599 int bits = end - start;
4600 int bits2 = end2 - start2;
4601 unsigned long value = 0;
4602 int width = 0;
4603
4604 if (bits2 < 0)
4605 abort ();
4606
4607 value = arm_decode_field (given, start, end);
4608 width += bits + 1;
4609
4610 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4611 return value;
4612}
4613
4614/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4615 This helps us decode instructions that change mnemonic depending on specific
4616 operand values/encodings. */
4617
4618static bfd_boolean
4619is_mve_encoding_conflict (unsigned long given,
4620 enum mve_instructions matched_insn)
4621{
143275ea
AV		 4622 switch (matched_insn)
4623 {
4624 case MVE_VPST:
4625 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4626 return TRUE;
4627 else
4628 return FALSE;
4629
4630 case MVE_VPT_FP_T1:
4631 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4632 return TRUE;
4633 if ((arm_decode_field (given, 12, 12) == 0)
4634 && (arm_decode_field (given, 0, 0) == 1))
4635 return TRUE;
4636 return FALSE;
4637
4638 case MVE_VPT_FP_T2:
4639 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4640 return TRUE;
4641 if (arm_decode_field (given, 0, 3) == 0xd)
4642 return TRUE;
4643 return FALSE;
4644
4645 case MVE_VPT_VEC_T1:
4646 case MVE_VPT_VEC_T2:
4647 case MVE_VPT_VEC_T3:
4648 case MVE_VPT_VEC_T4:
4649 case MVE_VPT_VEC_T5:
4650 case MVE_VPT_VEC_T6:
4651 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4652 return TRUE;
4653 if (arm_decode_field (given, 20, 21) == 3)
4654 return TRUE;
4655 return FALSE;
4656
4657 case MVE_VCMP_FP_T1:
4658 if ((arm_decode_field (given, 12, 12) == 0)
4659 && (arm_decode_field (given, 0, 0) == 1))
4660 return TRUE;
4661 else
4662 return FALSE;
4663
4664 case MVE_VCMP_FP_T2:
4665 if (arm_decode_field (given, 0, 3) == 0xd)
4666 return TRUE;
4667 else
4668 return FALSE;
4669
d3b63143
AV		 4670 case MVE_VQRDMLADH:
4671 case MVE_VQDMLAH:
4672 case MVE_VQRDMLAH:
4673 case MVE_VQDMLASH:
4674 case MVE_VQRDMLASH:
4675 case MVE_VQDMLSDH:
4676 case MVE_VQRDMLSDH:
4677 case MVE_VQDMULH_T3:
4678 case MVE_VQRDMULH_T4:
4679 case MVE_VQDMLADH:
4680 case MVE_VMLAS:
14925797 4681 case MVE_VMULL_INT:
9743db03
AV		 4682 case MVE_VHADD_T2:
4683 case MVE_VHSUB_T2:
143275ea
AV		 4684 case MVE_VCMP_VEC_T1:
4685 case MVE_VCMP_VEC_T2:
4686 case MVE_VCMP_VEC_T3:
4687 case MVE_VCMP_VEC_T4:
4688 case MVE_VCMP_VEC_T5:
4689 case MVE_VCMP_VEC_T6:
4690 if (arm_decode_field (given, 20, 21) == 3)
4691 return TRUE;
4692 else
4693 return FALSE;
4694
04d54ace
AV		 4695 case MVE_VLD2:
4696 case MVE_VLD4:
4697 case MVE_VST2:
4698 case MVE_VST4:
4699 if (arm_decode_field (given, 7, 8) == 3)
4700 return TRUE;
4701 else
4702 return FALSE;
4703
aef6d006
AV		 4704 case MVE_VSTRB_T1:
4705 case MVE_VSTRH_T2:
4706 if ((arm_decode_field (given, 24, 24) == 0)
4707 && (arm_decode_field (given, 21, 21) == 0))
4708 {
4709 return TRUE;
4710 }
4711 else if ((arm_decode_field (given, 7, 8) == 3))
4712 return TRUE;
4713 else
4714 return FALSE;
4715
4716 case MVE_VSTRB_T5:
4717 case MVE_VSTRH_T6:
4718 case MVE_VSTRW_T7:
4719 if ((arm_decode_field (given, 24, 24) == 0)
4720 && (arm_decode_field (given, 21, 21) == 0))
4721 {
4722 return TRUE;
4723 }
4724 else
4725 return FALSE;
4726
bf0b396d
AV		 4727 case MVE_VCVT_FP_FIX_VEC:
4728 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
4729
c507f10b
AV		 4730 case MVE_VBIC_IMM:
4731 case MVE_VORR_IMM:
4732 {
4733 unsigned long cmode = arm_decode_field (given, 8, 11);
4734
4735 if ((cmode & 1) == 0)
4736 return TRUE;
4737 else if ((cmode & 0xc) == 0xc)
4738 return TRUE;
4739 else
4740 return FALSE;
4741 }
4742
4743 case MVE_VMVN_IMM:
4744 {
4745 unsigned long cmode = arm_decode_field (given, 8, 11);
4746
4747 if ((cmode & 9) == 1)
4748 return TRUE;
4749 else if ((cmode & 5) == 1)
4750 return TRUE;
4751 else if ((cmode & 0xe) == 0xe)
4752 return TRUE;
4753 else
4754 return FALSE;
4755 }
4756
4757 case MVE_VMOV_IMM_TO_VEC:
4758 if ((arm_decode_field (given, 5, 5) == 1)
4759 && (arm_decode_field (given, 8, 11) != 0xe))
4760 return TRUE;
4761 else
4762 return FALSE;
4763
14925797
AV		 4764 case MVE_VMOVL:
4765 {
4766 unsigned long size = arm_decode_field (given, 19, 20);
4767 if ((size == 0) || (size == 3))
4768 return TRUE;
4769 else
4770 return FALSE;
4771 }
4772
d3b63143 4773 case MVE_VADDV:
14925797
AV		 4774 case MVE_VMOVN:
4775 case MVE_VQMOVUN:
4776 case MVE_VQMOVN:
4777 if (arm_decode_field (given, 18, 19) == 3)
4778 return TRUE;
4779 else
4780 return FALSE;
4781
d3b63143
AV		 4782 case MVE_VMLSLDAV:
4783 case MVE_VRMLSLDAVH:
4784 case MVE_VMLALDAV:
4785 case MVE_VADDLV:
4786 if (arm_decode_field (given, 20, 22) == 7)
4787 return TRUE;
4788 else
4789 return FALSE;
4790
4791 case MVE_VRMLALDAVH:
4792 if ((arm_decode_field (given, 20, 22) & 6) == 6)
4793 return TRUE;
4794 else
4795 return FALSE;
4796
143275ea
AV		 4797 default:
4798 return FALSE;
4799
4800 }
73cd51e5
AV		 4801}
4802
aef6d006
AV		 4803static void
4804print_mve_vld_str_addr (struct disassemble_info *info,
4805 unsigned long given,
4806 enum mve_instructions matched_insn)
4807{
4808 void *stream = info->stream;
4809 fprintf_ftype func = info->fprintf_func;
4810
4811 unsigned long p, w, gpr, imm, add, mod_imm;
4812
4813 imm = arm_decode_field (given, 0, 6);
4814 mod_imm = imm;
4815
4816 switch (matched_insn)
4817 {
4818 case MVE_VLDRB_T1:
4819 case MVE_VSTRB_T1:
4820 gpr = arm_decode_field (given, 16, 18);
4821 break;
4822
4823 case MVE_VLDRH_T2:
4824 case MVE_VSTRH_T2:
4825 gpr = arm_decode_field (given, 16, 18);
4826 mod_imm = imm << 1;
4827 break;
4828
4829 case MVE_VLDRH_T6:
4830 case MVE_VSTRH_T6:
4831 gpr = arm_decode_field (given, 16, 19);
4832 mod_imm = imm << 1;
4833 break;
4834
4835 case MVE_VLDRW_T7:
4836 case MVE_VSTRW_T7:
4837 gpr = arm_decode_field (given, 16, 19);
4838 mod_imm = imm << 2;
4839 break;
4840
4841 case MVE_VLDRB_T5:
4842 case MVE_VSTRB_T5:
4843 gpr = arm_decode_field (given, 16, 19);
4844 break;
4845
4846 default:
4847 return;
4848 }
4849
4850 p = arm_decode_field (given, 24, 24);
4851 w = arm_decode_field (given, 21, 21);
4852
4853 add = arm_decode_field (given, 23, 23);
4854
4855 char * add_sub;
4856
4857 /* Don't print anything for '+' as it is implied. */
4858 if (add == 1)
4859 add_sub = "";
4860 else
4861 add_sub = "-";
4862
4863 if (p == 1)
4864 {
4865 /* Offset mode. */
4866 if (w == 0)
4867 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
4868 /* Pre-indexed mode. */
4869 else
4870 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
4871 }
4872 else if ((p == 0) && (w == 1))
4873 /* Post-index mode. */
4874 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
4875}
4876
73cd51e5
AV		 4877/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4878 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4879 this encoding is undefined. */
4880
4881static bfd_boolean
4882is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
4883 enum mve_undefined *undefined_code)
4884{
4885 *undefined_code = UNDEF_NONE;
4886
9743db03
AV		 4887 switch (matched_insn)
4888 {
4889 case MVE_VDUP:
4890 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
4891 {
4892 *undefined_code = UNDEF_SIZE_3;
4893 return TRUE;
4894 }
4895 else
4896 return FALSE;
4897
d3b63143
AV		 4898 case MVE_VQDMULH_T1:
4899 case MVE_VQRDMULH_T2:
9743db03
AV		 4900 case MVE_VRHADD:
4901 case MVE_VHADD_T1:
4902 case MVE_VHSUB_T1:
4903 if (arm_decode_field (given, 20, 21) == 3)
4904 {
4905 *undefined_code = UNDEF_SIZE_3;
4906 return TRUE;
4907 }
4908 else
4909 return FALSE;
4910
aef6d006
AV		 4911 case MVE_VLDRB_T1:
4912 if (arm_decode_field (given, 7, 8) == 3)
4913 {
4914 *undefined_code = UNDEF_SIZE_3;
4915 return TRUE;
4916 }
4917 else
4918 return FALSE;
4919
4920 case MVE_VLDRH_T2:
4921 if (arm_decode_field (given, 7, 8) <= 1)
4922 {
4923 *undefined_code = UNDEF_SIZE_LE_1;
4924 return TRUE;
4925 }
4926 else
4927 return FALSE;
4928
4929 case MVE_VSTRB_T1:
4930 if ((arm_decode_field (given, 7, 8) == 0))
4931 {
4932 *undefined_code = UNDEF_SIZE_0;
4933 return TRUE;
4934 }
4935 else
4936 return FALSE;
4937
4938 case MVE_VSTRH_T2:
4939 if ((arm_decode_field (given, 7, 8) <= 1))
4940 {
4941 *undefined_code = UNDEF_SIZE_LE_1;
4942 return TRUE;
4943 }
4944 else
4945 return FALSE;
4946
ef1576a1
AV		 4947 case MVE_VLDRB_GATHER_T1:
4948 if (arm_decode_field (given, 7, 8) == 3)
4949 {
4950 *undefined_code = UNDEF_SIZE_3;
4951 return TRUE;
4952 }
4953 else if ((arm_decode_field (given, 28, 28) == 0)
4954 && (arm_decode_field (given, 7, 8) == 0))
4955 {
4956 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
4957 return TRUE;
4958 }
4959 else
4960 return FALSE;
4961
4962 case MVE_VLDRH_GATHER_T2:
4963 if (arm_decode_field (given, 7, 8) == 3)
4964 {
4965 *undefined_code = UNDEF_SIZE_3;
4966 return TRUE;
4967 }
4968 else if ((arm_decode_field (given, 28, 28) == 0)
4969 && (arm_decode_field (given, 7, 8) == 1))
4970 {
4971 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
4972 return TRUE;
4973 }
4974 else if (arm_decode_field (given, 7, 8) == 0)
4975 {
4976 *undefined_code = UNDEF_SIZE_0;
4977 return TRUE;
4978 }
4979 else
4980 return FALSE;
4981
4982 case MVE_VLDRW_GATHER_T3:
4983 if (arm_decode_field (given, 7, 8) != 2)
4984 {
4985 *undefined_code = UNDEF_SIZE_NOT_2;
4986 return TRUE;
4987 }
4988 else if (arm_decode_field (given, 28, 28) == 0)
4989 {
4990 *undefined_code = UNDEF_NOT_UNSIGNED;
4991 return TRUE;
4992 }
4993 else
4994 return FALSE;
4995
4996 case MVE_VLDRD_GATHER_T4:
4997 if (arm_decode_field (given, 7, 8) != 3)
4998 {
4999 *undefined_code = UNDEF_SIZE_NOT_3;
5000 return TRUE;
5001 }
5002 else if (arm_decode_field (given, 28, 28) == 0)
5003 {
5004 *undefined_code = UNDEF_NOT_UNSIGNED;
5005 return TRUE;
5006 }
5007 else
5008 return FALSE;
5009
5010 case MVE_VSTRB_SCATTER_T1:
5011 if (arm_decode_field (given, 7, 8) == 3)
5012 {
5013 *undefined_code = UNDEF_SIZE_3;
5014 return TRUE;
5015 }
5016 else
5017 return FALSE;
5018
5019 case MVE_VSTRH_SCATTER_T2:
5020 {
5021 unsigned long size = arm_decode_field (given, 7, 8);
5022 if (size == 3)
5023 {
5024 *undefined_code = UNDEF_SIZE_3;
5025 return TRUE;
5026 }
5027 else if (size == 0)
5028 {
5029 *undefined_code = UNDEF_SIZE_0;
5030 return TRUE;
5031 }
5032 else
5033 return FALSE;
5034 }
5035
5036 case MVE_VSTRW_SCATTER_T3:
5037 if (arm_decode_field (given, 7, 8) != 2)
5038 {
5039 *undefined_code = UNDEF_SIZE_NOT_2;
5040 return TRUE;
5041 }
5042 else
5043 return FALSE;
5044
5045 case MVE_VSTRD_SCATTER_T4:
5046 if (arm_decode_field (given, 7, 8) != 3)
5047 {
5048 *undefined_code = UNDEF_SIZE_NOT_3;
5049 return TRUE;
5050 }
5051 else
5052 return FALSE;
5053
bf0b396d
AV		 5054 case MVE_VCVT_FP_FIX_VEC:
5055 {
5056 unsigned long imm6 = arm_decode_field (given, 16, 21);
5057 if ((imm6 & 0x20) == 0)
5058 {
5059 *undefined_code = UNDEF_VCVT_IMM6;
5060 return TRUE;
5061 }
5062
5063 if ((arm_decode_field (given, 9, 9) == 0)
5064 && ((imm6 & 0x30) == 0x20))
5065 {
5066 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5067 return TRUE;
5068 }
5069
5070 return FALSE;
5071 }
5072
5073 case MVE_VCVT_BETWEEN_FP_INT:
5074 case MVE_VCVT_FROM_FP_TO_INT:
5075 {
5076 unsigned long size = arm_decode_field (given, 18, 19);
5077 if (size == 0)
5078 {
5079 *undefined_code = UNDEF_SIZE_0;
5080 return TRUE;
5081 }
5082 else if (size == 3)
5083 {
5084 *undefined_code = UNDEF_SIZE_3;
5085 return TRUE;
5086 }
5087 else
5088 return FALSE;
5089 }
5090
c507f10b
AV		 5091 case MVE_VMOV_VEC_LANE_TO_GP:
5092 {
5093 unsigned long op1 = arm_decode_field (given, 21, 22);
5094 unsigned long op2 = arm_decode_field (given, 5, 6);
5095 unsigned long u = arm_decode_field (given, 23, 23);
5096
5097 if ((op2 == 0) && (u == 1))
5098 {
5099 if ((op1 == 0) || (op1 == 1))
5100 {
5101 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5102 return TRUE;
5103 }
5104 else
5105 return FALSE;
5106 }
5107 else if (op2 == 2)
5108 {
5109 if ((op1 == 0) || (op1 == 1))
5110 {
5111 *undefined_code = UNDEF_BAD_OP1_OP2;
5112 return TRUE;
5113 }
5114 else
5115 return FALSE;
5116 }
5117
5118 return FALSE;
5119 }
5120
5121 case MVE_VMOV_GP_TO_VEC_LANE:
5122 if (arm_decode_field (given, 5, 6) == 2)
5123 {
5124 unsigned long op1 = arm_decode_field (given, 21, 22);
5125 if ((op1 == 0) || (op1 == 1))
5126 {
5127 *undefined_code = UNDEF_BAD_OP1_OP2;
5128 return TRUE;
5129 }
5130 else
5131 return FALSE;
5132 }
5133 else
5134 return FALSE;
5135
5136 case MVE_VMOV_IMM_TO_VEC:
5137 if (arm_decode_field (given, 5, 5) == 0)
5138 {
5139 unsigned long cmode = arm_decode_field (given, 8, 11);
5140
5141 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5142 {
5143 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5144 return TRUE;
5145 }
5146 else
5147 return FALSE;
5148 }
5149 else
5150 return FALSE;
5151
14925797
AV		 5152 case MVE_VMOVN:
5153 if (arm_decode_field (given, 18, 19) == 2)
5154 {
5155 *undefined_code = UNDEF_SIZE_2;
5156 return TRUE;
5157 }
5158 else
5159 return FALSE;
5160
d3b63143
AV		 5161 case MVE_VRMLALDAVH:
5162 case MVE_VMLADAV_T1:
5163 case MVE_VMLADAV_T2:
5164 case MVE_VMLALDAV:
5165 if ((arm_decode_field (given, 28, 28) == 1)
5166 && (arm_decode_field (given, 12, 12) == 1))
5167 {
5168 *undefined_code = UNDEF_XCHG_UNS;
5169 return TRUE;
5170 }
5171 else
5172 return FALSE;
5173
9743db03
AV		 5174 default:
5175 return FALSE;
5176 }
73cd51e5
AV		 5177}
5178
5179/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5180 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5181 why this encoding is unpredictable. */
5182
5183static bfd_boolean
5184is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5185 enum mve_unpredictable *unpredictable_code)
5186{
5187 *unpredictable_code = UNPRED_NONE;
5188
143275ea
AV		 5189 switch (matched_insn)
5190 {
5191 case MVE_VCMP_FP_T2:
5192 case MVE_VPT_FP_T2:
5193 if ((arm_decode_field (given, 12, 12) == 0)
5194 && (arm_decode_field (given, 5, 5) == 1))
5195 {
5196 *unpredictable_code = UNPRED_FCA_0_FCB_1;
5197 return TRUE;
5198 }
5199 else
5200 return FALSE;
73cd51e5 5201
143275ea
AV		 5202 case MVE_VPT_VEC_T4:
5203 case MVE_VPT_VEC_T5:
5204 case MVE_VPT_VEC_T6:
5205 case MVE_VCMP_VEC_T4:
5206 case MVE_VCMP_VEC_T5:
5207 case MVE_VCMP_VEC_T6:
5208 if (arm_decode_field (given, 0, 3) == 0xd)
5209 {
5210 *unpredictable_code = UNPRED_R13;
5211 return TRUE;
5212 }
5213 else
5214 return FALSE;
c1e26897 5215
9743db03
AV		 5216 case MVE_VDUP:
5217 {
5218 unsigned long gpr = arm_decode_field (given, 12, 15);
5219 if (gpr == 0xd)
5220 {
5221 *unpredictable_code = UNPRED_R13;
5222 return TRUE;
5223 }
5224 else if (gpr == 0xf)
5225 {
5226 *unpredictable_code = UNPRED_R15;
5227 return TRUE;
5228 }
5229
5230 return FALSE;
5231 }
5232
d3b63143
AV		 5233 case MVE_VQDMLAH:
5234 case MVE_VQRDMLAH:
5235 case MVE_VQDMLASH:
5236 case MVE_VQRDMLASH:
5237 case MVE_VQDMULH_T3:
5238 case MVE_VQRDMULH_T4:
5239 case MVE_VMLAS:
9743db03
AV		 5240 case MVE_VFMA_FP_SCALAR:
5241 case MVE_VFMAS_FP_SCALAR:
5242 case MVE_VHADD_T2:
5243 case MVE_VHSUB_T2:
5244 {
5245 unsigned long gpr = arm_decode_field (given, 0, 3);
5246 if (gpr == 0xd)
5247 {
5248 *unpredictable_code = UNPRED_R13;
5249 return TRUE;
5250 }
5251 else if (gpr == 0xf)
5252 {
5253 *unpredictable_code = UNPRED_R15;
5254 return TRUE;
5255 }
5256
5257 return FALSE;
5258 }
5259
04d54ace
AV		 5260 case MVE_VLD2:
5261 case MVE_VST2:
5262 {
5263 unsigned long rn = arm_decode_field (given, 16, 19);
5264
5265 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5266 {
5267 *unpredictable_code = UNPRED_R13_AND_WB;
5268 return TRUE;
5269 }
5270
5271 if (rn == 0xf)
5272 {
5273 *unpredictable_code = UNPRED_R15;
5274 return TRUE;
5275 }
5276
5277 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5278 {
5279 *unpredictable_code = UNPRED_Q_GT_6;
5280 return TRUE;
5281 }
5282 else
5283 return FALSE;
5284 }
5285
5286 case MVE_VLD4:
5287 case MVE_VST4:
5288 {
5289 unsigned long rn = arm_decode_field (given, 16, 19);
5290
5291 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5292 {
5293 *unpredictable_code = UNPRED_R13_AND_WB;
5294 return TRUE;
5295 }
5296
5297 if (rn == 0xf)
5298 {
5299 *unpredictable_code = UNPRED_R15;
5300 return TRUE;
5301 }
5302
5303 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5304 {
5305 *unpredictable_code = UNPRED_Q_GT_4;
5306 return TRUE;
5307 }
5308 else
5309 return FALSE;
5310 }
5311
aef6d006
AV		 5312 case MVE_VLDRB_T5:
5313 case MVE_VLDRH_T6:
5314 case MVE_VLDRW_T7:
5315 case MVE_VSTRB_T5:
5316 case MVE_VSTRH_T6:
5317 case MVE_VSTRW_T7:
5318 {
5319 unsigned long rn = arm_decode_field (given, 16, 19);
5320
5321 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5322 {
5323 *unpredictable_code = UNPRED_R13_AND_WB;
5324 return TRUE;
5325 }
5326 else if (rn == 0xf)
5327 {
5328 *unpredictable_code = UNPRED_R15;
5329 return TRUE;
5330 }
5331 else
5332 return FALSE;
5333 }
5334
ef1576a1
AV		 5335 case MVE_VLDRB_GATHER_T1:
5336 if (arm_decode_field (given, 0, 0) == 1)
5337 {
5338 *unpredictable_code = UNPRED_OS;
5339 return TRUE;
5340 }
5341
5342 /* fall through. */
5343 /* To handle common code with T2-T4 variants. */
5344 case MVE_VLDRH_GATHER_T2:
5345 case MVE_VLDRW_GATHER_T3:
5346 case MVE_VLDRD_GATHER_T4:
5347 {
5348 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5349 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5350
5351 if (qd == qm)
5352 {
5353 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5354 return TRUE;
5355 }
5356
5357 if (arm_decode_field (given, 16, 19) == 0xf)
5358 {
5359 *unpredictable_code = UNPRED_R15;
5360 return TRUE;
5361 }
5362
5363 return FALSE;
5364 }
5365
5366 case MVE_VLDRW_GATHER_T5:
5367 case MVE_VLDRD_GATHER_T6:
5368 {
5369 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5370 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
5371
5372 if (qd == qm)
5373 {
5374 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5375 return TRUE;
5376 }
5377 else
5378 return FALSE;
5379 }
5380
5381 case MVE_VSTRB_SCATTER_T1:
5382 if (arm_decode_field (given, 16, 19) == 0xf)
5383 {
5384 *unpredictable_code = UNPRED_R15;
5385 return TRUE;
5386 }
5387 else if (arm_decode_field (given, 0, 0) == 1)
5388 {
5389 *unpredictable_code = UNPRED_OS;
5390 return TRUE;
5391 }
5392 else
5393 return FALSE;
5394
5395 case MVE_VSTRH_SCATTER_T2:
5396 case MVE_VSTRW_SCATTER_T3:
5397 case MVE_VSTRD_SCATTER_T4:
5398 if (arm_decode_field (given, 16, 19) == 0xf)
5399 {
5400 *unpredictable_code = UNPRED_R15;
5401 return TRUE;
5402 }
5403 else
5404 return FALSE;
5405
c507f10b
AV		 5406 case MVE_VMOV2_VEC_LANE_TO_GP:
5407 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 5408 case MVE_VCVT_BETWEEN_FP_INT:
5409 case MVE_VCVT_FROM_FP_TO_INT:
5410 {
5411 unsigned long rt = arm_decode_field (given, 0, 3);
5412 unsigned long rt2 = arm_decode_field (given, 16, 19);
5413
5414 if ((rt == 0xd) || (rt2 == 0xd))
5415 {
5416 *unpredictable_code = UNPRED_R13;
5417 return TRUE;
5418 }
5419 else if ((rt == 0xf) || (rt2 == 0xf))
5420 {
5421 *unpredictable_code = UNPRED_R15;
5422 return TRUE;
5423 }
5424 else if (rt == rt2)
5425 {
5426 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
5427 return TRUE;
5428 }
5429
5430 return FALSE;
5431 }
5432
c507f10b
AV		 5433 case MVE_VMOV_HFP_TO_GP:
5434 case MVE_VMOV_GP_TO_VEC_LANE:
5435 case MVE_VMOV_VEC_LANE_TO_GP:
5436 {
5437 unsigned long rda = arm_decode_field (given, 12, 15);
5438 if (rda == 0xd)
5439 {
5440 *unpredictable_code = UNPRED_R13;
5441 return TRUE;
5442 }
5443 else if (rda == 0xf)
5444 {
5445 *unpredictable_code = UNPRED_R15;
5446 return TRUE;
5447 }
5448
5449 return FALSE;
5450 }
5451
d3b63143
AV		 5452 case MVE_VQRDMLADH:
5453 case MVE_VQDMLSDH:
5454 case MVE_VQRDMLSDH:
5455 case MVE_VQDMLADH:
14925797
AV		 5456 case MVE_VMULL_INT:
5457 {
5458 unsigned long Qd;
5459 unsigned long Qm;
5460 unsigned long Qn;
5461
5462 if (arm_decode_field (given, 20, 21) == 2)
5463 {
5464 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5465 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5466 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5467
5468 if ((Qd == Qn) || (Qd == Qm))
5469 {
5470 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5471 return TRUE;
5472 }
5473 else
5474 return FALSE;
5475 }
5476 else
5477 return FALSE;
5478 }
5479
5480 case MVE_VQDMULL_T1:
5481 {
5482 unsigned long Qd;
5483 unsigned long Qm;
5484 unsigned long Qn;
5485
5486 if (arm_decode_field (given, 28, 28) == 1)
5487 {
5488 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5489 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5490 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5491
5492 if ((Qd == Qn) || (Qd == Qm))
5493 {
5494 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5495 return TRUE;
5496 }
5497 else
5498 return FALSE;
5499 }
5500 else
5501 return FALSE;
5502 }
5503
5504 case MVE_VQDMULL_T2:
5505 {
5506 unsigned long gpr = arm_decode_field (given, 0, 3);
5507 if (gpr == 0xd)
5508 {
5509 *unpredictable_code = UNPRED_R13;
5510 return TRUE;
5511 }
5512 else if (gpr == 0xf)
5513 {
5514 *unpredictable_code = UNPRED_R15;
5515 return TRUE;
5516 }
5517
5518 if (arm_decode_field (given, 28, 28) == 1)
5519 {
5520 unsigned long Qd
5521 = arm_decode_field_multiple (given, 13, 15, 22, 22);
5522 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5523
5524 if ((Qd == Qn))
5525 {
5526 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5527 return TRUE;
5528 }
5529 else
5530 return FALSE;
5531 }
5532
5533 return FALSE;
5534 }
5535
d3b63143
AV		 5536 case MVE_VMLSLDAV:
5537 case MVE_VRMLSLDAVH:
5538 case MVE_VMLALDAV:
5539 case MVE_VADDLV:
5540 if (arm_decode_field (given, 20, 22) == 6)
5541 {
5542 *unpredictable_code = UNPRED_R13;
5543 return TRUE;
5544 }
5545 else
5546 return FALSE;
5547
143275ea
AV		 5548 default:
5549 return FALSE;
5550 }
5551}
c1e26897 5552
c507f10b
AV		 5553static void
5554print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
5555{
5556 unsigned long op1 = arm_decode_field (given, 21, 22);
5557 unsigned long op2 = arm_decode_field (given, 5, 6);
5558 unsigned long h = arm_decode_field (given, 16, 16);
5559 unsigned long index, esize, targetBeat, idx;
5560 void *stream = info->stream;
5561 fprintf_ftype func = info->fprintf_func;
5562
5563 if ((op1 & 0x2) == 0x2)
5564 {
5565 index = op2;
5566 esize = 8;
5567 }
5568 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
5569 {
5570 index = op2 >> 1;
5571 esize = 16;
5572 }
5573 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
5574 {
5575 index = 0;
5576 esize = 32;
5577 }
5578 else
5579 {
5580 func (stream, "<undefined index>");
5581 return;
5582 }
5583
5584 targetBeat = (op1 & 0x1) | (h << 1);
5585 idx = index + targetBeat * (32/esize);
5586
5587 func (stream, "%lu", idx);
5588}
5589
5590/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
5591 in length and integer of floating-point type. */
5592static void
5593print_simd_imm8 (struct disassemble_info *info, unsigned long given,
5594 unsigned int ibit_loc, const struct mopcode32 *insn)
5595{
5596 int bits = 0;
5597 int cmode = (given >> 8) & 0xf;
5598 int op = (given >> 5) & 0x1;
5599 unsigned long value = 0, hival = 0;
5600 unsigned shift;
5601 int size = 0;
5602 int isfloat = 0;
5603 void *stream = info->stream;
5604 fprintf_ftype func = info->fprintf_func;
5605
5606 /* On Neon the 'i' bit is at bit 24, on mve it is
5607 at bit 28. */
5608 bits |= ((given >> ibit_loc) & 1) << 7;
5609 bits |= ((given >> 16) & 7) << 4;
5610 bits |= ((given >> 0) & 15) << 0;
5611
5612 if (cmode < 8)
5613 {
5614 shift = (cmode >> 1) & 3;
5615 value = (unsigned long) bits << (8 * shift);
5616 size = 32;
5617 }
5618 else if (cmode < 12)
5619 {
5620 shift = (cmode >> 1) & 1;
5621 value = (unsigned long) bits << (8 * shift);
5622 size = 16;
5623 }
5624 else if (cmode < 14)
5625 {
5626 shift = (cmode & 1) + 1;
5627 value = (unsigned long) bits << (8 * shift);
5628 value |= (1ul << (8 * shift)) - 1;
5629 size = 32;
5630 }
5631 else if (cmode == 14)
5632 {
5633 if (op)
5634 {
5635 /* Bit replication into bytes. */
5636 int ix;
5637 unsigned long mask;
5638
5639 value = 0;
5640 hival = 0;
5641 for (ix = 7; ix >= 0; ix--)
5642 {
5643 mask = ((bits >> ix) & 1) ? 0xff : 0;
5644 if (ix <= 3)
5645 value = (value << 8) | mask;
5646 else
5647 hival = (hival << 8) | mask;
5648 }
5649 size = 64;
5650 }
5651 else
5652 {
5653 /* Byte replication. */
5654 value = (unsigned long) bits;
5655 size = 8;
5656 }
5657 }
5658 else if (!op)
5659 {
5660 /* Floating point encoding. */
5661 int tmp;
5662
5663 value = (unsigned long) (bits & 0x7f) << 19;
5664 value |= (unsigned long) (bits & 0x80) << 24;
5665 tmp = bits & 0x40 ? 0x3c : 0x40;
5666 value |= (unsigned long) tmp << 24;
5667 size = 32;
5668 isfloat = 1;
5669 }
5670 else
5671 {
5672 func (stream, "<illegal constant %.8x:%x:%x>",
5673 bits, cmode, op);
5674 size = 32;
5675 return;
5676 }
5677
5678 // printU determines whether the immediate value should be printed as
5679 // unsigned.
5680 unsigned printU = 0;
5681 switch (insn->mve_op)
5682 {
5683 default:
5684 break;
5685 // We want this for instructions that don't have a 'signed' type
5686 case MVE_VBIC_IMM:
5687 case MVE_VORR_IMM:
5688 case MVE_VMVN_IMM:
5689 case MVE_VMOV_IMM_TO_VEC:
5690 printU = 1;
5691 break;
5692 }
5693 switch (size)
5694 {
5695 case 8:
5696 func (stream, "#%ld\t; 0x%.2lx", value, value);
5697 break;
5698
5699 case 16:
5700 func (stream,
5701 printU
5702 ? "#%lu\t; 0x%.4lx"
5703 : "#%ld\t; 0x%.4lx", value, value);
5704 break;
5705
5706 case 32:
5707 if (isfloat)
5708 {
5709 unsigned char valbytes[4];
5710 double fvalue;
5711
5712 /* Do this a byte at a time so we don't have to
5713 worry about the host's endianness. */
5714 valbytes[0] = value & 0xff;
5715 valbytes[1] = (value >> 8) & 0xff;
5716 valbytes[2] = (value >> 16) & 0xff;
5717 valbytes[3] = (value >> 24) & 0xff;
5718
5719 floatformat_to_double
5720 (& floatformat_ieee_single_little, valbytes,
5721 & fvalue);
5722
5723 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
5724 value);
5725 }
5726 else
5727 func (stream,
5728 printU
5729 ? "#%lu\t; 0x%.8lx"
5730 : "#%ld\t; 0x%.8lx",
5731 (long) (((value & 0x80000000L) != 0)
5732 && !printU
5733 ? value | ~0xffffffffL : value),
5734 value);
5735 break;
5736
5737 case 64:
5738 func (stream, "#0x%.8lx%.8lx", hival, value);
5739 break;
5740
5741 default:
5742 abort ();
5743 }
5744
5745}
5746
73cd51e5
AV		 5747static void
5748print_mve_undefined (struct disassemble_info *info,
5749 enum mve_undefined undefined_code)
5750{
5751 void *stream = info->stream;
5752 fprintf_ftype func = info->fprintf_func;
5753
5754 func (stream, "\t\tundefined instruction: ");
5755
5756 switch (undefined_code)
5757 {
aef6d006
AV		 5758 case UNDEF_SIZE_0:
5759 func (stream, "size equals zero");
5760 break;
5761
c507f10b
AV		 5762 case UNDEF_SIZE_2:
5763 func (stream, "size equals two");
5764 break;
5765
9743db03
AV		 5766 case UNDEF_SIZE_3:
5767 func (stream, "size equals three");
5768 break;
5769
aef6d006
AV		 5770 case UNDEF_SIZE_LE_1:
5771 func (stream, "size <= 1");
5772 break;
5773
ef1576a1
AV		 5774 case UNDEF_SIZE_NOT_2:
5775 func (stream, "size not equal to 2");
5776 break;
5777
5778 case UNDEF_SIZE_NOT_3:
5779 func (stream, "size not equal to 3");
5780 break;
5781
5782 case UNDEF_NOT_UNS_SIZE_0:
5783 func (stream, "not unsigned and size = zero");
5784 break;
5785
5786 case UNDEF_NOT_UNS_SIZE_1:
5787 func (stream, "not unsigned and size = one");
5788 break;
5789
5790 case UNDEF_NOT_UNSIGNED:
5791 func (stream, "not unsigned");
5792 break;
5793
bf0b396d
AV		 5794 case UNDEF_VCVT_IMM6:
5795 func (stream, "invalid imm6");
5796 break;
5797
5798 case UNDEF_VCVT_FSI_IMM6:
5799 func (stream, "fsi = 0 and invalid imm6");
5800 break;
5801
c507f10b
AV		 5802 case UNDEF_BAD_OP1_OP2:
5803 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
5804 break;
5805
5806 case UNDEF_BAD_U_OP1_OP2:
5807 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
5808 break;
5809
5810 case UNDEF_OP_0_BAD_CMODE:
5811 func (stream, "op field equal 0 and bad cmode");
5812 break;
5813
d3b63143
AV		 5814 case UNDEF_XCHG_UNS:
5815 func (stream, "exchange and unsigned together");
5816 break;
5817
73cd51e5
AV		 5818 case UNDEF_NONE:
5819 break;
5820 }
5821
5822}
5823
5824static void
5825print_mve_unpredictable (struct disassemble_info *info,
5826 enum mve_unpredictable unpredict_code)
5827{
5828 void *stream = info->stream;
5829 fprintf_ftype func = info->fprintf_func;
5830
5831 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
5832
5833 switch (unpredict_code)
5834 {
5835 case UNPRED_IT_BLOCK:
5836 func (stream, "mve instruction in it block");
5837 break;
5838
143275ea
AV		 5839 case UNPRED_FCA_0_FCB_1:
5840 func (stream, "condition bits, fca = 0 and fcb = 1");
5841 break;
5842
5843 case UNPRED_R13:
5844 func (stream, "use of r13 (sp)");
5845 break;
5846
9743db03
AV		 5847 case UNPRED_R15:
5848 func (stream, "use of r15 (pc)");
5849 break;
5850
04d54ace
AV		 5851 case UNPRED_Q_GT_4:
5852 func (stream, "start register block > r4");
5853 break;
5854
5855 case UNPRED_Q_GT_6:
5856 func (stream, "start register block > r6");
5857 break;
5858
5859 case UNPRED_R13_AND_WB:
5860 func (stream, "use of r13 and write back");
5861 break;
5862
ef1576a1
AV		 5863 case UNPRED_Q_REGS_EQUAL:
5864 func (stream,
5865 "same vector register used for destination and other operand");
5866 break;
5867
5868 case UNPRED_OS:
5869 func (stream, "use of offset scaled");
5870 break;
5871
bf0b396d
AV		 5872 case UNPRED_GP_REGS_EQUAL:
5873 func (stream, "same general-purpose register used for both operands");
5874 break;
5875
c507f10b
AV		 5876 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
5877 func (stream, "use of identical q registers and size = 1");
5878 break;
5879
5880 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
5881 func (stream, "use of identical q registers and size = 1");
5882 break;
5883
73cd51e5
AV		 5884 case UNPRED_NONE:
5885 break;
5886 }
5887}
5888
04d54ace
AV		 5889/* Print register block operand for mve vld2/vld4/vst2/vld4. */
5890
5891static void
5892print_mve_register_blocks (struct disassemble_info *info,
5893 unsigned long given,
5894 enum mve_instructions matched_insn)
5895{
5896 void *stream = info->stream;
5897 fprintf_ftype func = info->fprintf_func;
5898
5899 unsigned long q_reg_start = arm_decode_field_multiple (given,
5900 13, 15,
5901 22, 22);
5902 switch (matched_insn)
5903 {
5904 case MVE_VLD2:
5905 case MVE_VST2:
5906 if (q_reg_start <= 6)
5907 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
5908 else
5909 func (stream, "<illegal reg q%ld>", q_reg_start);
5910 break;
5911
5912 case MVE_VLD4:
5913 case MVE_VST4:
5914 if (q_reg_start <= 4)
5915 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
5916 q_reg_start + 1, q_reg_start + 2,
5917 q_reg_start + 3);
5918 else
5919 func (stream, "<illegal reg q%ld>", q_reg_start);
5920 break;
5921
5922 default:
5923 break;
5924 }
5925}
5926
bf0b396d
AV		 5927static void
5928print_mve_rounding_mode (struct disassemble_info *info,
5929 unsigned long given,
5930 enum mve_instructions matched_insn)
5931{
5932 void *stream = info->stream;
5933 fprintf_ftype func = info->fprintf_func;
5934
5935 switch (matched_insn)
5936 {
5937 case MVE_VCVT_FROM_FP_TO_INT:
5938 {
5939 switch (arm_decode_field (given, 8, 9))
5940 {
5941 case 0:
5942 func (stream, "a");
5943 break;
5944
5945 case 1:
5946 func (stream, "n");
5947 break;
5948
5949 case 2:
5950 func (stream, "p");
5951 break;
5952
5953 case 3:
5954 func (stream, "m");
5955 break;
5956
5957 default:
5958 break;
5959 }
5960 }
5961 break;
5962
5963 case MVE_VRINT_FP:
5964 {
5965 switch (arm_decode_field (given, 7, 9))
5966 {
5967 case 0:
5968 func (stream, "n");
5969 break;
5970
5971 case 1:
5972 func (stream, "x");
5973 break;
5974
5975 case 2:
5976 func (stream, "a");
5977 break;
5978
5979 case 3:
5980 func (stream, "z");
5981 break;
5982
5983 case 5:
5984 func (stream, "m");
5985 break;
5986
5987 case 7:
5988 func (stream, "p");
5989
5990 case 4:
5991 case 6:
5992 default:
5993 break;
5994 }
5995 }
5996 break;
5997
5998 default:
5999 break;
6000 }
6001}
6002
6003static void
6004print_mve_vcvt_size (struct disassemble_info *info,
6005 unsigned long given,
6006 enum mve_instructions matched_insn)
6007{
6008 unsigned long mode = 0;
6009 void *stream = info->stream;
6010 fprintf_ftype func = info->fprintf_func;
6011
6012 switch (matched_insn)
6013 {
6014 case MVE_VCVT_FP_FIX_VEC:
6015 {
6016 mode = (((given & 0x200) >> 7)
6017 | ((given & 0x10000000) >> 27)
6018 | ((given & 0x100) >> 8));
6019
6020 switch (mode)
6021 {
6022 case 0:
6023 func (stream, "f16.s16");
6024 break;
6025
6026 case 1:
6027 func (stream, "s16.f16");
6028 break;
6029
6030 case 2:
6031 func (stream, "f16.u16");
6032 break;
6033
6034 case 3:
6035 func (stream, "u16.f16");
6036 break;
6037
6038 case 4:
6039 func (stream, "f32.s32");
6040 break;
6041
6042 case 5:
6043 func (stream, "s32.f32");
6044 break;
6045
6046 case 6:
6047 func (stream, "f32.u32");
6048 break;
6049
6050 case 7:
6051 func (stream, "u32.f32");
6052 break;
6053
6054 default:
6055 break;
6056 }
6057 break;
6058 }
6059 case MVE_VCVT_BETWEEN_FP_INT:
6060 {
6061 unsigned long size = arm_decode_field (given, 18, 19);
6062 unsigned long op = arm_decode_field (given, 7, 8);
6063
6064 if (size == 1)
6065 {
6066 switch (op)
6067 {
6068 case 0:
6069 func (stream, "f16.s16");
6070 break;
6071
6072 case 1:
6073 func (stream, "f16.u16");
6074 break;
6075
6076 case 2:
6077 func (stream, "s16.f16");
6078 break;
6079
6080 case 3:
6081 func (stream, "u16.f16");
6082 break;
6083
6084 default:
6085 break;
6086 }
6087 }
6088 else if (size == 2)
6089 {
6090 switch (op)
6091 {
6092 case 0:
6093 func (stream, "f32.s32");
6094 break;
6095
6096 case 1:
6097 func (stream, "f32.u32");
6098 break;
6099
6100 case 2:
6101 func (stream, "s32.f32");
6102 break;
6103
6104 case 3:
6105 func (stream, "u32.f32");
6106 break;
6107 }
6108 }
6109 }
6110 break;
6111
6112 case MVE_VCVT_FP_HALF_FP:
6113 {
6114 unsigned long op = arm_decode_field (given, 28, 28);
6115 if (op == 0)
6116 func (stream, "f16.f32");
6117 else if (op == 1)
6118 func (stream, "f32.f16");
6119 }
6120 break;
6121
6122 case MVE_VCVT_FROM_FP_TO_INT:
6123 {
6124 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6125
6126 switch (size)
6127 {
6128 case 2:
6129 func (stream, "s16.f16");
6130 break;
6131
6132 case 3:
6133 func (stream, "u16.f16");
6134 break;
6135
6136 case 4:
6137 func (stream, "s32.f32");
6138 break;
6139
6140 case 5:
6141 func (stream, "u32.f32");
6142 break;
6143
6144 default:
6145 break;
6146 }
6147 }
6148 break;
6149
6150 default:
6151 break;
6152 }
6153}
6154
143275ea
AV		 6155static void
6156print_instruction_predicate (struct disassemble_info *info)
6157{
6158 void *stream = info->stream;
6159 fprintf_ftype func = info->fprintf_func;
6160
6161 if (vpt_block_state.next_pred_state == PRED_THEN)
6162 func (stream, "t");
6163 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6164 func (stream, "e");
6165}
6166
6167static void
6168print_mve_size (struct disassemble_info *info,
6169 unsigned long size,
6170 enum mve_instructions matched_insn)
6171{
6172 void *stream = info->stream;
6173 fprintf_ftype func = info->fprintf_func;
6174
6175 switch (matched_insn)
6176 {
d3b63143 6177 case MVE_VADDV:
143275ea
AV		 6178 case MVE_VCMP_VEC_T1:
6179 case MVE_VCMP_VEC_T2:
6180 case MVE_VCMP_VEC_T3:
6181 case MVE_VCMP_VEC_T4:
6182 case MVE_VCMP_VEC_T5:
6183 case MVE_VCMP_VEC_T6:
9743db03
AV		 6184 case MVE_VHADD_T1:
6185 case MVE_VHADD_T2:
6186 case MVE_VHSUB_T1:
6187 case MVE_VHSUB_T2:
04d54ace
AV		 6188 case MVE_VLD2:
6189 case MVE_VLD4:
ef1576a1
AV		 6190 case MVE_VLDRB_GATHER_T1:
6191 case MVE_VLDRH_GATHER_T2:
6192 case MVE_VLDRW_GATHER_T3:
6193 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 6194 case MVE_VLDRB_T1:
6195 case MVE_VLDRH_T2:
d3b63143 6196 case MVE_VMLAS:
143275ea
AV		 6197 case MVE_VPT_VEC_T1:
6198 case MVE_VPT_VEC_T2:
6199 case MVE_VPT_VEC_T3:
6200 case MVE_VPT_VEC_T4:
6201 case MVE_VPT_VEC_T5:
6202 case MVE_VPT_VEC_T6:
d3b63143
AV		 6203 case MVE_VQDMLADH:
6204 case MVE_VQRDMLADH:
6205 case MVE_VQDMLAH:
6206 case MVE_VQRDMLAH:
6207 case MVE_VQDMLASH:
6208 case MVE_VQRDMLASH:
6209 case MVE_VQDMLSDH:
6210 case MVE_VQRDMLSDH:
6211 case MVE_VQDMULH_T1:
6212 case MVE_VQRDMULH_T2:
6213 case MVE_VQDMULH_T3:
6214 case MVE_VQRDMULH_T4:
9743db03 6215 case MVE_VRHADD:
bf0b396d 6216 case MVE_VRINT_FP:
04d54ace
AV		 6217 case MVE_VST2:
6218 case MVE_VST4:
ef1576a1
AV		 6219 case MVE_VSTRB_SCATTER_T1:
6220 case MVE_VSTRH_SCATTER_T2:
6221 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 6222 case MVE_VSTRB_T1:
6223 case MVE_VSTRH_T2:
143275ea
AV		 6224 if (size <= 3)
6225 func (stream, "%s", mve_vec_sizename[size]);
6226 else
6227 func (stream, "<undef size>");
6228 break;
6229
6230 case MVE_VCMP_FP_T1:
6231 case MVE_VCMP_FP_T2:
9743db03
AV		 6232 case MVE_VFMA_FP_SCALAR:
6233 case MVE_VFMA_FP:
6234 case MVE_VFMS_FP:
6235 case MVE_VFMAS_FP_SCALAR:
143275ea
AV		 6236 case MVE_VPT_FP_T1:
6237 case MVE_VPT_FP_T2:
6238 if (size == 0)
6239 func (stream, "32");
6240 else if (size == 1)
6241 func (stream, "16");
6242 break;
6243
d3b63143
AV		 6244 case MVE_VMLADAV_T1:
6245 case MVE_VMLALDAV:
6246 case MVE_VMLSDAV_T1:
6247 case MVE_VMLSLDAV:
14925797
AV		 6248 case MVE_VMOVN:
6249 case MVE_VQDMULL_T1:
6250 case MVE_VQDMULL_T2:
6251 case MVE_VQMOVN:
6252 case MVE_VQMOVUN:
6253 if (size == 0)
6254 func (stream, "16");
6255 else if (size == 1)
6256 func (stream, "32");
6257 break;
6258
6259 case MVE_VMOVL:
6260 if (size == 1)
6261 func (stream, "8");
6262 else if (size == 2)
6263 func (stream, "16");
6264 break;
6265
9743db03
AV		 6266 case MVE_VDUP:
6267 switch (size)
6268 {
6269 case 0:
6270 func (stream, "32");
6271 break;
6272 case 1:
6273 func (stream, "16");
6274 break;
6275 case 2:
6276 func (stream, "8");
6277 break;
6278 default:
6279 break;
6280 }
6281 break;
6282
c507f10b
AV		 6283 case MVE_VMOV_GP_TO_VEC_LANE:
6284 case MVE_VMOV_VEC_LANE_TO_GP:
6285 switch (size)
6286 {
6287 case 0: case 4:
6288 func (stream, "32");
6289 break;
6290
6291 case 1: case 3:
6292 case 5: case 7:
6293 func (stream, "16");
6294 break;
6295
6296 case 8: case 9: case 10: case 11:
6297 case 12: case 13: case 14: case 15:
6298 func (stream, "8");
6299 break;
6300
6301 default:
6302 break;
6303 }
6304 break;
6305
6306 case MVE_VMOV_IMM_TO_VEC:
6307 switch (size)
6308 {
6309 case 0: case 4: case 8:
6310 case 12: case 24: case 26:
6311 func (stream, "i32");
6312 break;
6313 case 16: case 20:
6314 func (stream, "i16");
6315 break;
6316 case 28:
6317 func (stream, "i8");
6318 break;
6319 case 29:
6320 func (stream, "i64");
6321 break;
6322 case 30:
6323 func (stream, "f32");
6324 break;
6325 default:
6326 break;
6327 }
6328 break;
6329
14925797
AV		 6330 case MVE_VMULL_POLY:
6331 if (size == 0)
6332 func (stream, "p8");
6333 else if (size == 1)
6334 func (stream, "p16");
6335 break;
6336
c507f10b
AV		 6337 case MVE_VMVN_IMM:
6338 switch (size)
6339 {
6340 case 0: case 2: case 4:
6341 case 6: case 12: case 13:
6342 func (stream, "32");
6343 break;
6344
6345 case 8: case 10:
6346 func (stream, "16");
6347 break;
6348
6349 default:
6350 break;
6351 }
6352 break;
6353
6354 case MVE_VBIC_IMM:
6355 case MVE_VORR_IMM:
6356 switch (size)
6357 {
6358 case 1: case 3:
6359 case 5: case 7:
6360 func (stream, "32");
6361 break;
6362
6363 case 9: case 11:
6364 func (stream, "16");
6365 break;
6366
6367 default:
6368 break;
6369 }
6370 break;
6371
143275ea
AV		 6372 default:
6373 break;
6374 }
6375}
6376
6377static void
6378print_vec_condition (struct disassemble_info *info, long given,
6379 enum mve_instructions matched_insn)
6380{
6381 void *stream = info->stream;
6382 fprintf_ftype func = info->fprintf_func;
6383 long vec_cond = 0;
6384
6385 switch (matched_insn)
6386 {
6387 case MVE_VPT_FP_T1:
6388 case MVE_VCMP_FP_T1:
6389 vec_cond = (((given & 0x1000) >> 10)
6390 | ((given & 1) << 1)
6391 | ((given & 0x0080) >> 7));
6392 func (stream, "%s",vec_condnames[vec_cond]);
6393 break;
6394
6395 case MVE_VPT_FP_T2:
6396 case MVE_VCMP_FP_T2:
6397 vec_cond = (((given & 0x1000) >> 10)
6398 | ((given & 0x0020) >> 4)
6399 | ((given & 0x0080) >> 7));
6400 func (stream, "%s",vec_condnames[vec_cond]);
6401 break;
6402
6403 case MVE_VPT_VEC_T1:
6404 case MVE_VCMP_VEC_T1:
6405 vec_cond = (given & 0x0080) >> 7;
6406 func (stream, "%s",vec_condnames[vec_cond]);
6407 break;
6408
6409 case MVE_VPT_VEC_T2:
6410 case MVE_VCMP_VEC_T2:
6411 vec_cond = 2 | ((given & 0x0080) >> 7);
6412 func (stream, "%s",vec_condnames[vec_cond]);
6413 break;
6414
6415 case MVE_VPT_VEC_T3:
6416 case MVE_VCMP_VEC_T3:
6417 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6418 func (stream, "%s",vec_condnames[vec_cond]);
6419 break;
6420
6421 case MVE_VPT_VEC_T4:
6422 case MVE_VCMP_VEC_T4:
6423 vec_cond = (given & 0x0080) >> 7;
6424 func (stream, "%s",vec_condnames[vec_cond]);
6425 break;
6426
6427 case MVE_VPT_VEC_T5:
6428 case MVE_VCMP_VEC_T5:
6429 vec_cond = 2 | ((given & 0x0080) >> 7);
6430 func (stream, "%s",vec_condnames[vec_cond]);
6431 break;
6432
6433 case MVE_VPT_VEC_T6:
6434 case MVE_VCMP_VEC_T6:
6435 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
6436 func (stream, "%s",vec_condnames[vec_cond]);
6437 break;
6438
6439 case MVE_NONE:
6440 case MVE_VPST:
6441 default:
6442 break;
6443 }
6444}
6445
6446#define W_BIT 21
6447#define I_BIT 22
6448#define U_BIT 23
6449#define P_BIT 24
6450
6451#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
6452#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
6453#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
6454#define PRE_BIT_SET (given & (1 << P_BIT))
6455
6456
8f06b2d8
PB		 6457/* Print one coprocessor instruction on INFO->STREAM.
6458 Return TRUE if the instuction matched, FALSE if this is not a
6459 recognised coprocessor instruction. */
6460
6461static bfd_boolean
fe56b6ce
NC		 6462print_insn_coprocessor (bfd_vma pc,
6463 struct disassemble_info *info,
6464 long given,
8f06b2d8
PB		 6465 bfd_boolean thumb)
6466{
6b0dd094 6467 const struct sopcode32 *insn;
8f06b2d8
PB		 6468 void *stream = info->stream;
6469 fprintf_ftype func = info->fprintf_func;
6470 unsigned long mask;
2edcd244 6471 unsigned long value = 0;
c22aaad1 6472 int cond;
8afc7bea 6473 int cp_num;
823d2571
TG		 6474 struct arm_private_data *private_data = info->private_data;
6475 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 6476 arm_feature_set arm_ext_v8_1m_main =
6477 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 6478
5b616bef 6479 allowed_arches = private_data->features;
8f06b2d8
PB		 6480
6481 for (insn = coprocessor_opcodes; insn->assembler; insn++)
6482 {
ff4a8d2b
NC		 6483 unsigned long u_reg = 16;
6484 bfd_boolean is_unpredictable = FALSE;
05413229 6485 signed long value_in_comment = 0;
0313a2b8
NC		 6486 const char *c;
6487
823d2571 6488 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 6489 switch (insn->value)
6490 {
6491 case SENTINEL_IWMMXT_START:
6492 if (info->mach != bfd_mach_arm_XScale
6493 && info->mach != bfd_mach_arm_iWMMXt
6494 && info->mach != bfd_mach_arm_iWMMXt2)
6495 do
6496 insn++;
823d2571
TG		 6497 while ((! ARM_FEATURE_ZERO (insn->arch))
6498 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 6499 continue;
6500
6501 case SENTINEL_IWMMXT_END:
6502 continue;
6503
6504 case SENTINEL_GENERIC_START:
5b616bef 6505 allowed_arches = private_data->features;
05413229
NC		 6506 continue;
6507
6508 default:
6509 abort ();
6510 }
8f06b2d8
PB		 6511
6512 mask = insn->mask;
6513 value = insn->value;
8afc7bea
RL		 6514 cp_num = (given >> 8) & 0xf;
6515
8f06b2d8
PB		 6516 if (thumb)
6517 {
6518 /* The high 4 bits are 0xe for Arm conditional instructions, and
6519 0xe for arm unconditional instructions. The rest of the
6520 encoding is the same. */
6521 mask |= 0xf0000000;
6522 value |= 0xe0000000;
c22aaad1
PB		 6523 if (ifthen_state)
6524 cond = IFTHEN_COND;
6525 else
e2efe87d 6526 cond = COND_UNCOND;
8f06b2d8
PB		 6527 }
6528 else
6529 {
6530 /* Only match unconditional instuctions against unconditional
6531 patterns. */
6532 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 6533 {
6534 mask |= 0xf0000000;
e2efe87d 6535 cond = COND_UNCOND;
c22aaad1
PB		 6536 }
6537 else
6538 {
6539 cond = (given >> 28) & 0xf;
6540 if (cond == 0xe)
e2efe87d 6541 cond = COND_UNCOND;
c22aaad1 6542 }
8f06b2d8 6543 }
823d2571 6544
6b0dd094
AV		 6545 if ((insn->isa == T32 && !thumb)
6546 || (insn->isa == ARM && thumb))
6547 continue;
6548
0313a2b8
NC		 6549 if ((given & mask) != value)
6550 continue;
8f06b2d8 6551
823d2571 6552 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 6553 continue;
6554
8afc7bea
RL		 6555 if (insn->value == 0xfe000010 /* mcr2 */
6556 || insn->value == 0xfe100010 /* mrc2 */
6557 || insn->value == 0xfc100000 /* ldc2 */
6558 || insn->value == 0xfc000000) /* stc2 */
6559 {
b0c11777 6560 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 6561 is_unpredictable = TRUE;
f08d8ce3
AV		 6562
6563 /* Armv8.1-M Mainline FP & MVE instructions. */
6564 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
6565 && !ARM_CPU_IS_ANY (allowed_arches)
6566 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
6567 continue;
6568
8afc7bea
RL		 6569 }
6570 else if (insn->value == 0x0e000000 /* cdp */
6571 || insn->value == 0xfe000000 /* cdp2 */
6572 || insn->value == 0x0e000010 /* mcr */
6573 || insn->value == 0x0e100010 /* mrc */
6574 || insn->value == 0x0c100000 /* ldc */
6575 || insn->value == 0x0c000000) /* stc */
6576 {
6577 /* Floating-point instructions. */
b0c11777 6578 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 6579 continue;
32c36c3c
AV		 6580
6581 /* Armv8.1-M Mainline FP & MVE instructions. */
6582 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
6583 && !ARM_CPU_IS_ANY (allowed_arches)
6584 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
6585 continue;
8afc7bea 6586 }
aef6d006
AV		 6587 else if ((insn->value == 0xec100f80 /* vldr (system register) */
6588 || insn->value == 0xec000f80) /* vstr (system register) */
6589 && arm_decode_field (given, 24, 24) == 0
6590 && arm_decode_field (given, 21, 21) == 0)
6591 /* If the P and W bits are both 0 then these encodings match the MVE
6592 VLDR and VSTR instructions, these are in a different table, so we
6593 don't let it match here. */
6594 continue;
6595
0313a2b8
NC		 6596 for (c = insn->assembler; *c; c++)
6597 {
6598 if (*c == '%')
8f06b2d8 6599 {
32c36c3c
AV		 6600 const char mod = *++c;
6601 switch (mod)
8f06b2d8 6602 {
0313a2b8
NC		 6603 case '%':
6604 func (stream, "%%");
6605 break;
6606
6607 case 'A':
32c36c3c 6608 case 'K':
05413229 6609 {
79862e45 6610 int rn = (given >> 16) & 0xf;
b0c11777 6611 bfd_vma offset = given & 0xff;
0313a2b8 6612
32c36c3c
AV		 6613 if (mod == 'K')
6614 offset = given & 0x7f;
6615
05413229 6616 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 6617
79862e45
DJ		 6618 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
6619 {
6620 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 6621 if (cp_num == 9)
6622 /* vldr.16/vstr.16 will shift the address
6623 left by 1 bit only. */
6624 offset = offset * 2;
6625 else
6626 offset = offset * 4;
6627
79862e45
DJ		 6628 if (NEGATIVE_BIT_SET)
6629 offset = - offset;
6630 if (rn != 15)
6631 value_in_comment = offset;
6632 }
6633
c1e26897 6634 if (PRE_BIT_SET)
05413229
NC		 6635 {
6636 if (offset)
fe56b6ce 6637 func (stream, ", #%d]%s",
d908c8af 6638 (int) offset,
c1e26897 6639 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 6640 else if (NEGATIVE_BIT_SET)
6641 func (stream, ", #-0]");
05413229
NC		 6642 else
6643 func (stream, "]");
6644 }
6645 else
6646 {
0313a2b8 6647 func (stream, "]");
8f06b2d8 6648
c1e26897 6649 if (WRITEBACK_BIT_SET)
05413229
NC		 6650 {
6651 if (offset)
d908c8af 6652 func (stream, ", #%d", (int) offset);
26d97720
NS		 6653 else if (NEGATIVE_BIT_SET)
6654 func (stream, ", #-0");
05413229
NC		 6655 }
6656 else
fe56b6ce 6657 {
26d97720
NS		 6658 func (stream, ", {%s%d}",
6659 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 6660 (int) offset);
fe56b6ce
NC		 6661 value_in_comment = offset;
6662 }
05413229 6663 }
79862e45
DJ		 6664 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
6665 {
6666 func (stream, "\t; ");
6844b2c2
MGD		 6667 /* For unaligned PCs, apply off-by-alignment
6668 correction. */
43e65147 6669 info->print_address_func (offset + pc
6844b2c2
MGD		 6670 + info->bytes_per_chunk * 2
6671 - (pc & 3),
dffaa15c 6672 info);
79862e45 6673 }
05413229 6674 }
0313a2b8 6675 break;
8f06b2d8 6676
0313a2b8
NC		 6677 case 'B':
6678 {
6679 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
6680 int offset = (given >> 1) & 0x3f;
6681
6682 if (offset == 1)
6683 func (stream, "{d%d}", regno);
6684 else if (regno + offset > 32)
6685 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
6686 else
6687 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
6688 }
6689 break;
8f06b2d8 6690
efd6b359
AV		 6691 case 'C':
6692 {
6693 bfd_boolean single = ((given >> 8) & 1) == 0;
6694 char reg_prefix = single ? 's' : 'd';
6695 int Dreg = (given >> 22) & 0x1;
6696 int Vdreg = (given >> 12) & 0xf;
6697 int reg = single ? ((Vdreg << 1) | Dreg)
6698 : ((Dreg << 4) | Vdreg);
6699 int num = (given >> (single ? 0 : 1)) & 0x7f;
6700 int maxreg = single ? 31 : 15;
6701 int topreg = reg + num - 1;
6702
6703 if (!num)
6704 func (stream, "{VPR}");
6705 else if (num == 1)
6706 func (stream, "{%c%d, VPR}", reg_prefix, reg);
6707 else if (topreg > maxreg)
6708 func (stream, "{%c%d-<overflow reg d%d, VPR}",
6709 reg_prefix, reg, single ? topreg >> 1 : topreg);
6710 else
6711 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
6712 reg_prefix, topreg);
6713 }
6714 break;
6715
e2efe87d
MGD		 6716 case 'u':
6717 if (cond != COND_UNCOND)
6718 is_unpredictable = TRUE;
6719
6720 /* Fall through. */
0313a2b8 6721 case 'c':
b0c11777
RL		 6722 if (cond != COND_UNCOND && cp_num == 9)
6723 is_unpredictable = TRUE;
6724
0313a2b8
NC		 6725 func (stream, "%s", arm_conditional[cond]);
6726 break;
8f06b2d8 6727
0313a2b8
NC		 6728 case 'I':
6729 /* Print a Cirrus/DSP shift immediate. */
6730 /* Immediates are 7bit signed ints with bits 0..3 in
6731 bits 0..3 of opcode and bits 4..6 in bits 5..7
6732 of opcode. */
6733 {
6734 int imm;
8f06b2d8 6735
0313a2b8 6736 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 6737
0313a2b8
NC		 6738 /* Is ``imm'' a negative number? */
6739 if (imm & 0x40)
24b4cf66 6740 imm -= 0x80;
8f06b2d8 6741
0313a2b8
NC		 6742 func (stream, "%d", imm);
6743 }
6744
6745 break;
8f06b2d8 6746
32c36c3c
AV		 6747 case 'J':
6748 {
73cd51e5
AV		 6749 unsigned long regno
6750 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 6751
6752 switch (regno)
6753 {
6754 case 0x1:
6755 func (stream, "FPSCR");
6756 break;
6757 case 0x2:
6758 func (stream, "FPSCR_nzcvqc");
6759 break;
6760 case 0xc:
6761 func (stream, "VPR");
6762 break;
6763 case 0xd:
6764 func (stream, "P0");
6765 break;
6766 case 0xe:
6767 func (stream, "FPCXTNS");
6768 break;
6769 case 0xf:
6770 func (stream, "FPCXTS");
6771 break;
6772 default:
73cd51e5 6773 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 6774 break;
6775 }
6776 }
6777 break;
6778
0313a2b8
NC		 6779 case 'F':
6780 switch (given & 0x00408000)
6781 {
6782 case 0:
6783 func (stream, "4");
6784 break;
6785 case 0x8000:
6786 func (stream, "1");
6787 break;
6788 case 0x00400000:
6789 func (stream, "2");
8f06b2d8 6790 break;
0313a2b8
NC		 6791 default:
6792 func (stream, "3");
6793 }
6794 break;
8f06b2d8 6795
0313a2b8
NC		 6796 case 'P':
6797 switch (given & 0x00080080)
6798 {
6799 case 0:
6800 func (stream, "s");
6801 break;
6802 case 0x80:
6803 func (stream, "d");
6804 break;
6805 case 0x00080000:
6806 func (stream, "e");
6807 break;
6808 default:
6809 func (stream, _("<illegal precision>"));
8f06b2d8 6810 break;
0313a2b8
NC		 6811 }
6812 break;
8f06b2d8 6813
0313a2b8
NC		 6814 case 'Q':
6815 switch (given & 0x00408000)
6816 {
6817 case 0:
6818 func (stream, "s");
8f06b2d8 6819 break;
0313a2b8
NC		 6820 case 0x8000:
6821 func (stream, "d");
8f06b2d8 6822 break;
0313a2b8
NC		 6823 case 0x00400000:
6824 func (stream, "e");
6825 break;
6826 default:
6827 func (stream, "p");
8f06b2d8 6828 break;
0313a2b8
NC		 6829 }
6830 break;
8f06b2d8 6831
0313a2b8
NC		 6832 case 'R':
6833 switch (given & 0x60)
6834 {
6835 case 0:
6836 break;
6837 case 0x20:
6838 func (stream, "p");
6839 break;
6840 case 0x40:
6841 func (stream, "m");
6842 break;
6843 default:
6844 func (stream, "z");
6845 break;
6846 }
6847 break;
16980d0b 6848
0313a2b8
NC		 6849 case '0': case '1': case '2': case '3': case '4':
6850 case '5': case '6': case '7': case '8': case '9':
6851 {
6852 int width;
8f06b2d8 6853
0313a2b8 6854 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 6855
0313a2b8
NC		 6856 switch (*c)
6857 {
ff4a8d2b
NC		 6858 case 'R':
6859 if (value == 15)
6860 is_unpredictable = TRUE;
6861 /* Fall through. */
0313a2b8 6862 case 'r':
ff4a8d2b
NC		 6863 if (c[1] == 'u')
6864 {
6865 /* Eat the 'u' character. */
6866 ++ c;
6867
6868 if (u_reg == value)
6869 is_unpredictable = TRUE;
6870 u_reg = value;
6871 }
0313a2b8
NC		 6872 func (stream, "%s", arm_regnames[value]);
6873 break;
c28eeff2
SN		 6874 case 'V':
6875 if (given & (1 << 6))
6876 goto Q;
6877 /* FALLTHROUGH */
0313a2b8
NC		 6878 case 'D':
6879 func (stream, "d%ld", value);
6880 break;
6881 case 'Q':
c28eeff2 6882 Q:
0313a2b8
NC		 6883 if (value & 1)
6884 func (stream, "<illegal reg q%ld.5>", value >> 1);
6885 else
6886 func (stream, "q%ld", value >> 1);
6887 break;
6888 case 'd':
6889 func (stream, "%ld", value);
05413229 6890 value_in_comment = value;
0313a2b8 6891 break;
6f1c2142
AM		 6892 case 'E':
6893 {
6894 /* Converts immediate 8 bit back to float value. */
6895 unsigned floatVal = (value & 0x80) << 24
6896 | (value & 0x3F) << 19
6897 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
6898
6899 /* Quarter float have a maximum value of 31.0.
6900 Get floating point value multiplied by 1e7.
6901 The maximum value stays in limit of a 32-bit int. */
6902 unsigned decVal =
6903 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
6904 (16 + (value & 0xF));
6905
6906 if (!(decVal % 1000000))
6907 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
6908 floatVal, value & 0x80 ? '-' : ' ',
6909 decVal / 10000000,
6910 decVal % 10000000 / 1000000);
6911 else if (!(decVal % 10000))
6912 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
6913 floatVal, value & 0x80 ? '-' : ' ',
6914 decVal / 10000000,
6915 decVal % 10000000 / 10000);
6916 else
6917 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
6918 floatVal, value & 0x80 ? '-' : ' ',
6919 decVal / 10000000, decVal % 10000000);
6920 break;
6921 }
0313a2b8
NC		 6922 case 'k':
6923 {
6924 int from = (given & (1 << 7)) ? 32 : 16;
6925 func (stream, "%ld", from - value);
6926 }
6927 break;
8f06b2d8 6928
0313a2b8
NC		 6929 case 'f':
6930 if (value > 7)
6931 func (stream, "#%s", arm_fp_const[value & 7]);
6932 else
6933 func (stream, "f%ld", value);
6934 break;
4146fd53 6935
0313a2b8
NC		 6936 case 'w':
6937 if (width == 2)
6938 func (stream, "%s", iwmmxt_wwnames[value]);
6939 else
6940 func (stream, "%s", iwmmxt_wwssnames[value]);
6941 break;
4146fd53 6942
0313a2b8
NC		 6943 case 'g':
6944 func (stream, "%s", iwmmxt_regnames[value]);
6945 break;
6946 case 'G':
6947 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 6948 break;
8f06b2d8 6949
0313a2b8 6950 case 'x':
d1aaab3c 6951 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 6952 break;
8f06b2d8 6953
33399f07
MGD		 6954 case 'c':
6955 switch (value)
6956 {
6957 case 0:
6958 func (stream, "eq");
6959 break;
6960
6961 case 1:
6962 func (stream, "vs");
6963 break;
6964
6965 case 2:
6966 func (stream, "ge");
6967 break;
6968
6969 case 3:
6970 func (stream, "gt");
6971 break;
6972
6973 default:
6974 func (stream, "??");
6975 break;
6976 }
6977 break;
6978
0313a2b8
NC		 6979 case '`':
6980 c++;
6981 if (value == 0)
6982 func (stream, "%c", *c);
6983 break;
6984 case '\'':
6985 c++;
6986 if (value == ((1ul << width) - 1))
6987 func (stream, "%c", *c);
6988 break;
6989 case '?':
fe56b6ce 6990 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 6991 c += 1 << width;
6992 break;
6993 default:
6994 abort ();
6995 }
dffaa15c
AM		 6996 }
6997 break;
0313a2b8 6998
dffaa15c
AM		 6999 case 'y':
7000 case 'z':
7001 {
7002 int single = *c++ == 'y';
7003 int regno;
8f06b2d8 7004
dffaa15c
AM		 7005 switch (*c)
7006 {
7007 case '4': /* Sm pair */
7008 case '0': /* Sm, Dm */
7009 regno = given & 0x0000000f;
7010 if (single)
7011 {
7012 regno <<= 1;
7013 regno += (given >> 5) & 1;
7014 }
7015 else
7016 regno += ((given >> 5) & 1) << 4;
7017 break;
8f06b2d8 7018
dffaa15c
AM		 7019 case '1': /* Sd, Dd */
7020 regno = (given >> 12) & 0x0000000f;
7021 if (single)
7022 {
7023 regno <<= 1;
7024 regno += (given >> 22) & 1;
7025 }
7026 else
7027 regno += ((given >> 22) & 1) << 4;
7028 break;
7df76b80 7029
dffaa15c
AM		 7030 case '2': /* Sn, Dn */
7031 regno = (given >> 16) & 0x0000000f;
7032 if (single)
7033 {
7034 regno <<= 1;
7035 regno += (given >> 7) & 1;
7036 }
7037 else
7038 regno += ((given >> 7) & 1) << 4;
7039 break;
a7f8487e 7040
dffaa15c
AM		 7041 case '3': /* List */
7042 func (stream, "{");
7043 regno = (given >> 12) & 0x0000000f;
7044 if (single)
7045 {
7046 regno <<= 1;
7047 regno += (given >> 22) & 1;
7048 }
7049 else
7050 regno += ((given >> 22) & 1) << 4;
7051 break;
a7f8487e 7052
dffaa15c
AM		 7053 default:
7054 abort ();
7055 }
0313a2b8 7056
dffaa15c 7057 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 7058
dffaa15c
AM		 7059 if (*c == '3')
7060 {
7061 int count = given & 0xff;
b34976b6 7062
dffaa15c
AM		 7063 if (single == 0)
7064 count >>= 1;
0313a2b8 7065
dffaa15c
AM		 7066 if (--count)
7067 {
7068 func (stream, "-%c%d",
7069 single ? 's' : 'd',
7070 regno + count);
7071 }
0313a2b8 7072
dffaa15c 7073 func (stream, "}");
0313a2b8 7074 }
dffaa15c
AM		 7075 else if (*c == '4')
7076 func (stream, ", %c%d", single ? 's' : 'd',
7077 regno + 1);
7078 }
7079 break;
b34976b6 7080
dffaa15c
AM		 7081 case 'L':
7082 switch (given & 0x00400100)
0313a2b8 7083 {
dffaa15c
AM		 7084 case 0x00000000: func (stream, "b"); break;
7085 case 0x00400000: func (stream, "h"); break;
7086 case 0x00000100: func (stream, "w"); break;
7087 case 0x00400100: func (stream, "d"); break;
7088 default:
7089 break;
0313a2b8 7090 }
dffaa15c 7091 break;
2d447fca 7092
dffaa15c
AM		 7093 case 'Z':
7094 {
7095 /* given (20, 23) | given (0, 3) */
7096 value = ((given >> 16) & 0xf0) | (given & 0xf);
7097 func (stream, "%d", (int) value);
7098 }
7099 break;
0313a2b8 7100
dffaa15c
AM		 7101 case 'l':
7102 /* This is like the 'A' operator, except that if
7103 the width field "M" is zero, then the offset is
7104 *not* multiplied by four. */
7105 {
7106 int offset = given & 0xff;
7107 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 7108
dffaa15c 7109 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 7110
dffaa15c
AM		 7111 if (multiplier > 1)
7112 {
7113 value_in_comment = offset * multiplier;
7114 if (NEGATIVE_BIT_SET)
7115 value_in_comment = - value_in_comment;
7116 }
0313a2b8 7117
dffaa15c
AM		 7118 if (offset)
7119 {
7120 if (PRE_BIT_SET)
7121 func (stream, ", #%s%d]%s",
7122 NEGATIVE_BIT_SET ? "-" : "",
7123 offset * multiplier,
7124 WRITEBACK_BIT_SET ? "!" : "");
7125 else
7126 func (stream, "], #%s%d",
7127 NEGATIVE_BIT_SET ? "-" : "",
7128 offset * multiplier);
7129 }
7130 else
7131 func (stream, "]");
7132 }
7133 break;
2d447fca 7134
dffaa15c
AM		 7135 case 'r':
7136 {
7137 int imm4 = (given >> 4) & 0xf;
7138 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
7139 int ubit = ! NEGATIVE_BIT_SET;
7140 const char *rm = arm_regnames [given & 0xf];
7141 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 7142
dffaa15c
AM		 7143 switch (puw_bits)
7144 {
7145 case 1:
7146 case 3:
7147 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
7148 if (imm4)
7149 func (stream, ", lsl #%d", imm4);
7150 break;
0313a2b8 7151
dffaa15c
AM		 7152 case 4:
7153 case 5:
7154 case 6:
7155 case 7:
7156 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
7157 if (imm4 > 0)
7158 func (stream, ", lsl #%d", imm4);
7159 func (stream, "]");
7160 if (puw_bits == 5 || puw_bits == 7)
7161 func (stream, "!");
7162 break;
2d447fca 7163
dffaa15c
AM		 7164 default:
7165 func (stream, "INVALID");
7166 }
7167 }
7168 break;
0313a2b8 7169
dffaa15c
AM		 7170 case 'i':
7171 {
7172 long imm5;
7173 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
7174 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 7175 }
dffaa15c
AM		 7176 break;
7177
7178 default:
7179 abort ();
252b5132 7180 }
252b5132 7181 }
0313a2b8
NC		 7182 else
7183 func (stream, "%c", *c);
252b5132 7184 }
05413229
NC		 7185
7186 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 7187 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 7188
ff4a8d2b
NC		 7189 if (is_unpredictable)
7190 func (stream, UNPREDICTABLE_INSTRUCTION);
7191
0313a2b8 7192 return TRUE;
252b5132 7193 }
8f06b2d8 7194 return FALSE;
252b5132
RH		 7195}
7196
05413229
NC		 7197/* Decodes and prints ARM addressing modes. Returns the offset
7198 used in the address, if any, if it is worthwhile printing the
7199 offset as a hexadecimal value in a comment at the end of the
7200 line of disassembly. */
7201
7202static signed long
62b3e311
PB		 7203print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
7204{
7205 void *stream = info->stream;
7206 fprintf_ftype func = info->fprintf_func;
f8b960bc 7207 bfd_vma offset = 0;
62b3e311
PB		 7208
7209 if (((given & 0x000f0000) == 0x000f0000)
7210 && ((given & 0x02000000) == 0))
7211 {
05413229 7212 offset = given & 0xfff;
62b3e311
PB		 7213
7214 func (stream, "[pc");
7215
c1e26897 7216 if (PRE_BIT_SET)
62b3e311 7217 {
26d97720
NS		 7218 /* Pre-indexed. Elide offset of positive zero when
7219 non-writeback. */
7220 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 7221 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 7222
7223 if (NEGATIVE_BIT_SET)
7224 offset = -offset;
62b3e311
PB		 7225
7226 offset += pc + 8;
7227
7228 /* Cope with the possibility of write-back
7229 being used. Probably a very dangerous thing
7230 for the programmer to do, but who are we to
7231 argue ? */
26d97720 7232 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 7233 }
c1e26897 7234 else /* Post indexed. */
62b3e311 7235 {
d908c8af 7236 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 7237
c1e26897 7238 /* Ie ignore the offset. */
62b3e311
PB		 7239 offset = pc + 8;
7240 }
7241
7242 func (stream, "\t; ");
7243 info->print_address_func (offset, info);
05413229 7244 offset = 0;
62b3e311
PB		 7245 }
7246 else
7247 {
7248 func (stream, "[%s",
7249 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 7250
7251 if (PRE_BIT_SET)
62b3e311
PB		 7252 {
7253 if ((given & 0x02000000) == 0)
7254 {
26d97720 7255 /* Elide offset of positive zero when non-writeback. */
05413229 7256 offset = given & 0xfff;
26d97720 7257 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 7258 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7259 }
7260 else
7261 {
26d97720 7262 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7263 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7264 }
7265
7266 func (stream, "]%s",
c1e26897 7267 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 7268 }
7269 else
7270 {
7271 if ((given & 0x02000000) == 0)
7272 {
26d97720 7273 /* Always show offset. */
05413229 7274 offset = given & 0xfff;
26d97720 7275 func (stream, "], #%s%d",
d908c8af 7276 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7277 }
7278 else
7279 {
7280 func (stream, "], %s",
c1e26897 7281 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7282 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7283 }
7284 }
84919466
MR		 7285 if (NEGATIVE_BIT_SET)
7286 offset = -offset;
62b3e311 7287 }
05413229
NC		 7288
7289 return (signed long) offset;
62b3e311
PB		 7290}
7291
16980d0b
JB		 7292/* Print one neon instruction on INFO->STREAM.
7293 Return TRUE if the instuction matched, FALSE if this is not a
7294 recognised neon instruction. */
7295
7296static bfd_boolean
7297print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
7298{
7299 const struct opcode32 *insn;
7300 void *stream = info->stream;
7301 fprintf_ftype func = info->fprintf_func;
7302
7303 if (thumb)
7304 {
7305 if ((given & 0xef000000) == 0xef000000)
7306 {
0313a2b8 7307 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 7308 unsigned long bit28 = given & (1 << 28);
7309
7310 given &= 0x00ffffff;
7311 if (bit28)
7312 given |= 0xf3000000;
7313 else
7314 given |= 0xf2000000;
7315 }
7316 else if ((given & 0xff000000) == 0xf9000000)
7317 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 7318 /* vdup is also a valid neon instruction. */
7319 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 7320 return FALSE;
7321 }
43e65147 7322
16980d0b
JB		 7323 for (insn = neon_opcodes; insn->assembler; insn++)
7324 {
7325 if ((given & insn->mask) == insn->value)
7326 {
05413229 7327 signed long value_in_comment = 0;
e2efe87d 7328 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 7329 const char *c;
7330
7331 for (c = insn->assembler; *c; c++)
7332 {
7333 if (*c == '%')
7334 {
7335 switch (*++c)
7336 {
7337 case '%':
7338 func (stream, "%%");
7339 break;
7340
e2efe87d
MGD		 7341 case 'u':
7342 if (thumb && ifthen_state)
7343 is_unpredictable = TRUE;
7344
7345 /* Fall through. */
c22aaad1
PB		 7346 case 'c':
7347 if (thumb && ifthen_state)
7348 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7349 break;
7350
16980d0b
JB		 7351 case 'A':
7352 {
43e65147 7353 static const unsigned char enc[16] =
16980d0b
JB		 7354 {
7355 0x4, 0x14, /* st4 0,1 */
7356 0x4, /* st1 2 */
7357 0x4, /* st2 3 */
7358 0x3, /* st3 4 */
7359 0x13, /* st3 5 */
7360 0x3, /* st1 6 */
7361 0x1, /* st1 7 */
7362 0x2, /* st2 8 */
7363 0x12, /* st2 9 */
7364 0x2, /* st1 10 */
7365 0, 0, 0, 0, 0
7366 };
7367 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7368 int rn = ((given >> 16) & 0xf);
7369 int rm = ((given >> 0) & 0xf);
7370 int align = ((given >> 4) & 0x3);
7371 int type = ((given >> 8) & 0xf);
7372 int n = enc[type] & 0xf;
7373 int stride = (enc[type] >> 4) + 1;
7374 int ix;
43e65147 7375
16980d0b
JB		 7376 func (stream, "{");
7377 if (stride > 1)
7378 for (ix = 0; ix != n; ix++)
7379 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
7380 else if (n == 1)
7381 func (stream, "d%d", rd);
7382 else
7383 func (stream, "d%d-d%d", rd, rd + n - 1);
7384 func (stream, "}, [%s", arm_regnames[rn]);
7385 if (align)
8e560766 7386 func (stream, " :%d", 32 << align);
16980d0b
JB		 7387 func (stream, "]");
7388 if (rm == 0xd)
7389 func (stream, "!");
7390 else if (rm != 0xf)
7391 func (stream, ", %s", arm_regnames[rm]);
7392 }
7393 break;
43e65147 7394
16980d0b
JB		 7395 case 'B':
7396 {
7397 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7398 int rn = ((given >> 16) & 0xf);
7399 int rm = ((given >> 0) & 0xf);
7400 int idx_align = ((given >> 4) & 0xf);
7401 int align = 0;
7402 int size = ((given >> 10) & 0x3);
7403 int idx = idx_align >> (size + 1);
7404 int length = ((given >> 8) & 3) + 1;
7405 int stride = 1;
7406 int i;
7407
7408 if (length > 1 && size > 0)
7409 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 7410
16980d0b
JB		 7411 switch (length)
7412 {
7413 case 1:
7414 {
7415 int amask = (1 << size) - 1;
7416 if ((idx_align & (1 << size)) != 0)
7417 return FALSE;
7418 if (size > 0)
7419 {
7420 if ((idx_align & amask) == amask)
7421 align = 8 << size;
7422 else if ((idx_align & amask) != 0)
7423 return FALSE;
7424 }
7425 }
7426 break;
43e65147 7427
16980d0b
JB		 7428 case 2:
7429 if (size == 2 && (idx_align & 2) != 0)
7430 return FALSE;
7431 align = (idx_align & 1) ? 16 << size : 0;
7432 break;
43e65147 7433
16980d0b
JB		 7434 case 3:
7435 if ((size == 2 && (idx_align & 3) != 0)
7436 || (idx_align & 1) != 0)
7437 return FALSE;
7438 break;
43e65147 7439
16980d0b
JB		 7440 case 4:
7441 if (size == 2)
7442 {
7443 if ((idx_align & 3) == 3)
7444 return FALSE;
7445 align = (idx_align & 3) * 64;
7446 }
7447 else
7448 align = (idx_align & 1) ? 32 << size : 0;
7449 break;
43e65147 7450
16980d0b
JB		 7451 default:
7452 abort ();
7453 }
43e65147 7454
16980d0b
JB		 7455 func (stream, "{");
7456 for (i = 0; i < length; i++)
7457 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
7458 rd + i * stride, idx);
7459 func (stream, "}, [%s", arm_regnames[rn]);
7460 if (align)
8e560766 7461 func (stream, " :%d", align);
16980d0b
JB		 7462 func (stream, "]");
7463 if (rm == 0xd)
7464 func (stream, "!");
7465 else if (rm != 0xf)
7466 func (stream, ", %s", arm_regnames[rm]);
7467 }
7468 break;
43e65147 7469
16980d0b
JB		 7470 case 'C':
7471 {
7472 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7473 int rn = ((given >> 16) & 0xf);
7474 int rm = ((given >> 0) & 0xf);
7475 int align = ((given >> 4) & 0x1);
7476 int size = ((given >> 6) & 0x3);
7477 int type = ((given >> 8) & 0x3);
7478 int n = type + 1;
7479 int stride = ((given >> 5) & 0x1);
7480 int ix;
43e65147 7481
16980d0b
JB		 7482 if (stride && (n == 1))
7483 n++;
7484 else
7485 stride++;
43e65147 7486
16980d0b
JB		 7487 func (stream, "{");
7488 if (stride > 1)
7489 for (ix = 0; ix != n; ix++)
7490 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
7491 else if (n == 1)
7492 func (stream, "d%d[]", rd);
7493 else
7494 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
7495 func (stream, "}, [%s", arm_regnames[rn]);
7496 if (align)
7497 {
91d6fa6a 7498 align = (8 * (type + 1)) << size;
16980d0b
JB		 7499 if (type == 3)
7500 align = (size > 1) ? align >> 1 : align;
7501 if (type == 2 || (type == 0 && !size))
8e560766 7502 func (stream, " :<bad align %d>", align);
16980d0b 7503 else
8e560766 7504 func (stream, " :%d", align);
16980d0b
JB		 7505 }
7506 func (stream, "]");
7507 if (rm == 0xd)
7508 func (stream, "!");
7509 else if (rm != 0xf)
7510 func (stream, ", %s", arm_regnames[rm]);
7511 }
7512 break;
43e65147 7513
16980d0b
JB		 7514 case 'D':
7515 {
7516 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
7517 int size = (given >> 20) & 3;
7518 int reg = raw_reg & ((4 << size) - 1);
7519 int ix = raw_reg >> size >> 2;
43e65147 7520
16980d0b
JB		 7521 func (stream, "d%d[%d]", reg, ix);
7522 }
7523 break;
43e65147 7524
16980d0b 7525 case 'E':
fe56b6ce 7526 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 7527 {
7528 int bits = 0;
7529 int cmode = (given >> 8) & 0xf;
7530 int op = (given >> 5) & 0x1;
7531 unsigned long value = 0, hival = 0;
7532 unsigned shift;
7533 int size = 0;
0dbde4cf 7534 int isfloat = 0;
43e65147 7535
16980d0b
JB		 7536 bits |= ((given >> 24) & 1) << 7;
7537 bits |= ((given >> 16) & 7) << 4;
7538 bits |= ((given >> 0) & 15) << 0;
43e65147 7539
16980d0b
JB		 7540 if (cmode < 8)
7541 {
7542 shift = (cmode >> 1) & 3;
fe56b6ce 7543 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7544 size = 32;
7545 }
7546 else if (cmode < 12)
7547 {
7548 shift = (cmode >> 1) & 1;
fe56b6ce 7549 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7550 size = 16;
7551 }
7552 else if (cmode < 14)
7553 {
7554 shift = (cmode & 1) + 1;
fe56b6ce 7555 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7556 value |= (1ul << (8 * shift)) - 1;
7557 size = 32;
7558 }
7559 else if (cmode == 14)
7560 {
7561 if (op)
7562 {
fe56b6ce 7563 /* Bit replication into bytes. */
16980d0b
JB		 7564 int ix;
7565 unsigned long mask;
43e65147 7566
16980d0b
JB		 7567 value = 0;
7568 hival = 0;
7569 for (ix = 7; ix >= 0; ix--)
7570 {
7571 mask = ((bits >> ix) & 1) ? 0xff : 0;
7572 if (ix <= 3)
7573 value = (value << 8) | mask;
7574 else
7575 hival = (hival << 8) | mask;
7576 }
7577 size = 64;
7578 }
7579 else
7580 {
fe56b6ce
NC		 7581 /* Byte replication. */
7582 value = (unsigned long) bits;
16980d0b
JB		 7583 size = 8;
7584 }
7585 }
7586 else if (!op)
7587 {
fe56b6ce 7588 /* Floating point encoding. */
16980d0b 7589 int tmp;
43e65147 7590
fe56b6ce
NC		 7591 value = (unsigned long) (bits & 0x7f) << 19;
7592 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 7593 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 7594 value |= (unsigned long) tmp << 24;
16980d0b 7595 size = 32;
0dbde4cf 7596 isfloat = 1;
16980d0b
JB		 7597 }
7598 else
7599 {
7600 func (stream, "<illegal constant %.8x:%x:%x>",
7601 bits, cmode, op);
7602 size = 32;
7603 break;
7604 }
7605 switch (size)
7606 {
7607 case 8:
7608 func (stream, "#%ld\t; 0x%.2lx", value, value);
7609 break;
43e65147 7610
16980d0b
JB		 7611 case 16:
7612 func (stream, "#%ld\t; 0x%.4lx", value, value);
7613 break;
7614
7615 case 32:
0dbde4cf
JB		 7616 if (isfloat)
7617 {
7618 unsigned char valbytes[4];
7619 double fvalue;
43e65147 7620
0dbde4cf
JB		 7621 /* Do this a byte at a time so we don't have to
7622 worry about the host's endianness. */
7623 valbytes[0] = value & 0xff;
7624 valbytes[1] = (value >> 8) & 0xff;
7625 valbytes[2] = (value >> 16) & 0xff;
7626 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 7627
7628 floatformat_to_double
c1e26897
NC		 7629 (& floatformat_ieee_single_little, valbytes,
7630 & fvalue);
43e65147 7631
0dbde4cf
JB		 7632 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7633 value);
7634 }
7635 else
4e9d3b81 7636 func (stream, "#%ld\t; 0x%.8lx",
43e65147 7637 (long) (((value & 0x80000000L) != 0)
9d82ec38 7638 ? value | ~0xffffffffL : value),
c1e26897 7639 value);
16980d0b
JB		 7640 break;
7641
7642 case 64:
7643 func (stream, "#0x%.8lx%.8lx", hival, value);
7644 break;
43e65147 7645
16980d0b
JB		 7646 default:
7647 abort ();
7648 }
7649 }
7650 break;
43e65147 7651
16980d0b
JB		 7652 case 'F':
7653 {
7654 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
7655 int num = (given >> 8) & 0x3;
43e65147 7656
16980d0b
JB		 7657 if (!num)
7658 func (stream, "{d%d}", regno);
7659 else if (num + regno >= 32)
7660 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
7661 else
7662 func (stream, "{d%d-d%d}", regno, regno + num);
7663 }
7664 break;
7e8e6784 7665
16980d0b
JB		 7666
7667 case '0': case '1': case '2': case '3': case '4':
7668 case '5': case '6': case '7': case '8': case '9':
7669 {
7670 int width;
7671 unsigned long value;
7672
7673 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 7674
16980d0b
JB		 7675 switch (*c)
7676 {
7677 case 'r':
7678 func (stream, "%s", arm_regnames[value]);
7679 break;
7680 case 'd':
7681 func (stream, "%ld", value);
05413229 7682 value_in_comment = value;
16980d0b
JB		 7683 break;
7684 case 'e':
7685 func (stream, "%ld", (1ul << width) - value);
7686 break;
43e65147 7687
16980d0b
JB		 7688 case 'S':
7689 case 'T':
7690 case 'U':
05413229 7691 /* Various width encodings. */
16980d0b
JB		 7692 {
7693 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
7694 int limit;
7695 unsigned low, high;
7696
7697 c++;
7698 if (*c >= '0' && *c <= '9')
7699 limit = *c - '0';
7700 else if (*c >= 'a' && *c <= 'f')
7701 limit = *c - 'a' + 10;
7702 else
7703 abort ();
7704 low = limit >> 2;
7705 high = limit & 3;
7706
7707 if (value < low || value > high)
7708 func (stream, "<illegal width %d>", base << value);
7709 else
7710 func (stream, "%d", base << value);
7711 }
7712 break;
7713 case 'R':
7714 if (given & (1 << 6))
7715 goto Q;
7716 /* FALLTHROUGH */
7717 case 'D':
7718 func (stream, "d%ld", value);
7719 break;
7720 case 'Q':
7721 Q:
7722 if (value & 1)
7723 func (stream, "<illegal reg q%ld.5>", value >> 1);
7724 else
7725 func (stream, "q%ld", value >> 1);
7726 break;
43e65147 7727
16980d0b
JB		 7728 case '`':
7729 c++;
7730 if (value == 0)
7731 func (stream, "%c", *c);
7732 break;
7733 case '\'':
7734 c++;
7735 if (value == ((1ul << width) - 1))
7736 func (stream, "%c", *c);
7737 break;
7738 case '?':
fe56b6ce 7739 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 7740 c += 1 << width;
7741 break;
7742 default:
7743 abort ();
7744 }
16980d0b 7745 }
dffaa15c
AM		 7746 break;
7747
7748 default:
7749 abort ();
16980d0b
JB		 7750 }
7751 }
7752 else
7753 func (stream, "%c", *c);
7754 }
05413229
NC		 7755
7756 if (value_in_comment > 32 || value_in_comment < -16)
7757 func (stream, "\t; 0x%lx", value_in_comment);
7758
e2efe87d
MGD		 7759 if (is_unpredictable)
7760 func (stream, UNPREDICTABLE_INSTRUCTION);
7761
16980d0b
JB		 7762 return TRUE;
7763 }
7764 }
7765 return FALSE;
7766}
7767
73cd51e5
AV		 7768/* Print one mve instruction on INFO->STREAM.
7769 Return TRUE if the instuction matched, FALSE if this is not a
7770 recognised mve instruction. */
7771
7772static bfd_boolean
7773print_insn_mve (struct disassemble_info *info, long given)
7774{
7775 const struct mopcode32 *insn;
7776 void *stream = info->stream;
7777 fprintf_ftype func = info->fprintf_func;
7778
7779 for (insn = mve_opcodes; insn->assembler; insn++)
7780 {
7781 if (((given & insn->mask) == insn->value)
7782 && !is_mve_encoding_conflict (given, insn->mve_op))
7783 {
7784 signed long value_in_comment = 0;
7785 bfd_boolean is_unpredictable = FALSE;
7786 bfd_boolean is_undefined = FALSE;
7787 const char *c;
7788 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
7789 enum mve_undefined undefined_cond = UNDEF_NONE;
7790
7791 /* Most vector mve instruction are illegal in a it block.
7792 There are a few exceptions; check for them. */
7793 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
7794 {
7795 is_unpredictable = TRUE;
7796 unpredictable_cond = UNPRED_IT_BLOCK;
7797 }
7798 else if (is_mve_unpredictable (given, insn->mve_op,
7799 &unpredictable_cond))
7800 is_unpredictable = TRUE;
7801
7802 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
7803 is_undefined = TRUE;
7804
7805 for (c = insn->assembler; *c; c++)
7806 {
7807 if (*c == '%')
7808 {
7809 switch (*++c)
7810 {
7811 case '%':
7812 func (stream, "%%");
7813 break;
7814
ef1576a1
AV		 7815 case 'a':
7816 /* Don't print anything for '+' as it is implied. */
7817 if (arm_decode_field (given, 23, 23) == 0)
7818 func (stream, "-");
7819 break;
7820
143275ea
AV		 7821 case 'c':
7822 if (ifthen_state)
7823 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7824 break;
7825
aef6d006
AV		 7826 case 'd':
7827 print_mve_vld_str_addr (info, given, insn->mve_op);
7828 break;
7829
143275ea
AV		 7830 case 'i':
7831 {
7832 long mve_mask = mve_extract_pred_mask (given);
7833 func (stream, "%s", mve_predicatenames[mve_mask]);
7834 }
7835 break;
7836
7837 case 'n':
7838 print_vec_condition (info, given, insn->mve_op);
7839 break;
7840
ef1576a1
AV		 7841 case 'o':
7842 if (arm_decode_field (given, 0, 0) == 1)
7843 {
7844 unsigned long size
7845 = arm_decode_field (given, 4, 4)
7846 | (arm_decode_field (given, 6, 6) << 1);
7847
7848 func (stream, ", uxtw #%lu", size);
7849 }
7850 break;
7851
bf0b396d
AV		 7852 case 'm':
7853 print_mve_rounding_mode (info, given, insn->mve_op);
7854 break;
7855
7856 case 's':
7857 print_mve_vcvt_size (info, given, insn->mve_op);
7858 break;
7859
aef6d006
AV		 7860 case 'u':
7861 {
c507f10b
AV		 7862 unsigned long op1 = arm_decode_field (given, 21, 22);
7863
7864 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
7865 {
7866 /* Check for signed. */
7867 if (arm_decode_field (given, 23, 23) == 0)
7868 {
7869 /* We don't print 's' for S32. */
7870 if ((arm_decode_field (given, 5, 6) == 0)
7871 && ((op1 == 0) || (op1 == 1)))
7872 ;
7873 else
7874 func (stream, "s");
7875 }
7876 else
7877 func (stream, "u");
7878 }
aef6d006 7879 else
c507f10b
AV		 7880 {
7881 if (arm_decode_field (given, 28, 28) == 0)
7882 func (stream, "s");
7883 else
7884 func (stream, "u");
7885 }
aef6d006 7886 }
ef1576a1 7887 break;
aef6d006 7888
143275ea
AV		 7889 case 'v':
7890 print_instruction_predicate (info);
7891 break;
7892
04d54ace
AV		 7893 case 'w':
7894 if (arm_decode_field (given, 21, 21) == 1)
7895 func (stream, "!");
7896 break;
7897
7898 case 'B':
7899 print_mve_register_blocks (info, given, insn->mve_op);
7900 break;
7901
c507f10b
AV		 7902 case 'E':
7903 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
7904
7905 print_simd_imm8 (info, given, 28, insn);
7906 break;
7907
7908 case 'N':
7909 print_mve_vmov_index (info, given);
7910 break;
7911
14925797
AV		 7912 case 'T':
7913 if (arm_decode_field (given, 12, 12) == 0)
7914 func (stream, "b");
7915 else
7916 func (stream, "t");
7917 break;
7918
d3b63143
AV		 7919 case 'X':
7920 if (arm_decode_field (given, 12, 12) == 1)
7921 func (stream, "x");
7922 break;
7923
143275ea
AV		 7924 case '0': case '1': case '2': case '3': case '4':
7925 case '5': case '6': case '7': case '8': case '9':
7926 {
7927 int width;
7928 unsigned long value;
7929
7930 c = arm_decode_bitfield (c, given, &value, &width);
7931
7932 switch (*c)
7933 {
7934 case 'Z':
7935 if (value == 13)
7936 is_unpredictable = TRUE;
7937 else if (value == 15)
7938 func (stream, "zr");
7939 else
7940 func (stream, "%s", arm_regnames[value]);
7941 break;
7942 case 's':
7943 print_mve_size (info,
7944 value,
7945 insn->mve_op);
7946 break;
d3b63143
AV		 7947 case 'A':
7948 if (value == 1)
7949 func (stream, "a");
7950 break;
ef1576a1
AV		 7951 case 'i':
7952 {
7953 unsigned long imm
7954 = arm_decode_field (given, 0, 6);
7955 unsigned long mod_imm = imm;
7956
7957 switch (insn->mve_op)
7958 {
7959 case MVE_VLDRW_GATHER_T5:
7960 case MVE_VSTRW_SCATTER_T5:
7961 mod_imm = mod_imm << 2;
7962 break;
7963 case MVE_VSTRD_SCATTER_T6:
7964 case MVE_VLDRD_GATHER_T6:
7965 mod_imm = mod_imm << 3;
7966 break;
7967
7968 default:
7969 break;
7970 }
7971
7972 func (stream, "%lu", mod_imm);
7973 }
7974 break;
bf0b396d
AV		 7975 case 'k':
7976 func (stream, "%lu", 64 - value);
7977 break;
9743db03
AV		 7978 case 'r':
7979 func (stream, "%s", arm_regnames[value]);
7980 break;
04d54ace
AV		 7981 case 'd':
7982 func (stream, "%ld", value);
7983 value_in_comment = value;
7984 break;
c507f10b
AV		 7985 case 'F':
7986 func (stream, "s%ld", value);
7987 break;
143275ea
AV		 7988 case 'Q':
7989 if (value & 0x8)
7990 func (stream, "<illegal reg q%ld.5>", value);
7991 else
7992 func (stream, "q%ld", value);
7993 break;
c507f10b
AV		 7994 case 'x':
7995 func (stream, "0x%08lx", value);
7996 break;
143275ea
AV		 7997 default:
7998 abort ();
7999 }
8000 break;
8001 default:
8002 abort ();
8003 }
73cd51e5
AV		 8004 }
8005 }
8006 else
8007 func (stream, "%c", *c);
8008 }
8009
8010 if (value_in_comment > 32 || value_in_comment < -16)
8011 func (stream, "\t; 0x%lx", value_in_comment);
8012
8013 if (is_unpredictable)
8014 print_mve_unpredictable (info, unpredictable_cond);
8015
8016 if (is_undefined)
8017 print_mve_undefined (info, undefined_cond);
8018
143275ea
AV		 8019 if ((vpt_block_state.in_vpt_block == FALSE)
8020 && !ifthen_state
8021 && (is_vpt_instruction (given) == TRUE))
8022 mark_inside_vpt_block (given);
8023 else if (vpt_block_state.in_vpt_block == TRUE)
8024 update_vpt_block_state ();
8025
73cd51e5
AV		 8026 return TRUE;
8027 }
8028 }
8029 return FALSE;
8030}
8031
8032
90ec0d68
MGD		 8033/* Return the name of a v7A special register. */
8034
43e65147 8035static const char *
90ec0d68
MGD		 8036banked_regname (unsigned reg)
8037{
8038 switch (reg)
8039 {
8040 case 15: return "CPSR";
43e65147 8041 case 32: return "R8_usr";
90ec0d68
MGD		 8042 case 33: return "R9_usr";
8043 case 34: return "R10_usr";
8044 case 35: return "R11_usr";
8045 case 36: return "R12_usr";
8046 case 37: return "SP_usr";
8047 case 38: return "LR_usr";
43e65147 8048 case 40: return "R8_fiq";
90ec0d68
MGD		 8049 case 41: return "R9_fiq";
8050 case 42: return "R10_fiq";
8051 case 43: return "R11_fiq";
8052 case 44: return "R12_fiq";
8053 case 45: return "SP_fiq";
8054 case 46: return "LR_fiq";
8055 case 48: return "LR_irq";
8056 case 49: return "SP_irq";
8057 case 50: return "LR_svc";
8058 case 51: return "SP_svc";
8059 case 52: return "LR_abt";
8060 case 53: return "SP_abt";
8061 case 54: return "LR_und";
8062 case 55: return "SP_und";
8063 case 60: return "LR_mon";
8064 case 61: return "SP_mon";
8065 case 62: return "ELR_hyp";
8066 case 63: return "SP_hyp";
8067 case 79: return "SPSR";
8068 case 110: return "SPSR_fiq";
8069 case 112: return "SPSR_irq";
8070 case 114: return "SPSR_svc";
8071 case 116: return "SPSR_abt";
8072 case 118: return "SPSR_und";
8073 case 124: return "SPSR_mon";
8074 case 126: return "SPSR_hyp";
8075 default: return NULL;
8076 }
8077}
8078
e797f7e0
MGD		 8079/* Return the name of the DMB/DSB option. */
8080static const char *
8081data_barrier_option (unsigned option)
8082{
8083 switch (option & 0xf)
8084 {
8085 case 0xf: return "sy";
8086 case 0xe: return "st";
8087 case 0xd: return "ld";
8088 case 0xb: return "ish";
8089 case 0xa: return "ishst";
8090 case 0x9: return "ishld";
8091 case 0x7: return "un";
8092 case 0x6: return "unst";
8093 case 0x5: return "nshld";
8094 case 0x3: return "osh";
8095 case 0x2: return "oshst";
8096 case 0x1: return "oshld";
8097 default: return NULL;
8098 }
8099}
8100
4a5329c6
ZW		 8101/* Print one ARM instruction from PC on INFO->STREAM. */
8102
8103static void
8104print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8105{
6b5d3a4d 8106 const struct opcode32 *insn;
6a51a8a8 8107 void *stream = info->stream;
6b5d3a4d 8108 fprintf_ftype func = info->fprintf_func;
b0e28b39 8109 struct arm_private_data *private_data = info->private_data;
252b5132 8110
16980d0b
JB		 8111 if (print_insn_coprocessor (pc, info, given, FALSE))
8112 return;
8113
8114 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 8115 return;
8116
252b5132
RH		 8117 for (insn = arm_opcodes; insn->assembler; insn++)
8118 {
0313a2b8
NC		 8119 if ((given & insn->mask) != insn->value)
8120 continue;
823d2571
TG		 8121
8122 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 8123 continue;
8124
8125 /* Special case: an instruction with all bits set in the condition field
8126 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8127 or by the catchall at the end of the table. */
8128 if ((given & 0xF0000000) != 0xF0000000
8129 || (insn->mask & 0xF0000000) == 0xF0000000
8130 || (insn->mask == 0 && insn->value == 0))
252b5132 8131 {
ff4a8d2b
NC		 8132 unsigned long u_reg = 16;
8133 unsigned long U_reg = 16;
ab8e2090 8134 bfd_boolean is_unpredictable = FALSE;
05413229 8135 signed long value_in_comment = 0;
6b5d3a4d 8136 const char *c;
b34976b6 8137
252b5132
RH		 8138 for (c = insn->assembler; *c; c++)
8139 {
8140 if (*c == '%')
8141 {
c1e26897
NC		 8142 bfd_boolean allow_unpredictable = FALSE;
8143
252b5132
RH		 8144 switch (*++c)
8145 {
8146 case '%':
8147 func (stream, "%%");
8148 break;
8149
8150 case 'a':
05413229 8151 value_in_comment = print_arm_address (pc, info, given);
62b3e311 8152 break;
252b5132 8153
62b3e311
PB		 8154 case 'P':
8155 /* Set P address bit and use normal address
8156 printing routine. */
c1e26897 8157 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 8158 break;
8159
c1e26897
NC		 8160 case 'S':
8161 allow_unpredictable = TRUE;
1a0670f3 8162 /* Fall through. */
252b5132
RH		 8163 case 's':
8164 if ((given & 0x004f0000) == 0x004f0000)
8165 {
58efb6c0 8166 /* PC relative with immediate offset. */
f8b960bc 8167 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 8168
aefd8a40
NC		 8169 if (PRE_BIT_SET)
8170 {
26d97720
NS		 8171 /* Elide positive zero offset. */
8172 if (offset || NEGATIVE_BIT_SET)
8173 func (stream, "[pc, #%s%d]\t; ",
d908c8af 8174 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 8175 else
26d97720
NS		 8176 func (stream, "[pc]\t; ");
8177 if (NEGATIVE_BIT_SET)
8178 offset = -offset;
aefd8a40
NC		 8179 info->print_address_func (offset + pc + 8, info);
8180 }
8181 else
8182 {
26d97720
NS		 8183 /* Always show the offset. */
8184 func (stream, "[pc], #%s%d",
d908c8af 8185 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 8186 if (! allow_unpredictable)
8187 is_unpredictable = TRUE;
aefd8a40 8188 }
252b5132
RH		 8189 }
8190 else
8191 {
fe56b6ce
NC		 8192 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
8193
b34976b6 8194 func (stream, "[%s",
252b5132 8195 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 8196
c1e26897 8197 if (PRE_BIT_SET)
252b5132 8198 {
c1e26897 8199 if (IMMEDIATE_BIT_SET)
252b5132 8200 {
26d97720
NS		 8201 /* Elide offset for non-writeback
8202 positive zero. */
8203 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
8204 || offset)
8205 func (stream, ", #%s%d",
8206 NEGATIVE_BIT_SET ? "-" : "", offset);
8207
8208 if (NEGATIVE_BIT_SET)
8209 offset = -offset;
945ee430 8210
fe56b6ce 8211 value_in_comment = offset;
252b5132 8212 }
945ee430 8213 else
ff4a8d2b
NC		 8214 {
8215 /* Register Offset or Register Pre-Indexed. */
8216 func (stream, ", %s%s",
8217 NEGATIVE_BIT_SET ? "-" : "",
8218 arm_regnames[given & 0xf]);
8219
8220 /* Writing back to the register that is the source/
8221 destination of the load/store is unpredictable. */
8222 if (! allow_unpredictable
8223 && WRITEBACK_BIT_SET
8224 && ((given & 0xf) == ((given >> 12) & 0xf)))
8225 is_unpredictable = TRUE;
8226 }
252b5132 8227
b34976b6 8228 func (stream, "]%s",
c1e26897 8229 WRITEBACK_BIT_SET ? "!" : "");
252b5132 8230 }
945ee430 8231 else
252b5132 8232 {
c1e26897 8233 if (IMMEDIATE_BIT_SET)
252b5132 8234 {
945ee430 8235 /* Immediate Post-indexed. */
aefd8a40 8236 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 8237 func (stream, "], #%s%d",
8238 NEGATIVE_BIT_SET ? "-" : "", offset);
8239 if (NEGATIVE_BIT_SET)
8240 offset = -offset;
fe56b6ce 8241 value_in_comment = offset;
252b5132 8242 }
945ee430 8243 else
ff4a8d2b
NC		 8244 {
8245 /* Register Post-indexed. */
8246 func (stream, "], %s%s",
8247 NEGATIVE_BIT_SET ? "-" : "",
8248 arm_regnames[given & 0xf]);
8249
8250 /* Writing back to the register that is the source/
8251 destination of the load/store is unpredictable. */
8252 if (! allow_unpredictable
8253 && (given & 0xf) == ((given >> 12) & 0xf))
8254 is_unpredictable = TRUE;
8255 }
c1e26897 8256
07a28fab
NC		 8257 if (! allow_unpredictable)
8258 {
8259 /* Writeback is automatically implied by post- addressing.
8260 Setting the W bit is unnecessary and ARM specify it as
8261 being unpredictable. */
8262 if (WRITEBACK_BIT_SET
8263 /* Specifying the PC register as the post-indexed
8264 registers is also unpredictable. */
ab8e2090
NC		 8265 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
8266 is_unpredictable = TRUE;
07a28fab 8267 }
252b5132
RH		 8268 }
8269 }
8270 break;
b34976b6 8271
252b5132 8272 case 'b':
6b5d3a4d 8273 {
f8b960bc 8274 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 8275 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 8276 }
252b5132
RH		 8277 break;
8278
8279 case 'c':
c22aaad1
PB		 8280 if (((given >> 28) & 0xf) != 0xe)
8281 func (stream, "%s",
8282 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 8283 break;
8284
8285 case 'm':
8286 {
8287 int started = 0;
8288 int reg;
8289
8290 func (stream, "{");
8291 for (reg = 0; reg < 16; reg++)
8292 if ((given & (1 << reg)) != 0)
8293 {
8294 if (started)
8295 func (stream, ", ");
8296 started = 1;
8297 func (stream, "%s", arm_regnames[reg]);
8298 }
8299 func (stream, "}");
ab8e2090
NC		 8300 if (! started)
8301 is_unpredictable = TRUE;
252b5132
RH		 8302 }
8303 break;
8304
37b37b2d 8305 case 'q':
78c66db8 8306 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 8307 break;
8308
252b5132
RH		 8309 case 'o':
8310 if ((given & 0x02000000) != 0)
8311 {
a415b1cd
JB		 8312 unsigned int rotate = (given & 0xf00) >> 7;
8313 unsigned int immed = (given & 0xff);
8314 unsigned int a, i;
8315
8316 a = (((immed << (32 - rotate))
8317 | (immed >> rotate)) & 0xffffffff);
8318 /* If there is another encoding with smaller rotate,
8319 the rotate should be specified directly. */
8320 for (i = 0; i < 32; i += 2)
8321 if ((a << i | a >> (32 - i)) <= 0xff)
8322 break;
8323
8324 if (i != rotate)
8325 func (stream, "#%d, %d", immed, rotate);
8326 else
8327 func (stream, "#%d", a);
8328 value_in_comment = a;
252b5132
RH		 8329 }
8330 else
78c66db8 8331 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 8332 break;
8333
8334 case 'p':
8335 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 8336 {
823d2571
TG		 8337 arm_feature_set arm_ext_v6 =
8338 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
8339
aefd8a40
NC		 8340 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8341 mechanism for setting PSR flag bits. They are
8342 obsolete in V6 onwards. */
823d2571
TG		 8343 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
8344 arm_ext_v6))
aefd8a40 8345 func (stream, "p");
4ab90a7a
AV		 8346 else
8347 is_unpredictable = TRUE;
aefd8a40 8348 }
252b5132
RH		 8349 break;
8350
8351 case 't':
8352 if ((given & 0x01200000) == 0x00200000)
8353 func (stream, "t");
8354 break;
8355
252b5132 8356 case 'A':
05413229
NC		 8357 {
8358 int offset = given & 0xff;
f02232aa 8359
05413229 8360 value_in_comment = offset * 4;
c1e26897 8361 if (NEGATIVE_BIT_SET)
05413229 8362 value_in_comment = - value_in_comment;
f02232aa 8363
05413229 8364 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 8365
c1e26897 8366 if (PRE_BIT_SET)
05413229
NC		 8367 {
8368 if (offset)
fe56b6ce 8369 func (stream, ", #%d]%s",
d908c8af 8370 (int) value_in_comment,
c1e26897 8371 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 8372 else
8373 func (stream, "]");
8374 }
8375 else
8376 {
8377 func (stream, "]");
f02232aa 8378
c1e26897 8379 if (WRITEBACK_BIT_SET)
05413229
NC		 8380 {
8381 if (offset)
d908c8af 8382 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 8383 }
8384 else
fe56b6ce 8385 {
d908c8af 8386 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 8387 value_in_comment = offset;
8388 }
05413229
NC		 8389 }
8390 }
252b5132
RH		 8391 break;
8392
077b8428
NC		 8393 case 'B':
8394 /* Print ARM V5 BLX(1) address: pc+25 bits. */
8395 {
8396 bfd_vma address;
8397 bfd_vma offset = 0;
b34976b6 8398
c1e26897 8399 if (! NEGATIVE_BIT_SET)
077b8428
NC		 8400 /* Is signed, hi bits should be ones. */
8401 offset = (-1) ^ 0x00ffffff;
8402
8403 /* Offset is (SignExtend(offset field)<<2). */
8404 offset += given & 0x00ffffff;
8405 offset <<= 2;
8406 address = offset + pc + 8;
b34976b6 8407
8f06b2d8
PB		 8408 if (given & 0x01000000)
8409 /* H bit allows addressing to 2-byte boundaries. */
8410 address += 2;
b1ee46c5 8411
8f06b2d8 8412 info->print_address_func (address, info);
b1ee46c5 8413 }
b1ee46c5
AH		 8414 break;
8415
252b5132 8416 case 'C':
90ec0d68
MGD		 8417 if ((given & 0x02000200) == 0x200)
8418 {
8419 const char * name;
8420 unsigned sysm = (given & 0x004f0000) >> 16;
8421
8422 sysm |= (given & 0x300) >> 4;
8423 name = banked_regname (sysm);
8424
8425 if (name != NULL)
8426 func (stream, "%s", name);
8427 else
d908c8af 8428 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 8429 }
8430 else
8431 {
43e65147 8432 func (stream, "%cPSR_",
90ec0d68
MGD		 8433 (given & 0x00400000) ? 'S' : 'C');
8434 if (given & 0x80000)
8435 func (stream, "f");
8436 if (given & 0x40000)
8437 func (stream, "s");
8438 if (given & 0x20000)
8439 func (stream, "x");
8440 if (given & 0x10000)
8441 func (stream, "c");
8442 }
252b5132
RH		 8443 break;
8444
62b3e311 8445 case 'U':
43e65147 8446 if ((given & 0xf0) == 0x60)
62b3e311 8447 {
52e7f43d
RE		 8448 switch (given & 0xf)
8449 {
8450 case 0xf: func (stream, "sy"); break;
8451 default:
8452 func (stream, "#%d", (int) given & 0xf);
8453 break;
8454 }
43e65147
L		 8455 }
8456 else
52e7f43d 8457 {
e797f7e0
MGD		 8458 const char * opt = data_barrier_option (given & 0xf);
8459 if (opt != NULL)
8460 func (stream, "%s", opt);
8461 else
52e7f43d 8462 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 8463 }
8464 break;
8465
b34976b6 8466 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 8467 case '5': case '6': case '7': case '8': case '9':
8468 {
16980d0b
JB		 8469 int width;
8470 unsigned long value;
252b5132 8471
16980d0b 8472 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 8473
252b5132
RH		 8474 switch (*c)
8475 {
ab8e2090
NC		 8476 case 'R':
8477 if (value == 15)
8478 is_unpredictable = TRUE;
8479 /* Fall through. */
16980d0b 8480 case 'r':
9eb6c0f1
MGD		 8481 case 'T':
8482 /* We want register + 1 when decoding T. */
8483 if (*c == 'T')
8484 ++value;
8485
ff4a8d2b
NC		 8486 if (c[1] == 'u')
8487 {
8488 /* Eat the 'u' character. */
8489 ++ c;
8490
8491 if (u_reg == value)
8492 is_unpredictable = TRUE;
8493 u_reg = value;
8494 }
8495 if (c[1] == 'U')
8496 {
8497 /* Eat the 'U' character. */
8498 ++ c;
8499
8500 if (U_reg == value)
8501 is_unpredictable = TRUE;
8502 U_reg = value;
8503 }
16980d0b
JB		 8504 func (stream, "%s", arm_regnames[value]);
8505 break;
8506 case 'd':
8507 func (stream, "%ld", value);
05413229 8508 value_in_comment = value;
16980d0b
JB		 8509 break;
8510 case 'b':
8511 func (stream, "%ld", value * 8);
05413229 8512 value_in_comment = value * 8;
16980d0b
JB		 8513 break;
8514 case 'W':
8515 func (stream, "%ld", value + 1);
05413229 8516 value_in_comment = value + 1;
16980d0b
JB		 8517 break;
8518 case 'x':
8519 func (stream, "0x%08lx", value);
8520
8521 /* Some SWI instructions have special
8522 meanings. */
8523 if ((given & 0x0fffffff) == 0x0FF00000)
8524 func (stream, "\t; IMB");
8525 else if ((given & 0x0fffffff) == 0x0FF00001)
8526 func (stream, "\t; IMBRange");
8527 break;
8528 case 'X':
8529 func (stream, "%01lx", value & 0xf);
05413229 8530 value_in_comment = value;
252b5132
RH		 8531 break;
8532 case '`':
8533 c++;
16980d0b 8534 if (value == 0)
252b5132
RH		 8535 func (stream, "%c", *c);
8536 break;
8537 case '\'':
8538 c++;
16980d0b 8539 if (value == ((1ul << width) - 1))
252b5132
RH		 8540 func (stream, "%c", *c);
8541 break;
8542 case '?':
fe56b6ce 8543 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 8544 c += 1 << width;
252b5132
RH		 8545 break;
8546 default:
8547 abort ();
8548 }
dffaa15c
AM		 8549 }
8550 break;
0dd132b6 8551
dffaa15c
AM		 8552 case 'e':
8553 {
8554 int imm;
0dd132b6 8555
dffaa15c
AM		 8556 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
8557 func (stream, "%d", imm);
8558 value_in_comment = imm;
8559 }
8560 break;
fe56b6ce 8561
dffaa15c
AM		 8562 case 'E':
8563 /* LSB and WIDTH fields of BFI or BFC. The machine-
8564 language instruction encodes LSB and MSB. */
8565 {
8566 long msb = (given & 0x001f0000) >> 16;
8567 long lsb = (given & 0x00000f80) >> 7;
8568 long w = msb - lsb + 1;
0a003adc 8569
dffaa15c
AM		 8570 if (w > 0)
8571 func (stream, "#%lu, #%lu", lsb, w);
8572 else
8573 func (stream, "(invalid: %lu:%lu)", lsb, msb);
8574 }
8575 break;
90ec0d68 8576
dffaa15c
AM		 8577 case 'R':
8578 /* Get the PSR/banked register name. */
8579 {
8580 const char * name;
8581 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 8582
dffaa15c
AM		 8583 sysm |= (given & 0x300) >> 4;
8584 name = banked_regname (sysm);
90ec0d68 8585
dffaa15c
AM		 8586 if (name != NULL)
8587 func (stream, "%s", name);
8588 else
8589 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
8590 }
8591 break;
fe56b6ce 8592
dffaa15c
AM		 8593 case 'V':
8594 /* 16-bit unsigned immediate from a MOVT or MOVW
8595 instruction, encoded in bits 0:11 and 15:19. */
8596 {
8597 long hi = (given & 0x000f0000) >> 4;
8598 long lo = (given & 0x00000fff);
8599 long imm16 = hi | lo;
0a003adc 8600
dffaa15c
AM		 8601 func (stream, "#%lu", imm16);
8602 value_in_comment = imm16;
252b5132 8603 }
dffaa15c
AM		 8604 break;
8605
8606 default:
8607 abort ();
252b5132
RH		 8608 }
8609 }
8610 else
8611 func (stream, "%c", *c);
8612 }
05413229
NC		 8613
8614 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8615 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 8616
8617 if (is_unpredictable)
8618 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 8619
4a5329c6 8620 return;
252b5132
RH		 8621 }
8622 }
0b347048
TC		 8623 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
8624 return;
252b5132
RH		 8625}
8626
4a5329c6 8627/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 8628
4a5329c6
ZW		 8629static void
8630print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8631{
6b5d3a4d 8632 const struct opcode16 *insn;
6a51a8a8
AM		 8633 void *stream = info->stream;
8634 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 8635
8636 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 8637 if ((given & insn->mask) == insn->value)
8638 {
05413229 8639 signed long value_in_comment = 0;
6b5d3a4d 8640 const char *c = insn->assembler;
05413229 8641
c19d1205
ZW		 8642 for (; *c; c++)
8643 {
8644 int domaskpc = 0;
8645 int domasklr = 0;
8646
8647 if (*c != '%')
8648 {
8649 func (stream, "%c", *c);
8650 continue;
8651 }
252b5132 8652
c19d1205
ZW		 8653 switch (*++c)
8654 {
8655 case '%':
8656 func (stream, "%%");
8657 break;
b34976b6 8658
c22aaad1
PB		 8659 case 'c':
8660 if (ifthen_state)
8661 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8662 break;
8663
8664 case 'C':
8665 if (ifthen_state)
8666 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8667 else
8668 func (stream, "s");
8669 break;
8670
8671 case 'I':
8672 {
8673 unsigned int tmp;
8674
8675 ifthen_next_state = given & 0xff;
8676 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
8677 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
8678 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
8679 }
8680 break;
8681
8682 case 'x':
8683 if (ifthen_next_state)
8684 func (stream, "\t; unpredictable branch in IT block\n");
8685 break;
8686
8687 case 'X':
8688 if (ifthen_state)
8689 func (stream, "\t; unpredictable <IT:%s>",
8690 arm_conditional[IFTHEN_COND]);
8691 break;
8692
c19d1205
ZW		 8693 case 'S':
8694 {
8695 long reg;
8696
8697 reg = (given >> 3) & 0x7;
8698 if (given & (1 << 6))
8699 reg += 8;
4f3c3dbb 8700
c19d1205
ZW		 8701 func (stream, "%s", arm_regnames[reg]);
8702 }
8703 break;
baf0cc5e 8704
c19d1205 8705 case 'D':
4f3c3dbb 8706 {
c19d1205
ZW		 8707 long reg;
8708
8709 reg = given & 0x7;
8710 if (given & (1 << 7))
8711 reg += 8;
8712
8713 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 8714 }
c19d1205
ZW		 8715 break;
8716
8717 case 'N':
8718 if (given & (1 << 8))
8719 domasklr = 1;
8720 /* Fall through. */
8721 case 'O':
8722 if (*c == 'O' && (given & (1 << 8)))
8723 domaskpc = 1;
8724 /* Fall through. */
8725 case 'M':
8726 {
8727 int started = 0;
8728 int reg;
8729
8730 func (stream, "{");
8731
8732 /* It would be nice if we could spot
8733 ranges, and generate the rS-rE format: */
8734 for (reg = 0; (reg < 8); reg++)
8735 if ((given & (1 << reg)) != 0)
8736 {
8737 if (started)
8738 func (stream, ", ");
8739 started = 1;
8740 func (stream, "%s", arm_regnames[reg]);
8741 }
8742
8743 if (domasklr)
8744 {
8745 if (started)
8746 func (stream, ", ");
8747 started = 1;
d908c8af 8748 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 8749 }
8750
8751 if (domaskpc)
8752 {
8753 if (started)
8754 func (stream, ", ");
d908c8af 8755 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 8756 }
8757
8758 func (stream, "}");
8759 }
8760 break;
8761
4547cb56
NC		 8762 case 'W':
8763 /* Print writeback indicator for a LDMIA. We are doing a
8764 writeback if the base register is not in the register
8765 mask. */
8766 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
8767 func (stream, "!");
dffaa15c 8768 break;
4547cb56 8769
c19d1205
ZW		 8770 case 'b':
8771 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
8772 {
8773 bfd_vma address = (pc + 4
8774 + ((given & 0x00f8) >> 2)
8775 + ((given & 0x0200) >> 3));
8776 info->print_address_func (address, info);
8777 }
8778 break;
8779
8780 case 's':
8781 /* Right shift immediate -- bits 6..10; 1-31 print
8782 as themselves, 0 prints as 32. */
8783 {
8784 long imm = (given & 0x07c0) >> 6;
8785 if (imm == 0)
8786 imm = 32;
0fd3a477 8787 func (stream, "#%ld", imm);
c19d1205
ZW		 8788 }
8789 break;
8790
8791 case '0': case '1': case '2': case '3': case '4':
8792 case '5': case '6': case '7': case '8': case '9':
8793 {
8794 int bitstart = *c++ - '0';
8795 int bitend = 0;
8796
8797 while (*c >= '0' && *c <= '9')
8798 bitstart = (bitstart * 10) + *c++ - '0';
8799
8800 switch (*c)
8801 {
8802 case '-':
8803 {
f8b960bc 8804 bfd_vma reg;
c19d1205
ZW		 8805
8806 c++;
8807 while (*c >= '0' && *c <= '9')
8808 bitend = (bitend * 10) + *c++ - '0';
8809 if (!bitend)
8810 abort ();
8811 reg = given >> bitstart;
8812 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 8813
c19d1205
ZW		 8814 switch (*c)
8815 {
8816 case 'r':
8817 func (stream, "%s", arm_regnames[reg]);
8818 break;
8819
8820 case 'd':
d908c8af 8821 func (stream, "%ld", (long) reg);
05413229 8822 value_in_comment = reg;
c19d1205
ZW		 8823 break;
8824
8825 case 'H':
d908c8af 8826 func (stream, "%ld", (long) (reg << 1));
05413229 8827 value_in_comment = reg << 1;
c19d1205
ZW		 8828 break;
8829
8830 case 'W':
d908c8af 8831 func (stream, "%ld", (long) (reg << 2));
05413229 8832 value_in_comment = reg << 2;
c19d1205
ZW		 8833 break;
8834
8835 case 'a':
8836 /* PC-relative address -- the bottom two
8837 bits of the address are dropped
8838 before the calculation. */
8839 info->print_address_func
8840 (((pc + 4) & ~3) + (reg << 2), info);
05413229 8841 value_in_comment = 0;
c19d1205
ZW		 8842 break;
8843
8844 case 'x':
d908c8af 8845 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 8846 break;
8847
c19d1205
ZW		 8848 case 'B':
8849 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 8850 info->print_address_func (reg * 2 + pc + 4, info);
05413229 8851 value_in_comment = 0;
c19d1205
ZW		 8852 break;
8853
8854 case 'c':
c22aaad1 8855 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 8856 break;
8857
8858 default:
8859 abort ();
8860 }
8861 }
8862 break;
8863
8864 case '\'':
8865 c++;
8866 if ((given & (1 << bitstart)) != 0)
8867 func (stream, "%c", *c);
8868 break;
8869
8870 case '?':
8871 ++c;
8872 if ((given & (1 << bitstart)) != 0)
8873 func (stream, "%c", *c++);
8874 else
8875 func (stream, "%c", *++c);
8876 break;
8877
8878 default:
8879 abort ();
8880 }
8881 }
8882 break;
8883
8884 default:
8885 abort ();
8886 }
8887 }
05413229
NC		 8888
8889 if (value_in_comment > 32 || value_in_comment < -16)
8890 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 8891 return;
c19d1205
ZW		 8892 }
8893
8894 /* No match. */
0b347048
TC		 8895 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
8896 return;
c19d1205
ZW		 8897}
8898
62b3e311 8899/* Return the name of an V7M special register. */
fe56b6ce 8900
62b3e311
PB		 8901static const char *
8902psr_name (int regno)
8903{
8904 switch (regno)
8905 {
1a336194
TP		 8906 case 0x0: return "APSR";
8907 case 0x1: return "IAPSR";
8908 case 0x2: return "EAPSR";
8909 case 0x3: return "PSR";
8910 case 0x5: return "IPSR";
8911 case 0x6: return "EPSR";
8912 case 0x7: return "IEPSR";
8913 case 0x8: return "MSP";
8914 case 0x9: return "PSP";
8915 case 0xa: return "MSPLIM";
8916 case 0xb: return "PSPLIM";
8917 case 0x10: return "PRIMASK";
8918 case 0x11: return "BASEPRI";
8919 case 0x12: return "BASEPRI_MAX";
8920 case 0x13: return "FAULTMASK";
8921 case 0x14: return "CONTROL";
16a1fa25
TP		 8922 case 0x88: return "MSP_NS";
8923 case 0x89: return "PSP_NS";
1a336194
TP		 8924 case 0x8a: return "MSPLIM_NS";
8925 case 0x8b: return "PSPLIM_NS";
8926 case 0x90: return "PRIMASK_NS";
8927 case 0x91: return "BASEPRI_NS";
8928 case 0x93: return "FAULTMASK_NS";
8929 case 0x94: return "CONTROL_NS";
8930 case 0x98: return "SP_NS";
62b3e311
PB		 8931 default: return "<unknown>";
8932 }
8933}
8934
4a5329c6
ZW		 8935/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
8936
8937static void
8938print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 8939{
6b5d3a4d 8940 const struct opcode32 *insn;
c19d1205
ZW		 8941 void *stream = info->stream;
8942 fprintf_ftype func = info->fprintf_func;
73cd51e5 8943 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 8944
16980d0b
JB		 8945 if (print_insn_coprocessor (pc, info, given, TRUE))
8946 return;
8947
73cd51e5
AV		 8948 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
8949 return;
8950
8951 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 8952 return;
8953
c19d1205
ZW		 8954 for (insn = thumb32_opcodes; insn->assembler; insn++)
8955 if ((given & insn->mask) == insn->value)
8956 {
4b5a202f 8957 bfd_boolean is_clrm = FALSE;
ff4a8d2b 8958 bfd_boolean is_unpredictable = FALSE;
05413229 8959 signed long value_in_comment = 0;
6b5d3a4d 8960 const char *c = insn->assembler;
05413229 8961
c19d1205
ZW		 8962 for (; *c; c++)
8963 {
8964 if (*c != '%')
8965 {
8966 func (stream, "%c", *c);
8967 continue;
8968 }
8969
8970 switch (*++c)
8971 {
8972 case '%':
8973 func (stream, "%%");
8974 break;
8975
c22aaad1
PB		 8976 case 'c':
8977 if (ifthen_state)
8978 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8979 break;
8980
8981 case 'x':
8982 if (ifthen_next_state)
8983 func (stream, "\t; unpredictable branch in IT block\n");
8984 break;
8985
8986 case 'X':
8987 if (ifthen_state)
8988 func (stream, "\t; unpredictable <IT:%s>",
8989 arm_conditional[IFTHEN_COND]);
8990 break;
8991
c19d1205
ZW		 8992 case 'I':
8993 {
8994 unsigned int imm12 = 0;
fe56b6ce 8995
c19d1205
ZW		 8996 imm12 |= (given & 0x000000ffu);
8997 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 8998 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 8999 func (stream, "#%u", imm12);
9000 value_in_comment = imm12;
c19d1205
ZW		 9001 }
9002 break;
9003
9004 case 'M':
9005 {
9006 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 9007
c19d1205
ZW		 9008 bits |= (given & 0x000000ffu);
9009 bits |= (given & 0x00007000u) >> 4;
9010 bits |= (given & 0x04000000u) >> 15;
9011 imm8 = (bits & 0x0ff);
9012 mod = (bits & 0xf00) >> 8;
9013 switch (mod)
9014 {
9015 case 0: imm = imm8; break;
c1e26897
NC		 9016 case 1: imm = ((imm8 << 16) | imm8); break;
9017 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
9018 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 9019 default:
9020 mod = (bits & 0xf80) >> 7;
9021 imm8 = (bits & 0x07f) | 0x80;
9022 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
9023 }
fe56b6ce
NC		 9024 func (stream, "#%u", imm);
9025 value_in_comment = imm;
c19d1205
ZW		 9026 }
9027 break;
43e65147 9028
c19d1205
ZW		 9029 case 'J':
9030 {
9031 unsigned int imm = 0;
fe56b6ce 9032
c19d1205
ZW		 9033 imm |= (given & 0x000000ffu);
9034 imm |= (given & 0x00007000u) >> 4;
9035 imm |= (given & 0x04000000u) >> 15;
9036 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 9037 func (stream, "#%u", imm);
9038 value_in_comment = imm;
c19d1205
ZW		 9039 }
9040 break;
9041
9042 case 'K':
9043 {
9044 unsigned int imm = 0;
fe56b6ce 9045
c19d1205
ZW		 9046 imm |= (given & 0x000f0000u) >> 16;
9047 imm |= (given & 0x00000ff0u) >> 0;
9048 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 9049 func (stream, "#%u", imm);
9050 value_in_comment = imm;
c19d1205
ZW		 9051 }
9052 break;
9053
74db7efb
NC		 9054 case 'H':
9055 {
9056 unsigned int imm = 0;
9057
9058 imm |= (given & 0x000f0000u) >> 4;
9059 imm |= (given & 0x00000fffu) >> 0;
9060 func (stream, "#%u", imm);
9061 value_in_comment = imm;
9062 }
9063 break;
9064
90ec0d68
MGD		 9065 case 'V':
9066 {
9067 unsigned int imm = 0;
9068
9069 imm |= (given & 0x00000fffu);
9070 imm |= (given & 0x000f0000u) >> 4;
9071 func (stream, "#%u", imm);
9072 value_in_comment = imm;
9073 }
9074 break;
9075
c19d1205
ZW		 9076 case 'S':
9077 {
9078 unsigned int reg = (given & 0x0000000fu);
9079 unsigned int stp = (given & 0x00000030u) >> 4;
9080 unsigned int imm = 0;
9081 imm |= (given & 0x000000c0u) >> 6;
9082 imm |= (given & 0x00007000u) >> 10;
9083
9084 func (stream, "%s", arm_regnames[reg]);
9085 switch (stp)
9086 {
9087 case 0:
9088 if (imm > 0)
9089 func (stream, ", lsl #%u", imm);
9090 break;
9091
9092 case 1:
9093 if (imm == 0)
9094 imm = 32;
9095 func (stream, ", lsr #%u", imm);
9096 break;
9097
9098 case 2:
9099 if (imm == 0)
9100 imm = 32;
9101 func (stream, ", asr #%u", imm);
9102 break;
9103
9104 case 3:
9105 if (imm == 0)
9106 func (stream, ", rrx");
9107 else
9108 func (stream, ", ror #%u", imm);
9109 }
9110 }
9111 break;
9112
9113 case 'a':
9114 {
9115 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 9116 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 9117 unsigned int op = (given & 0x00000f00) >> 8;
9118 unsigned int i12 = (given & 0x00000fff);
9119 unsigned int i8 = (given & 0x000000ff);
9120 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 9121 bfd_vma offset = 0;
c19d1205
ZW		 9122
9123 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 9124 if (U) /* 12-bit positive immediate offset. */
9125 {
9126 offset = i12;
9127 if (Rn != 15)
9128 value_in_comment = offset;
9129 }
9130 else if (Rn == 15) /* 12-bit negative immediate offset. */
9131 offset = - (int) i12;
9132 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 9133 {
9134 unsigned int Rm = (i8 & 0x0f);
9135 unsigned int sh = (i8 & 0x30) >> 4;
05413229 9136
c19d1205
ZW		 9137 func (stream, ", %s", arm_regnames[Rm]);
9138 if (sh)
9139 func (stream, ", lsl #%u", sh);
9140 func (stream, "]");
9141 break;
9142 }
9143 else switch (op)
9144 {
05413229 9145 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 9146 offset = i8;
9147 break;
9148
05413229 9149 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 9150 offset = -i8;
9151 break;
9152
05413229 9153 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 9154 offset = i8;
9155 writeback = TRUE;
9156 break;
9157
05413229 9158 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 9159 offset = -i8;
9160 writeback = TRUE;
9161 break;
9162
05413229 9163 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 9164 offset = i8;
9165 postind = TRUE;
9166 break;
9167
05413229 9168 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 9169 offset = -i8;
9170 postind = TRUE;
9171 break;
9172
9173 default:
9174 func (stream, ", <undefined>]");
9175 goto skip;
9176 }
9177
9178 if (postind)
d908c8af 9179 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 9180 else
9181 {
9182 if (offset)
d908c8af 9183 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 9184 func (stream, writeback ? "]!" : "]");
9185 }
9186
9187 if (Rn == 15)
9188 {
9189 func (stream, "\t; ");
9190 info->print_address_func (((pc + 4) & ~3) + offset, info);
9191 }
9192 }
9193 skip:
9194 break;
9195
9196 case 'A':
9197 {
c1e26897
NC		 9198 unsigned int U = ! NEGATIVE_BIT_SET;
9199 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 9200 unsigned int Rn = (given & 0x000f0000) >> 16;
9201 unsigned int off = (given & 0x000000ff);
9202
9203 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 9204
9205 if (PRE_BIT_SET)
c19d1205
ZW		 9206 {
9207 if (off || !U)
05413229
NC		 9208 {
9209 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 9210 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 9211 }
c19d1205
ZW		 9212 func (stream, "]");
9213 if (W)
9214 func (stream, "!");
9215 }
9216 else
9217 {
9218 func (stream, "], ");
9219 if (W)
05413229
NC		 9220 {
9221 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 9222 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 9223 }
c19d1205 9224 else
fe56b6ce
NC		 9225 {
9226 func (stream, "{%u}", off);
9227 value_in_comment = off;
9228 }
c19d1205
ZW		 9229 }
9230 }
9231 break;
9232
9233 case 'w':
9234 {
9235 unsigned int Sbit = (given & 0x01000000) >> 24;
9236 unsigned int type = (given & 0x00600000) >> 21;
05413229 9237
c19d1205
ZW		 9238 switch (type)
9239 {
9240 case 0: func (stream, Sbit ? "sb" : "b"); break;
9241 case 1: func (stream, Sbit ? "sh" : "h"); break;
9242 case 2:
9243 if (Sbit)
9244 func (stream, "??");
9245 break;
9246 case 3:
9247 func (stream, "??");
9248 break;
9249 }
9250 }
9251 break;
9252
4b5a202f
AV		 9253 case 'n':
9254 is_clrm = TRUE;
9255 /* Fall through. */
c19d1205
ZW		 9256 case 'm':
9257 {
9258 int started = 0;
9259 int reg;
9260
9261 func (stream, "{");
9262 for (reg = 0; reg < 16; reg++)
9263 if ((given & (1 << reg)) != 0)
9264 {
9265 if (started)
9266 func (stream, ", ");
9267 started = 1;
4b5a202f
AV		 9268 if (is_clrm && reg == 13)
9269 func (stream, "(invalid: %s)", arm_regnames[reg]);
9270 else if (is_clrm && reg == 15)
9271 func (stream, "%s", "APSR");
9272 else
9273 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 9274 }
9275 func (stream, "}");
9276 }
9277 break;
9278
9279 case 'E':
9280 {
9281 unsigned int msb = (given & 0x0000001f);
9282 unsigned int lsb = 0;
fe56b6ce 9283
c19d1205
ZW		 9284 lsb |= (given & 0x000000c0u) >> 6;
9285 lsb |= (given & 0x00007000u) >> 10;
9286 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
9287 }
9288 break;
9289
9290 case 'F':
9291 {
9292 unsigned int width = (given & 0x0000001f) + 1;
9293 unsigned int lsb = 0;
fe56b6ce 9294
c19d1205
ZW		 9295 lsb |= (given & 0x000000c0u) >> 6;
9296 lsb |= (given & 0x00007000u) >> 10;
9297 func (stream, "#%u, #%u", lsb, width);
9298 }
9299 break;
9300
e12437dc
AV		 9301 case 'G':
9302 {
9303 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
9304 func (stream, "%x", boff);
9305 }
9306 break;
9307
e5d6e09e
AV		 9308 case 'W':
9309 {
9310 unsigned int immA = (given & 0x001f0000u) >> 16;
9311 unsigned int immB = (given & 0x000007feu) >> 1;
9312 unsigned int immC = (given & 0x00000800u) >> 11;
9313 bfd_vma offset = 0;
9314
9315 offset |= immA << 12;
9316 offset |= immB << 2;
9317 offset |= immC << 1;
9318 /* Sign extend. */
9319 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
9320
9321 info->print_address_func (pc + 4 + offset, info);
9322 }
9323 break;
9324
1caf72a5
AV		 9325 case 'Y':
9326 {
9327 unsigned int immA = (given & 0x007f0000u) >> 16;
9328 unsigned int immB = (given & 0x000007feu) >> 1;
9329 unsigned int immC = (given & 0x00000800u) >> 11;
9330 bfd_vma offset = 0;
9331
9332 offset |= immA << 12;
9333 offset |= immB << 2;
9334 offset |= immC << 1;
9335 /* Sign extend. */
9336 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
9337
9338 info->print_address_func (pc + 4 + offset, info);
9339 }
9340 break;
9341
1889da70
AV		 9342 case 'Z':
9343 {
9344 unsigned int immA = (given & 0x00010000u) >> 16;
9345 unsigned int immB = (given & 0x000007feu) >> 1;
9346 unsigned int immC = (given & 0x00000800u) >> 11;
9347 bfd_vma offset = 0;
9348
9349 offset |= immA << 12;
9350 offset |= immB << 2;
9351 offset |= immC << 1;
9352 /* Sign extend. */
9353 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
9354
9355 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 9356
9357 unsigned int T = (given & 0x00020000u) >> 17;
9358 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
9359 unsigned int boffset = (T == 1) ? 4 : 2;
9360 func (stream, ", ");
9361 func (stream, "%x", endoffset + boffset);
1889da70
AV		 9362 }
9363 break;
9364
60f993ce
AV		 9365 case 'Q':
9366 {
9367 unsigned int immh = (given & 0x000007feu) >> 1;
9368 unsigned int imml = (given & 0x00000800u) >> 11;
9369 bfd_vma imm32 = 0;
9370
9371 imm32 |= immh << 2;
9372 imm32 |= imml << 1;
9373
9374 info->print_address_func (pc + 4 + imm32, info);
9375 }
9376 break;
9377
9378 case 'P':
9379 {
9380 unsigned int immh = (given & 0x000007feu) >> 1;
9381 unsigned int imml = (given & 0x00000800u) >> 11;
9382 bfd_vma imm32 = 0;
9383
9384 imm32 |= immh << 2;
9385 imm32 |= imml << 1;
9386
9387 info->print_address_func (pc + 4 - imm32, info);
9388 }
9389 break;
9390
c19d1205
ZW		 9391 case 'b':
9392 {
9393 unsigned int S = (given & 0x04000000u) >> 26;
9394 unsigned int J1 = (given & 0x00002000u) >> 13;
9395 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 9396 bfd_vma offset = 0;
c19d1205
ZW		 9397
9398 offset |= !S << 20;
9399 offset |= J2 << 19;
9400 offset |= J1 << 18;
9401 offset |= (given & 0x003f0000) >> 4;
9402 offset |= (given & 0x000007ff) << 1;
9403 offset -= (1 << 20);
9404
9405 info->print_address_func (pc + 4 + offset, info);
9406 }
9407 break;
9408
9409 case 'B':
9410 {
9411 unsigned int S = (given & 0x04000000u) >> 26;
9412 unsigned int I1 = (given & 0x00002000u) >> 13;
9413 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 9414 bfd_vma offset = 0;
c19d1205
ZW		 9415
9416 offset |= !S << 24;
9417 offset |= !(I1 ^ S) << 23;
9418 offset |= !(I2 ^ S) << 22;
9419 offset |= (given & 0x03ff0000u) >> 4;
9420 offset |= (given & 0x000007ffu) << 1;
9421 offset -= (1 << 24);
36b0c57d 9422 offset += pc + 4;
c19d1205 9423
36b0c57d
PB		 9424 /* BLX target addresses are always word aligned. */
9425 if ((given & 0x00001000u) == 0)
9426 offset &= ~2u;
9427
9428 info->print_address_func (offset, info);
c19d1205
ZW		 9429 }
9430 break;
9431
9432 case 's':
9433 {
9434 unsigned int shift = 0;
fe56b6ce 9435
c19d1205
ZW		 9436 shift |= (given & 0x000000c0u) >> 6;
9437 shift |= (given & 0x00007000u) >> 10;
c1e26897 9438 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 9439 func (stream, ", asr #%u", shift);
9440 else if (shift)
9441 func (stream, ", lsl #%u", shift);
9442 /* else print nothing - lsl #0 */
9443 }
9444 break;
9445
9446 case 'R':
9447 {
9448 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 9449
c19d1205
ZW		 9450 if (rot)
9451 func (stream, ", ror #%u", rot * 8);
9452 }
9453 break;
9454
62b3e311 9455 case 'U':
43e65147 9456 if ((given & 0xf0) == 0x60)
62b3e311 9457 {
52e7f43d
RE		 9458 switch (given & 0xf)
9459 {
9460 case 0xf: func (stream, "sy"); break;
9461 default:
9462 func (stream, "#%d", (int) given & 0xf);
9463 break;
9464 }
62b3e311 9465 }
43e65147 9466 else
52e7f43d 9467 {
e797f7e0
MGD		 9468 const char * opt = data_barrier_option (given & 0xf);
9469 if (opt != NULL)
9470 func (stream, "%s", opt);
9471 else
9472 func (stream, "#%d", (int) given & 0xf);
52e7f43d 9473 }
62b3e311
PB		 9474 break;
9475
9476 case 'C':
9477 if ((given & 0xff) == 0)
9478 {
9479 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
9480 if (given & 0x800)
9481 func (stream, "f");
9482 if (given & 0x400)
9483 func (stream, "s");
9484 if (given & 0x200)
9485 func (stream, "x");
9486 if (given & 0x100)
9487 func (stream, "c");
9488 }
90ec0d68
MGD		 9489 else if ((given & 0x20) == 0x20)
9490 {
9491 char const* name;
9492 unsigned sysm = (given & 0xf00) >> 8;
9493
9494 sysm |= (given & 0x30);
9495 sysm |= (given & 0x00100000) >> 14;
9496 name = banked_regname (sysm);
43e65147 9497
90ec0d68
MGD		 9498 if (name != NULL)
9499 func (stream, "%s", name);
9500 else
d908c8af 9501 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 9502 }
62b3e311
PB		 9503 else
9504 {
d908c8af 9505 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 9506 }
9507 break;
9508
9509 case 'D':
90ec0d68
MGD		 9510 if (((given & 0xff) == 0)
9511 || ((given & 0x20) == 0x20))
9512 {
9513 char const* name;
9514 unsigned sm = (given & 0xf0000) >> 16;
9515
9516 sm |= (given & 0x30);
9517 sm |= (given & 0x00100000) >> 14;
9518 name = banked_regname (sm);
9519
9520 if (name != NULL)
9521 func (stream, "%s", name);
9522 else
d908c8af 9523 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 9524 }
62b3e311 9525 else
d908c8af 9526 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 9527 break;
9528
c19d1205
ZW		 9529 case '0': case '1': case '2': case '3': case '4':
9530 case '5': case '6': case '7': case '8': case '9':
9531 {
16980d0b
JB		 9532 int width;
9533 unsigned long val;
c19d1205 9534
16980d0b 9535 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 9536
c19d1205
ZW		 9537 switch (*c)
9538 {
05413229
NC		 9539 case 'd':
9540 func (stream, "%lu", val);
9541 value_in_comment = val;
9542 break;
ff4a8d2b 9543
f0fba320
RL		 9544 case 'D':
9545 func (stream, "%lu", val + 1);
9546 value_in_comment = val + 1;
9547 break;
9548
05413229
NC		 9549 case 'W':
9550 func (stream, "%lu", val * 4);
9551 value_in_comment = val * 4;
9552 break;
ff4a8d2b 9553
f1c7f421
AV		 9554 case 'S':
9555 if (val == 13)
9556 is_unpredictable = TRUE;
9557 /* Fall through. */
ff4a8d2b
NC		 9558 case 'R':
9559 if (val == 15)
9560 is_unpredictable = TRUE;
9561 /* Fall through. */
9562 case 'r':
9563 func (stream, "%s", arm_regnames[val]);
9564 break;
c19d1205
ZW		 9565
9566 case 'c':
c22aaad1 9567 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 9568 break;
9569
9570 case '\'':
c19d1205 9571 c++;
16980d0b
JB		 9572 if (val == ((1ul << width) - 1))
9573 func (stream, "%c", *c);
c19d1205 9574 break;
43e65147 9575
c19d1205 9576 case '`':
c19d1205 9577 c++;
16980d0b
JB		 9578 if (val == 0)
9579 func (stream, "%c", *c);
c19d1205
ZW		 9580 break;
9581
9582 case '?':
fe56b6ce 9583 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 9584 c += 1 << width;
c19d1205 9585 break;
43e65147 9586
0bb027fd
RR		 9587 case 'x':
9588 func (stream, "0x%lx", val & 0xffffffffUL);
9589 break;
c19d1205
ZW		 9590
9591 default:
9592 abort ();
9593 }
9594 }
9595 break;
9596
32a94698
NC		 9597 case 'L':
9598 /* PR binutils/12534
9599 If we have a PC relative offset in an LDRD or STRD
9600 instructions then display the decoded address. */
9601 if (((given >> 16) & 0xf) == 0xf)
9602 {
9603 bfd_vma offset = (given & 0xff) * 4;
9604
9605 if ((given & (1 << 23)) == 0)
9606 offset = - offset;
9607 func (stream, "\t; ");
9608 info->print_address_func ((pc & ~3) + 4 + offset, info);
9609 }
9610 break;
9611
c19d1205
ZW		 9612 default:
9613 abort ();
9614 }
9615 }
05413229
NC		 9616
9617 if (value_in_comment > 32 || value_in_comment < -16)
9618 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 9619
9620 if (is_unpredictable)
9621 func (stream, UNPREDICTABLE_INSTRUCTION);
9622
4a5329c6 9623 return;
c19d1205 9624 }
252b5132 9625
58efb6c0 9626 /* No match. */
0b347048
TC		 9627 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9628 return;
252b5132
RH		 9629}
9630
e821645d
DJ		 9631/* Print data bytes on INFO->STREAM. */
9632
9633static void
fe56b6ce
NC		 9634print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
9635 struct disassemble_info *info,
e821645d
DJ		 9636 long given)
9637{
9638 switch (info->bytes_per_chunk)
9639 {
9640 case 1:
9641 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
9642 break;
9643 case 2:
9644 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
9645 break;
9646 case 4:
9647 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
9648 break;
9649 default:
9650 abort ();
9651 }
9652}
9653
22a398e1 9654/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 9655 being displayed in symbol relative addresses.
9656
9657 Also disallow private symbol, with __tagsym$$ prefix,
9658 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 9659
9660bfd_boolean
9661arm_symbol_is_valid (asymbol * sym,
9662 struct disassemble_info * info ATTRIBUTE_UNUSED)
9663{
9664 const char * name;
43e65147 9665
22a398e1
NC		 9666 if (sym == NULL)
9667 return FALSE;
9668
9669 name = bfd_asymbol_name (sym);
9670
d8282f0e 9671 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 9672}
9673
65b48a81 9674/* Parse the string of disassembler options. */
baf0cc5e 9675
65b48a81 9676static void
f995bbe8 9677parse_arm_disassembler_options (const char *options)
dd92f639 9678{
f995bbe8 9679 const char *opt;
b34976b6 9680
65b48a81 9681 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 9682 {
65b48a81
PB		 9683 if (CONST_STRNEQ (opt, "reg-names-"))
9684 {
9685 unsigned int i;
9686 for (i = 0; i < NUM_ARM_OPTIONS; i++)
9687 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
9688 {
9689 regname_selected = i;
9690 break;
9691 }
b34976b6 9692
65b48a81 9693 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 9694 /* xgettext: c-format */
9695 opcodes_error_handler (_("unrecognised register name set: %s"),
9696 opt);
65b48a81
PB		 9697 }
9698 else if (CONST_STRNEQ (opt, "force-thumb"))
9699 force_thumb = 1;
9700 else if (CONST_STRNEQ (opt, "no-force-thumb"))
9701 force_thumb = 0;
9702 else
a6743a54
AM		 9703 /* xgettext: c-format */
9704 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 9705 }
b34976b6 9706
dd92f639
NC		 9707 return;
9708}
9709
5bc5ae88
RL		 9710static bfd_boolean
9711mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
9712 enum map_type *map_symbol);
9713
c22aaad1
PB		 9714/* Search back through the insn stream to determine if this instruction is
9715 conditionally executed. */
fe56b6ce 9716
c22aaad1 9717static void
fe56b6ce
NC		 9718find_ifthen_state (bfd_vma pc,
9719 struct disassemble_info *info,
c22aaad1
PB		 9720 bfd_boolean little)
9721{
9722 unsigned char b[2];
9723 unsigned int insn;
9724 int status;
9725 /* COUNT is twice the number of instructions seen. It will be odd if we
9726 just crossed an instruction boundary. */
9727 int count;
9728 int it_count;
9729 unsigned int seen_it;
9730 bfd_vma addr;
9731
9732 ifthen_address = pc;
9733 ifthen_state = 0;
9734
9735 addr = pc;
9736 count = 1;
9737 it_count = 0;
9738 seen_it = 0;
9739 /* Scan backwards looking for IT instructions, keeping track of where
9740 instruction boundaries are. We don't know if something is actually an
9741 IT instruction until we find a definite instruction boundary. */
9742 for (;;)
9743 {
fe56b6ce 9744 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 9745 {
9746 /* A symbol must be on an instruction boundary, and will not
9747 be within an IT block. */
9748 if (seen_it && (count & 1))
9749 break;
9750
9751 return;
9752 }
9753 addr -= 2;
fe56b6ce 9754 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 9755 if (status)
9756 return;
9757
9758 if (little)
9759 insn = (b[0]) | (b[1] << 8);
9760 else
9761 insn = (b[1]) | (b[0] << 8);
9762 if (seen_it)
9763 {
9764 if ((insn & 0xf800) < 0xe800)
9765 {
9766 /* Addr + 2 is an instruction boundary. See if this matches
9767 the expected boundary based on the position of the last
9768 IT candidate. */
9769 if (count & 1)
9770 break;
9771 seen_it = 0;
9772 }
9773 }
9774 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
9775 {
5bc5ae88
RL		 9776 enum map_type type = MAP_ARM;
9777 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
9778
9779 if (!found || (found && type == MAP_THUMB))
9780 {
9781 /* This could be an IT instruction. */
9782 seen_it = insn;
9783 it_count = count >> 1;
9784 }
c22aaad1
PB		 9785 }
9786 if ((insn & 0xf800) >= 0xe800)
9787 count++;
9788 else
9789 count = (count + 2) | 1;
9790 /* IT blocks contain at most 4 instructions. */
9791 if (count >= 8 && !seen_it)
9792 return;
9793 }
9794 /* We found an IT instruction. */
9795 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
9796 if ((ifthen_state & 0xf) == 0)
9797 ifthen_state = 0;
9798}
9799
b0e28b39
DJ		 9800/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
9801 mapping symbol. */
9802
9803static int
9804is_mapping_symbol (struct disassemble_info *info, int n,
9805 enum map_type *map_type)
9806{
9807 const char *name;
9808
9809 name = bfd_asymbol_name (info->symtab[n]);
9810 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
9811 && (name[2] == 0 || name[2] == '.'))
9812 {
9813 *map_type = ((name[1] == 'a') ? MAP_ARM
9814 : (name[1] == 't') ? MAP_THUMB
9815 : MAP_DATA);
9816 return TRUE;
9817 }
9818
9819 return FALSE;
9820}
9821
9822/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
9823 Returns nonzero if *MAP_TYPE was set. */
9824
9825static int
9826get_map_sym_type (struct disassemble_info *info,
9827 int n,
9828 enum map_type *map_type)
9829{
9830 /* If the symbol is in a different section, ignore it. */
9831 if (info->section != NULL && info->section != info->symtab[n]->section)
9832 return FALSE;
9833
9834 return is_mapping_symbol (info, n, map_type);
9835}
9836
9837/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 9838 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 9839
9840static int
fe56b6ce
NC		 9841get_sym_code_type (struct disassemble_info *info,
9842 int n,
e821645d 9843 enum map_type *map_type)
2087ad84
PB		 9844{
9845 elf_symbol_type *es;
9846 unsigned int type;
b0e28b39
DJ		 9847
9848 /* If the symbol is in a different section, ignore it. */
9849 if (info->section != NULL && info->section != info->symtab[n]->section)
9850 return FALSE;
2087ad84 9851
e821645d 9852 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 9853 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
9854
9855 /* If the symbol has function type then use that. */
34e77a92 9856 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 9857 {
39d911fc
TP		 9858 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
9859 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 9860 *map_type = MAP_THUMB;
9861 else
9862 *map_type = MAP_ARM;
2087ad84
PB		 9863 return TRUE;
9864 }
9865
2087ad84
PB		 9866 return FALSE;
9867}
9868
5bc5ae88
RL		 9869/* Search the mapping symbol state for instruction at pc. This is only
9870 applicable for elf target.
9871
9872 There is an assumption Here, info->private_data contains the correct AND
9873 up-to-date information about current scan process. The information will be
9874 used to speed this search process.
9875
9876 Return TRUE if the mapping state can be determined, and map_symbol
9877 will be updated accordingly. Otherwise, return FALSE. */
9878
9879static bfd_boolean
9880mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
9881 enum map_type *map_symbol)
9882{
796d6298
TC		 9883 bfd_vma addr, section_vma = 0;
9884 int n, last_sym = -1;
5bc5ae88 9885 bfd_boolean found = FALSE;
796d6298
TC		 9886 bfd_boolean can_use_search_opt_p = FALSE;
9887
9888 /* Default to DATA. A text section is required by the ABI to contain an
9889 INSN mapping symbol at the start. A data section has no such
9890 requirement, hence if no mapping symbol is found the section must
9891 contain only data. This however isn't very useful if the user has
9892 fully stripped the binaries. If this is the case use the section
9893 attributes to determine the default. If we have no section default to
9894 INSN as well, as we may be disassembling some raw bytes on a baremetal
9895 HEX file or similar. */
9896 enum map_type type = MAP_DATA;
9897 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
9898 type = MAP_ARM;
5bc5ae88
RL		 9899 struct arm_private_data *private_data;
9900
796d6298 9901 if (info->private_data == NULL
5bc5ae88
RL		 9902 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
9903 return FALSE;
9904
9905 private_data = info->private_data;
5bc5ae88 9906
796d6298
TC		 9907 /* First, look for mapping symbols. */
9908 if (info->symtab_size != 0)
9909 {
9910 if (pc <= private_data->last_mapping_addr)
9911 private_data->last_mapping_sym = -1;
9912
9913 /* Start scanning at the start of the function, or wherever
9914 we finished last time. */
9915 n = info->symtab_pos + 1;
9916
9917 /* If the last stop offset is different from the current one it means we
9918 are disassembling a different glob of bytes. As such the optimization
9919 would not be safe and we should start over. */
9920 can_use_search_opt_p
9921 = private_data->last_mapping_sym >= 0
9922 && info->stop_offset == private_data->last_stop_offset;
9923
9924 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
9925 n = private_data->last_mapping_sym;
9926
9927 /* Look down while we haven't passed the location being disassembled.
9928 The reason for this is that there's no defined order between a symbol
9929 and an mapping symbol that may be at the same address. We may have to
9930 look at least one position ahead. */
9931 for (; n < info->symtab_size; n++)
9932 {
9933 addr = bfd_asymbol_value (info->symtab[n]);
9934 if (addr > pc)
9935 break;
9936 if (get_map_sym_type (info, n, &type))
9937 {
9938 last_sym = n;
9939 found = TRUE;
9940 }
9941 }
5bc5ae88 9942
796d6298
TC		 9943 if (!found)
9944 {
9945 n = info->symtab_pos;
9946 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
9947 n = private_data->last_mapping_sym;
9948
9949 /* No mapping symbol found at this address. Look backwards
9950 for a preceeding one, but don't go pass the section start
9951 otherwise a data section with no mapping symbol can pick up
9952 a text mapping symbol of a preceeding section. The documentation
9953 says section can be NULL, in which case we will seek up all the
9954 way to the top. */
9955 if (info->section)
9956 section_vma = info->section->vma;
9957
9958 for (; n >= 0; n--)
9959 {
9960 addr = bfd_asymbol_value (info->symtab[n]);
9961 if (addr < section_vma)
9962 break;
9963
9964 if (get_map_sym_type (info, n, &type))
9965 {
9966 last_sym = n;
9967 found = TRUE;
9968 break;
9969 }
9970 }
9971 }
9972 }
9973
9974 /* If no mapping symbol was found, try looking up without a mapping
9975 symbol. This is done by walking up from the current PC to the nearest
9976 symbol. We don't actually have to loop here since symtab_pos will
9977 contain the nearest symbol already. */
9978 if (!found)
5bc5ae88 9979 {
796d6298
TC		 9980 n = info->symtab_pos;
9981 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 9982 {
796d6298
TC		 9983 last_sym = n;
9984 found = TRUE;
5bc5ae88
RL		 9985 }
9986 }
9987
796d6298
TC		 9988 private_data->last_mapping_sym = last_sym;
9989 private_data->last_type = type;
9990 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 9991
9992 *map_symbol = type;
9993 return found;
9994}
9995
0313a2b8
NC		 9996/* Given a bfd_mach_arm_XXX value, this function fills in the fields
9997 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 9998 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 9999
10000 FIXME: This could more efficiently implemented as a constant array,
10001 although it would also be less robust. */
10002
10003static void
10004select_arm_features (unsigned long mach,
10005 arm_feature_set * features)
10006{
c0c468d5
TP		 10007 arm_feature_set arch_fset;
10008 const arm_feature_set fpu_any = FPU_ANY;
10009
1af1dd51
MW		 10010#undef ARM_SET_FEATURES
10011#define ARM_SET_FEATURES(FSET) \
10012 { \
10013 const arm_feature_set fset = FSET; \
c0c468d5 10014 arch_fset = fset; \
1af1dd51 10015 }
823d2571 10016
c0c468d5
TP		 10017 /* When several architecture versions share the same bfd_mach_arm_XXX value
10018 the most featureful is chosen. */
0313a2b8
NC		 10019 switch (mach)
10020 {
c0c468d5
TP		 10021 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
10022 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
10023 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
10024 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
10025 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
10026 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
10027 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
10028 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
10029 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
10030 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 10031 case bfd_mach_arm_ep9312:
c0c468d5
TP		 10032 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
10033 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 10034 break;
c0c468d5
TP		 10035 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
10036 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
10037 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
10038 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
10039 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
10040 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
10041 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
10042 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
10043 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
10044 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
10045 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
10046 case bfd_mach_arm_8:
10047 {
0632eeea
SD		 10048 /* Add bits for extensions that Armv8.5-A recognizes. */
10049 arm_feature_set armv8_5_ext_fset
10050 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
10051 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
10052 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 10053 break;
10054 }
10055 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
10056 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
10057 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 10058 case bfd_mach_arm_8_1M_MAIN:
10059 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
10060 force_thumb = 1;
10061 break;
c0c468d5
TP		 10062 /* If the machine type is unknown allow all architecture types and all
10063 extensions. */
10064 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 10065 default:
10066 abort ();
10067 }
1af1dd51 10068#undef ARM_SET_FEATURES
c0c468d5
TP		 10069
10070 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10071 and thus on bfd_mach_arm_XXX value. Therefore for a given
10072 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10073 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 10074}
10075
10076
58efb6c0
NC		 10077/* NOTE: There are no checks in these routines that
10078 the relevant number of data bytes exist. */
baf0cc5e 10079
58efb6c0 10080static int
4a5329c6 10081print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 10082{
c19d1205
ZW		 10083 unsigned char b[4];
10084 long given;
10085 int status;
e821645d 10086 int is_thumb = FALSE;
b0e28b39 10087 int is_data = FALSE;
bd2e2557 10088 int little_code;
e821645d 10089 unsigned int size = 4;
4a5329c6 10090 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 10091 bfd_boolean found = FALSE;
b0e28b39 10092 struct arm_private_data *private_data;
58efb6c0 10093
dd92f639
NC		 10094 if (info->disassembler_options)
10095 {
65b48a81 10096 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 10097
58efb6c0 10098 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 10099 info->disassembler_options = NULL;
10100 }
b34976b6 10101
0313a2b8
NC		 10102 /* PR 10288: Control which instructions will be disassembled. */
10103 if (info->private_data == NULL)
10104 {
b0e28b39 10105 static struct arm_private_data private;
0313a2b8
NC		 10106
10107 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
10108 /* If the user did not use the -m command line switch then default to
10109 disassembling all types of ARM instruction.
43e65147 10110
0313a2b8
NC		 10111 The info->mach value has to be ignored as this will be based on
10112 the default archictecture for the target and/or hints in the notes
10113 section, but it will never be greater than the current largest arm
10114 machine value (iWMMXt2), which is only equivalent to the V5TE
10115 architecture. ARM architectures have advanced beyond the machine
10116 value encoding, and these newer architectures would be ignored if
10117 the machine value was used.
10118
10119 Ie the -m switch is used to restrict which instructions will be
10120 disassembled. If it is necessary to use the -m switch to tell
10121 objdump that an ARM binary is being disassembled, eg because the
10122 input is a raw binary file, but it is also desired to disassemble
10123 all ARM instructions then use "-marm". This will select the
10124 "unknown" arm architecture which is compatible with any ARM
10125 instruction. */
10126 info->mach = bfd_mach_arm_unknown;
10127
10128 /* Compute the architecture bitmask from the machine number.
10129 Note: This assumes that the machine number will not change
10130 during disassembly.... */
b0e28b39 10131 select_arm_features (info->mach, & private.features);
0313a2b8 10132
1fbaefec
PB		 10133 private.last_mapping_sym = -1;
10134 private.last_mapping_addr = 0;
796d6298 10135 private.last_stop_offset = 0;
b0e28b39
DJ		 10136
10137 info->private_data = & private;
0313a2b8 10138 }
b0e28b39
DJ		 10139
10140 private_data = info->private_data;
10141
bd2e2557
SS		 10142 /* Decide if our code is going to be little-endian, despite what the
10143 function argument might say. */
10144 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
10145
b0e28b39
DJ		 10146 /* For ELF, consult the symbol table to determine what kind of code
10147 or data we have. */
8977d4b2 10148 if (info->symtab_size != 0
e821645d
DJ		 10149 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
10150 {
10151 bfd_vma addr;
796d6298 10152 int n;
e821645d 10153 int last_sym = -1;
b0e28b39 10154 enum map_type type = MAP_ARM;
e821645d 10155
796d6298
TC		 10156 found = mapping_symbol_for_insn (pc, info, &type);
10157 last_sym = private_data->last_mapping_sym;
e821645d 10158
1fbaefec
PB		 10159 is_thumb = (private_data->last_type == MAP_THUMB);
10160 is_data = (private_data->last_type == MAP_DATA);
b34976b6 10161
e821645d
DJ		 10162 /* Look a little bit ahead to see if we should print out
10163 two or four bytes of data. If there's a symbol,
10164 mapping or otherwise, after two bytes then don't
10165 print more. */
10166 if (is_data)
10167 {
10168 size = 4 - (pc & 3);
10169 for (n = last_sym + 1; n < info->symtab_size; n++)
10170 {
10171 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 10172 if (addr > pc
10173 && (info->section == NULL
10174 || info->section == info->symtab[n]->section))
e821645d
DJ		 10175 {
10176 if (addr - pc < size)
10177 size = addr - pc;
10178 break;
10179 }
10180 }
10181 /* If the next symbol is after three bytes, we need to
10182 print only part of the data, so that we can use either
10183 .byte or .short. */
10184 if (size == 3)
10185 size = (pc & 1) ? 1 : 2;
10186 }
10187 }
10188
10189 if (info->symbols != NULL)
252b5132 10190 {
5876e06d
NC		 10191 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
10192 {
2f0ca46a 10193 coff_symbol_type * cs;
b34976b6 10194
5876e06d
NC		 10195 cs = coffsymbol (*info->symbols);
10196 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
10197 || cs->native->u.syment.n_sclass == C_THUMBSTAT
10198 || cs->native->u.syment.n_sclass == C_THUMBLABEL
10199 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
10200 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
10201 }
e821645d
DJ		 10202 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
10203 && !found)
5876e06d 10204 {
2087ad84
PB		 10205 /* If no mapping symbol has been found then fall back to the type
10206 of the function symbol. */
e821645d
DJ		 10207 elf_symbol_type * es;
10208 unsigned int type;
2087ad84 10209
e821645d
DJ		 10210 es = *(elf_symbol_type **)(info->symbols);
10211 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 10212
39d911fc
TP		 10213 is_thumb =
10214 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10215 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 10216 }
e49d43ff
TG		 10217 else if (bfd_asymbol_flavour (*info->symbols)
10218 == bfd_target_mach_o_flavour)
10219 {
10220 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
10221
10222 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
10223 }
5876e06d 10224 }
b34976b6 10225
e821645d
DJ		 10226 if (force_thumb)
10227 is_thumb = TRUE;
10228
b8f9ee44
CL		 10229 if (is_data)
10230 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10231 else
10232 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10233
c19d1205 10234 info->bytes_per_line = 4;
252b5132 10235
1316c8b3
NC		 10236 /* PR 10263: Disassemble data if requested to do so by the user. */
10237 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 10238 {
10239 int i;
10240
1316c8b3 10241 /* Size was already set above. */
e821645d
DJ		 10242 info->bytes_per_chunk = size;
10243 printer = print_insn_data;
10244
fe56b6ce 10245 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 10246 given = 0;
10247 if (little)
10248 for (i = size - 1; i >= 0; i--)
10249 given = b[i] | (given << 8);
10250 else
10251 for (i = 0; i < (int) size; i++)
10252 given = b[i] | (given << 8);
10253 }
10254 else if (!is_thumb)
252b5132 10255 {
c19d1205
ZW		 10256 /* In ARM mode endianness is a straightforward issue: the instruction
10257 is four bytes long and is either ordered 0123 or 3210. */
10258 printer = print_insn_arm;
10259 info->bytes_per_chunk = 4;
4a5329c6 10260 size = 4;
c19d1205 10261
0313a2b8 10262 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 10263 if (little_code)
c19d1205
ZW		 10264 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
10265 else
10266 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 10267 }
58efb6c0 10268 else
252b5132 10269 {
c19d1205
ZW		 10270 /* In Thumb mode we have the additional wrinkle of two
10271 instruction lengths. Fortunately, the bits that determine
10272 the length of the current instruction are always to be found
10273 in the first two bytes. */
4a5329c6 10274 printer = print_insn_thumb16;
c19d1205 10275 info->bytes_per_chunk = 2;
4a5329c6
ZW		 10276 size = 2;
10277
fe56b6ce 10278 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 10279 if (little_code)
9a2ff3f5
AM		 10280 given = (b[0]) | (b[1] << 8);
10281 else
10282 given = (b[1]) | (b[0] << 8);
10283
c19d1205 10284 if (!status)
252b5132 10285 {
c19d1205
ZW		 10286 /* These bit patterns signal a four-byte Thumb
10287 instruction. */
10288 if ((given & 0xF800) == 0xF800
10289 || (given & 0xF800) == 0xF000
10290 || (given & 0xF800) == 0xE800)
252b5132 10291 {
0313a2b8 10292 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 10293 if (little_code)
c19d1205 10294 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 10295 else
c19d1205
ZW		 10296 given = (b[1]) | (b[0] << 8) | (given << 16);
10297
10298 printer = print_insn_thumb32;
4a5329c6 10299 size = 4;
252b5132 10300 }
252b5132 10301 }
c22aaad1
PB		 10302
10303 if (ifthen_address != pc)
0313a2b8 10304 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 10305
10306 if (ifthen_state)
10307 {
10308 if ((ifthen_state & 0xf) == 0x8)
10309 ifthen_next_state = 0;
10310 else
10311 ifthen_next_state = (ifthen_state & 0xe0)
10312 | ((ifthen_state & 0xf) << 1);
10313 }
252b5132 10314 }
b34976b6 10315
c19d1205
ZW		 10316 if (status)
10317 {
10318 info->memory_error_func (status, pc, info);
10319 return -1;
10320 }
6a56ec7e
NC		 10321 if (info->flags & INSN_HAS_RELOC)
10322 /* If the instruction has a reloc associated with it, then
10323 the offset field in the instruction will actually be the
10324 addend for the reloc. (We are using REL type relocs).
10325 In such cases, we can ignore the pc when computing
10326 addresses, since the addend is not currently pc-relative. */
10327 pc = 0;
b34976b6 10328
4a5329c6 10329 printer (pc, info, given);
c22aaad1
PB		 10330
10331 if (is_thumb)
10332 {
10333 ifthen_state = ifthen_next_state;
10334 ifthen_address += size;
10335 }
4a5329c6 10336 return size;
252b5132
RH		 10337}
10338
10339int
4a5329c6 10340print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 10341{
bd2e2557
SS		 10342 /* Detect BE8-ness and record it in the disassembler info. */
10343 if (info->flavour == bfd_target_elf_flavour
10344 && info->section != NULL
10345 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
10346 info->endian_code = BFD_ENDIAN_LITTLE;
10347
b34976b6 10348 return print_insn (pc, info, FALSE);
58efb6c0 10349}
01c7f630 10350
58efb6c0 10351int
4a5329c6 10352print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 10353{
b34976b6 10354 return print_insn (pc, info, TRUE);
58efb6c0 10355}
252b5132 10356
471b9d15 10357const disasm_options_and_args_t *
65b48a81
PB		 10358disassembler_options_arm (void)
10359{
471b9d15 10360 static disasm_options_and_args_t *opts_and_args;
65b48a81 10361
471b9d15 10362 if (opts_and_args == NULL)
65b48a81 10363 {
471b9d15 10364 disasm_options_t *opts;
65b48a81 10365 unsigned int i;
471b9d15
MR		 10366
10367 opts_and_args = XNEW (disasm_options_and_args_t);
10368 opts_and_args->args = NULL;
10369
10370 opts = &opts_and_args->options;
65b48a81
PB		 10371 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
10372 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 10373 opts->arg = NULL;
65b48a81
PB		 10374 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10375 {
10376 opts->name[i] = regnames[i].name;
10377 if (regnames[i].description != NULL)
10378 opts->description[i] = _(regnames[i].description);
10379 else
10380 opts->description[i] = NULL;
10381 }
10382 /* The array we return must be NULL terminated. */
10383 opts->name[i] = NULL;
10384 opts->description[i] = NULL;
10385 }
10386
471b9d15 10387 return opts_and_args;
65b48a81
PB		 10388}
10389
58efb6c0 10390void
4a5329c6 10391print_arm_disassembler_options (FILE *stream)
58efb6c0 10392{
65b48a81 10393 unsigned int i, max_len = 0;
58efb6c0
NC		 10394 fprintf (stream, _("\n\
10395The following ARM specific disassembler options are supported for use with\n\
10396the -M switch:\n"));
b34976b6 10397
65b48a81
PB		 10398 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10399 {
10400 unsigned int len = strlen (regnames[i].name);
10401 if (max_len < len)
10402 max_len = len;
10403 }
58efb6c0 10404
65b48a81
PB		 10405 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
10406 fprintf (stream, " %s%*c %s\n",
10407 regnames[i].name,
10408 (int)(max_len - strlen (regnames[i].name)), ' ',
10409 _(regnames[i].description));
252b5132 10410}
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