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252b5132 1/* Instruction printing code for the ARM
b90efa5b 2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
37
6b5d3a4d 38/* FIXME: Belongs in global header. */
01c7f630 39#ifndef strneq
58efb6c0
NC		 40#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41#endif
42
43#ifndef NUM_ELEM
44#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Whether any mapping symbols are present in the provided symbol
61 table. -1 if we do not know yet, otherwise 0 or 1. */
62 int has_mapping_symbols;
1fbaefec
PB		 63
64 /* Track the last type (although this doesn't seem to be useful) */
65 enum map_type last_type;
66
67 /* Tracking symbol table information */
68 int last_mapping_sym;
69 bfd_vma last_mapping_addr;
b0e28b39
DJ		 70};
71
6b5d3a4d
ZW		 72struct opcode32
73{
823d2571
TG		 74 arm_feature_set arch; /* Architecture defining this insn. */
75 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 76 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 77 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 78};
79
80struct opcode16
81{
823d2571 82 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 83 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 84 const char *assembler; /* How to disassemble this insn. */
85};
b7693d02 86
8f06b2d8 87/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 88
2fbad815 89 %% %
4a5329c6 90
c22aaad1 91 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 92 %q print shifter argument
e2efe87d
MGD		 93 %u print condition code (unconditional in ARM mode,
94 UNPREDICTABLE if not AL in Thumb)
4a5329c6 95 %A print address for ldc/stc/ldf/stf instruction
16980d0b 96 %B print vstm/vldm register list
4a5329c6 97 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 98 %F print the COUNT field of a LFM/SFM instruction.
99 %P print floating point precision in arithmetic insn
100 %Q print floating point precision in ldf/stf insn
101 %R print floating point rounding mode
102
33399f07 103 %<bitfield>c print as a condition code (for vsel)
4a5329c6 104 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 105 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
106 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 107 %<bitfield>d print the bitfield in decimal
16980d0b 108 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 109 %<bitfield>x print the bitfield in hex
110 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 111 %<bitfield>f print a floating point constant if >7 else a
112 floating point register
4a5329c6
ZW		 113 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
114 %<bitfield>g print as an iWMMXt 64-bit register
115 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 116 %<bitfield>D print as a NEON D register
117 %<bitfield>Q print as a NEON Q register
6f1c2142 118 %<bitfield>E print a quarter-float immediate value
4a5329c6 119
16980d0b 120 %y<code> print a single precision VFP reg.
2fbad815 121 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 122 %z<code> print a double precision VFP reg
2fbad815 123 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 124
16980d0b
JB		 125 %<bitfield>'c print specified char iff bitfield is all ones
126 %<bitfield>`c print specified char iff bitfield is all zeroes
127 %<bitfield>?ab... select from array of values in big endian order
43e65147 128
2fbad815 129 %L print as an iWMMXt N/M width field.
4a5329c6 130 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 131 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 132 versions.
133 %i print 5-bit immediate in bits 8,3..0
134 (print "32" when 0)
fe56b6ce 135 %r print register offset address for wldt/wstr instruction. */
2fbad815 136
21d799b5 137enum opcode_sentinel_enum
05413229
NC		 138{
139 SENTINEL_IWMMXT_START = 1,
140 SENTINEL_IWMMXT_END,
141 SENTINEL_GENERIC_START
142} opcode_sentinels;
143
aefd8a40 144#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 145#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 146
8f06b2d8 147/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 148
8f06b2d8 149static const struct opcode32 coprocessor_opcodes[] =
2fbad815 150{
2fbad815 151 /* XScale instructions. */
823d2571
TG		 152 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
153 0x0e200010, 0x0fff0ff0,
154 "mia%c\tacc0, %0-3r, %12-15r"},
155 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
156 0x0e280010, 0x0fff0ff0,
157 "miaph%c\tacc0, %0-3r, %12-15r"},
158 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
159 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
160 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
161 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
162 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
163 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 164
2fbad815 165 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 166 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
167 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
168 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
169 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
170 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
171 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
172 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
173 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
174 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
175 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
176 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
177 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
178 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
179 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
180 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
181 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
182 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
183 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
184 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
185 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
186 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
187 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
188 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
189 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
190 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
191 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
192 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
193 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
194 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
195 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
196 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
197 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
198 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
199 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
200 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
201 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
202 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
203 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
204 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
205 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
206 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
207 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
208 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
209 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
210 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
211 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
212 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
213 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
214 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
215 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
216 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
217 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
218 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
219 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
220 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
221 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
222 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
223 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
224 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
225 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
226 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
227 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
228 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
229 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
230 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
231 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
232 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
233 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
234 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
235 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
236 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
237 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
238 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
239 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
240 0x0e800120, 0x0f800ff0,
241 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
242 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
243 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
244 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
245 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
246 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
247 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
248 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
249 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
250 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
251 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
252 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
253 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
254 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
255 0x0e8000a0, 0x0f800ff0,
256 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
257 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
258 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
259 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
260 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
261 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
262 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
263 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
264 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
265 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
266 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
267 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
268 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
269 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
270 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
271 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
272 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
273 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
274 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
275 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
276 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
277 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
278 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
279 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
280 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
281 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
282 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
283 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
284 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
285 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
286 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
287 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
288 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
289 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
290 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
291 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
292 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
293 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
294 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
295 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
296 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
297 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
298 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
299 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
300 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
301 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
302 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
303 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
304 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
305 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
306 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
307 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
308 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
309 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
310 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
311 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
312 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
313 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
314 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
315 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
316 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
317 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
318 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
319 {ARM_FEATURE_CORE_LOW (0),
320 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 321
fe56b6ce 322 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 323 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
324 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
325 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
326 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
327 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
328 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
329 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
330 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
331 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
332 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
333 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
334 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
335 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
336 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
337 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
338 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
339 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
340 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
341 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
342 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
343 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
344 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
345 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
346 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
347 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
348 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
349 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
350 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
351 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
352 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
353 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
354 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
355 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
356 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
357 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
358 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
359 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
360 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
361 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
362 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
363 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
364 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
365 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
366 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
367 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
368 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
369 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
370 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
371 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
372 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
373 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
374 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
375 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
376 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
377 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
378 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
379 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
380 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
381 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
382 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
383 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
384 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
385 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
386 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
387 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
388 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
389 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
390 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
391 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
392 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
393 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
394 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
395 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
396 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
397 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
398 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
399 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
400 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
401 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
402 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
403 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
404 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
405 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
406 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
407 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
408 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 409
fe56b6ce 410 /* Register load/store. */
823d2571
TG		 411 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
412 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
413 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
414 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
415 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
416 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
417 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
418 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
419 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
420 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
421 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
422 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
423 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
424 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
425 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
426 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
427 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
428 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
429 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
430 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
431 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
432 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
433 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
434 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
435 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
436 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
437 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
438 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
439 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
440 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
441 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
442 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
443
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
448 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
449 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
450 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
451 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 452
fe56b6ce 453 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
455 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
457 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
459 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
461 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
463 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
465 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
467 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
469 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
471 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
473 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
475 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
477 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
479 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
481 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 482 /* Half-precision conversion instructions. */
823d2571
TG		 483 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
484 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
485 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
486 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
487 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
488 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
489 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
490 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 491
fe56b6ce 492 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 493 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
494 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
495 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
496 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
497 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
498 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
499 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
500 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
501 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
502 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
503 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
504 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
505 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
506 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
507 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
508 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
509 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
510 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
511 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
512 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
513 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
514 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
515 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
516 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
517 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
518 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
520 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
522 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
523 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
524 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
525 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
526 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
527 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
528 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
529 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
530 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
531 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
532 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
533 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
534 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
535 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
536 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
537 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
538 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
539 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
540 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
541 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
542 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
543 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
544 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
545 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
546 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
547 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
548 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
549 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
550 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
551 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
552 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
553 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
554 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
555 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
556 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
557 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
558 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
559 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
560 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
561 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
562 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
563 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
564 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
565 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
566 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
567 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
568 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
569 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
570 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
571 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
572 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
573 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
574 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
575 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
576 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
577 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
578 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
579 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
580 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
581 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 582 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 583 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 584 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 585 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
586 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
587 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
588 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
589 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
590 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
591 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
592 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
593 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
594 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
595 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
596 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
597 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
598 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
599 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
600 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
601 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
602 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
603 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
604 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
605 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
606 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
607 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
608 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
609 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
610 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
611 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
612 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
613 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
614 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
615 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
616 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
617 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
618 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
619 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
620 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
621 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
622 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
623 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
624 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
625 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
626 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 627
628 /* Cirrus coprocessor instructions. */
823d2571
TG		 629 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
630 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
631 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
632 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
633 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
634 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
635 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
636 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
637 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
638 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
639 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
640 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
641 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
642 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
643 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
644 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
645 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
646 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
647 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
648 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
649 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
650 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
651 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
652 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
653 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
654 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
655 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
656 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
657 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
658 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
659 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
660 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
661 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
662 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
663 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
664 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
665 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
666 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
667 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
668 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
669 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
670 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
671 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
672 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
673 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
674 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
675 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
676 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
677 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
678 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
679 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
680 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
681 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
682 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
683 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
684 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
685 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
686 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
687 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
688 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
689 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
690 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
691 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
692 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
693 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
694 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
695 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
696 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
697 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
698 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
699 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
700 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
701 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
702 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
703 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
704 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
705 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
706 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
707 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
708 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
709 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
710 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
711 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
712 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
713 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
714 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
715 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
716 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
717 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
718 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
719 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
720 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
721 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
722 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
723 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
724 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
725 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
726 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
727 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
728 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
729 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
730 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
731 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
732 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
733 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
734 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
735 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
736 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
737 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
738 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
739 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
740 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
741 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
742 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
743 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
744 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
745 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
746 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
747 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
748 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
749 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
750 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
751 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
752 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
753 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
754 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
755 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
756 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
757 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
758 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
759 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
760 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
761 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
762 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
763 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
764 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
765 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
766 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
767 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
768 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
769 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
770 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
771 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
772 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
773 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
774 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
775 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
776 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
777 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
778 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
779 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
780 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
781 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
782 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
783 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
784 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
785 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
786 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
787 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
788 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
789 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
790 0x0e000600, 0x0ff00f10,
791 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e100600, 0x0ff00f10,
794 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
795 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
796 0x0e200600, 0x0ff00f10,
797 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
798 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
799 0x0e300600, 0x0ff00f10,
800 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 801
62f3b8c8 802 /* VFP Fused multiply add instructions. */
823d2571
TG		 803 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
804 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
805 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
806 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
807 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
808 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
809 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
810 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
811 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
812 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
813 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
814 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
815 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
816 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
817 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
818 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 819
33399f07 820 /* FP v5. */
823d2571
TG		 821 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
822 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
824 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
825 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
826 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
827 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
828 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
829 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
830 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
831 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
832 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
833 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
834 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
835 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
836 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
837 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
838 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
839 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
840 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
841 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
842 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
843 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
844 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 845
05413229 846 /* Generic coprocessor instructions. */
823d2571
TG		 847 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
849 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
851 0x0c500000, 0x0ff00000,
852 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
854 0x0e000000, 0x0f000010,
855 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
857 0x0e10f010, 0x0f10f010,
858 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
860 0x0e100010, 0x0f100010,
861 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
863 0x0e000010, 0x0f100010,
864 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
866 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
868 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 869
05413229 870 /* V6 coprocessor instructions. */
823d2571
TG		 871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
872 0xfc500000, 0xfff00000,
873 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
875 0xfc400000, 0xfff00000,
876 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 877
05413229 878 /* V5 coprocessor instructions. */
823d2571
TG		 879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
880 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
882 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
884 0xfe000000, 0xff000010,
885 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
887 0xfe000010, 0xff100010,
888 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
890 0xfe100010, 0xff100010,
891 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
892
893 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 894};
895
16980d0b
JB		 896/* Neon opcode table: This does not encode the top byte -- that is
897 checked by the print_insn_neon routine, as it depends on whether we are
898 doing thumb32 or arm32 disassembly. */
899
900/* print_insn_neon recognizes the following format control codes:
901
902 %% %
903
c22aaad1 904 %c print condition code
e2efe87d
MGD		 905 %u print condition code (unconditional in ARM mode,
906 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 907 %A print v{st,ld}[1234] operands
908 %B print v{st,ld}[1234] any one operands
909 %C print v{st,ld}[1234] single->all operands
910 %D print scalar
911 %E print vmov, vmvn, vorr, vbic encoded constant
912 %F print vtbl,vtbx register list
913
914 %<bitfield>r print as an ARM register
915 %<bitfield>d print the bitfield in decimal
916 %<bitfield>e print the 2^N - bitfield in decimal
917 %<bitfield>D print as a NEON D register
918 %<bitfield>Q print as a NEON Q register
919 %<bitfield>R print as a NEON D or Q register
920 %<bitfield>Sn print byte scaled width limited by n
921 %<bitfield>Tn print short scaled width limited by n
922 %<bitfield>Un print long scaled width limited by n
43e65147 923
16980d0b
JB		 924 %<bitfield>'c print specified char iff bitfield is all ones
925 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 926 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 927
928static const struct opcode32 neon_opcodes[] =
929{
fe56b6ce 930 /* Extract. */
823d2571
TG		 931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
932 0xf2b00840, 0xffb00850,
933 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
935 0xf2b00000, 0xffb00810,
936 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 937
fe56b6ce 938 /* Move data element to all lanes. */
823d2571
TG		 939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
940 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
942 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
944 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 945
fe56b6ce 946 /* Table lookup. */
823d2571
TG		 947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
948 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
950 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
951
8e79c3df 952 /* Half-precision conversions. */
823d2571
TG		 953 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
954 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
955 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
956 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 957
958 /* NEON fused multiply add instructions. */
823d2571
TG		 959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
960 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
962 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 963
fe56b6ce 964 /* Two registers, miscellaneous. */
823d2571
TG		 965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
966 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
967 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
968 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
969 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
970 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
971 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
972 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
973 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
974 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
975 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
976 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
977 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
978 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
979 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
980 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
981 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
982 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
984 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
986 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
988 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
990 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
992 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
994 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
996 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
998 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
999 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1000 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1002 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1004 0xf3b20300, 0xffb30fd0,
1005 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1007 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1008 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1009 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1011 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1013 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1015 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1017 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1019 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1021 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1023 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1025 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1026 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1027 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1028 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1029 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1031 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1032 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1033 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1034 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1035 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1037 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1039 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1040 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1041 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1043 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1045 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1046 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1047 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1049 0xf3b30600, 0xffb30e10,
1050 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
16980d0b 1051
fe56b6ce 1052 /* Three registers of the same length. */
823d2571
TG		 1053 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1054 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1055 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1056 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1057 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1058 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1059 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1060 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1061 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1062 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1063 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1064 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1065 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1066 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1068 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1069 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1070 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1071 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1072 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1073 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1074 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1076 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1078 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1079 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1080 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1081 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1082 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1084 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1086 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1087 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1088 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1089 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1090 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1091 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1092 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1094 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1096 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1097 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1098 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1102 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1104 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1106 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1108 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1110 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1112 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1114 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1116 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1118 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1120 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1122 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1124 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1125 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1126 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1128 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130 0xf2000b00, 0xff800f10,
1131 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133 0xf2000b10, 0xff800f10,
1134 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1136 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1140 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1142 0xf3000b00, 0xff800f10,
1143 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145 0xf2000000, 0xfe800f10,
1146 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148 0xf2000010, 0xfe800f10,
1149 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1151 0xf2000100, 0xfe800f10,
1152 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154 0xf2000200, 0xfe800f10,
1155 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1157 0xf2000210, 0xfe800f10,
1158 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf2000300, 0xfe800f10,
1161 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1163 0xf2000310, 0xfe800f10,
1164 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf2000400, 0xfe800f10,
1167 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1169 0xf2000410, 0xfe800f10,
1170 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf2000500, 0xfe800f10,
1173 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1174 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1175 0xf2000510, 0xfe800f10,
1176 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf2000600, 0xfe800f10,
1179 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1180 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1181 0xf2000610, 0xfe800f10,
1182 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184 0xf2000700, 0xfe800f10,
1185 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1186 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1187 0xf2000710, 0xfe800f10,
1188 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190 0xf2000910, 0xfe800f10,
1191 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1192 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1193 0xf2000a00, 0xfe800f10,
1194 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196 0xf2000a10, 0xfe800f10,
1197 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1198 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1199 0xf3000b10, 0xff800f10,
1200 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1202 0xf3000c10, 0xff800f10,
1203 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1204
fe56b6ce 1205 /* One register and an immediate value. */
823d2571
TG		 1206 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1207 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1208 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1209 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1210 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1211 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1212 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1213 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1214 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1215 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1216 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1217 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1219 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1220 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1221 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1223 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1224 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1225 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1227 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1229 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1231 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1232
fe56b6ce 1233 /* Two registers and a shift amount. */
823d2571
TG		 1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1235 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1236 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1237 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245 0xf2880950, 0xfeb80fd0,
1246 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1248 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1252 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0xf2900950, 0xfeb00fd0,
1269 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1271 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1272 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1273 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1275 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1276 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1277 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1279 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1281 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1283 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1284 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1285 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1287 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1288 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1289 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1291 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1295 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1296 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1297 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1300 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1301 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1303 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1305 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1306 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1307 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1309 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1313 0xf2a00950, 0xfea00fd0,
1314 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1321 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1322 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1333 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1334 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf2a00e10, 0xfea00e90,
1353 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1354
fe56b6ce 1355 /* Three registers of different lengths. */
823d2571
TG		 1356 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1357 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf2800400, 0xff800f50,
1362 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1363 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1364 0xf2800600, 0xff800f50,
1365 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0xf2800900, 0xff800f50,
1368 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370 0xf2800b00, 0xff800f50,
1371 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf2800d00, 0xff800f50,
1374 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376 0xf3800400, 0xff800f50,
1377 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf3800600, 0xff800f50,
1380 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf2800000, 0xfe800f50,
1383 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf2800100, 0xfe800f50,
1386 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf2800200, 0xfe800f50,
1389 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf2800300, 0xfe800f50,
1392 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf2800500, 0xfe800f50,
1395 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2800700, 0xfe800f50,
1398 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf2800800, 0xfe800f50,
1401 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2800a00, 0xfe800f50,
1404 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406 0xf2800c00, 0xfe800f50,
1407 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1408
fe56b6ce 1409 /* Two registers and a scalar. */
823d2571
TG		 1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf2800240, 0xfe800f50,
1450 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf2800640, 0xfe800f50,
1453 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf2800a40, 0xfe800f50,
1456 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1458 0xf2800e40, 0xff800f50,
1459 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1461 0xf2800f40, 0xff800f50,
1462 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1464 0xf3800e40, 0xff800f50,
1465 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1467 0xf3800f40, 0xff800f50,
1468 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1469 },
16980d0b 1470
fe56b6ce 1471 /* Element and structure load/store. */
823d2571
TG		 1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1510
1511 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1512};
1513
8f06b2d8
PB		 1514/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1515 ordered: they must be searched linearly from the top to obtain a correct
1516 match. */
1517
1518/* print_insn_arm recognizes the following format control codes:
1519
1520 %% %
1521
1522 %a print address for ldr/str instruction
1523 %s print address for ldr/str halfword/signextend instruction
c1e26897 1524 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1525 %b print branch destination
1526 %c print condition code (always bits 28-31)
1527 %m print register mask for ldm/stm instruction
1528 %o print operand2 (immediate or register + shift)
1529 %p print 'p' iff bits 12-15 are 15
1530 %t print 't' iff bit 21 set and bit 24 clear
1531 %B print arm BLX(1) destination
1532 %C print the PSR sub type.
62b3e311
PB		 1533 %U print barrier type.
1534 %P print address for pli instruction.
8f06b2d8
PB		 1535
1536 %<bitfield>r print as an ARM register
9eb6c0f1 1537 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1538 %<bitfield>R as %r but r15 is UNPREDICTABLE
1539 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1540 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1541 %<bitfield>d print the bitfield in decimal
43e65147 1542 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1543 %<bitfield>x print the bitfield in hex
1544 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1545
16980d0b
JB		 1546 %<bitfield>'c print specified char iff bitfield is all ones
1547 %<bitfield>`c print specified char iff bitfield is all zeroes
1548 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1549
8f06b2d8
PB		 1550 %e print arm SMI operand (bits 0..7,8..19).
1551 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1552 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1553 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1554
8f06b2d8
PB		 1555static const struct opcode32 arm_opcodes[] =
1556{
1557 /* ARM instructions. */
823d2571
TG		 1558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1559 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1561 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1562
1563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1564 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1566 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1568 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1570 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1572 0x00800090, 0x0fa000f0,
1573 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1575 0x00a00090, 0x0fa000f0,
1576 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1577
53c4b28b 1578 /* V8 instructions. */
823d2571
TG		 1579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1580 0x0320f005, 0x0fffffff, "sevl"},
1581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1582 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1584 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1586 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1588 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1590 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1592 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1594 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1596 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1598 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1600 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1602 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1604 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1606 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1608 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1610 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
dd5181d5 1611 /* CRC32 instructions. */
823d2571
TG		 1612 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1613 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1614 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1615 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1616 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1617 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1618 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1619 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1620 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1621 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1622 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1623 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1624
ddfded2f
MW		 1625 /* Privileged Access Never extension instructions. */
1626 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1627 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1628
90ec0d68 1629 /* Virtualization Extension instructions. */
823d2571
TG		 1630 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1631 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1632
eea54501 1633 /* Integer Divide Extension instructions. */
823d2571
TG		 1634 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1635 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1636 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1637 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1638
60e5ef9f 1639 /* MP Extension instructions. */
823d2571 1640 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1641
62b3e311 1642 /* V7 instructions. */
823d2571
TG		 1643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
62b3e311 1650
c19d1205 1651 /* ARM V6T2 instructions. */
823d2571
TG		 1652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1653 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1655 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1657 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1659 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1660
1661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1662 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1664 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1665
1666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1667 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1669 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1671 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1673 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1674
f4c65163 1675 /* ARM Security extension instructions. */
823d2571
TG		 1676 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1677 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1678
8f06b2d8 1679 /* ARM V6K instructions. */
823d2571
TG		 1680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1681 0xf57ff01f, 0xffffffff, "clrex"},
1682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1683 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1685 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1687 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1689 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1691 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1693 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1694
8f06b2d8 1695 /* ARM V6K NOP hints. */
823d2571
TG		 1696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1697 0x0320f001, 0x0fffffff, "yield%c"},
1698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1699 0x0320f002, 0x0fffffff, "wfe%c"},
1700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1701 0x0320f003, 0x0fffffff, "wfi%c"},
1702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1703 0x0320f004, 0x0fffffff, "sev%c"},
1704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1705 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1706
fe56b6ce 1707 /* ARM V6 instructions. */
823d2571
TG		 1708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1709 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1711 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1713 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1715 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1717 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1719 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1721 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1723 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1725 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1727 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1729 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1731 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1733 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1735 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1737 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1739 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1741 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1743 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1745 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1747 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1749 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1751 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1753 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1755 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1757 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1759 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1761 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1763 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1765 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1767 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1769 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1771 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1773 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1775 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1777 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1779 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1781 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1783 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1785 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1787 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1789 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1791 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1793 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1795 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1797 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1799 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1801 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1803 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1805 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1807 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1809 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1811 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1813 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1815 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1817 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1819 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1821 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1823 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1825 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1827 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1829 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1831 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1833 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1835 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1837 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1839 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1841 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1843 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1845 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1847 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1849 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1851 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1853 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1855 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1857 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1859 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1861 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1863 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1865 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1867 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1869 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1871 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1873 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1875 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1877 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1879 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1881 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1883 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1885 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1887 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1889 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1891 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1893 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1895 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1897 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1899 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1901 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1903 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1905 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1907 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1909 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1911 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1913 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1915 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1917 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1919 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1921 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1923 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1925 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1927 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1929 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1931 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1933 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1935 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1937 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1939 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1941 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1943 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1945 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1947 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1949 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1951 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 1952
8f06b2d8 1953 /* V5J instruction. */
823d2571
TG		 1954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1955 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 1956
8f06b2d8 1957 /* V5 Instructions. */
823d2571
TG		 1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1959 0xe1200070, 0xfff000f0,
1960 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1962 0xfa000000, 0xfe000000, "blx\t%B"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1964 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1966 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1967
1968 /* V5E "El Segundo" Instructions. */
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1970 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1972 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1974 0xf450f000, 0xfc70f000, "pld\t%a"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1976 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1978 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1980 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1982 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1983
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1985 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1987 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1988
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1990 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1992 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1994 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1996 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1997
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1999 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2001 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2003 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2005 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2006
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2008 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2010 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2011
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2013 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2015 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2017 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2019 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2020
8f06b2d8 2021 /* ARM Instructions. */
823d2571
TG		 2022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2023 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2024
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2026 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2028 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2030 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2032 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2034 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2036 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2037
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2039 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2041 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2043 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2045 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2046
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2048 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2050 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2052 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2054 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2055
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2057 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2059 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2061 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2062
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2064 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2066 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2068 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2069
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2071 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2073 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2075 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2076
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2078 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2080 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2082 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2083
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2085 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2087 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2089 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2090
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2092 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2094 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2096 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2097
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2099 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2101 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2103 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2104
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2106 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2108 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2110 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2111
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2113 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2115 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2117 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2118
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2120 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2122 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2124 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2125
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2127 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2129 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2131 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
2132
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2134 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2136 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2138 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2139
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2141 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2143 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2145 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2146
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2148 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2150 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2152 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2153
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2155 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2157 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2159 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2161 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2163 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2165 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2167 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2168
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2172 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2174 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2175
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2177 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2181 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2182
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2184 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2186 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2187
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2190
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2192 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2194 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2195
2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2197 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2199 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2201 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2205 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2207 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2209 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2211 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2213 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2215 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2223 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2225 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2227 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2229 0x092d0000, 0x0fff0000, "push%c\t%m"},
2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2231 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2233 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2234
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2244 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2258 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2268 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2273
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2278
2279 /* The rest. */
823d2571
TG		 2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2282 {ARM_FEATURE_CORE_LOW (0),
2283 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2284};
2285
2286/* print_insn_thumb16 recognizes the following format control codes:
2287
2288 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2289 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2290 %<bitfield>I print bitfield as a signed decimal
2291 (top bit of range being the sign bit)
2292 %N print Thumb register mask (with LR)
2293 %O print Thumb register mask (with PC)
2294 %M print Thumb register mask
2295 %b print CZB's 6-bit unsigned branch destination
2296 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2297 %c print the condition code
2298 %C print the condition code, or "s" if not conditional
2299 %x print warning if conditional an not at end of IT block"
2300 %X print "\t; unpredictable <IT:code>" if conditional
2301 %I print IT instruction suffix and operands
4547cb56 2302 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2303 %<bitfield>r print bitfield as an ARM register
2304 %<bitfield>d print bitfield as a decimal
2305 %<bitfield>H print (bitfield * 2) as a decimal
2306 %<bitfield>W print (bitfield * 4) as a decimal
2307 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2308 %<bitfield>B print Thumb branch destination (signed displacement)
2309 %<bitfield>c print bitfield as a condition code
2310 %<bitnum>'c print specified char iff bit is one
2311 %<bitnum>?ab print a if bit is one else print b. */
2312
2313static const struct opcode16 thumb_opcodes[] =
2314{
2315 /* Thumb instructions. */
2316
53c4b28b 2317 /* ARM V8 instructions. */
823d2571
TG		 2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2321
8f06b2d8 2322 /* ARM V6K no-argument instructions. */
823d2571
TG		 2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2329
2330 /* ARM V6T2 instructions. */
823d2571
TG		 2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2334
2335 /* ARM V6. */
823d2571
TG		 2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2347
2348 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2350 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2351 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2353 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2354 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2356 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2357 /* Format 4. */
823d2571
TG		 2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2374 /* format 13 */
823d2571
TG		 2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2377 /* format 5 */
823d2571
TG		 2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2382 /* format 14 */
823d2571
TG		 2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2385 /* format 2 */
823d2571
TG		 2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2387 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2389 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2391 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2393 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2394 /* format 8 */
823d2571
TG		 2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2396 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2398 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2400 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2401 /* format 7 */
823d2571
TG		 2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2403 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2405 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2406 /* format 1 */
823d2571
TG		 2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2409 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2412 /* format 3 */
823d2571
TG		 2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2417 /* format 6 */
823d2571
TG		 2418 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2420 0x4800, 0xF800,
2421 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2422 /* format 9 */
823d2571
TG		 2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2424 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2426 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2428 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2430 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2431 /* format 10 */
823d2571
TG		 2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2433 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2435 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2436 /* format 11 */
823d2571
TG		 2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2438 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2440 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2441 /* format 12 */
823d2571
TG		 2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2443 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2445 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2446 /* format 15 */
823d2571
TG		 2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2449 /* format 17 */
823d2571 2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2451 /* format 16 */
823d2571
TG		 2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2455 /* format 18 */
823d2571 2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2457
2458 /* The E800 .. FFFF range is unconditionally redirected to the
2459 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2460 are processed via that table. Thus, we can never encounter a
2461 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2463 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2464};
2465
2466/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2467 We adopt the convention that hw1 is the high 16 bits of .value and
2468 .mask, hw2 the low 16 bits.
2469
2470 print_insn_thumb32 recognizes the following format control codes:
2471
2472 %% %
2473
2474 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2475 %M print a modified 12-bit immediate (same location)
2476 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2477 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2478 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2479 %S print a possibly-shifted Rm
2480
32a94698 2481 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2482 %a print the address of a plain load/store
2483 %w print the width and signedness of a core load/store
2484 %m print register mask for ldm/stm
2485
2486 %E print the lsb and width fields of a bfc/bfi instruction
2487 %F print the lsb and width fields of a sbfx/ubfx instruction
2488 %b print a conditional branch offset
2489 %B print an unconditional branch offset
2490 %s print the shift field of an SSAT instruction
2491 %R print the rotation field of an SXT instruction
62b3e311
PB		 2492 %U print barrier type.
2493 %P print address for pli instruction.
c22aaad1
PB		 2494 %c print the condition code
2495 %x print warning if conditional an not at end of IT block"
2496 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2497
2498 %<bitfield>d print bitfield in decimal
f0fba320 2499 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2500 %<bitfield>W print bitfield*4 in decimal
2501 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2502 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2503 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2504 %<bitfield>c print bitfield as a condition code
2505
16980d0b
JB		 2506 %<bitfield>'c print specified char iff bitfield is all ones
2507 %<bitfield>`c print specified char iff bitfield is all zeroes
2508 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2509
2510 With one exception at the bottom (done because BL and BLX(1) need
2511 to come dead last), this table was machine-sorted first in
2512 decreasing order of number of bits set in the mask, then in
2513 increasing numeric order of mask, then in increasing numeric order
2514 of opcode. This order is not the clearest for a human reader, but
2515 is guaranteed never to catch a special-case bit pattern with a more
2516 general mask, which is important, because this instruction encoding
2517 makes heavy use of special-case bit patterns. */
2518static const struct opcode32 thumb32_opcodes[] =
2519{
53c4b28b 2520 /* V8 instructions. */
823d2571
TG		 2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2522 0xf3af8005, 0xffffffff, "sevl%c.w"},
2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2524 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2526 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2528 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2530 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2532 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2534 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2536 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2538 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2540 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2542 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2544 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2546 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2548 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2550 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2552 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2553
dd5181d5 2554 /* CRC32 instructions. */
823d2571
TG		 2555 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2556 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2557 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2558 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2559 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2560 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2561 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2562 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2563 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2564 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2565 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2566 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2567
62b3e311 2568 /* V7 instructions. */
823d2571
TG		 2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2577 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2579 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2580
90ec0d68 2581 /* Virtualization Extension instructions. */
823d2571 2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2583 /* We skip ERET as that is SUBS pc, lr, #0. */
2584
60e5ef9f 2585 /* MP Extension instructions. */
823d2571 2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2587
f4c65163 2588 /* Security extension instructions. */
823d2571 2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2590
8f06b2d8 2591 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2598 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2600
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2602 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2604 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2606 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2608 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2610 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2612 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2614 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2616 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2618 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2620 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2622 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2624 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2626 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2628 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2630 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2632 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2634 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2636 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2638 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2640 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2642 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2644 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2646 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2648 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2650 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2652 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2654 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2656 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2658 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2660 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2662 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2664 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2666 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2668 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2670 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2672 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2674 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2676 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2678 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2680 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2682 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2684 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2686 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2688 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2690 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2692 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2694 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2696 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2698 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2700 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2702 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2704 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2706 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2708 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2710 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2712 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2714 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2716 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2718 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2720 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2722 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2724 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2726 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2728 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2730 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2732 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2734 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2736 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2738 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2740 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2742 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2744 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2746 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2748 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2750 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2752 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2754 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2756 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2758 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2760 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2762 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2764 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2766 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2768 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2770 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2772 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2774 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2776 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2778 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2780 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2782 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2784 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2786 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2788 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2790 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2792 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2794 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2796 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2798 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2800 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2802 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2804 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2806 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2808 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2810 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2812 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2814 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2816 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2818 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2820 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2822 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2824 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2826 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2828 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2832 0xf810f000, 0xff70f000, "pld%c\t%a"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2834 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2836 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2838 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2840 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2842 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2844 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2846 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2848 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2850 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858 0xfb100000, 0xfff000c0,
2859 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xfbc00080, 0xfff000c0,
2862 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2864 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2866 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2868 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2880 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2882 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2900 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934 0xe9400000, 0xff500000,
2935 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xe9500000, 0xff500000,
2938 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2940 0xe8600000, 0xff700000,
2941 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xe8700000, 0xff700000,
2944 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2948 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 2949
2950 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 2959
8f06b2d8 2960 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2962 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2964 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 2965
2966 /* Fallback. */
823d2571
TG		 2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2968 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2969 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 2970};
ff4a8d2b 2971
8f06b2d8
PB		 2972static const char *const arm_conditional[] =
2973{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 2974 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 2975
2976static const char *const arm_fp_const[] =
2977{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
2978
2979static const char *const arm_shift[] =
2980{"lsl", "lsr", "asr", "ror"};
2981
2982typedef struct
2983{
2984 const char *name;
2985 const char *description;
2986 const char *reg_names[16];
2987}
2988arm_regname;
2989
2990static const arm_regname regnames[] =
2991{
2992 { "raw" , "Select raw register names",
2993 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
2994 { "gcc", "Select register names used by GCC",
2995 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
2996 { "std", "Select register names used in ARM's ISA documentation",
2997 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
2998 { "apcs", "Select register names used in the APCS",
2999 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3000 { "atpcs", "Select register names used in the ATPCS",
3001 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3002 { "special-atpcs", "Select special register names used in the ATPCS",
3003 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3004};
3005
3006static const char *const iwmmxt_wwnames[] =
3007{"b", "h", "w", "d"};
3008
3009static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3010{"b", "bus", "bc", "bss",
3011 "h", "hus", "hc", "hss",
3012 "w", "wus", "wc", "wss",
3013 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3014};
3015
3016static const char *const iwmmxt_regnames[] =
3017{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3018 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3019};
3020
3021static const char *const iwmmxt_cregnames[] =
3022{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3023 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3024};
3025
3026/* Default to GCC register name set. */
3027static unsigned int regname_selected = 1;
3028
3029#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3030#define arm_regnames regnames[regname_selected].reg_names
3031
3032static bfd_boolean force_thumb = FALSE;
3033
c22aaad1
PB		 3034/* Current IT instruction state. This contains the same state as the IT
3035 bits in the CPSR. */
3036static unsigned int ifthen_state;
3037/* IT state for the next instruction. */
3038static unsigned int ifthen_next_state;
3039/* The address of the insn for which the IT state is valid. */
3040static bfd_vma ifthen_address;
3041#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3042/* Indicates that the current Conditional state is unconditional or outside
3043 an IT block. */
3044#define COND_UNCOND 16
c22aaad1 3045
8f06b2d8
PB		 3046\f
3047/* Functions. */
3048int
3049get_arm_regname_num_options (void)
3050{
3051 return NUM_ARM_REGNAMES;
3052}
3053
3054int
3055set_arm_regname_option (int option)
3056{
3057 int old = regname_selected;
3058 regname_selected = option;
3059 return old;
3060}
3061
3062int
fe56b6ce
NC		 3063get_arm_regnames (int option,
3064 const char **setname,
3065 const char **setdescription,
8f06b2d8
PB		 3066 const char *const **register_names)
3067{
3068 *setname = regnames[option].name;
3069 *setdescription = regnames[option].description;
3070 *register_names = regnames[option].reg_names;
3071 return 16;
3072}
3073
16980d0b
JB		 3074/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3075 Returns pointer to following character of the format string and
3076 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3077 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3078
3079static const char *
fe56b6ce
NC		 3080arm_decode_bitfield (const char *ptr,
3081 unsigned long insn,
3082 unsigned long *valuep,
3083 int *widthp)
16980d0b
JB		 3084{
3085 unsigned long value = 0;
3086 int width = 0;
43e65147
L		 3087
3088 do
16980d0b
JB		 3089 {
3090 int start, end;
3091 int bits;
3092
3093 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3094 start = start * 10 + *ptr - '0';
3095 if (*ptr == '-')
3096 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3097 end = end * 10 + *ptr - '0';
3098 else
3099 end = start;
3100 bits = end - start;
3101 if (bits < 0)
3102 abort ();
3103 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3104 width += bits + 1;
3105 }
3106 while (*ptr++ == ',');
3107 *valuep = value;
3108 if (widthp)
3109 *widthp = width;
3110 return ptr - 1;
3111}
3112
8f06b2d8 3113static void
37b37b2d 3114arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3115 bfd_boolean print_shift)
8f06b2d8
PB		 3116{
3117 func (stream, "%s", arm_regnames[given & 0xf]);
3118
3119 if ((given & 0xff0) != 0)
3120 {
3121 if ((given & 0x10) == 0)
3122 {
3123 int amount = (given & 0xf80) >> 7;
3124 int shift = (given & 0x60) >> 5;
3125
3126 if (amount == 0)
3127 {
3128 if (shift == 3)
3129 {
3130 func (stream, ", rrx");
3131 return;
3132 }
3133
3134 amount = 32;
3135 }
3136
37b37b2d
RE		 3137 if (print_shift)
3138 func (stream, ", %s #%d", arm_shift[shift], amount);
3139 else
3140 func (stream, ", #%d", amount);
8f06b2d8 3141 }
74bdfecf 3142 else if ((given & 0x80) == 0x80)
aefd8a40 3143 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3144 else if (print_shift)
8f06b2d8
PB		 3145 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3146 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3147 else
3148 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3149 }
3150}
3151
c1e26897
NC		 3152#define W_BIT 21
3153#define I_BIT 22
3154#define U_BIT 23
3155#define P_BIT 24
3156
3157#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3158#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3159#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3160#define PRE_BIT_SET (given & (1 << P_BIT))
3161
8f06b2d8
PB		 3162/* Print one coprocessor instruction on INFO->STREAM.
3163 Return TRUE if the instuction matched, FALSE if this is not a
3164 recognised coprocessor instruction. */
3165
3166static bfd_boolean
fe56b6ce
NC		 3167print_insn_coprocessor (bfd_vma pc,
3168 struct disassemble_info *info,
3169 long given,
8f06b2d8
PB		 3170 bfd_boolean thumb)
3171{
3172 const struct opcode32 *insn;
3173 void *stream = info->stream;
3174 fprintf_ftype func = info->fprintf_func;
3175 unsigned long mask;
2edcd244 3176 unsigned long value = 0;
c22aaad1 3177 int cond;
823d2571
TG		 3178 struct arm_private_data *private_data = info->private_data;
3179 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3180
3181 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3182
3183 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3184 {
ff4a8d2b
NC		 3185 unsigned long u_reg = 16;
3186 bfd_boolean is_unpredictable = FALSE;
05413229 3187 signed long value_in_comment = 0;
0313a2b8
NC		 3188 const char *c;
3189
823d2571 3190 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3191 switch (insn->value)
3192 {
3193 case SENTINEL_IWMMXT_START:
3194 if (info->mach != bfd_mach_arm_XScale
3195 && info->mach != bfd_mach_arm_iWMMXt
3196 && info->mach != bfd_mach_arm_iWMMXt2)
3197 do
3198 insn++;
823d2571
TG		 3199 while ((! ARM_FEATURE_ZERO (insn->arch))
3200 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3201 continue;
3202
3203 case SENTINEL_IWMMXT_END:
3204 continue;
3205
3206 case SENTINEL_GENERIC_START:
823d2571 3207 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3208 continue;
3209
3210 default:
3211 abort ();
3212 }
8f06b2d8
PB		 3213
3214 mask = insn->mask;
3215 value = insn->value;
3216 if (thumb)
3217 {
3218 /* The high 4 bits are 0xe for Arm conditional instructions, and
3219 0xe for arm unconditional instructions. The rest of the
3220 encoding is the same. */
3221 mask |= 0xf0000000;
3222 value |= 0xe0000000;
c22aaad1
PB		 3223 if (ifthen_state)
3224 cond = IFTHEN_COND;
3225 else
e2efe87d 3226 cond = COND_UNCOND;
8f06b2d8
PB		 3227 }
3228 else
3229 {
3230 /* Only match unconditional instuctions against unconditional
3231 patterns. */
3232 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3233 {
3234 mask |= 0xf0000000;
e2efe87d 3235 cond = COND_UNCOND;
c22aaad1
PB		 3236 }
3237 else
3238 {
3239 cond = (given >> 28) & 0xf;
3240 if (cond == 0xe)
e2efe87d 3241 cond = COND_UNCOND;
c22aaad1 3242 }
8f06b2d8 3243 }
823d2571 3244
0313a2b8
NC		 3245 if ((given & mask) != value)
3246 continue;
8f06b2d8 3247
823d2571 3248 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3249 continue;
3250
3251 for (c = insn->assembler; *c; c++)
3252 {
3253 if (*c == '%')
8f06b2d8 3254 {
0313a2b8 3255 switch (*++c)
8f06b2d8 3256 {
0313a2b8
NC		 3257 case '%':
3258 func (stream, "%%");
3259 break;
3260
3261 case 'A':
05413229 3262 {
79862e45 3263 int rn = (given >> 16) & 0xf;
f8b960bc 3264 bfd_vma offset = given & 0xff;
0313a2b8 3265
05413229 3266 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3267
79862e45
DJ		 3268 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3269 {
3270 /* Not unindexed. The offset is scaled. */
3271 offset = offset * 4;
3272 if (NEGATIVE_BIT_SET)
3273 offset = - offset;
3274 if (rn != 15)
3275 value_in_comment = offset;
3276 }
3277
c1e26897 3278 if (PRE_BIT_SET)
05413229
NC		 3279 {
3280 if (offset)
fe56b6ce 3281 func (stream, ", #%d]%s",
d908c8af 3282 (int) offset,
c1e26897 3283 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3284 else if (NEGATIVE_BIT_SET)
3285 func (stream, ", #-0]");
05413229
NC		 3286 else
3287 func (stream, "]");
3288 }
3289 else
3290 {
0313a2b8 3291 func (stream, "]");
8f06b2d8 3292
c1e26897 3293 if (WRITEBACK_BIT_SET)
05413229
NC		 3294 {
3295 if (offset)
d908c8af 3296 func (stream, ", #%d", (int) offset);
26d97720
NS		 3297 else if (NEGATIVE_BIT_SET)
3298 func (stream, ", #-0");
05413229
NC		 3299 }
3300 else
fe56b6ce 3301 {
26d97720
NS		 3302 func (stream, ", {%s%d}",
3303 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3304 (int) offset);
fe56b6ce
NC		 3305 value_in_comment = offset;
3306 }
05413229 3307 }
79862e45
DJ		 3308 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3309 {
3310 func (stream, "\t; ");
6844b2c2
MGD		 3311 /* For unaligned PCs, apply off-by-alignment
3312 correction. */
43e65147 3313 info->print_address_func (offset + pc
6844b2c2
MGD		 3314 + info->bytes_per_chunk * 2
3315 - (pc & 3),
3316 info);
79862e45 3317 }
05413229 3318 }
0313a2b8 3319 break;
8f06b2d8 3320
0313a2b8
NC		 3321 case 'B':
3322 {
3323 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3324 int offset = (given >> 1) & 0x3f;
3325
3326 if (offset == 1)
3327 func (stream, "{d%d}", regno);
3328 else if (regno + offset > 32)
3329 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3330 else
3331 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3332 }
3333 break;
8f06b2d8 3334
e2efe87d
MGD		 3335 case 'u':
3336 if (cond != COND_UNCOND)
3337 is_unpredictable = TRUE;
3338
3339 /* Fall through. */
0313a2b8
NC		 3340 case 'c':
3341 func (stream, "%s", arm_conditional[cond]);
3342 break;
8f06b2d8 3343
0313a2b8
NC		 3344 case 'I':
3345 /* Print a Cirrus/DSP shift immediate. */
3346 /* Immediates are 7bit signed ints with bits 0..3 in
3347 bits 0..3 of opcode and bits 4..6 in bits 5..7
3348 of opcode. */
3349 {
3350 int imm;
8f06b2d8 3351
0313a2b8 3352 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3353
0313a2b8
NC		 3354 /* Is ``imm'' a negative number? */
3355 if (imm & 0x40)
24b4cf66 3356 imm -= 0x80;
8f06b2d8 3357
0313a2b8
NC		 3358 func (stream, "%d", imm);
3359 }
3360
3361 break;
8f06b2d8 3362
0313a2b8
NC		 3363 case 'F':
3364 switch (given & 0x00408000)
3365 {
3366 case 0:
3367 func (stream, "4");
3368 break;
3369 case 0x8000:
3370 func (stream, "1");
3371 break;
3372 case 0x00400000:
3373 func (stream, "2");
8f06b2d8 3374 break;
0313a2b8
NC		 3375 default:
3376 func (stream, "3");
3377 }
3378 break;
8f06b2d8 3379
0313a2b8
NC		 3380 case 'P':
3381 switch (given & 0x00080080)
3382 {
3383 case 0:
3384 func (stream, "s");
3385 break;
3386 case 0x80:
3387 func (stream, "d");
3388 break;
3389 case 0x00080000:
3390 func (stream, "e");
3391 break;
3392 default:
3393 func (stream, _("<illegal precision>"));
8f06b2d8 3394 break;
0313a2b8
NC		 3395 }
3396 break;
8f06b2d8 3397
0313a2b8
NC		 3398 case 'Q':
3399 switch (given & 0x00408000)
3400 {
3401 case 0:
3402 func (stream, "s");
8f06b2d8 3403 break;
0313a2b8
NC		 3404 case 0x8000:
3405 func (stream, "d");
8f06b2d8 3406 break;
0313a2b8
NC		 3407 case 0x00400000:
3408 func (stream, "e");
3409 break;
3410 default:
3411 func (stream, "p");
8f06b2d8 3412 break;
0313a2b8
NC		 3413 }
3414 break;
8f06b2d8 3415
0313a2b8
NC		 3416 case 'R':
3417 switch (given & 0x60)
3418 {
3419 case 0:
3420 break;
3421 case 0x20:
3422 func (stream, "p");
3423 break;
3424 case 0x40:
3425 func (stream, "m");
3426 break;
3427 default:
3428 func (stream, "z");
3429 break;
3430 }
3431 break;
16980d0b 3432
0313a2b8
NC		 3433 case '0': case '1': case '2': case '3': case '4':
3434 case '5': case '6': case '7': case '8': case '9':
3435 {
3436 int width;
8f06b2d8 3437
0313a2b8 3438 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3439
0313a2b8
NC		 3440 switch (*c)
3441 {
ff4a8d2b
NC		 3442 case 'R':
3443 if (value == 15)
3444 is_unpredictable = TRUE;
3445 /* Fall through. */
0313a2b8 3446 case 'r':
ff4a8d2b
NC		 3447 if (c[1] == 'u')
3448 {
3449 /* Eat the 'u' character. */
3450 ++ c;
3451
3452 if (u_reg == value)
3453 is_unpredictable = TRUE;
3454 u_reg = value;
3455 }
0313a2b8
NC		 3456 func (stream, "%s", arm_regnames[value]);
3457 break;
3458 case 'D':
3459 func (stream, "d%ld", value);
3460 break;
3461 case 'Q':
3462 if (value & 1)
3463 func (stream, "<illegal reg q%ld.5>", value >> 1);
3464 else
3465 func (stream, "q%ld", value >> 1);
3466 break;
3467 case 'd':
3468 func (stream, "%ld", value);
05413229 3469 value_in_comment = value;
0313a2b8 3470 break;
6f1c2142
AM		 3471 case 'E':
3472 {
3473 /* Converts immediate 8 bit back to float value. */
3474 unsigned floatVal = (value & 0x80) << 24
3475 | (value & 0x3F) << 19
3476 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3477
3478 /* Quarter float have a maximum value of 31.0.
3479 Get floating point value multiplied by 1e7.
3480 The maximum value stays in limit of a 32-bit int. */
3481 unsigned decVal =
3482 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3483 (16 + (value & 0xF));
3484
3485 if (!(decVal % 1000000))
3486 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3487 floatVal, value & 0x80 ? '-' : ' ',
3488 decVal / 10000000,
3489 decVal % 10000000 / 1000000);
3490 else if (!(decVal % 10000))
3491 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3492 floatVal, value & 0x80 ? '-' : ' ',
3493 decVal / 10000000,
3494 decVal % 10000000 / 10000);
3495 else
3496 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3497 floatVal, value & 0x80 ? '-' : ' ',
3498 decVal / 10000000, decVal % 10000000);
3499 break;
3500 }
0313a2b8
NC		 3501 case 'k':
3502 {
3503 int from = (given & (1 << 7)) ? 32 : 16;
3504 func (stream, "%ld", from - value);
3505 }
3506 break;
8f06b2d8 3507
0313a2b8
NC		 3508 case 'f':
3509 if (value > 7)
3510 func (stream, "#%s", arm_fp_const[value & 7]);
3511 else
3512 func (stream, "f%ld", value);
3513 break;
4146fd53 3514
0313a2b8
NC		 3515 case 'w':
3516 if (width == 2)
3517 func (stream, "%s", iwmmxt_wwnames[value]);
3518 else
3519 func (stream, "%s", iwmmxt_wwssnames[value]);
3520 break;
4146fd53 3521
0313a2b8
NC		 3522 case 'g':
3523 func (stream, "%s", iwmmxt_regnames[value]);
3524 break;
3525 case 'G':
3526 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3527 break;
8f06b2d8 3528
0313a2b8 3529 case 'x':
d1aaab3c 3530 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3531 break;
8f06b2d8 3532
33399f07
MGD		 3533 case 'c':
3534 switch (value)
3535 {
3536 case 0:
3537 func (stream, "eq");
3538 break;
3539
3540 case 1:
3541 func (stream, "vs");
3542 break;
3543
3544 case 2:
3545 func (stream, "ge");
3546 break;
3547
3548 case 3:
3549 func (stream, "gt");
3550 break;
3551
3552 default:
3553 func (stream, "??");
3554 break;
3555 }
3556 break;
3557
0313a2b8
NC		 3558 case '`':
3559 c++;
3560 if (value == 0)
3561 func (stream, "%c", *c);
3562 break;
3563 case '\'':
3564 c++;
3565 if (value == ((1ul << width) - 1))
3566 func (stream, "%c", *c);
3567 break;
3568 case '?':
fe56b6ce 3569 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3570 c += 1 << width;
3571 break;
3572 default:
3573 abort ();
3574 }
3575 break;
8f06b2d8 3576
0313a2b8
NC		 3577 case 'y':
3578 case 'z':
3579 {
3580 int single = *c++ == 'y';
3581 int regno;
3582
3583 switch (*c)
3584 {
3585 case '4': /* Sm pair */
3586 case '0': /* Sm, Dm */
3587 regno = given & 0x0000000f;
3588 if (single)
3589 {
3590 regno <<= 1;
3591 regno += (given >> 5) & 1;
16980d0b 3592 }
0313a2b8
NC		 3593 else
3594 regno += ((given >> 5) & 1) << 4;
3595 break;
8f06b2d8 3596
0313a2b8
NC		 3597 case '1': /* Sd, Dd */
3598 regno = (given >> 12) & 0x0000000f;
3599 if (single)
3600 {
3601 regno <<= 1;
3602 regno += (given >> 22) & 1;
3603 }
3604 else
3605 regno += ((given >> 22) & 1) << 4;
3606 break;
8f06b2d8 3607
0313a2b8
NC		 3608 case '2': /* Sn, Dn */
3609 regno = (given >> 16) & 0x0000000f;
3610 if (single)
8f06b2d8 3611 {
0313a2b8
NC		 3612 regno <<= 1;
3613 regno += (given >> 7) & 1;
8f06b2d8 3614 }
0313a2b8
NC		 3615 else
3616 regno += ((given >> 7) & 1) << 4;
3617 break;
7df76b80 3618
0313a2b8
NC		 3619 case '3': /* List */
3620 func (stream, "{");
3621 regno = (given >> 12) & 0x0000000f;
3622 if (single)
3623 {
3624 regno <<= 1;
3625 regno += (given >> 22) & 1;
3626 }
3627 else
3628 regno += ((given >> 22) & 1) << 4;
3629 break;
a7f8487e 3630
0313a2b8
NC		 3631 default:
3632 abort ();
8f06b2d8 3633 }
a7f8487e 3634
0313a2b8
NC		 3635 func (stream, "%c%d", single ? 's' : 'd', regno);
3636
3637 if (*c == '3')
8f06b2d8 3638 {
0313a2b8 3639 int count = given & 0xff;
a7f8487e 3640
0313a2b8
NC		 3641 if (single == 0)
3642 count >>= 1;
b34976b6 3643
0313a2b8 3644 if (--count)
8f06b2d8 3645 {
0313a2b8
NC		 3646 func (stream, "-%c%d",
3647 single ? 's' : 'd',
3648 regno + count);
8f06b2d8 3649 }
0313a2b8
NC		 3650
3651 func (stream, "}");
8f06b2d8 3652 }
0313a2b8
NC		 3653 else if (*c == '4')
3654 func (stream, ", %c%d", single ? 's' : 'd',
3655 regno + 1);
3656 }
3657 break;
3658
3659 case 'L':
3660 switch (given & 0x00400100)
3661 {
3662 case 0x00000000: func (stream, "b"); break;
3663 case 0x00400000: func (stream, "h"); break;
3664 case 0x00000100: func (stream, "w"); break;
3665 case 0x00400100: func (stream, "d"); break;
3666 default:
8f06b2d8 3667 break;
0313a2b8
NC		 3668 }
3669 break;
b34976b6 3670
0313a2b8
NC		 3671 case 'Z':
3672 {
0313a2b8
NC		 3673 /* given (20, 23) | given (0, 3) */
3674 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3675 func (stream, "%d", (int) value);
0313a2b8
NC		 3676 }
3677 break;
2d447fca 3678
0313a2b8
NC		 3679 case 'l':
3680 /* This is like the 'A' operator, except that if
3681 the width field "M" is zero, then the offset is
3682 *not* multiplied by four. */
3683 {
3684 int offset = given & 0xff;
3685 int multiplier = (given & 0x00000100) ? 4 : 1;
3686
3687 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3688
05413229
NC		 3689 if (multiplier > 1)
3690 {
3691 value_in_comment = offset * multiplier;
c1e26897 3692 if (NEGATIVE_BIT_SET)
05413229
NC		 3693 value_in_comment = - value_in_comment;
3694 }
3695
0313a2b8
NC		 3696 if (offset)
3697 {
c1e26897 3698 if (PRE_BIT_SET)
0313a2b8 3699 func (stream, ", #%s%d]%s",
c1e26897 3700 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3701 offset * multiplier,
c1e26897 3702 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3703 else
3704 func (stream, "], #%s%d",
c1e26897 3705 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3706 offset * multiplier);
2d447fca 3707 }
0313a2b8
NC		 3708 else
3709 func (stream, "]");
3710 }
3711 break;
3712
3713 case 'r':
3714 {
3715 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3716 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3717 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3718 const char *rm = arm_regnames [given & 0xf];
3719 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3720
0313a2b8 3721 switch (puw_bits)
2d447fca 3722 {
0313a2b8
NC		 3723 case 1:
3724 case 3:
3725 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3726 if (imm4)
3727 func (stream, ", lsl #%d", imm4);
3728 break;
3729
3730 case 4:
3731 case 5:
3732 case 6:
3733 case 7:
3734 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3735 if (imm4 > 0)
3736 func (stream, ", lsl #%d", imm4);
3737 func (stream, "]");
3738 if (puw_bits == 5 || puw_bits == 7)
3739 func (stream, "!");
3740 break;
3741
3742 default:
3743 func (stream, "INVALID");
2d447fca 3744 }
0313a2b8
NC		 3745 }
3746 break;
2d447fca 3747
0313a2b8
NC		 3748 case 'i':
3749 {
3750 long imm5;
3751 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3752 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3753 }
0313a2b8
NC		 3754 break;
3755
3756 default:
3757 abort ();
3758 }
252b5132 3759 }
252b5132 3760 }
0313a2b8
NC		 3761 else
3762 func (stream, "%c", *c);
252b5132 3763 }
05413229
NC		 3764
3765 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3766 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3767
ff4a8d2b
NC		 3768 if (is_unpredictable)
3769 func (stream, UNPREDICTABLE_INSTRUCTION);
3770
0313a2b8 3771 return TRUE;
252b5132 3772 }
8f06b2d8 3773 return FALSE;
252b5132
RH		 3774}
3775
05413229
NC		 3776/* Decodes and prints ARM addressing modes. Returns the offset
3777 used in the address, if any, if it is worthwhile printing the
3778 offset as a hexadecimal value in a comment at the end of the
3779 line of disassembly. */
3780
3781static signed long
62b3e311
PB		 3782print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3783{
3784 void *stream = info->stream;
3785 fprintf_ftype func = info->fprintf_func;
f8b960bc 3786 bfd_vma offset = 0;
62b3e311
PB		 3787
3788 if (((given & 0x000f0000) == 0x000f0000)
3789 && ((given & 0x02000000) == 0))
3790 {
05413229 3791 offset = given & 0xfff;
62b3e311
PB		 3792
3793 func (stream, "[pc");
3794
c1e26897 3795 if (PRE_BIT_SET)
62b3e311 3796 {
26d97720
NS		 3797 /* Pre-indexed. Elide offset of positive zero when
3798 non-writeback. */
3799 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3800 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 3801
3802 if (NEGATIVE_BIT_SET)
3803 offset = -offset;
62b3e311
PB		 3804
3805 offset += pc + 8;
3806
3807 /* Cope with the possibility of write-back
3808 being used. Probably a very dangerous thing
3809 for the programmer to do, but who are we to
3810 argue ? */
26d97720 3811 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 3812 }
c1e26897 3813 else /* Post indexed. */
62b3e311 3814 {
d908c8af 3815 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 3816
c1e26897 3817 /* Ie ignore the offset. */
62b3e311
PB		 3818 offset = pc + 8;
3819 }
3820
3821 func (stream, "\t; ");
3822 info->print_address_func (offset, info);
05413229 3823 offset = 0;
62b3e311
PB		 3824 }
3825 else
3826 {
3827 func (stream, "[%s",
3828 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 3829
3830 if (PRE_BIT_SET)
62b3e311
PB		 3831 {
3832 if ((given & 0x02000000) == 0)
3833 {
26d97720 3834 /* Elide offset of positive zero when non-writeback. */
05413229 3835 offset = given & 0xfff;
26d97720 3836 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3837 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3838 }
3839 else
3840 {
26d97720 3841 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3842 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3843 }
3844
3845 func (stream, "]%s",
c1e26897 3846 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 3847 }
3848 else
3849 {
3850 if ((given & 0x02000000) == 0)
3851 {
26d97720 3852 /* Always show offset. */
05413229 3853 offset = given & 0xfff;
26d97720 3854 func (stream, "], #%s%d",
d908c8af 3855 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3856 }
3857 else
3858 {
3859 func (stream, "], %s",
c1e26897 3860 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3861 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3862 }
3863 }
84919466
MR		 3864 if (NEGATIVE_BIT_SET)
3865 offset = -offset;
62b3e311 3866 }
05413229
NC		 3867
3868 return (signed long) offset;
62b3e311
PB		 3869}
3870
16980d0b
JB		 3871/* Print one neon instruction on INFO->STREAM.
3872 Return TRUE if the instuction matched, FALSE if this is not a
3873 recognised neon instruction. */
3874
3875static bfd_boolean
3876print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3877{
3878 const struct opcode32 *insn;
3879 void *stream = info->stream;
3880 fprintf_ftype func = info->fprintf_func;
3881
3882 if (thumb)
3883 {
3884 if ((given & 0xef000000) == 0xef000000)
3885 {
0313a2b8 3886 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 3887 unsigned long bit28 = given & (1 << 28);
3888
3889 given &= 0x00ffffff;
3890 if (bit28)
3891 given |= 0xf3000000;
3892 else
3893 given |= 0xf2000000;
3894 }
3895 else if ((given & 0xff000000) == 0xf9000000)
3896 given ^= 0xf9000000 ^ 0xf4000000;
3897 else
3898 return FALSE;
3899 }
43e65147 3900
16980d0b
JB		 3901 for (insn = neon_opcodes; insn->assembler; insn++)
3902 {
3903 if ((given & insn->mask) == insn->value)
3904 {
05413229 3905 signed long value_in_comment = 0;
e2efe87d 3906 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 3907 const char *c;
3908
3909 for (c = insn->assembler; *c; c++)
3910 {
3911 if (*c == '%')
3912 {
3913 switch (*++c)
3914 {
3915 case '%':
3916 func (stream, "%%");
3917 break;
3918
e2efe87d
MGD		 3919 case 'u':
3920 if (thumb && ifthen_state)
3921 is_unpredictable = TRUE;
3922
3923 /* Fall through. */
c22aaad1
PB		 3924 case 'c':
3925 if (thumb && ifthen_state)
3926 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3927 break;
3928
16980d0b
JB		 3929 case 'A':
3930 {
43e65147 3931 static const unsigned char enc[16] =
16980d0b
JB		 3932 {
3933 0x4, 0x14, /* st4 0,1 */
3934 0x4, /* st1 2 */
3935 0x4, /* st2 3 */
3936 0x3, /* st3 4 */
3937 0x13, /* st3 5 */
3938 0x3, /* st1 6 */
3939 0x1, /* st1 7 */
3940 0x2, /* st2 8 */
3941 0x12, /* st2 9 */
3942 0x2, /* st1 10 */
3943 0, 0, 0, 0, 0
3944 };
3945 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3946 int rn = ((given >> 16) & 0xf);
3947 int rm = ((given >> 0) & 0xf);
3948 int align = ((given >> 4) & 0x3);
3949 int type = ((given >> 8) & 0xf);
3950 int n = enc[type] & 0xf;
3951 int stride = (enc[type] >> 4) + 1;
3952 int ix;
43e65147 3953
16980d0b
JB		 3954 func (stream, "{");
3955 if (stride > 1)
3956 for (ix = 0; ix != n; ix++)
3957 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3958 else if (n == 1)
3959 func (stream, "d%d", rd);
3960 else
3961 func (stream, "d%d-d%d", rd, rd + n - 1);
3962 func (stream, "}, [%s", arm_regnames[rn]);
3963 if (align)
8e560766 3964 func (stream, " :%d", 32 << align);
16980d0b
JB		 3965 func (stream, "]");
3966 if (rm == 0xd)
3967 func (stream, "!");
3968 else if (rm != 0xf)
3969 func (stream, ", %s", arm_regnames[rm]);
3970 }
3971 break;
43e65147 3972
16980d0b
JB		 3973 case 'B':
3974 {
3975 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3976 int rn = ((given >> 16) & 0xf);
3977 int rm = ((given >> 0) & 0xf);
3978 int idx_align = ((given >> 4) & 0xf);
3979 int align = 0;
3980 int size = ((given >> 10) & 0x3);
3981 int idx = idx_align >> (size + 1);
3982 int length = ((given >> 8) & 3) + 1;
3983 int stride = 1;
3984 int i;
3985
3986 if (length > 1 && size > 0)
3987 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 3988
16980d0b
JB		 3989 switch (length)
3990 {
3991 case 1:
3992 {
3993 int amask = (1 << size) - 1;
3994 if ((idx_align & (1 << size)) != 0)
3995 return FALSE;
3996 if (size > 0)
3997 {
3998 if ((idx_align & amask) == amask)
3999 align = 8 << size;
4000 else if ((idx_align & amask) != 0)
4001 return FALSE;
4002 }
4003 }
4004 break;
43e65147 4005
16980d0b
JB		 4006 case 2:
4007 if (size == 2 && (idx_align & 2) != 0)
4008 return FALSE;
4009 align = (idx_align & 1) ? 16 << size : 0;
4010 break;
43e65147 4011
16980d0b
JB		 4012 case 3:
4013 if ((size == 2 && (idx_align & 3) != 0)
4014 || (idx_align & 1) != 0)
4015 return FALSE;
4016 break;
43e65147 4017
16980d0b
JB		 4018 case 4:
4019 if (size == 2)
4020 {
4021 if ((idx_align & 3) == 3)
4022 return FALSE;
4023 align = (idx_align & 3) * 64;
4024 }
4025 else
4026 align = (idx_align & 1) ? 32 << size : 0;
4027 break;
43e65147 4028
16980d0b
JB		 4029 default:
4030 abort ();
4031 }
43e65147 4032
16980d0b
JB		 4033 func (stream, "{");
4034 for (i = 0; i < length; i++)
4035 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4036 rd + i * stride, idx);
4037 func (stream, "}, [%s", arm_regnames[rn]);
4038 if (align)
8e560766 4039 func (stream, " :%d", align);
16980d0b
JB		 4040 func (stream, "]");
4041 if (rm == 0xd)
4042 func (stream, "!");
4043 else if (rm != 0xf)
4044 func (stream, ", %s", arm_regnames[rm]);
4045 }
4046 break;
43e65147 4047
16980d0b
JB		 4048 case 'C':
4049 {
4050 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4051 int rn = ((given >> 16) & 0xf);
4052 int rm = ((given >> 0) & 0xf);
4053 int align = ((given >> 4) & 0x1);
4054 int size = ((given >> 6) & 0x3);
4055 int type = ((given >> 8) & 0x3);
4056 int n = type + 1;
4057 int stride = ((given >> 5) & 0x1);
4058 int ix;
43e65147 4059
16980d0b
JB		 4060 if (stride && (n == 1))
4061 n++;
4062 else
4063 stride++;
43e65147 4064
16980d0b
JB		 4065 func (stream, "{");
4066 if (stride > 1)
4067 for (ix = 0; ix != n; ix++)
4068 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4069 else if (n == 1)
4070 func (stream, "d%d[]", rd);
4071 else
4072 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4073 func (stream, "}, [%s", arm_regnames[rn]);
4074 if (align)
4075 {
91d6fa6a 4076 align = (8 * (type + 1)) << size;
16980d0b
JB		 4077 if (type == 3)
4078 align = (size > 1) ? align >> 1 : align;
4079 if (type == 2 || (type == 0 && !size))
8e560766 4080 func (stream, " :<bad align %d>", align);
16980d0b 4081 else
8e560766 4082 func (stream, " :%d", align);
16980d0b
JB		 4083 }
4084 func (stream, "]");
4085 if (rm == 0xd)
4086 func (stream, "!");
4087 else if (rm != 0xf)
4088 func (stream, ", %s", arm_regnames[rm]);
4089 }
4090 break;
43e65147 4091
16980d0b
JB		 4092 case 'D':
4093 {
4094 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4095 int size = (given >> 20) & 3;
4096 int reg = raw_reg & ((4 << size) - 1);
4097 int ix = raw_reg >> size >> 2;
43e65147 4098
16980d0b
JB		 4099 func (stream, "d%d[%d]", reg, ix);
4100 }
4101 break;
43e65147 4102
16980d0b 4103 case 'E':
fe56b6ce 4104 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4105 {
4106 int bits = 0;
4107 int cmode = (given >> 8) & 0xf;
4108 int op = (given >> 5) & 0x1;
4109 unsigned long value = 0, hival = 0;
4110 unsigned shift;
4111 int size = 0;
0dbde4cf 4112 int isfloat = 0;
43e65147 4113
16980d0b
JB		 4114 bits |= ((given >> 24) & 1) << 7;
4115 bits |= ((given >> 16) & 7) << 4;
4116 bits |= ((given >> 0) & 15) << 0;
43e65147 4117
16980d0b
JB		 4118 if (cmode < 8)
4119 {
4120 shift = (cmode >> 1) & 3;
fe56b6ce 4121 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4122 size = 32;
4123 }
4124 else if (cmode < 12)
4125 {
4126 shift = (cmode >> 1) & 1;
fe56b6ce 4127 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4128 size = 16;
4129 }
4130 else if (cmode < 14)
4131 {
4132 shift = (cmode & 1) + 1;
fe56b6ce 4133 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4134 value |= (1ul << (8 * shift)) - 1;
4135 size = 32;
4136 }
4137 else if (cmode == 14)
4138 {
4139 if (op)
4140 {
fe56b6ce 4141 /* Bit replication into bytes. */
16980d0b
JB		 4142 int ix;
4143 unsigned long mask;
43e65147 4144
16980d0b
JB		 4145 value = 0;
4146 hival = 0;
4147 for (ix = 7; ix >= 0; ix--)
4148 {
4149 mask = ((bits >> ix) & 1) ? 0xff : 0;
4150 if (ix <= 3)
4151 value = (value << 8) | mask;
4152 else
4153 hival = (hival << 8) | mask;
4154 }
4155 size = 64;
4156 }
4157 else
4158 {
fe56b6ce
NC		 4159 /* Byte replication. */
4160 value = (unsigned long) bits;
16980d0b
JB		 4161 size = 8;
4162 }
4163 }
4164 else if (!op)
4165 {
fe56b6ce 4166 /* Floating point encoding. */
16980d0b 4167 int tmp;
43e65147 4168
fe56b6ce
NC		 4169 value = (unsigned long) (bits & 0x7f) << 19;
4170 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4171 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4172 value |= (unsigned long) tmp << 24;
16980d0b 4173 size = 32;
0dbde4cf 4174 isfloat = 1;
16980d0b
JB		 4175 }
4176 else
4177 {
4178 func (stream, "<illegal constant %.8x:%x:%x>",
4179 bits, cmode, op);
4180 size = 32;
4181 break;
4182 }
4183 switch (size)
4184 {
4185 case 8:
4186 func (stream, "#%ld\t; 0x%.2lx", value, value);
4187 break;
43e65147 4188
16980d0b
JB		 4189 case 16:
4190 func (stream, "#%ld\t; 0x%.4lx", value, value);
4191 break;
4192
4193 case 32:
0dbde4cf
JB		 4194 if (isfloat)
4195 {
4196 unsigned char valbytes[4];
4197 double fvalue;
43e65147 4198
0dbde4cf
JB		 4199 /* Do this a byte at a time so we don't have to
4200 worry about the host's endianness. */
4201 valbytes[0] = value & 0xff;
4202 valbytes[1] = (value >> 8) & 0xff;
4203 valbytes[2] = (value >> 16) & 0xff;
4204 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4205
4206 floatformat_to_double
c1e26897
NC		 4207 (& floatformat_ieee_single_little, valbytes,
4208 & fvalue);
43e65147 4209
0dbde4cf
JB		 4210 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4211 value);
4212 }
4213 else
4e9d3b81 4214 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4215 (long) (((value & 0x80000000L) != 0)
9d82ec38 4216 ? value | ~0xffffffffL : value),
c1e26897 4217 value);
16980d0b
JB		 4218 break;
4219
4220 case 64:
4221 func (stream, "#0x%.8lx%.8lx", hival, value);
4222 break;
43e65147 4223
16980d0b
JB		 4224 default:
4225 abort ();
4226 }
4227 }
4228 break;
43e65147 4229
16980d0b
JB		 4230 case 'F':
4231 {
4232 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4233 int num = (given >> 8) & 0x3;
43e65147 4234
16980d0b
JB		 4235 if (!num)
4236 func (stream, "{d%d}", regno);
4237 else if (num + regno >= 32)
4238 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4239 else
4240 func (stream, "{d%d-d%d}", regno, regno + num);
4241 }
4242 break;
7e8e6784 4243
16980d0b
JB		 4244
4245 case '0': case '1': case '2': case '3': case '4':
4246 case '5': case '6': case '7': case '8': case '9':
4247 {
4248 int width;
4249 unsigned long value;
4250
4251 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4252
16980d0b
JB		 4253 switch (*c)
4254 {
4255 case 'r':
4256 func (stream, "%s", arm_regnames[value]);
4257 break;
4258 case 'd':
4259 func (stream, "%ld", value);
05413229 4260 value_in_comment = value;
16980d0b
JB		 4261 break;
4262 case 'e':
4263 func (stream, "%ld", (1ul << width) - value);
4264 break;
43e65147 4265
16980d0b
JB		 4266 case 'S':
4267 case 'T':
4268 case 'U':
05413229 4269 /* Various width encodings. */
16980d0b
JB		 4270 {
4271 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4272 int limit;
4273 unsigned low, high;
4274
4275 c++;
4276 if (*c >= '0' && *c <= '9')
4277 limit = *c - '0';
4278 else if (*c >= 'a' && *c <= 'f')
4279 limit = *c - 'a' + 10;
4280 else
4281 abort ();
4282 low = limit >> 2;
4283 high = limit & 3;
4284
4285 if (value < low || value > high)
4286 func (stream, "<illegal width %d>", base << value);
4287 else
4288 func (stream, "%d", base << value);
4289 }
4290 break;
4291 case 'R':
4292 if (given & (1 << 6))
4293 goto Q;
4294 /* FALLTHROUGH */
4295 case 'D':
4296 func (stream, "d%ld", value);
4297 break;
4298 case 'Q':
4299 Q:
4300 if (value & 1)
4301 func (stream, "<illegal reg q%ld.5>", value >> 1);
4302 else
4303 func (stream, "q%ld", value >> 1);
4304 break;
43e65147 4305
16980d0b
JB		 4306 case '`':
4307 c++;
4308 if (value == 0)
4309 func (stream, "%c", *c);
4310 break;
4311 case '\'':
4312 c++;
4313 if (value == ((1ul << width) - 1))
4314 func (stream, "%c", *c);
4315 break;
4316 case '?':
fe56b6ce 4317 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4318 c += 1 << width;
4319 break;
4320 default:
4321 abort ();
4322 }
4323 break;
4324
4325 default:
4326 abort ();
4327 }
4328 }
4329 }
4330 else
4331 func (stream, "%c", *c);
4332 }
05413229
NC		 4333
4334 if (value_in_comment > 32 || value_in_comment < -16)
4335 func (stream, "\t; 0x%lx", value_in_comment);
4336
e2efe87d
MGD		 4337 if (is_unpredictable)
4338 func (stream, UNPREDICTABLE_INSTRUCTION);
4339
16980d0b
JB		 4340 return TRUE;
4341 }
4342 }
4343 return FALSE;
4344}
4345
90ec0d68
MGD		 4346/* Return the name of a v7A special register. */
4347
43e65147 4348static const char *
90ec0d68
MGD		 4349banked_regname (unsigned reg)
4350{
4351 switch (reg)
4352 {
4353 case 15: return "CPSR";
43e65147 4354 case 32: return "R8_usr";
90ec0d68
MGD		 4355 case 33: return "R9_usr";
4356 case 34: return "R10_usr";
4357 case 35: return "R11_usr";
4358 case 36: return "R12_usr";
4359 case 37: return "SP_usr";
4360 case 38: return "LR_usr";
43e65147 4361 case 40: return "R8_fiq";
90ec0d68
MGD		 4362 case 41: return "R9_fiq";
4363 case 42: return "R10_fiq";
4364 case 43: return "R11_fiq";
4365 case 44: return "R12_fiq";
4366 case 45: return "SP_fiq";
4367 case 46: return "LR_fiq";
4368 case 48: return "LR_irq";
4369 case 49: return "SP_irq";
4370 case 50: return "LR_svc";
4371 case 51: return "SP_svc";
4372 case 52: return "LR_abt";
4373 case 53: return "SP_abt";
4374 case 54: return "LR_und";
4375 case 55: return "SP_und";
4376 case 60: return "LR_mon";
4377 case 61: return "SP_mon";
4378 case 62: return "ELR_hyp";
4379 case 63: return "SP_hyp";
4380 case 79: return "SPSR";
4381 case 110: return "SPSR_fiq";
4382 case 112: return "SPSR_irq";
4383 case 114: return "SPSR_svc";
4384 case 116: return "SPSR_abt";
4385 case 118: return "SPSR_und";
4386 case 124: return "SPSR_mon";
4387 case 126: return "SPSR_hyp";
4388 default: return NULL;
4389 }
4390}
4391
e797f7e0
MGD		 4392/* Return the name of the DMB/DSB option. */
4393static const char *
4394data_barrier_option (unsigned option)
4395{
4396 switch (option & 0xf)
4397 {
4398 case 0xf: return "sy";
4399 case 0xe: return "st";
4400 case 0xd: return "ld";
4401 case 0xb: return "ish";
4402 case 0xa: return "ishst";
4403 case 0x9: return "ishld";
4404 case 0x7: return "un";
4405 case 0x6: return "unst";
4406 case 0x5: return "nshld";
4407 case 0x3: return "osh";
4408 case 0x2: return "oshst";
4409 case 0x1: return "oshld";
4410 default: return NULL;
4411 }
4412}
4413
4a5329c6
ZW		 4414/* Print one ARM instruction from PC on INFO->STREAM. */
4415
4416static void
4417print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4418{
6b5d3a4d 4419 const struct opcode32 *insn;
6a51a8a8 4420 void *stream = info->stream;
6b5d3a4d 4421 fprintf_ftype func = info->fprintf_func;
b0e28b39 4422 struct arm_private_data *private_data = info->private_data;
252b5132 4423
16980d0b
JB		 4424 if (print_insn_coprocessor (pc, info, given, FALSE))
4425 return;
4426
4427 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4428 return;
4429
252b5132
RH		 4430 for (insn = arm_opcodes; insn->assembler; insn++)
4431 {
0313a2b8
NC		 4432 if ((given & insn->mask) != insn->value)
4433 continue;
823d2571
TG		 4434
4435 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4436 continue;
4437
4438 /* Special case: an instruction with all bits set in the condition field
4439 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4440 or by the catchall at the end of the table. */
4441 if ((given & 0xF0000000) != 0xF0000000
4442 || (insn->mask & 0xF0000000) == 0xF0000000
4443 || (insn->mask == 0 && insn->value == 0))
252b5132 4444 {
ff4a8d2b
NC		 4445 unsigned long u_reg = 16;
4446 unsigned long U_reg = 16;
ab8e2090 4447 bfd_boolean is_unpredictable = FALSE;
05413229 4448 signed long value_in_comment = 0;
6b5d3a4d 4449 const char *c;
b34976b6 4450
252b5132
RH		 4451 for (c = insn->assembler; *c; c++)
4452 {
4453 if (*c == '%')
4454 {
c1e26897
NC		 4455 bfd_boolean allow_unpredictable = FALSE;
4456
252b5132
RH		 4457 switch (*++c)
4458 {
4459 case '%':
4460 func (stream, "%%");
4461 break;
4462
4463 case 'a':
05413229 4464 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4465 break;
252b5132 4466
62b3e311
PB		 4467 case 'P':
4468 /* Set P address bit and use normal address
4469 printing routine. */
c1e26897 4470 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4471 break;
4472
c1e26897
NC		 4473 case 'S':
4474 allow_unpredictable = TRUE;
252b5132
RH		 4475 case 's':
4476 if ((given & 0x004f0000) == 0x004f0000)
4477 {
58efb6c0 4478 /* PC relative with immediate offset. */
f8b960bc 4479 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4480
aefd8a40
NC		 4481 if (PRE_BIT_SET)
4482 {
26d97720
NS		 4483 /* Elide positive zero offset. */
4484 if (offset || NEGATIVE_BIT_SET)
4485 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4486 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4487 else
26d97720
NS		 4488 func (stream, "[pc]\t; ");
4489 if (NEGATIVE_BIT_SET)
4490 offset = -offset;
aefd8a40
NC		 4491 info->print_address_func (offset + pc + 8, info);
4492 }
4493 else
4494 {
26d97720
NS		 4495 /* Always show the offset. */
4496 func (stream, "[pc], #%s%d",
d908c8af 4497 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4498 if (! allow_unpredictable)
4499 is_unpredictable = TRUE;
aefd8a40 4500 }
252b5132
RH		 4501 }
4502 else
4503 {
fe56b6ce
NC		 4504 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4505
b34976b6 4506 func (stream, "[%s",
252b5132 4507 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4508
c1e26897 4509 if (PRE_BIT_SET)
252b5132 4510 {
c1e26897 4511 if (IMMEDIATE_BIT_SET)
252b5132 4512 {
26d97720
NS		 4513 /* Elide offset for non-writeback
4514 positive zero. */
4515 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4516 || offset)
4517 func (stream, ", #%s%d",
4518 NEGATIVE_BIT_SET ? "-" : "", offset);
4519
4520 if (NEGATIVE_BIT_SET)
4521 offset = -offset;
945ee430 4522
fe56b6ce 4523 value_in_comment = offset;
252b5132 4524 }
945ee430 4525 else
ff4a8d2b
NC		 4526 {
4527 /* Register Offset or Register Pre-Indexed. */
4528 func (stream, ", %s%s",
4529 NEGATIVE_BIT_SET ? "-" : "",
4530 arm_regnames[given & 0xf]);
4531
4532 /* Writing back to the register that is the source/
4533 destination of the load/store is unpredictable. */
4534 if (! allow_unpredictable
4535 && WRITEBACK_BIT_SET
4536 && ((given & 0xf) == ((given >> 12) & 0xf)))
4537 is_unpredictable = TRUE;
4538 }
252b5132 4539
b34976b6 4540 func (stream, "]%s",
c1e26897 4541 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4542 }
945ee430 4543 else
252b5132 4544 {
c1e26897 4545 if (IMMEDIATE_BIT_SET)
252b5132 4546 {
945ee430 4547 /* Immediate Post-indexed. */
aefd8a40 4548 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4549 func (stream, "], #%s%d",
4550 NEGATIVE_BIT_SET ? "-" : "", offset);
4551 if (NEGATIVE_BIT_SET)
4552 offset = -offset;
fe56b6ce 4553 value_in_comment = offset;
252b5132 4554 }
945ee430 4555 else
ff4a8d2b
NC		 4556 {
4557 /* Register Post-indexed. */
4558 func (stream, "], %s%s",
4559 NEGATIVE_BIT_SET ? "-" : "",
4560 arm_regnames[given & 0xf]);
4561
4562 /* Writing back to the register that is the source/
4563 destination of the load/store is unpredictable. */
4564 if (! allow_unpredictable
4565 && (given & 0xf) == ((given >> 12) & 0xf))
4566 is_unpredictable = TRUE;
4567 }
c1e26897 4568
07a28fab
NC		 4569 if (! allow_unpredictable)
4570 {
4571 /* Writeback is automatically implied by post- addressing.
4572 Setting the W bit is unnecessary and ARM specify it as
4573 being unpredictable. */
4574 if (WRITEBACK_BIT_SET
4575 /* Specifying the PC register as the post-indexed
4576 registers is also unpredictable. */
ab8e2090
NC		 4577 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4578 is_unpredictable = TRUE;
07a28fab 4579 }
252b5132
RH		 4580 }
4581 }
4582 break;
b34976b6 4583
252b5132 4584 case 'b':
6b5d3a4d 4585 {
f8b960bc 4586 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4587 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4588 }
252b5132
RH		 4589 break;
4590
4591 case 'c':
c22aaad1
PB		 4592 if (((given >> 28) & 0xf) != 0xe)
4593 func (stream, "%s",
4594 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4595 break;
4596
4597 case 'm':
4598 {
4599 int started = 0;
4600 int reg;
4601
4602 func (stream, "{");
4603 for (reg = 0; reg < 16; reg++)
4604 if ((given & (1 << reg)) != 0)
4605 {
4606 if (started)
4607 func (stream, ", ");
4608 started = 1;
4609 func (stream, "%s", arm_regnames[reg]);
4610 }
4611 func (stream, "}");
ab8e2090
NC		 4612 if (! started)
4613 is_unpredictable = TRUE;
252b5132
RH		 4614 }
4615 break;
4616
37b37b2d 4617 case 'q':
78c66db8 4618 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4619 break;
4620
252b5132
RH		 4621 case 'o':
4622 if ((given & 0x02000000) != 0)
4623 {
a415b1cd
JB		 4624 unsigned int rotate = (given & 0xf00) >> 7;
4625 unsigned int immed = (given & 0xff);
4626 unsigned int a, i;
4627
4628 a = (((immed << (32 - rotate))
4629 | (immed >> rotate)) & 0xffffffff);
4630 /* If there is another encoding with smaller rotate,
4631 the rotate should be specified directly. */
4632 for (i = 0; i < 32; i += 2)
4633 if ((a << i | a >> (32 - i)) <= 0xff)
4634 break;
4635
4636 if (i != rotate)
4637 func (stream, "#%d, %d", immed, rotate);
4638 else
4639 func (stream, "#%d", a);
4640 value_in_comment = a;
252b5132
RH		 4641 }
4642 else
78c66db8 4643 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4644 break;
4645
4646 case 'p':
4647 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4648 {
823d2571
TG		 4649 arm_feature_set arm_ext_v6 =
4650 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4651
aefd8a40
NC		 4652 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4653 mechanism for setting PSR flag bits. They are
4654 obsolete in V6 onwards. */
823d2571
TG		 4655 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4656 arm_ext_v6))
aefd8a40
NC		 4657 func (stream, "p");
4658 }
252b5132
RH		 4659 break;
4660
4661 case 't':
4662 if ((given & 0x01200000) == 0x00200000)
4663 func (stream, "t");
4664 break;
4665
252b5132 4666 case 'A':
05413229
NC		 4667 {
4668 int offset = given & 0xff;
f02232aa 4669
05413229 4670 value_in_comment = offset * 4;
c1e26897 4671 if (NEGATIVE_BIT_SET)
05413229 4672 value_in_comment = - value_in_comment;
f02232aa 4673
05413229 4674 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4675
c1e26897 4676 if (PRE_BIT_SET)
05413229
NC		 4677 {
4678 if (offset)
fe56b6ce 4679 func (stream, ", #%d]%s",
d908c8af 4680 (int) value_in_comment,
c1e26897 4681 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4682 else
4683 func (stream, "]");
4684 }
4685 else
4686 {
4687 func (stream, "]");
f02232aa 4688
c1e26897 4689 if (WRITEBACK_BIT_SET)
05413229
NC		 4690 {
4691 if (offset)
d908c8af 4692 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4693 }
4694 else
fe56b6ce 4695 {
d908c8af 4696 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4697 value_in_comment = offset;
4698 }
05413229
NC		 4699 }
4700 }
252b5132
RH		 4701 break;
4702
077b8428
NC		 4703 case 'B':
4704 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4705 {
4706 bfd_vma address;
4707 bfd_vma offset = 0;
b34976b6 4708
c1e26897 4709 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4710 /* Is signed, hi bits should be ones. */
4711 offset = (-1) ^ 0x00ffffff;
4712
4713 /* Offset is (SignExtend(offset field)<<2). */
4714 offset += given & 0x00ffffff;
4715 offset <<= 2;
4716 address = offset + pc + 8;
b34976b6 4717
8f06b2d8
PB		 4718 if (given & 0x01000000)
4719 /* H bit allows addressing to 2-byte boundaries. */
4720 address += 2;
b1ee46c5 4721
8f06b2d8 4722 info->print_address_func (address, info);
b1ee46c5 4723 }
b1ee46c5
AH		 4724 break;
4725
252b5132 4726 case 'C':
90ec0d68
MGD		 4727 if ((given & 0x02000200) == 0x200)
4728 {
4729 const char * name;
4730 unsigned sysm = (given & 0x004f0000) >> 16;
4731
4732 sysm |= (given & 0x300) >> 4;
4733 name = banked_regname (sysm);
4734
4735 if (name != NULL)
4736 func (stream, "%s", name);
4737 else
d908c8af 4738 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4739 }
4740 else
4741 {
43e65147 4742 func (stream, "%cPSR_",
90ec0d68
MGD		 4743 (given & 0x00400000) ? 'S' : 'C');
4744 if (given & 0x80000)
4745 func (stream, "f");
4746 if (given & 0x40000)
4747 func (stream, "s");
4748 if (given & 0x20000)
4749 func (stream, "x");
4750 if (given & 0x10000)
4751 func (stream, "c");
4752 }
252b5132
RH		 4753 break;
4754
62b3e311 4755 case 'U':
43e65147 4756 if ((given & 0xf0) == 0x60)
62b3e311 4757 {
52e7f43d
RE		 4758 switch (given & 0xf)
4759 {
4760 case 0xf: func (stream, "sy"); break;
4761 default:
4762 func (stream, "#%d", (int) given & 0xf);
4763 break;
4764 }
43e65147
L		 4765 }
4766 else
52e7f43d 4767 {
e797f7e0
MGD		 4768 const char * opt = data_barrier_option (given & 0xf);
4769 if (opt != NULL)
4770 func (stream, "%s", opt);
4771 else
52e7f43d 4772 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4773 }
4774 break;
4775
b34976b6 4776 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4777 case '5': case '6': case '7': case '8': case '9':
4778 {
16980d0b
JB		 4779 int width;
4780 unsigned long value;
252b5132 4781
16980d0b 4782 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4783
252b5132
RH		 4784 switch (*c)
4785 {
ab8e2090
NC		 4786 case 'R':
4787 if (value == 15)
4788 is_unpredictable = TRUE;
4789 /* Fall through. */
16980d0b 4790 case 'r':
9eb6c0f1
MGD		 4791 case 'T':
4792 /* We want register + 1 when decoding T. */
4793 if (*c == 'T')
4794 ++value;
4795
ff4a8d2b
NC		 4796 if (c[1] == 'u')
4797 {
4798 /* Eat the 'u' character. */
4799 ++ c;
4800
4801 if (u_reg == value)
4802 is_unpredictable = TRUE;
4803 u_reg = value;
4804 }
4805 if (c[1] == 'U')
4806 {
4807 /* Eat the 'U' character. */
4808 ++ c;
4809
4810 if (U_reg == value)
4811 is_unpredictable = TRUE;
4812 U_reg = value;
4813 }
16980d0b
JB		 4814 func (stream, "%s", arm_regnames[value]);
4815 break;
4816 case 'd':
4817 func (stream, "%ld", value);
05413229 4818 value_in_comment = value;
16980d0b
JB		 4819 break;
4820 case 'b':
4821 func (stream, "%ld", value * 8);
05413229 4822 value_in_comment = value * 8;
16980d0b
JB		 4823 break;
4824 case 'W':
4825 func (stream, "%ld", value + 1);
05413229 4826 value_in_comment = value + 1;
16980d0b
JB		 4827 break;
4828 case 'x':
4829 func (stream, "0x%08lx", value);
4830
4831 /* Some SWI instructions have special
4832 meanings. */
4833 if ((given & 0x0fffffff) == 0x0FF00000)
4834 func (stream, "\t; IMB");
4835 else if ((given & 0x0fffffff) == 0x0FF00001)
4836 func (stream, "\t; IMBRange");
4837 break;
4838 case 'X':
4839 func (stream, "%01lx", value & 0xf);
05413229 4840 value_in_comment = value;
252b5132
RH		 4841 break;
4842 case '`':
4843 c++;
16980d0b 4844 if (value == 0)
252b5132
RH		 4845 func (stream, "%c", *c);
4846 break;
4847 case '\'':
4848 c++;
16980d0b 4849 if (value == ((1ul << width) - 1))
252b5132
RH		 4850 func (stream, "%c", *c);
4851 break;
4852 case '?':
fe56b6ce 4853 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 4854 c += 1 << width;
252b5132
RH		 4855 break;
4856 default:
4857 abort ();
4858 }
4859 break;
4860
0dd132b6
NC		 4861 case 'e':
4862 {
4863 int imm;
4864
4865 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4866 func (stream, "%d", imm);
fe56b6ce 4867 value_in_comment = imm;
0dd132b6
NC		 4868 }
4869 break;
4870
0a003adc
ZW		 4871 case 'E':
4872 /* LSB and WIDTH fields of BFI or BFC. The machine-
4873 language instruction encodes LSB and MSB. */
4874 {
4875 long msb = (given & 0x001f0000) >> 16;
4876 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 4877 long w = msb - lsb + 1;
fe56b6ce 4878
91d6fa6a
NC		 4879 if (w > 0)
4880 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 4881 else
4882 func (stream, "(invalid: %lu:%lu)", lsb, msb);
4883 }
4884 break;
4885
90ec0d68
MGD		 4886 case 'R':
4887 /* Get the PSR/banked register name. */
4888 {
4889 const char * name;
4890 unsigned sysm = (given & 0x004f0000) >> 16;
4891
4892 sysm |= (given & 0x300) >> 4;
4893 name = banked_regname (sysm);
4894
4895 if (name != NULL)
4896 func (stream, "%s", name);
4897 else
d908c8af 4898 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4899 }
4900 break;
4901
0a003adc
ZW		 4902 case 'V':
4903 /* 16-bit unsigned immediate from a MOVT or MOVW
4904 instruction, encoded in bits 0:11 and 15:19. */
4905 {
4906 long hi = (given & 0x000f0000) >> 4;
4907 long lo = (given & 0x00000fff);
4908 long imm16 = hi | lo;
fe56b6ce
NC		 4909
4910 func (stream, "#%lu", imm16);
4911 value_in_comment = imm16;
0a003adc
ZW		 4912 }
4913 break;
4914
252b5132
RH		 4915 default:
4916 abort ();
4917 }
4918 }
4919 }
4920 else
4921 func (stream, "%c", *c);
4922 }
05413229
NC		 4923
4924 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4925 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 4926
4927 if (is_unpredictable)
4928 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 4929
4a5329c6 4930 return;
252b5132
RH		 4931 }
4932 }
4933 abort ();
4934}
4935
4a5329c6 4936/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 4937
4a5329c6
ZW		 4938static void
4939print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4940{
6b5d3a4d 4941 const struct opcode16 *insn;
6a51a8a8
AM		 4942 void *stream = info->stream;
4943 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 4944
4945 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 4946 if ((given & insn->mask) == insn->value)
4947 {
05413229 4948 signed long value_in_comment = 0;
6b5d3a4d 4949 const char *c = insn->assembler;
05413229 4950
c19d1205
ZW		 4951 for (; *c; c++)
4952 {
4953 int domaskpc = 0;
4954 int domasklr = 0;
4955
4956 if (*c != '%')
4957 {
4958 func (stream, "%c", *c);
4959 continue;
4960 }
252b5132 4961
c19d1205
ZW		 4962 switch (*++c)
4963 {
4964 case '%':
4965 func (stream, "%%");
4966 break;
b34976b6 4967
c22aaad1
PB		 4968 case 'c':
4969 if (ifthen_state)
4970 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4971 break;
4972
4973 case 'C':
4974 if (ifthen_state)
4975 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4976 else
4977 func (stream, "s");
4978 break;
4979
4980 case 'I':
4981 {
4982 unsigned int tmp;
4983
4984 ifthen_next_state = given & 0xff;
4985 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
4986 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
4987 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
4988 }
4989 break;
4990
4991 case 'x':
4992 if (ifthen_next_state)
4993 func (stream, "\t; unpredictable branch in IT block\n");
4994 break;
4995
4996 case 'X':
4997 if (ifthen_state)
4998 func (stream, "\t; unpredictable <IT:%s>",
4999 arm_conditional[IFTHEN_COND]);
5000 break;
5001
c19d1205
ZW		 5002 case 'S':
5003 {
5004 long reg;
5005
5006 reg = (given >> 3) & 0x7;
5007 if (given & (1 << 6))
5008 reg += 8;
4f3c3dbb 5009
c19d1205
ZW		 5010 func (stream, "%s", arm_regnames[reg]);
5011 }
5012 break;
baf0cc5e 5013
c19d1205 5014 case 'D':
4f3c3dbb 5015 {
c19d1205
ZW		 5016 long reg;
5017
5018 reg = given & 0x7;
5019 if (given & (1 << 7))
5020 reg += 8;
5021
5022 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5023 }
c19d1205
ZW		 5024 break;
5025
5026 case 'N':
5027 if (given & (1 << 8))
5028 domasklr = 1;
5029 /* Fall through. */
5030 case 'O':
5031 if (*c == 'O' && (given & (1 << 8)))
5032 domaskpc = 1;
5033 /* Fall through. */
5034 case 'M':
5035 {
5036 int started = 0;
5037 int reg;
5038
5039 func (stream, "{");
5040
5041 /* It would be nice if we could spot
5042 ranges, and generate the rS-rE format: */
5043 for (reg = 0; (reg < 8); reg++)
5044 if ((given & (1 << reg)) != 0)
5045 {
5046 if (started)
5047 func (stream, ", ");
5048 started = 1;
5049 func (stream, "%s", arm_regnames[reg]);
5050 }
5051
5052 if (domasklr)
5053 {
5054 if (started)
5055 func (stream, ", ");
5056 started = 1;
d908c8af 5057 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5058 }
5059
5060 if (domaskpc)
5061 {
5062 if (started)
5063 func (stream, ", ");
d908c8af 5064 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5065 }
5066
5067 func (stream, "}");
5068 }
5069 break;
5070
4547cb56
NC		 5071 case 'W':
5072 /* Print writeback indicator for a LDMIA. We are doing a
5073 writeback if the base register is not in the register
5074 mask. */
5075 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5076 func (stream, "!");
5077 break;
5078
c19d1205
ZW		 5079 case 'b':
5080 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5081 {
5082 bfd_vma address = (pc + 4
5083 + ((given & 0x00f8) >> 2)
5084 + ((given & 0x0200) >> 3));
5085 info->print_address_func (address, info);
5086 }
5087 break;
5088
5089 case 's':
5090 /* Right shift immediate -- bits 6..10; 1-31 print
5091 as themselves, 0 prints as 32. */
5092 {
5093 long imm = (given & 0x07c0) >> 6;
5094 if (imm == 0)
5095 imm = 32;
0fd3a477 5096 func (stream, "#%ld", imm);
c19d1205
ZW		 5097 }
5098 break;
5099
5100 case '0': case '1': case '2': case '3': case '4':
5101 case '5': case '6': case '7': case '8': case '9':
5102 {
5103 int bitstart = *c++ - '0';
5104 int bitend = 0;
5105
5106 while (*c >= '0' && *c <= '9')
5107 bitstart = (bitstart * 10) + *c++ - '0';
5108
5109 switch (*c)
5110 {
5111 case '-':
5112 {
f8b960bc 5113 bfd_vma reg;
c19d1205
ZW		 5114
5115 c++;
5116 while (*c >= '0' && *c <= '9')
5117 bitend = (bitend * 10) + *c++ - '0';
5118 if (!bitend)
5119 abort ();
5120 reg = given >> bitstart;
5121 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5122
c19d1205
ZW		 5123 switch (*c)
5124 {
5125 case 'r':
5126 func (stream, "%s", arm_regnames[reg]);
5127 break;
5128
5129 case 'd':
d908c8af 5130 func (stream, "%ld", (long) reg);
05413229 5131 value_in_comment = reg;
c19d1205
ZW		 5132 break;
5133
5134 case 'H':
d908c8af 5135 func (stream, "%ld", (long) (reg << 1));
05413229 5136 value_in_comment = reg << 1;
c19d1205
ZW		 5137 break;
5138
5139 case 'W':
d908c8af 5140 func (stream, "%ld", (long) (reg << 2));
05413229 5141 value_in_comment = reg << 2;
c19d1205
ZW		 5142 break;
5143
5144 case 'a':
5145 /* PC-relative address -- the bottom two
5146 bits of the address are dropped
5147 before the calculation. */
5148 info->print_address_func
5149 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5150 value_in_comment = 0;
c19d1205
ZW		 5151 break;
5152
5153 case 'x':
d908c8af 5154 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5155 break;
5156
c19d1205
ZW		 5157 case 'B':
5158 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5159 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5160 value_in_comment = 0;
c19d1205
ZW		 5161 break;
5162
5163 case 'c':
c22aaad1 5164 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5165 break;
5166
5167 default:
5168 abort ();
5169 }
5170 }
5171 break;
5172
5173 case '\'':
5174 c++;
5175 if ((given & (1 << bitstart)) != 0)
5176 func (stream, "%c", *c);
5177 break;
5178
5179 case '?':
5180 ++c;
5181 if ((given & (1 << bitstart)) != 0)
5182 func (stream, "%c", *c++);
5183 else
5184 func (stream, "%c", *++c);
5185 break;
5186
5187 default:
5188 abort ();
5189 }
5190 }
5191 break;
5192
5193 default:
5194 abort ();
5195 }
5196 }
05413229
NC		 5197
5198 if (value_in_comment > 32 || value_in_comment < -16)
5199 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5200 return;
c19d1205
ZW		 5201 }
5202
5203 /* No match. */
5204 abort ();
5205}
5206
62b3e311 5207/* Return the name of an V7M special register. */
fe56b6ce 5208
62b3e311
PB		 5209static const char *
5210psr_name (int regno)
5211{
5212 switch (regno)
5213 {
5214 case 0: return "APSR";
5215 case 1: return "IAPSR";
5216 case 2: return "EAPSR";
5217 case 3: return "PSR";
5218 case 5: return "IPSR";
5219 case 6: return "EPSR";
5220 case 7: return "IEPSR";
5221 case 8: return "MSP";
5222 case 9: return "PSP";
5223 case 16: return "PRIMASK";
5224 case 17: return "BASEPRI";
00bbc0bd 5225 case 18: return "BASEPRI_MAX";
62b3e311
PB		 5226 case 19: return "FAULTMASK";
5227 case 20: return "CONTROL";
5228 default: return "<unknown>";
5229 }
5230}
5231
4a5329c6
ZW		 5232/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5233
5234static void
5235print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5236{
6b5d3a4d 5237 const struct opcode32 *insn;
c19d1205
ZW		 5238 void *stream = info->stream;
5239 fprintf_ftype func = info->fprintf_func;
5240
16980d0b
JB		 5241 if (print_insn_coprocessor (pc, info, given, TRUE))
5242 return;
5243
5244 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5245 return;
5246
c19d1205
ZW		 5247 for (insn = thumb32_opcodes; insn->assembler; insn++)
5248 if ((given & insn->mask) == insn->value)
5249 {
ff4a8d2b 5250 bfd_boolean is_unpredictable = FALSE;
05413229 5251 signed long value_in_comment = 0;
6b5d3a4d 5252 const char *c = insn->assembler;
05413229 5253
c19d1205
ZW		 5254 for (; *c; c++)
5255 {
5256 if (*c != '%')
5257 {
5258 func (stream, "%c", *c);
5259 continue;
5260 }
5261
5262 switch (*++c)
5263 {
5264 case '%':
5265 func (stream, "%%");
5266 break;
5267
c22aaad1
PB		 5268 case 'c':
5269 if (ifthen_state)
5270 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5271 break;
5272
5273 case 'x':
5274 if (ifthen_next_state)
5275 func (stream, "\t; unpredictable branch in IT block\n");
5276 break;
5277
5278 case 'X':
5279 if (ifthen_state)
5280 func (stream, "\t; unpredictable <IT:%s>",
5281 arm_conditional[IFTHEN_COND]);
5282 break;
5283
c19d1205
ZW		 5284 case 'I':
5285 {
5286 unsigned int imm12 = 0;
fe56b6ce 5287
c19d1205
ZW		 5288 imm12 |= (given & 0x000000ffu);
5289 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5290 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5291 func (stream, "#%u", imm12);
5292 value_in_comment = imm12;
c19d1205
ZW		 5293 }
5294 break;
5295
5296 case 'M':
5297 {
5298 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5299
c19d1205
ZW		 5300 bits |= (given & 0x000000ffu);
5301 bits |= (given & 0x00007000u) >> 4;
5302 bits |= (given & 0x04000000u) >> 15;
5303 imm8 = (bits & 0x0ff);
5304 mod = (bits & 0xf00) >> 8;
5305 switch (mod)
5306 {
5307 case 0: imm = imm8; break;
c1e26897
NC		 5308 case 1: imm = ((imm8 << 16) | imm8); break;
5309 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5310 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5311 default:
5312 mod = (bits & 0xf80) >> 7;
5313 imm8 = (bits & 0x07f) | 0x80;
5314 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5315 }
fe56b6ce
NC		 5316 func (stream, "#%u", imm);
5317 value_in_comment = imm;
c19d1205
ZW		 5318 }
5319 break;
43e65147 5320
c19d1205
ZW		 5321 case 'J':
5322 {
5323 unsigned int imm = 0;
fe56b6ce 5324
c19d1205
ZW		 5325 imm |= (given & 0x000000ffu);
5326 imm |= (given & 0x00007000u) >> 4;
5327 imm |= (given & 0x04000000u) >> 15;
5328 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5329 func (stream, "#%u", imm);
5330 value_in_comment = imm;
c19d1205
ZW		 5331 }
5332 break;
5333
5334 case 'K':
5335 {
5336 unsigned int imm = 0;
fe56b6ce 5337
c19d1205
ZW		 5338 imm |= (given & 0x000f0000u) >> 16;
5339 imm |= (given & 0x00000ff0u) >> 0;
5340 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5341 func (stream, "#%u", imm);
5342 value_in_comment = imm;
c19d1205
ZW		 5343 }
5344 break;
5345
74db7efb
NC		 5346 case 'H':
5347 {
5348 unsigned int imm = 0;
5349
5350 imm |= (given & 0x000f0000u) >> 4;
5351 imm |= (given & 0x00000fffu) >> 0;
5352 func (stream, "#%u", imm);
5353 value_in_comment = imm;
5354 }
5355 break;
5356
90ec0d68
MGD		 5357 case 'V':
5358 {
5359 unsigned int imm = 0;
5360
5361 imm |= (given & 0x00000fffu);
5362 imm |= (given & 0x000f0000u) >> 4;
5363 func (stream, "#%u", imm);
5364 value_in_comment = imm;
5365 }
5366 break;
5367
c19d1205
ZW		 5368 case 'S':
5369 {
5370 unsigned int reg = (given & 0x0000000fu);
5371 unsigned int stp = (given & 0x00000030u) >> 4;
5372 unsigned int imm = 0;
5373 imm |= (given & 0x000000c0u) >> 6;
5374 imm |= (given & 0x00007000u) >> 10;
5375
5376 func (stream, "%s", arm_regnames[reg]);
5377 switch (stp)
5378 {
5379 case 0:
5380 if (imm > 0)
5381 func (stream, ", lsl #%u", imm);
5382 break;
5383
5384 case 1:
5385 if (imm == 0)
5386 imm = 32;
5387 func (stream, ", lsr #%u", imm);
5388 break;
5389
5390 case 2:
5391 if (imm == 0)
5392 imm = 32;
5393 func (stream, ", asr #%u", imm);
5394 break;
5395
5396 case 3:
5397 if (imm == 0)
5398 func (stream, ", rrx");
5399 else
5400 func (stream, ", ror #%u", imm);
5401 }
5402 }
5403 break;
5404
5405 case 'a':
5406 {
5407 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5408 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5409 unsigned int op = (given & 0x00000f00) >> 8;
5410 unsigned int i12 = (given & 0x00000fff);
5411 unsigned int i8 = (given & 0x000000ff);
5412 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5413 bfd_vma offset = 0;
c19d1205
ZW		 5414
5415 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5416 if (U) /* 12-bit positive immediate offset. */
5417 {
5418 offset = i12;
5419 if (Rn != 15)
5420 value_in_comment = offset;
5421 }
5422 else if (Rn == 15) /* 12-bit negative immediate offset. */
5423 offset = - (int) i12;
5424 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5425 {
5426 unsigned int Rm = (i8 & 0x0f);
5427 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5428
c19d1205
ZW		 5429 func (stream, ", %s", arm_regnames[Rm]);
5430 if (sh)
5431 func (stream, ", lsl #%u", sh);
5432 func (stream, "]");
5433 break;
5434 }
5435 else switch (op)
5436 {
05413229 5437 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5438 offset = i8;
5439 break;
5440
05413229 5441 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5442 offset = -i8;
5443 break;
5444
05413229 5445 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5446 offset = i8;
5447 writeback = TRUE;
5448 break;
5449
05413229 5450 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5451 offset = -i8;
5452 writeback = TRUE;
5453 break;
5454
05413229 5455 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5456 offset = i8;
5457 postind = TRUE;
5458 break;
5459
05413229 5460 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5461 offset = -i8;
5462 postind = TRUE;
5463 break;
5464
5465 default:
5466 func (stream, ", <undefined>]");
5467 goto skip;
5468 }
5469
5470 if (postind)
d908c8af 5471 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5472 else
5473 {
5474 if (offset)
d908c8af 5475 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5476 func (stream, writeback ? "]!" : "]");
5477 }
5478
5479 if (Rn == 15)
5480 {
5481 func (stream, "\t; ");
5482 info->print_address_func (((pc + 4) & ~3) + offset, info);
5483 }
5484 }
5485 skip:
5486 break;
5487
5488 case 'A':
5489 {
c1e26897
NC		 5490 unsigned int U = ! NEGATIVE_BIT_SET;
5491 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5492 unsigned int Rn = (given & 0x000f0000) >> 16;
5493 unsigned int off = (given & 0x000000ff);
5494
5495 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5496
5497 if (PRE_BIT_SET)
c19d1205
ZW		 5498 {
5499 if (off || !U)
05413229
NC		 5500 {
5501 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5502 value_in_comment = off * 4 * U ? 1 : -1;
5503 }
c19d1205
ZW		 5504 func (stream, "]");
5505 if (W)
5506 func (stream, "!");
5507 }
5508 else
5509 {
5510 func (stream, "], ");
5511 if (W)
05413229
NC		 5512 {
5513 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5514 value_in_comment = off * 4 * U ? 1 : -1;
5515 }
c19d1205 5516 else
fe56b6ce
NC		 5517 {
5518 func (stream, "{%u}", off);
5519 value_in_comment = off;
5520 }
c19d1205
ZW		 5521 }
5522 }
5523 break;
5524
5525 case 'w':
5526 {
5527 unsigned int Sbit = (given & 0x01000000) >> 24;
5528 unsigned int type = (given & 0x00600000) >> 21;
05413229 5529
c19d1205
ZW		 5530 switch (type)
5531 {
5532 case 0: func (stream, Sbit ? "sb" : "b"); break;
5533 case 1: func (stream, Sbit ? "sh" : "h"); break;
5534 case 2:
5535 if (Sbit)
5536 func (stream, "??");
5537 break;
5538 case 3:
5539 func (stream, "??");
5540 break;
5541 }
5542 }
5543 break;
5544
5545 case 'm':
5546 {
5547 int started = 0;
5548 int reg;
5549
5550 func (stream, "{");
5551 for (reg = 0; reg < 16; reg++)
5552 if ((given & (1 << reg)) != 0)
5553 {
5554 if (started)
5555 func (stream, ", ");
5556 started = 1;
5557 func (stream, "%s", arm_regnames[reg]);
5558 }
5559 func (stream, "}");
5560 }
5561 break;
5562
5563 case 'E':
5564 {
5565 unsigned int msb = (given & 0x0000001f);
5566 unsigned int lsb = 0;
fe56b6ce 5567
c19d1205
ZW		 5568 lsb |= (given & 0x000000c0u) >> 6;
5569 lsb |= (given & 0x00007000u) >> 10;
5570 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5571 }
5572 break;
5573
5574 case 'F':
5575 {
5576 unsigned int width = (given & 0x0000001f) + 1;
5577 unsigned int lsb = 0;
fe56b6ce 5578
c19d1205
ZW		 5579 lsb |= (given & 0x000000c0u) >> 6;
5580 lsb |= (given & 0x00007000u) >> 10;
5581 func (stream, "#%u, #%u", lsb, width);
5582 }
5583 break;
5584
5585 case 'b':
5586 {
5587 unsigned int S = (given & 0x04000000u) >> 26;
5588 unsigned int J1 = (given & 0x00002000u) >> 13;
5589 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5590 bfd_vma offset = 0;
c19d1205
ZW		 5591
5592 offset |= !S << 20;
5593 offset |= J2 << 19;
5594 offset |= J1 << 18;
5595 offset |= (given & 0x003f0000) >> 4;
5596 offset |= (given & 0x000007ff) << 1;
5597 offset -= (1 << 20);
5598
5599 info->print_address_func (pc + 4 + offset, info);
5600 }
5601 break;
5602
5603 case 'B':
5604 {
5605 unsigned int S = (given & 0x04000000u) >> 26;
5606 unsigned int I1 = (given & 0x00002000u) >> 13;
5607 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5608 bfd_vma offset = 0;
c19d1205
ZW		 5609
5610 offset |= !S << 24;
5611 offset |= !(I1 ^ S) << 23;
5612 offset |= !(I2 ^ S) << 22;
5613 offset |= (given & 0x03ff0000u) >> 4;
5614 offset |= (given & 0x000007ffu) << 1;
5615 offset -= (1 << 24);
36b0c57d 5616 offset += pc + 4;
c19d1205 5617
36b0c57d
PB		 5618 /* BLX target addresses are always word aligned. */
5619 if ((given & 0x00001000u) == 0)
5620 offset &= ~2u;
5621
5622 info->print_address_func (offset, info);
c19d1205
ZW		 5623 }
5624 break;
5625
5626 case 's':
5627 {
5628 unsigned int shift = 0;
fe56b6ce 5629
c19d1205
ZW		 5630 shift |= (given & 0x000000c0u) >> 6;
5631 shift |= (given & 0x00007000u) >> 10;
c1e26897 5632 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5633 func (stream, ", asr #%u", shift);
5634 else if (shift)
5635 func (stream, ", lsl #%u", shift);
5636 /* else print nothing - lsl #0 */
5637 }
5638 break;
5639
5640 case 'R':
5641 {
5642 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5643
c19d1205
ZW		 5644 if (rot)
5645 func (stream, ", ror #%u", rot * 8);
5646 }
5647 break;
5648
62b3e311 5649 case 'U':
43e65147 5650 if ((given & 0xf0) == 0x60)
62b3e311 5651 {
52e7f43d
RE		 5652 switch (given & 0xf)
5653 {
5654 case 0xf: func (stream, "sy"); break;
5655 default:
5656 func (stream, "#%d", (int) given & 0xf);
5657 break;
5658 }
62b3e311 5659 }
43e65147 5660 else
52e7f43d 5661 {
e797f7e0
MGD		 5662 const char * opt = data_barrier_option (given & 0xf);
5663 if (opt != NULL)
5664 func (stream, "%s", opt);
5665 else
5666 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5667 }
62b3e311
PB		 5668 break;
5669
5670 case 'C':
5671 if ((given & 0xff) == 0)
5672 {
5673 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5674 if (given & 0x800)
5675 func (stream, "f");
5676 if (given & 0x400)
5677 func (stream, "s");
5678 if (given & 0x200)
5679 func (stream, "x");
5680 if (given & 0x100)
5681 func (stream, "c");
5682 }
90ec0d68
MGD		 5683 else if ((given & 0x20) == 0x20)
5684 {
5685 char const* name;
5686 unsigned sysm = (given & 0xf00) >> 8;
5687
5688 sysm |= (given & 0x30);
5689 sysm |= (given & 0x00100000) >> 14;
5690 name = banked_regname (sysm);
43e65147 5691
90ec0d68
MGD		 5692 if (name != NULL)
5693 func (stream, "%s", name);
5694 else
d908c8af 5695 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5696 }
62b3e311
PB		 5697 else
5698 {
d908c8af 5699 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5700 }
5701 break;
5702
5703 case 'D':
90ec0d68
MGD		 5704 if (((given & 0xff) == 0)
5705 || ((given & 0x20) == 0x20))
5706 {
5707 char const* name;
5708 unsigned sm = (given & 0xf0000) >> 16;
5709
5710 sm |= (given & 0x30);
5711 sm |= (given & 0x00100000) >> 14;
5712 name = banked_regname (sm);
5713
5714 if (name != NULL)
5715 func (stream, "%s", name);
5716 else
d908c8af 5717 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5718 }
62b3e311 5719 else
d908c8af 5720 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5721 break;
5722
c19d1205
ZW		 5723 case '0': case '1': case '2': case '3': case '4':
5724 case '5': case '6': case '7': case '8': case '9':
5725 {
16980d0b
JB		 5726 int width;
5727 unsigned long val;
c19d1205 5728
16980d0b 5729 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5730
c19d1205
ZW		 5731 switch (*c)
5732 {
05413229
NC		 5733 case 'd':
5734 func (stream, "%lu", val);
5735 value_in_comment = val;
5736 break;
ff4a8d2b 5737
f0fba320
RL		 5738 case 'D':
5739 func (stream, "%lu", val + 1);
5740 value_in_comment = val + 1;
5741 break;
5742
05413229
NC		 5743 case 'W':
5744 func (stream, "%lu", val * 4);
5745 value_in_comment = val * 4;
5746 break;
ff4a8d2b 5747
dd5181d5
KT		 5748 case 'S':
5749 if (val == 13)
5750 is_unpredictable = TRUE;
5751 /* Fall through. */
ff4a8d2b
NC		 5752 case 'R':
5753 if (val == 15)
5754 is_unpredictable = TRUE;
5755 /* Fall through. */
5756 case 'r':
5757 func (stream, "%s", arm_regnames[val]);
5758 break;
c19d1205
ZW		 5759
5760 case 'c':
c22aaad1 5761 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5762 break;
5763
5764 case '\'':
c19d1205 5765 c++;
16980d0b
JB		 5766 if (val == ((1ul << width) - 1))
5767 func (stream, "%c", *c);
c19d1205 5768 break;
43e65147 5769
c19d1205 5770 case '`':
c19d1205 5771 c++;
16980d0b
JB		 5772 if (val == 0)
5773 func (stream, "%c", *c);
c19d1205
ZW		 5774 break;
5775
5776 case '?':
fe56b6ce 5777 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 5778 c += 1 << width;
c19d1205 5779 break;
43e65147 5780
0bb027fd
RR		 5781 case 'x':
5782 func (stream, "0x%lx", val & 0xffffffffUL);
5783 break;
c19d1205
ZW		 5784
5785 default:
5786 abort ();
5787 }
5788 }
5789 break;
5790
32a94698
NC		 5791 case 'L':
5792 /* PR binutils/12534
5793 If we have a PC relative offset in an LDRD or STRD
5794 instructions then display the decoded address. */
5795 if (((given >> 16) & 0xf) == 0xf)
5796 {
5797 bfd_vma offset = (given & 0xff) * 4;
5798
5799 if ((given & (1 << 23)) == 0)
5800 offset = - offset;
5801 func (stream, "\t; ");
5802 info->print_address_func ((pc & ~3) + 4 + offset, info);
5803 }
5804 break;
5805
c19d1205
ZW		 5806 default:
5807 abort ();
5808 }
5809 }
05413229
NC		 5810
5811 if (value_in_comment > 32 || value_in_comment < -16)
5812 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 5813
5814 if (is_unpredictable)
5815 func (stream, UNPREDICTABLE_INSTRUCTION);
5816
4a5329c6 5817 return;
c19d1205 5818 }
252b5132 5819
58efb6c0 5820 /* No match. */
252b5132
RH		 5821 abort ();
5822}
5823
e821645d
DJ		 5824/* Print data bytes on INFO->STREAM. */
5825
5826static void
fe56b6ce
NC		 5827print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5828 struct disassemble_info *info,
e821645d
DJ		 5829 long given)
5830{
5831 switch (info->bytes_per_chunk)
5832 {
5833 case 1:
5834 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5835 break;
5836 case 2:
5837 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5838 break;
5839 case 4:
5840 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5841 break;
5842 default:
5843 abort ();
5844 }
5845}
5846
22a398e1 5847/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 5848 being displayed in symbol relative addresses.
5849
5850 Also disallow private symbol, with __tagsym$$ prefix,
5851 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 5852
5853bfd_boolean
5854arm_symbol_is_valid (asymbol * sym,
5855 struct disassemble_info * info ATTRIBUTE_UNUSED)
5856{
5857 const char * name;
43e65147 5858
22a398e1
NC		 5859 if (sym == NULL)
5860 return FALSE;
5861
5862 name = bfd_asymbol_name (sym);
5863
d8282f0e 5864 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 5865}
5866
58efb6c0 5867/* Parse an individual disassembler option. */
baf0cc5e 5868
a3d9c82d 5869void
4a5329c6 5870parse_arm_disassembler_option (char *option)
dd92f639 5871{
01c7f630 5872 if (option == NULL)
dd92f639 5873 return;
b34976b6 5874
0112cd26 5875 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 5876 {
58efb6c0 5877 int i;
b34976b6 5878
01c7f630 5879 option += 10;
58efb6c0
NC		 5880
5881 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 5882 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 5883 {
5884 regname_selected = i;
5885 break;
5886 }
b34976b6 5887
58efb6c0 5888 if (i < 0)
31e0f3cd 5889 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5890 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 5891 }
0112cd26 5892 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 5893 force_thumb = 1;
0112cd26 5894 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 5895 force_thumb = 0;
dd92f639 5896 else
31e0f3cd 5897 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5898 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 5899
dd92f639
NC		 5900 return;
5901}
5902
31e0f3cd
NC		 5903/* Parse the string of disassembler options, spliting it at whitespaces
5904 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 5905
01c7f630 5906static void
4a5329c6 5907parse_disassembler_options (char *options)
01c7f630 5908{
01c7f630
NC		 5909 if (options == NULL)
5910 return;
5911
31e0f3cd 5912 while (*options)
01c7f630 5913 {
31e0f3cd
NC		 5914 parse_arm_disassembler_option (options);
5915
5916 /* Skip forward to next seperator. */
5917 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5918 ++ options;
5919 /* Skip forward past seperators. */
5920 while (ISSPACE (*options) || (*options == ','))
43e65147 5921 ++ options;
01c7f630 5922 }
01c7f630
NC		 5923}
5924
c22aaad1
PB		 5925/* Search back through the insn stream to determine if this instruction is
5926 conditionally executed. */
fe56b6ce 5927
c22aaad1 5928static void
fe56b6ce
NC		 5929find_ifthen_state (bfd_vma pc,
5930 struct disassemble_info *info,
c22aaad1
PB		 5931 bfd_boolean little)
5932{
5933 unsigned char b[2];
5934 unsigned int insn;
5935 int status;
5936 /* COUNT is twice the number of instructions seen. It will be odd if we
5937 just crossed an instruction boundary. */
5938 int count;
5939 int it_count;
5940 unsigned int seen_it;
5941 bfd_vma addr;
5942
5943 ifthen_address = pc;
5944 ifthen_state = 0;
5945
5946 addr = pc;
5947 count = 1;
5948 it_count = 0;
5949 seen_it = 0;
5950 /* Scan backwards looking for IT instructions, keeping track of where
5951 instruction boundaries are. We don't know if something is actually an
5952 IT instruction until we find a definite instruction boundary. */
5953 for (;;)
5954 {
fe56b6ce 5955 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 5956 {
5957 /* A symbol must be on an instruction boundary, and will not
5958 be within an IT block. */
5959 if (seen_it && (count & 1))
5960 break;
5961
5962 return;
5963 }
5964 addr -= 2;
fe56b6ce 5965 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 5966 if (status)
5967 return;
5968
5969 if (little)
5970 insn = (b[0]) | (b[1] << 8);
5971 else
5972 insn = (b[1]) | (b[0] << 8);
5973 if (seen_it)
5974 {
5975 if ((insn & 0xf800) < 0xe800)
5976 {
5977 /* Addr + 2 is an instruction boundary. See if this matches
5978 the expected boundary based on the position of the last
5979 IT candidate. */
5980 if (count & 1)
5981 break;
5982 seen_it = 0;
5983 }
5984 }
5985 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
5986 {
5987 /* This could be an IT instruction. */
5988 seen_it = insn;
5989 it_count = count >> 1;
5990 }
5991 if ((insn & 0xf800) >= 0xe800)
5992 count++;
5993 else
5994 count = (count + 2) | 1;
5995 /* IT blocks contain at most 4 instructions. */
5996 if (count >= 8 && !seen_it)
5997 return;
5998 }
5999 /* We found an IT instruction. */
6000 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6001 if ((ifthen_state & 0xf) == 0)
6002 ifthen_state = 0;
6003}
6004
b0e28b39
DJ		 6005/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6006 mapping symbol. */
6007
6008static int
6009is_mapping_symbol (struct disassemble_info *info, int n,
6010 enum map_type *map_type)
6011{
6012 const char *name;
6013
6014 name = bfd_asymbol_name (info->symtab[n]);
6015 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6016 && (name[2] == 0 || name[2] == '.'))
6017 {
6018 *map_type = ((name[1] == 'a') ? MAP_ARM
6019 : (name[1] == 't') ? MAP_THUMB
6020 : MAP_DATA);
6021 return TRUE;
6022 }
6023
6024 return FALSE;
6025}
6026
6027/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6028 Returns nonzero if *MAP_TYPE was set. */
6029
6030static int
6031get_map_sym_type (struct disassemble_info *info,
6032 int n,
6033 enum map_type *map_type)
6034{
6035 /* If the symbol is in a different section, ignore it. */
6036 if (info->section != NULL && info->section != info->symtab[n]->section)
6037 return FALSE;
6038
6039 return is_mapping_symbol (info, n, map_type);
6040}
6041
6042/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6043 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6044
6045static int
fe56b6ce
NC		 6046get_sym_code_type (struct disassemble_info *info,
6047 int n,
e821645d 6048 enum map_type *map_type)
2087ad84
PB		 6049{
6050 elf_symbol_type *es;
6051 unsigned int type;
b0e28b39
DJ		 6052
6053 /* If the symbol is in a different section, ignore it. */
6054 if (info->section != NULL && info->section != info->symtab[n]->section)
6055 return FALSE;
2087ad84 6056
e821645d 6057 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6058 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6059
6060 /* If the symbol has function type then use that. */
34e77a92 6061 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6062 {
35fc36a8
RS		 6063 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6064 *map_type = MAP_THUMB;
6065 else
6066 *map_type = MAP_ARM;
2087ad84
PB		 6067 return TRUE;
6068 }
6069
2087ad84
PB		 6070 return FALSE;
6071}
6072
0313a2b8
NC		 6073/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6074 of the supplied arm_feature_set structure with bitmasks indicating
6075 the support base architectures and coprocessor extensions.
6076
6077 FIXME: This could more efficiently implemented as a constant array,
6078 although it would also be less robust. */
6079
6080static void
6081select_arm_features (unsigned long mach,
6082 arm_feature_set * features)
6083{
1af1dd51
MW		 6084#undef ARM_SET_FEATURES
6085#define ARM_SET_FEATURES(FSET) \
6086 { \
6087 const arm_feature_set fset = FSET; \
6088 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6089 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6090 }
823d2571 6091
0313a2b8
NC		 6092 switch (mach)
6093 {
1af1dd51
MW		 6094 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6095 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6096 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6097 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6098 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6099 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6100 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6101 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6102 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6103 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6104 case bfd_mach_arm_ep9312:
6105 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6106 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6107 break;
6108 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6109 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6110 /* If the machine type is unknown allow all
6111 architecture types and all extensions. */
1af1dd51 6112 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6113 default:
6114 abort ();
6115 }
1af1dd51
MW		 6116
6117#undef ARM_SET_FEATURES
0313a2b8
NC		 6118}
6119
6120
58efb6c0
NC		 6121/* NOTE: There are no checks in these routines that
6122 the relevant number of data bytes exist. */
baf0cc5e 6123
58efb6c0 6124static int
4a5329c6 6125print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6126{
c19d1205
ZW		 6127 unsigned char b[4];
6128 long given;
6129 int status;
e821645d 6130 int is_thumb = FALSE;
b0e28b39 6131 int is_data = FALSE;
bd2e2557 6132 int little_code;
e821645d 6133 unsigned int size = 4;
4a5329c6 6134 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6135 bfd_boolean found = FALSE;
b0e28b39 6136 struct arm_private_data *private_data;
58efb6c0 6137
dd92f639
NC		 6138 if (info->disassembler_options)
6139 {
6140 parse_disassembler_options (info->disassembler_options);
b34976b6 6141
58efb6c0 6142 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6143 info->disassembler_options = NULL;
6144 }
b34976b6 6145
0313a2b8
NC		 6146 /* PR 10288: Control which instructions will be disassembled. */
6147 if (info->private_data == NULL)
6148 {
b0e28b39 6149 static struct arm_private_data private;
0313a2b8
NC		 6150
6151 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6152 /* If the user did not use the -m command line switch then default to
6153 disassembling all types of ARM instruction.
43e65147 6154
0313a2b8
NC		 6155 The info->mach value has to be ignored as this will be based on
6156 the default archictecture for the target and/or hints in the notes
6157 section, but it will never be greater than the current largest arm
6158 machine value (iWMMXt2), which is only equivalent to the V5TE
6159 architecture. ARM architectures have advanced beyond the machine
6160 value encoding, and these newer architectures would be ignored if
6161 the machine value was used.
6162
6163 Ie the -m switch is used to restrict which instructions will be
6164 disassembled. If it is necessary to use the -m switch to tell
6165 objdump that an ARM binary is being disassembled, eg because the
6166 input is a raw binary file, but it is also desired to disassemble
6167 all ARM instructions then use "-marm". This will select the
6168 "unknown" arm architecture which is compatible with any ARM
6169 instruction. */
6170 info->mach = bfd_mach_arm_unknown;
6171
6172 /* Compute the architecture bitmask from the machine number.
6173 Note: This assumes that the machine number will not change
6174 during disassembly.... */
b0e28b39 6175 select_arm_features (info->mach, & private.features);
0313a2b8 6176
b0e28b39 6177 private.has_mapping_symbols = -1;
1fbaefec
PB		 6178 private.last_mapping_sym = -1;
6179 private.last_mapping_addr = 0;
b0e28b39
DJ		 6180
6181 info->private_data = & private;
0313a2b8 6182 }
b0e28b39
DJ		 6183
6184 private_data = info->private_data;
6185
bd2e2557
SS		 6186 /* Decide if our code is going to be little-endian, despite what the
6187 function argument might say. */
6188 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6189
b0e28b39
DJ		 6190 /* For ELF, consult the symbol table to determine what kind of code
6191 or data we have. */
8977d4b2 6192 if (info->symtab_size != 0
e821645d
DJ		 6193 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6194 {
6195 bfd_vma addr;
b0e28b39 6196 int n, start;
e821645d 6197 int last_sym = -1;
b0e28b39 6198 enum map_type type = MAP_ARM;
e821645d 6199
e821645d
DJ		 6200 /* Start scanning at the start of the function, or wherever
6201 we finished last time. */
6750a3a7
NC		 6202 /* PR 14006. When the address is 0 we are either at the start of the
6203 very first function, or else the first function in a new, unlinked
6204 executable section (eg because uf -ffunction-sections). Either way
6205 start scanning from the beginning of the symbol table, not where we
6206 left off last time. */
6207 if (pc == 0)
6208 start = 0;
6209 else
6210 {
6211 start = info->symtab_pos + 1;
6212 if (start < private_data->last_mapping_sym)
6213 start = private_data->last_mapping_sym;
6214 }
b0e28b39 6215 found = FALSE;
e821645d 6216
b0e28b39
DJ		 6217 /* First, look for mapping symbols. */
6218 if (private_data->has_mapping_symbols != 0)
e821645d 6219 {
b0e28b39
DJ		 6220 /* Scan up to the location being disassembled. */
6221 for (n = start; n < info->symtab_size; n++)
6222 {
6223 addr = bfd_asymbol_value (info->symtab[n]);
6224 if (addr > pc)
6225 break;
6226 if (get_map_sym_type (info, n, &type))
6227 {
6228 last_sym = n;
6229 found = TRUE;
6230 }
6231 }
6232
6233 if (!found)
6234 {
6235 /* No mapping symbol found at this address. Look backwards
cc643b88 6236 for a preceding one. */
b0e28b39
DJ		 6237 for (n = start - 1; n >= 0; n--)
6238 {
6239 if (get_map_sym_type (info, n, &type))
6240 {
6241 last_sym = n;
6242 found = TRUE;
6243 break;
6244 }
6245 }
6246 }
6247
6248 if (found)
6249 private_data->has_mapping_symbols = 1;
6250
6251 /* No mapping symbols were found. A leading $d may be
6252 omitted for sections which start with data; but for
6253 compatibility with legacy and stripped binaries, only
6254 assume the leading $d if there is at least one mapping
6255 symbol in the file. */
6256 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6257 {
b0e28b39
DJ		 6258 /* Look for mapping symbols, in any section. */
6259 for (n = 0; n < info->symtab_size; n++)
6260 if (is_mapping_symbol (info, n, &type))
6261 {
6262 private_data->has_mapping_symbols = 1;
6263 break;
6264 }
6265 if (private_data->has_mapping_symbols == -1)
6266 private_data->has_mapping_symbols = 0;
6267 }
6268
6269 if (!found && private_data->has_mapping_symbols == 1)
6270 {
6271 type = MAP_DATA;
e821645d
DJ		 6272 found = TRUE;
6273 }
6274 }
6275
b0e28b39
DJ		 6276 /* Next search for function symbols to separate ARM from Thumb
6277 in binaries without mapping symbols. */
e821645d
DJ		 6278 if (!found)
6279 {
b0e28b39
DJ		 6280 /* Scan up to the location being disassembled. */
6281 for (n = start; n < info->symtab_size; n++)
e821645d 6282 {
b0e28b39
DJ		 6283 addr = bfd_asymbol_value (info->symtab[n]);
6284 if (addr > pc)
6285 break;
6286 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6287 {
6288 last_sym = n;
6289 found = TRUE;
b0e28b39
DJ		 6290 }
6291 }
6292
6293 if (!found)
6294 {
6295 /* No mapping symbol found at this address. Look backwards
cc643b88 6296 for a preceding one. */
b0e28b39
DJ		 6297 for (n = start - 1; n >= 0; n--)
6298 {
6299 if (get_sym_code_type (info, n, &type))
6300 {
6301 last_sym = n;
6302 found = TRUE;
6303 break;
6304 }
e821645d
DJ		 6305 }
6306 }
6307 }
6308
1fbaefec
PB		 6309 private_data->last_mapping_sym = last_sym;
6310 private_data->last_type = type;
6311 is_thumb = (private_data->last_type == MAP_THUMB);
6312 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6313
e821645d
DJ		 6314 /* Look a little bit ahead to see if we should print out
6315 two or four bytes of data. If there's a symbol,
6316 mapping or otherwise, after two bytes then don't
6317 print more. */
6318 if (is_data)
6319 {
6320 size = 4 - (pc & 3);
6321 for (n = last_sym + 1; n < info->symtab_size; n++)
6322 {
6323 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6324 if (addr > pc
6325 && (info->section == NULL
6326 || info->section == info->symtab[n]->section))
e821645d
DJ		 6327 {
6328 if (addr - pc < size)
6329 size = addr - pc;
6330 break;
6331 }
6332 }
6333 /* If the next symbol is after three bytes, we need to
6334 print only part of the data, so that we can use either
6335 .byte or .short. */
6336 if (size == 3)
6337 size = (pc & 1) ? 1 : 2;
6338 }
6339 }
6340
6341 if (info->symbols != NULL)
252b5132 6342 {
5876e06d
NC		 6343 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6344 {
2f0ca46a 6345 coff_symbol_type * cs;
b34976b6 6346
5876e06d
NC		 6347 cs = coffsymbol (*info->symbols);
6348 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6349 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6350 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6351 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6352 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6353 }
e821645d
DJ		 6354 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6355 && !found)
5876e06d 6356 {
2087ad84
PB		 6357 /* If no mapping symbol has been found then fall back to the type
6358 of the function symbol. */
e821645d
DJ		 6359 elf_symbol_type * es;
6360 unsigned int type;
2087ad84 6361
e821645d
DJ		 6362 es = *(elf_symbol_type **)(info->symbols);
6363 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6364
35fc36a8
RS		 6365 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6366 == ST_BRANCH_TO_THUMB)
6367 || type == STT_ARM_16BIT);
5876e06d
NC		 6368 }
6369 }
b34976b6 6370
e821645d
DJ		 6371 if (force_thumb)
6372 is_thumb = TRUE;
6373
b8f9ee44
CL		 6374 if (is_data)
6375 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6376 else
6377 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6378
c19d1205 6379 info->bytes_per_line = 4;
252b5132 6380
1316c8b3
NC		 6381 /* PR 10263: Disassemble data if requested to do so by the user. */
6382 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6383 {
6384 int i;
6385
1316c8b3 6386 /* Size was already set above. */
e821645d
DJ		 6387 info->bytes_per_chunk = size;
6388 printer = print_insn_data;
6389
fe56b6ce 6390 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6391 given = 0;
6392 if (little)
6393 for (i = size - 1; i >= 0; i--)
6394 given = b[i] | (given << 8);
6395 else
6396 for (i = 0; i < (int) size; i++)
6397 given = b[i] | (given << 8);
6398 }
6399 else if (!is_thumb)
252b5132 6400 {
c19d1205
ZW		 6401 /* In ARM mode endianness is a straightforward issue: the instruction
6402 is four bytes long and is either ordered 0123 or 3210. */
6403 printer = print_insn_arm;
6404 info->bytes_per_chunk = 4;
4a5329c6 6405 size = 4;
c19d1205 6406
0313a2b8 6407 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6408 if (little_code)
c19d1205
ZW		 6409 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6410 else
6411 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6412 }
58efb6c0 6413 else
252b5132 6414 {
c19d1205
ZW		 6415 /* In Thumb mode we have the additional wrinkle of two
6416 instruction lengths. Fortunately, the bits that determine
6417 the length of the current instruction are always to be found
6418 in the first two bytes. */
4a5329c6 6419 printer = print_insn_thumb16;
c19d1205 6420 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6421 size = 2;
6422
fe56b6ce 6423 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6424 if (little_code)
9a2ff3f5
AM		 6425 given = (b[0]) | (b[1] << 8);
6426 else
6427 given = (b[1]) | (b[0] << 8);
6428
c19d1205 6429 if (!status)
252b5132 6430 {
c19d1205
ZW		 6431 /* These bit patterns signal a four-byte Thumb
6432 instruction. */
6433 if ((given & 0xF800) == 0xF800
6434 || (given & 0xF800) == 0xF000
6435 || (given & 0xF800) == 0xE800)
252b5132 6436 {
0313a2b8 6437 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6438 if (little_code)
c19d1205 6439 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6440 else
c19d1205
ZW		 6441 given = (b[1]) | (b[0] << 8) | (given << 16);
6442
6443 printer = print_insn_thumb32;
4a5329c6 6444 size = 4;
252b5132 6445 }
252b5132 6446 }
c22aaad1
PB		 6447
6448 if (ifthen_address != pc)
0313a2b8 6449 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6450
6451 if (ifthen_state)
6452 {
6453 if ((ifthen_state & 0xf) == 0x8)
6454 ifthen_next_state = 0;
6455 else
6456 ifthen_next_state = (ifthen_state & 0xe0)
6457 | ((ifthen_state & 0xf) << 1);
6458 }
252b5132 6459 }
b34976b6 6460
c19d1205
ZW		 6461 if (status)
6462 {
6463 info->memory_error_func (status, pc, info);
6464 return -1;
6465 }
6a56ec7e
NC		 6466 if (info->flags & INSN_HAS_RELOC)
6467 /* If the instruction has a reloc associated with it, then
6468 the offset field in the instruction will actually be the
6469 addend for the reloc. (We are using REL type relocs).
6470 In such cases, we can ignore the pc when computing
6471 addresses, since the addend is not currently pc-relative. */
6472 pc = 0;
b34976b6 6473
4a5329c6 6474 printer (pc, info, given);
c22aaad1
PB		 6475
6476 if (is_thumb)
6477 {
6478 ifthen_state = ifthen_next_state;
6479 ifthen_address += size;
6480 }
4a5329c6 6481 return size;
252b5132
RH		 6482}
6483
6484int
4a5329c6 6485print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6486{
bd2e2557
SS		 6487 /* Detect BE8-ness and record it in the disassembler info. */
6488 if (info->flavour == bfd_target_elf_flavour
6489 && info->section != NULL
6490 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6491 info->endian_code = BFD_ENDIAN_LITTLE;
6492
b34976b6 6493 return print_insn (pc, info, FALSE);
58efb6c0 6494}
01c7f630 6495
58efb6c0 6496int
4a5329c6 6497print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6498{
b34976b6 6499 return print_insn (pc, info, TRUE);
58efb6c0 6500}
252b5132 6501
58efb6c0 6502void
4a5329c6 6503print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 6504{
6505 int i;
252b5132 6506
58efb6c0
NC		 6507 fprintf (stream, _("\n\
6508The following ARM specific disassembler options are supported for use with\n\
6509the -M switch:\n"));
b34976b6 6510
58efb6c0
NC		 6511 for (i = NUM_ARM_REGNAMES; i--;)
6512 fprintf (stream, " reg-names-%s %*c%s\n",
6513 regnames[i].name,
d5b2f4d6 6514 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 6515 regnames[i].description);
6516
6517 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 6518 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 6519}
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