[thirdparty/binutils-gdb.git] / opcodes / avr-dis.c

/* Disassemble AVR instructions.
   Copyright 1999, 2000 Free Software Foundation, Inc.

   Contributed by Denis Chertykov <denisc@overta.ru>

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <assert.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opintl.h"


struct avr_opcodes_s
{
  char *name;
  char *constraints;
  char *opcode;
  int insn_size;		/* in words */
  int isa;
  unsigned int bin_opcode;
  unsigned int bin_mask;
};

#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0},

struct avr_opcodes_s avr_opcodes[] =
{
  #include "opcode/avr.h"
  {NULL, NULL, NULL, 0, 0, 0, 0}
};

static int avr_operand PARAMS ((unsigned int, unsigned int,
				unsigned int, int, char *, char *, int));

static int
avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
     unsigned int insn;
     unsigned int insn2;
     unsigned int pc;
     int constraint;
     char *buf;
     char *comment;
     int regs;
{
  int ok = 1;

  switch (constraint)
    {
      /* Any register operand.  */
    case 'r':
      if (regs)
	insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
      else
	insn = (insn & 0x01f0) >> 4; /* destination register */
      
      sprintf (buf, "r%d", insn);
      break;

    case 'd':
      if (regs)
	sprintf (buf, "r%d", 16 + (insn & 0xf));
      else
	sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
      break;
      
    case 'w':
      sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
      break;
      
    case 'a':
      if (regs)
	sprintf (buf, "r%d", 16 + (insn & 7));
      else
	sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
      break;

    case 'v':
      if (regs)
	sprintf (buf, "r%d", (insn & 0xf) * 2);
      else
	sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
      break;

    case 'e':
      {
	char *xyz;

	switch (insn & 0x100f)
	  {
	    case 0x0000: xyz = "Z";  break;
	    case 0x1001: xyz = "Z+"; break;
	    case 0x1002: xyz = "-Z"; break;
	    case 0x0008: xyz = "Y";  break;
	    case 0x1009: xyz = "Y+"; break;
	    case 0x100a: xyz = "-Y"; break;
	    case 0x100c: xyz = "X";  break;
	    case 0x100d: xyz = "X+"; break;
	    case 0x100e: xyz = "-X"; break;
	    default: xyz = "??"; ok = 0;
	  }
	sprintf (buf, xyz);

	if (AVR_UNDEF_P (insn))
	  sprintf (comment, _("undefined"));
      }
      break;

    case 'z':
      *buf++ = 'Z';
      if (insn & 0x1)
	*buf++ = '+';
      *buf = '\0';
      if (AVR_UNDEF_P (insn))
	sprintf (comment, _("undefined"));
      break;

    case 'b':
      {
	unsigned int x;
	
	x = (insn & 7);
	x |= (insn >> 7) & (3 << 3);
	x |= (insn >> 8) & (1 << 5);
	
	if (insn & 0x8)
	  *buf++ = 'Y';
	else
	  *buf++ = 'Z';
	sprintf (buf, "+%d", x);
	sprintf (comment, "0x%02x", x);
      }
      break;
      
    case 'h':
      sprintf (buf, "0x%x",
	       ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2);
      break;
      
    case 'L':
      {
	int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
	sprintf (buf, ".%+-8d", rel_addr);
	sprintf (comment, "0x%x", pc + 2 + rel_addr);
      }
      break;

    case 'l':
      {
	int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
	sprintf (buf, ".%+-8d", rel_addr);
	sprintf (comment, "0x%x", pc + 2 + rel_addr);
      }
      break;

    case 'i':
      sprintf (buf, "0x%04X", insn2);
      break;
      
    case 'M':
      sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
      sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
      break;

    case 'n':
      sprintf (buf, "??");
      fprintf (stderr, _("Internal disassembler error"));
      ok = 0;
      break;
      
    case 'K':
      {
	unsigned int x;

	x = (insn & 0xf) | ((insn >> 2) & 0x30);
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;
      
    case 's':
      sprintf (buf, "%d", insn & 7);
      break;
      
    case 'S':
      sprintf (buf, "%d", (insn >> 4) & 7);
      break;
      
    case 'P':
      {
	unsigned int x;
	x = (insn & 0xf);
	x |= (insn >> 5) & 0x30;
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;

    case 'p':
      {
	unsigned int x;
	
	x = (insn >> 3) & 0x1f;
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;
      
    case '?':
      *buf = '\0';
      break;
      
    default:
      sprintf (buf, "??");
      fprintf (stderr, _("unknown constraint `%c'"), constraint);
      ok = 0;
    }

    return ok;
}

static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));

static unsigned short
avrdis_opcode (addr, info)
     bfd_vma addr;
     disassemble_info *info;
{
  bfd_byte buffer[2];
  int status;
  status = info->read_memory_func(addr, buffer, 2, info);
  if (status != 0)
    {
      info->memory_error_func(status, addr, info);
      return -1;
    }
  return bfd_getl16 (buffer);
}


int
print_insn_avr(addr, info)
     bfd_vma addr;
     disassemble_info *info;
{
  unsigned int insn, insn2;
  struct avr_opcodes_s *opcode;
  void *stream = info->stream;
  fprintf_ftype prin = info->fprintf_func;
  static int initialized;
  int cmd_len = 2;
  int ok = 0;
  char op1[20], op2[20], comment1[40], comment2[40];

  if (!initialized)
    {
      initialized = 1;
      
      for (opcode = avr_opcodes; opcode->name; opcode++)
	{
	  char * s;
	  unsigned int bin = 0;
	  unsigned int mask = 0;
	
	  for (s = opcode->opcode; *s; ++s)
	    {
	      bin <<= 1;
	      mask <<= 1;
	      bin |= (*s == '1');
	      mask |= (*s == '1' || *s == '0');
	    }
	  assert (s - opcode->opcode == 16);
	  assert (opcode->bin_opcode == bin);
	  opcode->bin_mask = mask;
	}
    }

  insn = avrdis_opcode (addr, info);
  
  for (opcode = avr_opcodes; opcode->name; opcode++)
    {
      if ((insn & opcode->bin_mask) == opcode->bin_opcode)
	break;
    }
  
  /* Special case: disassemble `ldd r,b+0' as `ld r,b', and
     `std b+0,r' as `st b,r' (next entry in the table).  */

  if (AVR_DISP0_P (insn))
    opcode++;

  op1[0] = 0;
  op2[0] = 0;
  comment1[0] = 0;
  comment2[0] = 0;

  if (opcode->name)
    {
      char *op = opcode->constraints;

      insn2 = 0;
      ok = 1;

      if (opcode->insn_size > 1)
	{
	  insn2 = avrdis_opcode (addr + 2, info);
	  cmd_len = 4;
	}

      if (*op && *op != '?')
	{
	  int regs = REGISTER_P (*op);

	  ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0);

	  if (ok && *(++op) == ',')
	    ok = avr_operand (insn, insn2, addr, *(++op), op2,
			      *comment1 ? comment2 : comment1, regs);
	}
    }

  if (!ok)
    {
      /* Unknown opcode, or invalid combination of operands.  */
      sprintf (op1, "0x%04x", insn);
      op2[0] = 0;
      sprintf (comment1, "????");
      comment2[0] = 0;
    }

  (*prin) (stream, "%s", ok ? opcode->name : ".word");

  if (*op1)
    (*prin) (stream, "\t%s", op1);

  if (*op2)
    (*prin) (stream, ", %s", op2);

  if (*comment1)
    (*prin) (stream, "\t; %s", comment1);

  if (*comment2)
    (*prin) (stream, " %s", comment2);

  return cmd_len;
}
Commit	Line	Data
adde6300	1	/* Disassemble AVR instructions.
060d22b0	2	Copyright 1999, 2000 Free Software Foundation, Inc.
adde6300 AM	3
	4	Contributed by Denis Chertykov <denisc@overta.ru>
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	19
bab84c47	20	#include <assert.h>
0d8dfecf	21	#include "sysdep.h"
adde6300 AM	22	#include "dis-asm.h"
	23	#include "opintl.h"
	24
3c504221	25
bab84c47	26	struct avr_opcodes_s
adde6300	27	{
bab84c47 DC	28	char *name;
	29	char *constraints;
	30	char *opcode;
	31	int insn_size; /* in words */
	32	int isa;
	33	unsigned int bin_opcode;
	34	unsigned int bin_mask;
	35	};
adde6300	36
bab84c47 DC	37	#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
bab84c47 DC	38	{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0},
adde6300	39
bab84c47	40	struct avr_opcodes_s avr_opcodes[] =
adde6300	41	{
bab84c47 DC	42	#include "opcode/avr.h"
	43	{NULL, NULL, NULL, 0, 0, 0, 0}
	44	};
adde6300	45
463f102c DC	46	static int avr_operand PARAMS ((unsigned int, unsigned int,
463f102c DC	47	unsigned int, int, char , char , int));
adde6300	48
463f102c	49	static int
bab84c47 DC	50	avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
	51	unsigned int insn;
	52	unsigned int insn2;
	53	unsigned int pc;
	54	int constraint;
	55	char *buf;
	56	char *comment;
	57	int regs;
adde6300	58	{
463f102c DC	59	int ok = 1;
463f102c DC	60
bab84c47 DC	61	switch (constraint)
	62	{
	63	/* Any register operand. */
	64	case 'r':
	65	if (regs)
	66	insn = (insn & 0xf) \| ((insn & 0x0200) >> 5); /* source register */
	67	else
	68	insn = (insn & 0x01f0) >> 4; /* destination register */
	69
	70	sprintf (buf, "r%d", insn);
	71	break;
	72
	73	case 'd':
	74	if (regs)
	75	sprintf (buf, "r%d", 16 + (insn & 0xf));
	76	else
	77	sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
	78	break;
	79
	80	case 'w':
	81	sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
	82	break;
	83
	84	case 'a':
	85	if (regs)
	86	sprintf (buf, "r%d", 16 + (insn & 7));
	87	else
	88	sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
	89	break;
adde6300	90
bab84c47 DC	91	case 'v':
	92	if (regs)
	93	sprintf (buf, "r%d", (insn & 0xf) * 2);
	94	else
	95	sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
	96	break;
	97
	98	case 'e':
463f102c DC	99	{
	100	char *xyz;
	101
	102	switch (insn & 0x100f)
	103	{
	104	case 0x0000: xyz = "Z"; break;
	105	case 0x1001: xyz = "Z+"; break;
	106	case 0x1002: xyz = "-Z"; break;
	107	case 0x0008: xyz = "Y"; break;
	108	case 0x1009: xyz = "Y+"; break;
	109	case 0x100a: xyz = "-Y"; break;
	110	case 0x100c: xyz = "X"; break;
	111	case 0x100d: xyz = "X+"; break;
	112	case 0x100e: xyz = "-X"; break;
	113	default: xyz = "??"; ok = 0;
	114	}
	115	sprintf (buf, xyz);
	116
	117	if (AVR_UNDEF_P (insn))
	118	sprintf (comment, _("undefined"));
	119	}
bab84c47 DC	120	break;
	121
	122	case 'z':
	123	*buf++ = 'Z';
	124	if (insn & 0x1)
	125	*buf++ = '+';
	126	*buf = '\0';
463f102c DC	127	if (AVR_UNDEF_P (insn))
463f102c DC	128	sprintf (comment, _("undefined"));
bab84c47 DC	129	break;
	130
	131	case 'b':
	132	{
463f102c	133	unsigned int x;
bab84c47 DC	134
	135	x = (insn & 7);
	136	x \|= (insn >> 7) & (3 << 3);
	137	x \|= (insn >> 8) & (1 << 5);
	138
	139	if (insn & 0x8)
	140	*buf++ = 'Y';
	141	else
	142	*buf++ = 'Z';
	143	sprintf (buf, "+%d", x);
	144	sprintf (comment, "0x%02x", x);
	145	}
	146	break;
	147
	148	case 'h':
8776c5fe DC	149	sprintf (buf, "0x%x",
8776c5fe DC	150	((((insn & 1) \| ((insn & 0x1f0) >> 3)) << 16) \| insn2) * 2);
bab84c47 DC	151	break;
	152
	153	case 'L':
	154	{
	155	int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
	156	sprintf (buf, ".%+-8d", rel_addr);
	157	sprintf (comment, "0x%x", pc + 2 + rel_addr);
	158	}
	159	break;
	160
	161	case 'l':
	162	{
	163	int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
	164	sprintf (buf, ".%+-8d", rel_addr);
	165	sprintf (comment, "0x%x", pc + 2 + rel_addr);
	166	}
	167	break;
	168
	169	case 'i':
	170	sprintf (buf, "0x%04X", insn2);
	171	break;
	172
	173	case 'M':
	174	sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) \| (insn & 0xf));
	175	sprintf (comment, "%d", ((insn & 0xf00) >> 4) \| (insn & 0xf));
	176	break;
	177
	178	case 'n':
463f102c DC	179	sprintf (buf, "??");
	180	fprintf (stderr, _("Internal disassembler error"));
	181	ok = 0;
bab84c47 DC	182	break;
	183
	184	case 'K':
463f102c DC	185	{
	186	unsigned int x;
	187
	188	x = (insn & 0xf) \| ((insn >> 2) & 0x30);
	189	sprintf (buf, "0x%02x", x);
	190	sprintf (comment, "%d", x);
	191	}
bab84c47 DC	192	break;
	193
	194	case 's':
	195	sprintf (buf, "%d", insn & 7);
	196	break;
	197
	198	case 'S':
	199	sprintf (buf, "%d", (insn >> 4) & 7);
	200	break;
	201
	202	case 'P':
	203	{
	204	unsigned int x;
	205	x = (insn & 0xf);
	206	x \|= (insn >> 5) & 0x30;
	207	sprintf (buf, "0x%02x", x);
	208	sprintf (comment, "%d", x);
	209	}
	210	break;
	211
	212	case 'p':
	213	{
	214	unsigned int x;
	215
	216	x = (insn >> 3) & 0x1f;
	217	sprintf (buf, "0x%02x", x);
	218	sprintf (comment, "%d", x);
	219	}
	220	break;
	221
	222	case '?':
	223	*buf = '\0';
	224	break;
	225
	226	default:
463f102c DC	227	sprintf (buf, "??");
	228	fprintf (stderr, _("unknown constraint `%c'"), constraint);
	229	ok = 0;
bab84c47	230	}
463f102c DC	231
463f102c DC	232	return ok;
adde6300 AM	233	}
adde6300 AM	234
bab84c47	235	static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
adde6300	236
bab84c47	237	static unsigned short
adde6300 AM	238	avrdis_opcode (addr, info)
	239	bfd_vma addr;
	240	disassemble_info *info;
	241	{
	242	bfd_byte buffer[2];
	243	int status;
	244	status = info->read_memory_func(addr, buffer, 2, info);
	245	if (status != 0)
	246	{
	247	info->memory_error_func(status, addr, info);
	248	return -1;
	249	}
	250	return bfd_getl16 (buffer);
	251	}
	252
	253
	254	int
	255	print_insn_avr(addr, info)
	256	bfd_vma addr;
	257	disassemble_info *info;
	258	{
bab84c47 DC	259	unsigned int insn, insn2;
bab84c47 DC	260	struct avr_opcodes_s *opcode;
adde6300 AM	261	void *stream = info->stream;
adde6300 AM	262	fprintf_ftype prin = info->fprintf_func;
bab84c47	263	static int initialized;
adde6300	264	int cmd_len = 2;
463f102c DC	265	int ok = 0;
463f102c DC	266	char op1[20], op2[20], comment1[40], comment2[40];
adde6300	267
bab84c47 DC	268	if (!initialized)
	269	{
	270	initialized = 1;
	271
	272	for (opcode = avr_opcodes; opcode->name; opcode++)
	273	{
	274	char * s;
	275	unsigned int bin = 0;
	276	unsigned int mask = 0;
	277
	278	for (s = opcode->opcode; *s; ++s)
	279	{
	280	bin <<= 1;
	281	mask <<= 1;
	282	bin \|= (*s == '1');
	283	mask \|= (s == '1' \|\| s == '0');
	284	}
	285	assert (s - opcode->opcode == 16);
	286	assert (opcode->bin_opcode == bin);
	287	opcode->bin_mask = mask;
	288	}
	289	}
adde6300	290
bab84c47 DC	291	insn = avrdis_opcode (addr, info);
	292
	293	for (opcode = avr_opcodes; opcode->name; opcode++)
adde6300	294	{
bab84c47 DC	295	if ((insn & opcode->bin_mask) == opcode->bin_opcode)
bab84c47 DC	296	break;
adde6300	297	}
bab84c47	298
463f102c DC	299	/* Special case: disassemble `ldd r,b+0' as `ld r,b', and
	300	`std b+0,r' as `st b,r' (next entry in the table). */
	301
	302	if (AVR_DISP0_P (insn))
	303	opcode++;
	304
	305	op1[0] = 0;
	306	op2[0] = 0;
	307	comment1[0] = 0;
	308	comment2[0] = 0;
	309
bab84c47	310	if (opcode->name)
adde6300	311	{
bab84c47 DC	312	char *op = opcode->constraints;
bab84c47 DC	313
00d2865b	314	insn2 = 0;
463f102c	315	ok = 1;
bab84c47 DC	316
	317	if (opcode->insn_size > 1)
	318	{
	319	insn2 = avrdis_opcode (addr + 2, info);
	320	cmd_len = 4;
	321	}
	322
	323	if (op && op != '?')
	324	{
	325	int regs = REGISTER_P (*op);
	326
463f102c	327	ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0);
bab84c47	328
463f102c DC	329	if (ok && *(++op) == ',')
	330	ok = avr_operand (insn, insn2, addr, *(++op), op2,
	331	*comment1 ? comment2 : comment1, regs);
bab84c47	332	}
463f102c	333	}
bab84c47	334
463f102c DC	335	if (!ok)
	336	{
	337	/* Unknown opcode, or invalid combination of operands. */
	338	sprintf (op1, "0x%04x", insn);
	339	op2[0] = 0;
	340	sprintf (comment1, "????");
	341	comment2[0] = 0;
	342	}
bab84c47	343
463f102c	344	(*prin) (stream, "%s", ok ? opcode->name : ".word");
bab84c47	345
463f102c DC	346	if (*op1)
463f102c DC	347	(*prin) (stream, "\t%s", op1);
bab84c47	348
463f102c DC	349	if (*op2)
	350	(*prin) (stream, ", %s", op2);
	351
	352	if (*comment1)
	353	(*prin) (stream, "\t; %s", comment1);
	354
	355	if (*comment2)
	356	(*prin) (stream, " %s", comment2);
bab84c47	357
adde6300 AM	358	return cmd_len;
adde6300 AM	359	}