projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| b8891f8d | 1 | /* Declarations for C-SKY opcode table |
| b3adc24a | 2 | Copyright (C) 2007-2020 Free Software Foundation, Inc. |
| b8891f8d AJ |
3 | Contributed by C-SKY Microsystems and Mentor Graphics. |
| 4 | ||
| 5 | This file is part of the GNU opcodes library. | |
| 6 | ||
| 7 | This library is free software; you can redistribute it and/or modify | |
| 8 | it under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | It is distributed in the hope that it will be useful, but WITHOUT | |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 | License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with GAS; see the file COPYING. If not, write to the Free | |
| 19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
| 20 | 02110-1301, USA. */ | |
| 21 | ||
| 22 | #include "opcode/csky.h" | |
| afdcafe8 | 23 | #include "safe-ctype.h" |
| b8891f8d AJ |
24 | |
| 25 | #define OP_TABLE_NUM 2 | |
| 0c0577f6 | 26 | #define MAX_OPRND_NUM 5 |
| b8891f8d AJ |
27 | |
| 28 | enum operand_type | |
| 29 | { | |
| 30 | OPRND_TYPE_NONE = 0, | |
| 31 | /* Control register. */ | |
| 32 | OPRND_TYPE_CTRLREG, | |
| 33 | /* r0 - r7. */ | |
| 34 | OPRND_TYPE_GREG0_7, | |
| 35 | /* r0 - r15. */ | |
| 36 | OPRND_TYPE_GREG0_15, | |
| 37 | /* r16 - r31. */ | |
| 38 | OPRND_TYPE_GREG16_31, | |
| 39 | /* r0 - r31. */ | |
| 40 | OPRND_TYPE_AREG, | |
| 41 | /* (rx). */ | |
| 42 | OPRND_TYPE_AREG_WITH_BRACKET, | |
| 43 | OPRND_TYPE_AREG_WITH_LSHIFT, | |
| 44 | OPRND_TYPE_AREG_WITH_LSHIFT_FPU, | |
| 45 | ||
| 46 | OPRND_TYPE_FREG_WITH_INDEX, | |
| 47 | /* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */ | |
| 48 | OPRND_TYPE_REG_r1a, | |
| 49 | /* r1 only, for divs/divu in csky v1 ISA. */ | |
| 50 | OPRND_TYPE_REG_r1b, | |
| 51 | /* r28. */ | |
| 52 | OPRND_TYPE_REG_r28, | |
| 53 | OPRND_TYPE_REGr4_r7, | |
| 54 | /* sp register with bracket. */ | |
| 55 | OPRND_TYPE_REGbsp, | |
| 56 | /* sp register. */ | |
| 57 | OPRND_TYPE_REGsp, | |
| 58 | /* Register with bracket. */ | |
| 59 | OPRND_TYPE_REGnr4_r7, | |
| 60 | /* Not sp register. */ | |
| 61 | OPRND_TYPE_REGnsp, | |
| 62 | /* Not lr register. */ | |
| 63 | OPRND_TYPE_REGnlr, | |
| 64 | /* Not sp/lr register. */ | |
| 65 | OPRND_TYPE_REGnsplr, | |
| 66 | /* hi/lo register. */ | |
| 67 | OPRND_TYPE_REGhilo, | |
| 68 | /* VDSP register. */ | |
| 69 | OPRND_TYPE_VREG, | |
| 70 | ||
| 71 | /* cp index. */ | |
| 72 | OPRND_TYPE_CPIDX, | |
| 73 | /* cp regs. */ | |
| 74 | OPRND_TYPE_CPREG, | |
| 75 | /* cp cregs. */ | |
| 76 | OPRND_TYPE_CPCREG, | |
| 77 | /* fpu regs. */ | |
| 78 | OPRND_TYPE_FREG, | |
| 79 | /* fpu even regs. */ | |
| 80 | OPRND_TYPE_FEREG, | |
| 81 | /* Float round mode. */ | |
| 82 | OPRND_TYPE_RM, | |
| 83 | /* PSR bits. */ | |
| 84 | OPRND_TYPE_PSR_BITS_LIST, | |
| 85 | ||
| 86 | /* Constant. */ | |
| 87 | OPRND_TYPE_CONSTANT, | |
| 88 | /* Floating Constant. */ | |
| 89 | OPRND_TYPE_FCONSTANT, | |
| 90 | /* Extern lrw constant. */ | |
| 91 | OPRND_TYPE_ELRW_CONSTANT, | |
| 92 | /* [label]. */ | |
| 93 | OPRND_TYPE_LABEL_WITH_BRACKET, | |
| 94 | /* The operand is the same as first reg. It is a dummy reg that doesn't | |
| 95 | appear in the binary code of the instruction. It is also used by | |
| 96 | the disassembler. | |
| 97 | For example: bclri rz, rz, imm5 -> bclri rz, imm5. */ | |
| 98 | OPRND_TYPE_DUMMY_REG, | |
| 99 | /* The type of the operand is same as the first operand. If the value | |
| 100 | of the operand is same as the first operand, we can use a 16-bit | |
| 101 | instruction to represent the opcode. | |
| 102 | For example: addc r1, r1, r2 -> addc16 r1, r2. */ | |
| 103 | OPRND_TYPE_2IN1_DUMMY, | |
| 104 | /* Output a reg same as the first reg. | |
| 105 | For example: addc r17, r1 -> addc32 r17, r17, r1. | |
| 106 | The old "addc" cannot be represented by a 16-bit instruction because | |
| 107 | 16-bit "addc" only supports regs from r0 to r15. So we use "addc32" | |
| 108 | which has 3 operands, and duplicate the first operand to the second. */ | |
| 109 | OPRND_TYPE_DUP_GREG0_7, | |
| 110 | OPRND_TYPE_DUP_GREG0_15, | |
| 111 | OPRND_TYPE_DUP_AREG, | |
| 112 | /* Immediate. */ | |
| 113 | OPRND_TYPE_IMM1b, | |
| 114 | OPRND_TYPE_IMM2b, | |
| 115 | OPRND_TYPE_IMM3b, | |
| 116 | OPRND_TYPE_IMM4b, | |
| 117 | OPRND_TYPE_IMM5b, | |
| 118 | OPRND_TYPE_IMM7b, | |
| 119 | OPRND_TYPE_IMM8b, | |
| 1feede9b | 120 | OPRND_TYPE_IMM9b, |
| b8891f8d AJ |
121 | OPRND_TYPE_IMM12b, |
| 122 | OPRND_TYPE_IMM15b, | |
| 123 | OPRND_TYPE_IMM16b, | |
| 124 | OPRND_TYPE_IMM18b, | |
| 125 | OPRND_TYPE_IMM32b, | |
| 126 | /* Immediate left shift 2 bits. */ | |
| 127 | OPRND_TYPE_IMM7b_LS2, | |
| 128 | OPRND_TYPE_IMM8b_LS2, | |
| 129 | /* OPRND_TYPE_IMM5b_a_b means: Immediate in (a, b). */ | |
| 130 | OPRND_TYPE_IMM5b_1_31, | |
| 131 | OPRND_TYPE_IMM5b_7_31, | |
| afdcafe8 CQ |
132 | /* OPRND_TYPE_IMM5b_LS means: Imm <= prev Imm. */ |
| 133 | OPRND_TYPE_IMM5b_LS, | |
| b8891f8d AJ |
134 | /* Operand type for rori and rotri. */ |
| 135 | OPRND_TYPE_IMM5b_RORI, | |
| 136 | OPRND_TYPE_IMM5b_POWER, | |
| 137 | OPRND_TYPE_IMM5b_7_31_POWER, | |
| 138 | OPRND_TYPE_IMM5b_BMASKI, | |
| 139 | OPRND_TYPE_IMM8b_BMASKI, | |
| 140 | /* For v2 movih. */ | |
| 141 | OPRND_TYPE_IMM16b_MOVIH, | |
| 142 | /* For v2 ori. */ | |
| 143 | OPRND_TYPE_IMM16b_ORI, | |
| 144 | /* For v2 ld/st. */ | |
| 145 | OPRND_TYPE_IMM_LDST, | |
| 146 | OPRND_TYPE_IMM_FLDST, | |
| 147 | OPRND_TYPE_IMM2b_JMPIX, | |
| 148 | /* Offset for bloop. */ | |
| 149 | OPRND_TYPE_BLOOP_OFF4b, | |
| 150 | OPRND_TYPE_BLOOP_OFF12b, | |
| 151 | /* Offset for jump. */ | |
| 152 | OPRND_TYPE_OFF8b, | |
| 153 | OPRND_TYPE_OFF10b, | |
| 154 | OPRND_TYPE_OFF11b, | |
| 155 | OPRND_TYPE_OFF16b, | |
| 156 | OPRND_TYPE_OFF16b_LSL1, | |
| 157 | OPRND_TYPE_OFF26b, | |
| 158 | /* An immediate or label. */ | |
| 159 | OPRND_TYPE_IMM_OFF18b, | |
| 160 | /* Offset immediate. */ | |
| 161 | OPRND_TYPE_OIMM3b, | |
| 162 | OPRND_TYPE_OIMM4b, | |
| 163 | OPRND_TYPE_OIMM5b, | |
| 164 | OPRND_TYPE_OIMM8b, | |
| 165 | OPRND_TYPE_OIMM12b, | |
| 166 | OPRND_TYPE_OIMM16b, | |
| 167 | OPRND_TYPE_OIMM18b, | |
| 168 | /* For csky v2 idly. */ | |
| 169 | OPRND_TYPE_OIMM5b_IDLY, | |
| 170 | /* For v2 bmaski. */ | |
| 171 | OPRND_TYPE_OIMM5b_BMASKI, | |
| 172 | /* Constants. */ | |
| 173 | OPRND_TYPE_CONST1, | |
| 174 | /* PC relative offset. */ | |
| 175 | OPRND_TYPE_PCR_OFFSET_16K, | |
| 176 | OPRND_TYPE_PCR_OFFSET_64K, | |
| 177 | OPRND_TYPE_PCR_OFFSET_64M, | |
| 178 | OPRND_TYPE_CPFUNC, | |
| 179 | OPRND_TYPE_GOT_PLT, | |
| 180 | OPRND_TYPE_REGLIST_LDM, | |
| 181 | OPRND_TYPE_REGLIST_DASH, | |
| 182 | OPRND_TYPE_FREGLIST_DASH, | |
| 183 | OPRND_TYPE_REGLIST_COMMA, | |
| 184 | OPRND_TYPE_REGLIST_DASH_COMMA, | |
| 185 | OPRND_TYPE_BRACKET, | |
| 186 | OPRND_TYPE_ABRACKET, | |
| 187 | OPRND_TYPE_JBTF, | |
| 188 | OPRND_TYPE_JBR, | |
| 189 | OPRND_TYPE_JBSR, | |
| 190 | OPRND_TYPE_UNCOND10b, | |
| 191 | OPRND_TYPE_UNCOND16b, | |
| 192 | OPRND_TYPE_COND10b, | |
| 193 | OPRND_TYPE_COND16b, | |
| 194 | OPRND_TYPE_JCOMPZ, | |
| 195 | OPRND_TYPE_LSB2SIZE, | |
| 196 | OPRND_TYPE_MSB2SIZE, | |
| 197 | OPRND_TYPE_LSB, | |
| 198 | OPRND_TYPE_MSB, | |
| 199 | /* Single float and double float. */ | |
| 200 | OPRND_TYPE_SFLOAT, | |
| 201 | OPRND_TYPE_DFLOAT, | |
| 1feede9b CQ |
202 | OPRND_TYPE_HFLOAT_FMOVI, |
| 203 | OPRND_TYPE_SFLOAT_FMOVI, | |
| 204 | OPRND_TYPE_DFLOAT_FMOVI, | |
| b8891f8d AJ |
205 | }; |
| 206 | ||
| 207 | /* Operand descriptors. */ | |
| 208 | struct operand | |
| 209 | { | |
| 210 | /* Mask for suboperand. */ | |
| 211 | unsigned int mask; | |
| 212 | /* Suboperand type. */ | |
| 213 | enum operand_type type; | |
| 214 | /* Operand shift. */ | |
| 215 | int shift; | |
| 216 | }; | |
| 217 | ||
| 218 | struct soperand | |
| 219 | { | |
| 220 | /* Mask for operand. */ | |
| 221 | unsigned int mask; | |
| 222 | /* Operand type. */ | |
| 223 | enum operand_type type; | |
| 224 | /* Operand shift. */ | |
| 225 | int shift; | |
| 226 | /* Suboperand. */ | |
| 227 | struct operand subs[3]; | |
| 228 | }; | |
| 229 | ||
| 230 | union csky_operand | |
| 231 | { | |
| 0c0577f6 | 232 | struct operand oprnds[MAX_OPRND_NUM]; |
| b8891f8d AJ |
233 | struct suboperand1 |
| 234 | { | |
| 235 | struct operand oprnd; | |
| 236 | struct soperand soprnd; | |
| 237 | } soprnd1; | |
| 238 | struct suboperand2 | |
| 239 | { | |
| 240 | struct soperand soprnd; | |
| 241 | struct operand oprnd; | |
| 242 | } soprnd2; | |
| 243 | }; | |
| 244 | ||
| 245 | /* Describe a single instruction encoding. */ | |
| 246 | struct csky_opcode_info | |
| 247 | { | |
| 248 | /* How many operands. */ | |
| 249 | long operand_num; | |
| 250 | /* The instruction opcode. */ | |
| 251 | unsigned int opcode; | |
| 252 | /* Operand information. */ | |
| 253 | union csky_operand oprnd; | |
| 254 | }; | |
| 255 | ||
| 256 | /* C-SKY instruction description. Each mnemonic can have multiple | |
| 257 | 16-bit and 32-bit encodings. */ | |
| 258 | struct csky_opcode | |
| 259 | { | |
| 260 | /* The instruction name. */ | |
| 261 | const char *mnemonic; | |
| 262 | /* Whether this is an unconditional control transfer instruction, | |
| 263 | for the purposes of placing literal pools after it. | |
| 264 | 0 = no, 1 = within function, 2 = end of function. | |
| 265 | See check_literals in gas/config/tc-csky.c. */ | |
| 266 | int transfer; | |
| 267 | /* Encodings for 16-bit opcodes. */ | |
| 268 | struct csky_opcode_info op16[OP_TABLE_NUM]; | |
| 269 | /* Encodings for 32-bit opcodes. */ | |
| 270 | struct csky_opcode_info op32[OP_TABLE_NUM]; | |
| 271 | /* Instruction set flag. */ | |
| 0861f561 CQ |
272 | BFD_HOST_U_64_BIT isa_flag16; |
| 273 | BFD_HOST_U_64_BIT isa_flag32; | |
| b8891f8d AJ |
274 | /* Whether this insn needs relocation, 0: no, !=0: yes. */ |
| 275 | signed int reloc16; | |
| 276 | signed int reloc32; | |
| 277 | /* Whether this insn needs relaxation, 0: no, != 0: yes. */ | |
| 278 | signed int relax; | |
| 279 | /* Worker function to call when this instruction needs special assembler | |
| 280 | handling. */ | |
| 281 | bfd_boolean (*work)(void); | |
| 282 | }; | |
| 283 | ||
| 284 | /* The following are the opcodes used in relax/fix process. */ | |
| 285 | #define CSKYV1_INST_JMPI 0x7000 | |
| 286 | #define CSKYV1_INST_ADDI 0x2000 | |
| 287 | #define CSKYV1_INST_SUBI 0x2400 | |
| 288 | #define CSKYV1_INST_LDW 0x8000 | |
| 289 | #define CSKYV1_INST_STW 0x9000 | |
| 290 | #define CSKYV1_INST_BSR 0xf800 | |
| 291 | #define CSKYV1_INST_LRW 0x7000 | |
| 292 | #define CSKYV1_INST_ADDU 0x1c00 | |
| 293 | #define CSKYV1_INST_JMP 0x00c0 | |
| 294 | #define CSKYV1_INST_MOV_R1_RX 0x1201 | |
| 295 | #define CSKYV1_INST_MOV_RX_R1 0x1210 | |
| 296 | ||
| 297 | #define CSKYV2_INST_BT16 0x0800 | |
| 298 | #define CSKYV2_INST_BF16 0x0c00 | |
| 299 | #define CSKYV2_INST_BT32 0xe8600000 | |
| 300 | #define CSKYV2_INST_BF32 0xe8400000 | |
| 301 | #define CSKYV2_INST_BR32 0xe8000000 | |
| 302 | #define CSKYV2_INST_NOP 0x6c03 | |
| 303 | #define CSKYV2_INST_MOVI16 0x3000 | |
| 304 | #define CSKYV2_INST_MOVI32 0xea000000 | |
| 305 | #define CSKYV2_INST_MOVIH 0xea200000 | |
| 306 | #define CSKYV2_INST_LRW16 0x1000 | |
| 307 | #define CSKYV2_INST_LRW32 0xea800000 | |
| 308 | #define CSKYV2_INST_BSR32 0xe0000000 | |
| 309 | #define CSKYV2_INST_BR32 0xe8000000 | |
| 310 | #define CSKYV2_INST_FLRW 0xf4003800 | |
| 311 | #define CSKYV2_INST_JMPI32 0xeac00000 | |
| 312 | #define CSKYV2_INST_JSRI32 0xeae00000 | |
| 313 | #define CSKYV2_INST_JSRI_TO_LRW 0xea9a0000 | |
| 314 | #define CSKYV2_INST_JSR_R26 0xe8fa0000 | |
| 315 | #define CSKYV2_INST_MOV_R0_R0 0xc4004820 | |
| 316 | ||
| 317 | #define OPRND_SHIFT_0_BIT 0 | |
| 318 | #define OPRND_SHIFT_1_BIT 1 | |
| 319 | #define OPRND_SHIFT_2_BIT 2 | |
| 320 | #define OPRND_SHIFT_3_BIT 3 | |
| 321 | #define OPRND_SHIFT_4_BIT 4 | |
| 322 | ||
| 323 | #define OPRND_MASK_NONE 0x0 | |
| 324 | #define OPRND_MASK_0_1 0x3 | |
| 325 | #define OPRND_MASK_0_2 0x7 | |
| 326 | #define OPRND_MASK_0_3 0xf | |
| 327 | #define OPRND_MASK_0_4 0x1f | |
| 328 | #define OPRND_MASK_0_7 0xff | |
| 329 | #define OPRND_MASK_0_8 0x1ff | |
| 330 | #define OPRND_MASK_0_9 0x3ff | |
| 331 | #define OPRND_MASK_0_10 0x7ff | |
| 332 | #define OPRND_MASK_0_11 0xfff | |
| 333 | #define OPRND_MASK_0_14 0x7fff | |
| 334 | #define OPRND_MASK_0_15 0xffff | |
| 335 | #define OPRND_MASK_0_17 0x3ffff | |
| 336 | #define OPRND_MASK_0_25 0x3ffffff | |
| 337 | #define OPRND_MASK_2_4 0x1c | |
| 338 | #define OPRND_MASK_2_5 0x3c | |
| 339 | #define OPRND_MASK_3_7 0xf8 | |
| 340 | #define OPRND_MASK_4 0x10 | |
| 1feede9b | 341 | #define OPRND_MASK_4_5 0x30 |
| b8891f8d AJ |
342 | #define OPRND_MASK_4_6 0x70 |
| 343 | #define OPRND_MASK_4_7 0xf0 | |
| 344 | #define OPRND_MASK_4_8 0x1f0 | |
| 345 | #define OPRND_MASK_4_10 0x7f0 | |
| 346 | #define OPRND_MASK_5 0x20 | |
| 347 | #define OPRND_MASK_5_6 0x60 | |
| 348 | #define OPRND_MASK_5_7 0xe0 | |
| 349 | #define OPRND_MASK_5_8 0x1e0 | |
| 350 | #define OPRND_MASK_5_9 0x3e0 | |
| 1feede9b CQ |
351 | #define OPRND_MASK_6 0x40 |
| 352 | #define OPRND_MASK_6_7 0xc0 | |
| 353 | #define OPRND_MASK_6_8 0x1c0 | |
| b8891f8d AJ |
354 | #define OPRND_MASK_6_9 0x3c0 |
| 355 | #define OPRND_MASK_6_10 0x7c0 | |
| 1feede9b CQ |
356 | #define OPRND_MASK_7 0x80 |
| 357 | #define OPRND_MASK_7_8 0x180 | |
| b8891f8d AJ |
358 | #define OPRND_MASK_8_9 0x300 |
| 359 | #define OPRND_MASK_8_10 0x700 | |
| 360 | #define OPRND_MASK_8_11 0xf00 | |
| 361 | #define OPRND_MASK_9_10 0x600 | |
| 362 | #define OPRND_MASK_9_12 0x1e00 | |
| 363 | #define OPRND_MASK_10_11 0xc00 | |
| 364 | #define OPRND_MASK_10_14 0x7c00 | |
| 365 | #define OPRND_MASK_12_15 0xf000 | |
| 366 | #define OPRND_MASK_13_17 0x3e000 | |
| 367 | #define OPRND_MASK_16_19 0xf0000 | |
| 368 | #define OPRND_MASK_16_20 0x1f0000 | |
| 369 | #define OPRND_MASK_16_25 0x3ff0000 | |
| 1feede9b CQ |
370 | #define OPRND_MASK_17_24 0x1fe0000 |
| 371 | #define OPRND_MASK_20 0x0100000 | |
| 372 | #define OPRND_MASK_20_21 0x0300000 | |
| 373 | #define OPRND_MASK_20_22 0x0700000 | |
| 374 | #define OPRND_MASK_20_23 0x0f00000 | |
| 375 | #define OPRND_MASK_20_24 0x1f00000 | |
| 376 | #define OPRND_MASK_20_25 0x3f00000 | |
| b8891f8d AJ |
377 | #define OPRND_MASK_21_24 0x1e00000 |
| 378 | #define OPRND_MASK_21_25 0x3e00000 | |
| 379 | #define OPRND_MASK_25 0x2000000 | |
| 380 | #define OPRND_MASK_RSV 0xffffffff | |
| 1feede9b CQ |
381 | #define OPRND_MASK_0_3or5_8 OPRND_MASK_0_3 | OPRND_MASK_5_8 |
| 382 | #define OPRND_MASK_0_3or6_7 OPRND_MASK_0_3 | OPRND_MASK_6_7 | |
| b8891f8d | 383 | #define OPRND_MASK_0_3or21_24 OPRND_MASK_0_3 | OPRND_MASK_21_24 |
| 1feede9b CQ |
384 | #define OPRND_MASK_0_3or25 OPRND_MASK_0_3 | OPRND_MASK_25 |
| 385 | #define OPRND_MASK_0_4or21_24 OPRND_MASK_0_4 | OPRND_MASK_21_24 | |
| b8891f8d AJ |
386 | #define OPRND_MASK_0_4or21_25 OPRND_MASK_0_4 | OPRND_MASK_21_25 |
| 387 | #define OPRND_MASK_0_4or16_20 OPRND_MASK_0_4 | OPRND_MASK_16_20 | |
| 388 | #define OPRND_MASK_0_4or8_10 OPRND_MASK_0_4 | OPRND_MASK_8_10 | |
| 389 | #define OPRND_MASK_0_4or8_9 OPRND_MASK_0_4 | OPRND_MASK_8_9 | |
| 390 | #define OPRND_MASK_0_14or16_20 OPRND_MASK_0_14 | OPRND_MASK_16_20 | |
| 391 | #define OPRND_MASK_4or5_8 OPRND_MASK_4 | OPRND_MASK_5_8 | |
| 1feede9b CQ |
392 | #define OPRND_MASK_5or20_21 OPRND_MASK_5 | OPRND_MASK_20_21 |
| 393 | #define OPRND_MASK_5or20_22 OPRND_MASK_5 | OPRND_MASK_20_22 | |
| 394 | #define OPRND_MASK_5or20_23 OPRND_MASK_5 | OPRND_MASK_20_23 | |
| 395 | #define OPRND_MASK_5or20_24 OPRND_MASK_5 | OPRND_MASK_20_24 | |
| 396 | #define OPRND_MASK_5or20_25 OPRND_MASK_5 | OPRND_MASK_20_25 | |
| b8891f8d AJ |
397 | #define OPRND_MASK_5or21_24 OPRND_MASK_5 | OPRND_MASK_21_24 |
| 398 | #define OPRND_MASK_2_5or6_9 OPRND_MASK_2_5 | OPRND_MASK_6_9 | |
| 399 | #define OPRND_MASK_4_6or21_25 OPRND_MASK_4_6 | OPRND_MASK_21_25 | |
| 400 | #define OPRND_MASK_4_7or21_24 OPRND_MASK_4_7 | OPRND_MASK_21_24 | |
| 401 | #define OPRND_MASK_5_6or21_25 OPRND_MASK_5_6 | OPRND_MASK_21_25 | |
| 402 | #define OPRND_MASK_5_7or8_10 OPRND_MASK_5_7 | OPRND_MASK_8_10 | |
| 403 | #define OPRND_MASK_5_9or21_25 OPRND_MASK_5_9 | OPRND_MASK_21_25 | |
| 1feede9b CQ |
404 | #define OPRND_MASK_8_9or21_25 OPRND_MASK_8_9 | OPRND_MASK_21_25 |
| 405 | #define OPRND_MASK_8_9or16_25 OPRND_MASK_8_9 | OPRND_MASK_16_20 | OPRND_MASK_21_25 | |
| b8891f8d AJ |
406 | #define OPRND_MASK_16_19or21_24 OPRND_MASK_16_19 | OPRND_MASK_21_24 |
| 407 | #define OPRND_MASK_16_20or21_25 OPRND_MASK_16_20 | OPRND_MASK_21_25 | |
| 408 | #define OPRND_MASK_4or9_10or25 OPRND_MASK_4 | OPRND_MASK_9_10 | OPRND_MASK_25 | |
| 409 | #define OPRND_MASK_4_7or16_24 OPRND_MASK_4_7 | OPRND_MASK_16_20 | OPRND_MASK_21_24 | |
| 1feede9b CQ |
410 | #define OPRND_MASK_4_6or20 OPRND_MASK_4_6 | OPRND_MASK_20 |
| 411 | #define OPRND_MASK_5_7or20 OPRND_MASK_5_7 | OPRND_MASK_20 | |
| 412 | #define OPRND_MASK_4_5or20or25 OPRND_MASK_4 | OPRND_MASK_5 | OPRND_MASK_20 | OPRND_MASK_25 | |
| 413 | #define OPRND_MASK_4_6or20or25 OPRND_MASK_4_6 | OPRND_MASK_20 | OPRND_MASK_25 | |
| 414 | #define OPRND_MASK_4_7or20or25 OPRND_MASK_4_7 | OPRND_MASK_20 | OPRND_MASK_25 | |
| 415 | #define OPRND_MASK_6_9or17_24 OPRND_MASK_6_9 | OPRND_MASK_17_24 | |
| 416 | #define OPRND_MASK_6_7or20 OPRND_MASK_6_7 | OPRND_MASK_20 | |
| 417 | #define OPRND_MASK_6or20 OPRND_MASK_6 | OPRND_MASK_20 | |
| 418 | #define OPRND_MASK_7or20 OPRND_MASK_7 | OPRND_MASK_20 | |
| 419 | #define OPRND_MASK_5or8_9or16_25 OPRND_MASK_5 | OPRND_MASK_8_9or16_25 | |
| 420 | #define OPRND_MASK_5or8_9or20_25 OPRND_MASK_5 | OPRND_MASK_8_9 | OPRND_MASK_20_25 | |
| b8891f8d AJ |
421 | |
| 422 | #define OPERAND_INFO(mask, type, shift) \ | |
| 423 | {OPRND_MASK_##mask, OPRND_TYPE_##type, shift} | |
| 424 | ||
| 425 | #define OPCODE_INFO_NONE() \ | |
| 426 | {-2, 0, \ | |
| 427 | {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 428 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 429 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 430 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 431 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
| 432 | ||
| 433 | /* Here and in subsequent macros, the "oprnd" arguments are the | |
| 434 | parenthesized arglist to the OPERAND_INFO macro above. */ | |
| 435 | #define OPCODE_INFO(num, op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ | |
| 436 | {num, op, \ | |
| 437 | {OPERAND_INFO oprnd1, OPERAND_INFO oprnd2, OPERAND_INFO oprnd3, \ | |
| 438 | OPERAND_INFO oprnd4, OPERAND_INFO oprnd5}} | |
| 439 | ||
| 440 | #define OPCODE_INFO0(op) \ | |
| 441 | {0, op, \ | |
| 442 | {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 443 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 444 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 445 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 446 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
| 447 | #define OPCODE_INFO1(op, oprnd) \ | |
| 448 | {1, op, \ | |
| 449 | {{OPERAND_INFO oprnd, \ | |
| 450 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 451 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 452 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 453 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
| 454 | #define OPCODE_INFO2(op, oprnd1, oprnd2) \ | |
| 455 | {2, op, \ | |
| 456 | {{OPERAND_INFO oprnd1, \ | |
| 457 | OPERAND_INFO oprnd2, \ | |
| 458 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 459 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 460 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
| 461 | #define OPCODE_INFO3(op, oprnd1, oprnd2, oprnd3) \ | |
| 462 | {3, op, \ | |
| 463 | {{OPERAND_INFO oprnd1, \ | |
| 464 | OPERAND_INFO oprnd2, \ | |
| 465 | OPERAND_INFO oprnd3, \ | |
| 466 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 467 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
| 468 | #define OPCODE_INFO4(op, oprnd1, oprnd2, oprnd3, oprnd4) \ | |
| 469 | {4, op, \ | |
| 470 | {{OPERAND_INFO oprnd1, \ | |
| 471 | OPERAND_INFO oprnd2, \ | |
| 472 | OPERAND_INFO oprnd3, \ | |
| 473 | OPERAND_INFO oprnd4, \ | |
| 474 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
| 475 | #define OPCODE_INFO_LIST(op, oprnd) \ | |
| 476 | {-1, op, \ | |
| 477 | {{OPERAND_INFO oprnd, \ | |
| 478 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 479 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) , \ | |
| 480 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
| 481 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
| 482 | #define OPCODE_INFO5(op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ | |
| 483 | {5, op, \ | |
| 484 | {{OPERAND_INFO oprnd1, \ | |
| 485 | OPERAND_INFO oprnd2, \ | |
| 486 | OPERAND_INFO oprnd3, \ | |
| 487 | OPERAND_INFO oprnd4, \ | |
| 488 | OPERAND_INFO oprnd5}}} | |
| 489 | ||
| 490 | #define BRACKET_OPRND(oprnd1, oprnd2) \ | |
| 491 | OPERAND_INFO (RSV, BRACKET, OPRND_SHIFT_0_BIT), \ | |
| 492 | OPERAND_INFO oprnd1, \ | |
| 493 | OPERAND_INFO oprnd2, \ | |
| 494 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) | |
| 495 | #define ABRACKET_OPRND(oprnd1, oprnd2) \ | |
| 496 | OPERAND_INFO (RSV, ABRACKET, OPRND_SHIFT_0_BIT), \ | |
| 497 | OPERAND_INFO oprnd1, \ | |
| 498 | OPERAND_INFO oprnd2, \ | |
| 499 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) | |
| 500 | ||
| 501 | #define SOPCODE_INFO1(op, soprnd) \ | |
| 502 | {1, op, \ | |
| 503 | {{soprnd, \ | |
| 504 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
| 505 | #define SOPCODE_INFO2(op, oprnd, soprnd) \ | |
| 506 | {2, op, \ | |
| 507 | {{OPERAND_INFO oprnd, soprnd}}} | |
| 508 | ||
| 509 | ||
| 510 | /* Before using the opcode-defining macros, there need to be | |
| 511 | #defines for _TRANSFER, _RELOC16, _RELOC32, and _RELAX. See | |
| 512 | below. */ | |
| 513 | /* FIXME: it is a wart that these parameters are not explicit. */ | |
| 514 | ||
| 515 | #define OP16(mnem, opcode16, isa) \ | |
| 516 | {mnem, _TRANSFER, \ | |
| 517 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
| 518 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 519 | isa, 0, _RELOC16, 0, _RELAX, NULL} | |
| 520 | ||
| 521 | #ifdef BUILD_AS | |
| 522 | ||
| 523 | #define OP16_WITH_WORK(mnem, opcode16, isa, work) \ | |
| 524 | {mnem, _TRANSFER, \ | |
| 525 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
| 526 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 527 | isa, 0, _RELOC16, 0, _RELAX, work} | |
| 528 | #define OP32_WITH_WORK(mnem, opcode32, isa, work) \ | |
| 529 | {mnem, _TRANSFER, \ | |
| 530 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 531 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 532 | 0, isa, 0, _RELOC32, _RELAX, work} | |
| 533 | #define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ | |
| 534 | {mnem, _TRANSFER, \ | |
| 535 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
| 536 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 537 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} | |
| 538 | #define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ | |
| 539 | {mnem, _TRANSFER, \ | |
| 540 | {opcode16a, opcode16b}, \ | |
| 541 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 542 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} | |
| 543 | #define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ | |
| 544 | {mnem, _TRANSFER, \ | |
| 545 | {opcode16a, opcode16b}, \ | |
| 546 | {opcode32a, opcode32b}, \ | |
| 547 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} | |
| 548 | #define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ | |
| 549 | {mnem, _TRANSFER, \ | |
| 550 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 551 | {opcode32a, opcode32b}, \ | |
| 552 | 0, isa, 0, _RELOC32, _RELAX, work} | |
| 553 | ||
| 554 | #else /* ifdef BUILD_AS */ | |
| 555 | ||
| 556 | #define OP16_WITH_WORK(mnem, opcode16, isa, work) \ | |
| 557 | {mnem, _TRANSFER, \ | |
| 558 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
| 559 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 560 | isa, 0, _RELOC16, 0, _RELAX, NULL} | |
| 561 | #define OP32_WITH_WORK(mnem, opcode32, isa, work) \ | |
| 562 | {mnem, _TRANSFER, \ | |
| 563 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 564 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 565 | 0, isa, 0, _RELOC32, _RELAX, NULL} | |
| 566 | #define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ | |
| 567 | {mnem, _TRANSFER, \ | |
| 568 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
| 569 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 570 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
| 571 | #define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ | |
| 572 | {mnem, _TRANSFER, \ | |
| 573 | {opcode16a, opcode16b}, \ | |
| 574 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 575 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
| 576 | #define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ | |
| 577 | {mnem, _TRANSFER, \ | |
| 578 | {opcode16a, opcode16b}, \ | |
| 579 | {opcode32a, opcode32b}, \ | |
| 580 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
| 581 | #define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ | |
| 582 | {mnem, _TRANSFER, \ | |
| 583 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 584 | {opcode32a, opcode32b}, \ | |
| 585 | 0, isa, 0, _RELOC32, _RELAX, NULL} | |
| 586 | ||
| 587 | #endif /* ifdef BUILD_AS */ | |
| 588 | ||
| 589 | #define DOP16(mnem, opcode16_1, opcode16_2, isa) \ | |
| 590 | {mnem, _TRANSFER, \ | |
| 591 | {opcode16_1, opcode16_2}, \ | |
| 592 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 593 | isa, 0, _RELOC16, 0, _RELAX, NULL} | |
| 594 | #define OP32(mnem, opcode32, isa) \ | |
| 595 | {mnem, _TRANSFER, \ | |
| 596 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 597 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 598 | 0, isa, 0, _RELOC32, _RELAX, NULL} | |
| 599 | #define DOP32(mnem, opcode32a, opcode32b, isa) \ | |
| 600 | {mnem, _TRANSFER, \ | |
| 601 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
| 602 | {opcode32a, opcode32b}, \ | |
| 603 | 0, isa, 0, _RELOC32, _RELAX, NULL} | |
| 604 | #define OP16_OP32(mnem, opcode16, isa16, opcode32, isa32) \ | |
| 605 | {mnem, _TRANSFER, \ | |
| 606 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
| 607 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 608 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
| 609 | #define DOP16_OP32(mnem, opcode16a, opcode16b, isa16, opcode32, isa32) \ | |
| 610 | {mnem, _TRANSFER, \ | |
| 611 | {opcode16a, opcode16b}, \ | |
| 612 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
| 613 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
| 614 | #define OP16_DOP32(mnem, opcode16, isa16, opcode32a, opcode32b, isa32) \ | |
| 615 | {mnem, _TRANSFER, \ | |
| 616 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
| 617 | {opcode32a, opcode32b}, \ | |
| 618 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
| 619 | #define DOP16_DOP32(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32) \ | |
| 620 | {mnem, _TRANSFER, \ | |
| 621 | {opcode16a, opcode16b}, \ | |
| 622 | {opcode32a, opcode32b}, \ | |
| 623 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
| 624 | ||
| 625 | ||
| 626 | /* Register names and numbers. */ | |
| 627 | #define V1_REG_SP 0 | |
| 628 | #define V1_REG_LR 15 | |
| 629 | ||
| afdcafe8 | 630 | struct psrbit |
| b8891f8d | 631 | { |
| afdcafe8 CQ |
632 | int value; |
| 633 | int isa; | |
| b8891f8d | 634 | const char *name; |
| b8891f8d AJ |
635 | }; |
| 636 | ||
| afdcafe8 | 637 | const struct psrbit cskyv1_psr_bits[] = |
| b8891f8d | 638 | { |
| afdcafe8 CQ |
639 | {1, 0, "ie"}, |
| 640 | {2, 0, "fe"}, | |
| 641 | {4, 0, "ee"}, | |
| 642 | {8, 0, "af"}, | |
| 643 | {0, 0, NULL}, | |
| b8891f8d AJ |
644 | }; |
| 645 | ||
| afdcafe8 | 646 | const struct psrbit cskyv2_psr_bits[] = |
| b8891f8d | 647 | { |
| afdcafe8 CQ |
648 | {8, 0, "ee"}, |
| 649 | {4, 0, "ie"}, | |
| 650 | {2, 0, "fe"}, | |
| 651 | {1, 0, "af"}, | |
| 652 | {0x10, CSKY_ISA_TRUST, "sie"}, | |
| 653 | {0, 0, NULL}, | |
| b8891f8d AJ |
654 | }; |
| 655 | ||
| afdcafe8 CQ |
656 | #define GENARAL_REG_BANK 0x80000000 |
| 657 | #define REG_SUPPORT_ALL 0xffffffff | |
| 658 | ||
| 659 | /* CSKY register description. */ | |
| 660 | struct csky_reg_def | |
| b8891f8d | 661 | { |
| afdcafe8 CQ |
662 | /* The group number for control registers, |
| 663 | and set the bank of genaral registers to a special number. */ | |
| 664 | int bank; | |
| 665 | int regno; | |
| 666 | /* The name displayed by serial number. */ | |
| 667 | const char *name; | |
| 668 | /* The name displayed by ABI infomation, | |
| 669 | used when objdump add option -Mabi-names. */ | |
| 670 | const char *abi_name; | |
| 671 | /* The flags indicate which arches support the register. */ | |
| 672 | int arch_flag; | |
| 673 | /* Some registers depend on special features. */ | |
| 674 | char *features; | |
| b8891f8d AJ |
675 | }; |
| 676 | ||
| afdcafe8 CQ |
677 | /* Arch flag. */ |
| 678 | #define ASH(a) (1 << CSKY_ARCH_##a) | |
| 679 | ||
| 680 | /* All arches exclued 801. */ | |
| 681 | #define REG_SUPPORT_A (REG_SUPPORT_ALL & ~ASH(801)) | |
| 682 | ||
| 683 | /* All arches exclued 801 and 802. */ | |
| 684 | #define REG_SUPPORT_B (REG_SUPPORT_ALL & ~(ASH(801) | ASH(802))) | |
| 685 | ||
| 686 | /* All arches exclued 801, 802, 803, 805.*/ | |
| 687 | #define REG_SUPPORT_C (REG_SUPPORT_ALL & ~(ASH(801) \ | |
| 688 | | ASH(802) | ASH(803) | ASH(805))) | |
| 689 | ||
| 690 | /* All arches exclued 801, 802, 803, 805, 807, 810. */ | |
| 691 | #define REG_SUPPORT_D (REG_SUPPORT_C & ~(ASH(807) | ASH(810))) | |
| 692 | ||
| 693 | /* All arches exclued 807, 810, 860. */ | |
| 694 | #define REG_SUPPORT_E (REG_SUPPORT_ALL & ~(ASH(807) | ASH(810) | \ | |
| 695 | ASH(860))) | |
| 696 | ||
| 697 | /* C-SKY V1 general registers table. */ | |
| 698 | static struct csky_reg_def csky_abiv1_general_regs[] = | |
| b8891f8d | 699 | { |
| afdcafe8 CQ |
700 | #define DECLARE_REG(regno, abi_name, support) \ |
| 701 | {GENARAL_REG_BANK, regno, "r"#regno, abi_name, support, NULL} | |
| 702 | ||
| 703 | DECLARE_REG (0, "sp", REG_SUPPORT_ALL), | |
| 704 | DECLARE_REG (1, NULL, REG_SUPPORT_ALL), | |
| 705 | DECLARE_REG (2, "a0", REG_SUPPORT_ALL), | |
| 706 | DECLARE_REG (3, "a1", REG_SUPPORT_ALL), | |
| 707 | DECLARE_REG (4, "a2", REG_SUPPORT_ALL), | |
| 708 | DECLARE_REG (5, "a3", REG_SUPPORT_ALL), | |
| 709 | DECLARE_REG (6, "a4", REG_SUPPORT_ALL), | |
| 710 | DECLARE_REG (7, "a5", REG_SUPPORT_ALL), | |
| 711 | DECLARE_REG (8, "fp", REG_SUPPORT_ALL), | |
| 712 | DECLARE_REG (8, "l0", REG_SUPPORT_ALL), | |
| 713 | DECLARE_REG (9, "l1", REG_SUPPORT_ALL), | |
| 714 | DECLARE_REG (10, "l2", REG_SUPPORT_ALL), | |
| 715 | DECLARE_REG (11, "l3", REG_SUPPORT_ALL), | |
| 716 | DECLARE_REG (12, "l4", REG_SUPPORT_ALL), | |
| 717 | DECLARE_REG (13, "l5", REG_SUPPORT_ALL), | |
| 718 | DECLARE_REG (14, "gb", REG_SUPPORT_ALL), | |
| 719 | DECLARE_REG (15, "lr", REG_SUPPORT_ALL), | |
| 720 | #undef DECLARE_REG | |
| 721 | {-1, -1, NULL, NULL, 0, NULL}, | |
| b8891f8d AJ |
722 | }; |
| 723 | ||
| afdcafe8 CQ |
724 | /* C-SKY V1 control registers table. */ |
| 725 | static struct csky_reg_def csky_abiv1_control_regs[] = | |
| b8891f8d | 726 | { |
| afdcafe8 CQ |
727 | #define DECLARE_REG(regno, abi_name, support) \ |
| 728 | {0, regno, "cr"#regno, abi_name, support, NULL} | |
| 729 | ||
| 730 | DECLARE_REG (0, "psr", REG_SUPPORT_ALL), | |
| 731 | DECLARE_REG (1, "vbr", REG_SUPPORT_ALL), | |
| 732 | DECLARE_REG (2, "epsr", REG_SUPPORT_ALL), | |
| 733 | DECLARE_REG (3, "fpsr", REG_SUPPORT_ALL), | |
| 734 | DECLARE_REG (4, "epc", REG_SUPPORT_ALL), | |
| 735 | DECLARE_REG (5, "fpc", REG_SUPPORT_ALL), | |
| 736 | DECLARE_REG (6, "ss0", REG_SUPPORT_ALL), | |
| 737 | DECLARE_REG (7, "ss1", REG_SUPPORT_ALL), | |
| 738 | DECLARE_REG (8, "ss2", REG_SUPPORT_ALL), | |
| 739 | DECLARE_REG (9, "ss3", REG_SUPPORT_ALL), | |
| 740 | DECLARE_REG (10, "ss4", REG_SUPPORT_ALL), | |
| 741 | DECLARE_REG (11, "gcr", REG_SUPPORT_ALL), | |
| 742 | DECLARE_REG (12, "gsr", REG_SUPPORT_ALL), | |
| 743 | DECLARE_REG (13, "cpid", REG_SUPPORT_ALL), | |
| 744 | DECLARE_REG (14, "dcsr", REG_SUPPORT_ALL), | |
| 745 | DECLARE_REG (15, "cwr", REG_SUPPORT_ALL), | |
| 746 | DECLARE_REG (16, NULL, REG_SUPPORT_ALL), | |
| 747 | DECLARE_REG (17, "cfr", REG_SUPPORT_ALL), | |
| 748 | DECLARE_REG (18, "ccr", REG_SUPPORT_ALL), | |
| 749 | DECLARE_REG (19, "capr", REG_SUPPORT_ALL), | |
| 750 | DECLARE_REG (20, "pacr", REG_SUPPORT_ALL), | |
| 751 | DECLARE_REG (21, "prsr", REG_SUPPORT_ALL), | |
| 752 | DECLARE_REG (22, "mir", REG_SUPPORT_ALL), | |
| 753 | DECLARE_REG (23, "mrr", REG_SUPPORT_ALL), | |
| 754 | DECLARE_REG (24, "mel0", REG_SUPPORT_ALL), | |
| 755 | DECLARE_REG (25, "mel1", REG_SUPPORT_ALL), | |
| 756 | DECLARE_REG (26, "meh", REG_SUPPORT_ALL), | |
| 757 | DECLARE_REG (27, "mcr", REG_SUPPORT_ALL), | |
| 758 | DECLARE_REG (28, "mpr", REG_SUPPORT_ALL), | |
| 759 | DECLARE_REG (29, "mwr", REG_SUPPORT_ALL), | |
| 760 | DECLARE_REG (30, "mcir", REG_SUPPORT_ALL), | |
| 761 | #undef DECLARE_REG | |
| 762 | {-1, -1, NULL, NULL, 0, NULL}, | |
| b8891f8d AJ |
763 | }; |
| 764 | ||
| afdcafe8 CQ |
765 | /* C-SKY V2 general registers table. */ |
| 766 | static struct csky_reg_def csky_abiv2_general_regs[] = | |
| b8891f8d | 767 | { |
| afdcafe8 CQ |
768 | #ifdef DECLARE_REG |
| 769 | #undef DECLARE_REG | |
| 770 | #endif | |
| 771 | #define DECLARE_REG(regno, abi_name, support) \ | |
| 772 | {GENARAL_REG_BANK, regno, "r"#regno, abi_name, support, NULL} | |
| 773 | ||
| 774 | DECLARE_REG (0, "a0", REG_SUPPORT_ALL), | |
| 775 | DECLARE_REG (1, "a1", REG_SUPPORT_ALL), | |
| 776 | DECLARE_REG (2, "a2", REG_SUPPORT_ALL), | |
| 777 | DECLARE_REG (3, "a3", REG_SUPPORT_ALL), | |
| 778 | DECLARE_REG (4, "l0", REG_SUPPORT_ALL), | |
| 779 | DECLARE_REG (5, "l1", REG_SUPPORT_ALL), | |
| 780 | DECLARE_REG (6, "l2", REG_SUPPORT_ALL), | |
| 781 | DECLARE_REG (7, "l3", REG_SUPPORT_ALL), | |
| 782 | DECLARE_REG (8, "l4", REG_SUPPORT_ALL), | |
| 783 | DECLARE_REG (9, "l5", REG_SUPPORT_A), | |
| 784 | DECLARE_REG (10, "l6", REG_SUPPORT_A), | |
| 785 | DECLARE_REG (11, "l7", REG_SUPPORT_A), | |
| 786 | DECLARE_REG (12, "t0", REG_SUPPORT_A), | |
| 787 | DECLARE_REG (13, "t1", REG_SUPPORT_ALL), | |
| 788 | DECLARE_REG (14, "sp", REG_SUPPORT_ALL), | |
| 789 | DECLARE_REG (15, "lr", REG_SUPPORT_ALL), | |
| 790 | DECLARE_REG (16, "l8", REG_SUPPORT_B), | |
| 791 | DECLARE_REG (17, "l9", REG_SUPPORT_B), | |
| 792 | DECLARE_REG (18, "t2", REG_SUPPORT_B), | |
| 793 | DECLARE_REG (19, "t3", REG_SUPPORT_B), | |
| 794 | DECLARE_REG (20, "t4", REG_SUPPORT_B), | |
| 795 | DECLARE_REG (21, "t5", REG_SUPPORT_B), | |
| 796 | DECLARE_REG (22, "t6", REG_SUPPORT_B), | |
| 797 | DECLARE_REG (23, "t7", REG_SUPPORT_B), | |
| 798 | DECLARE_REG (24, "t8", REG_SUPPORT_B), | |
| 799 | DECLARE_REG (25, "t9", REG_SUPPORT_B), | |
| 800 | DECLARE_REG (26, NULL, REG_SUPPORT_B), | |
| 801 | DECLARE_REG (27, NULL, REG_SUPPORT_B), | |
| 802 | DECLARE_REG (28, "gb", REG_SUPPORT_B), | |
| 803 | DECLARE_REG (28, "rgb", REG_SUPPORT_B), | |
| 804 | DECLARE_REG (28, "rdb", REG_SUPPORT_B), | |
| 805 | DECLARE_REG (29, "tb", REG_SUPPORT_B), | |
| 806 | DECLARE_REG (29, "rtb", REG_SUPPORT_B), | |
| 807 | DECLARE_REG (30, "svbr", REG_SUPPORT_A), | |
| 808 | DECLARE_REG (31, "tls", REG_SUPPORT_B), | |
| 809 | ||
| 810 | /* The followings JAVA/BCTM's features. */ | |
| 811 | DECLARE_REG (23, "fp", REG_SUPPORT_ALL), | |
| 812 | DECLARE_REG (24, "top", REG_SUPPORT_ALL), | |
| 813 | DECLARE_REG (25, "bsp", REG_SUPPORT_ALL), | |
| 814 | ||
| 815 | {-1, -1, NULL, NULL, 0, NULL}, | |
| b8891f8d AJ |
816 | }; |
| 817 | ||
| afdcafe8 CQ |
818 | /* C-SKY V2 control registers table. */ |
| 819 | static struct csky_reg_def csky_abiv2_control_regs[] = | |
| b8891f8d | 820 | { |
| afdcafe8 CQ |
821 | |
| 822 | #ifdef DECLARE_REG | |
| 823 | #undef DECLARE_REG | |
| 824 | #endif | |
| 825 | /* Bank0. */ | |
| 826 | #define DECLARE_REG(regno, abi_name) \ | |
| 827 | {0, regno, "cr<"#regno", 0>", abi_name, REG_SUPPORT_ALL, NULL} | |
| 828 | DECLARE_REG (0, "psr"), | |
| 829 | DECLARE_REG (1, "vbr"), | |
| 830 | DECLARE_REG (2, "epsr"), | |
| 831 | DECLARE_REG (3, "fpsr"), | |
| 832 | DECLARE_REG (4, "epc"), | |
| 833 | DECLARE_REG (5, "fpc"), | |
| 834 | DECLARE_REG (6, "ss0"), | |
| 835 | DECLARE_REG (7, "ss1"), | |
| 836 | DECLARE_REG (8, "ss2"), | |
| 837 | DECLARE_REG (9, "ss3"), | |
| 838 | DECLARE_REG (10, "ss4"), | |
| 839 | DECLARE_REG (11, "gcr"), | |
| 840 | DECLARE_REG (12, "gsr"), | |
| 841 | DECLARE_REG (13, "cpid"), | |
| 842 | DECLARE_REG (14, "dcsr"), | |
| 843 | DECLARE_REG (15, NULL), | |
| 844 | DECLARE_REG (16, NULL), | |
| 845 | DECLARE_REG (17, "cfr"), | |
| 846 | DECLARE_REG (18, "ccr"), | |
| 847 | DECLARE_REG (19, "capr"), | |
| 848 | DECLARE_REG (20, "pacr"), | |
| 849 | DECLARE_REG (21, "prsr"), | |
| 850 | DECLARE_REG (22, "cir"), | |
| 851 | DECLARE_REG (23, "ccr2"), | |
| 852 | DECLARE_REG (24, NULL), | |
| 853 | DECLARE_REG (25, "cer2"), | |
| 854 | DECLARE_REG (26, NULL), | |
| 855 | DECLARE_REG (27, NULL), | |
| 856 | DECLARE_REG (28, "rvbr"), | |
| 857 | DECLARE_REG (29, "rmr"), | |
| 858 | DECLARE_REG (30, "mpid"), | |
| 859 | ||
| 860 | #undef DECLARE_REG | |
| 861 | #define DECLARE_REG(regno, abi_name, support) \ | |
| 862 | {0, regno, "cr<"#regno", 0>", abi_name, support, NULL} | |
| 863 | DECLARE_REG (31, "chr", REG_SUPPORT_E), | |
| 864 | DECLARE_REG (31, "hint", REG_SUPPORT_C), | |
| 865 | ||
| 866 | /* Bank1. */ | |
| 867 | #undef DECLARE_REG | |
| 868 | #define DECLARE_REG(regno, abi_name) \ | |
| 869 | {1, regno, "cr<"#regno", 1>", abi_name, REG_SUPPORT_ALL, NULL} | |
| 870 | ||
| 871 | DECLARE_REG (14, "usp"), | |
| 872 | DECLARE_REG (26, "cindex"), | |
| 873 | DECLARE_REG (27, "cdata0"), | |
| 874 | DECLARE_REG (28, "cdata1"), | |
| 875 | DECLARE_REG (29, "cdata2"), | |
| 876 | DECLARE_REG (30, "cdata3"), | |
| 877 | DECLARE_REG (31, "cins"), | |
| 878 | ||
| 879 | /* Bank2. */ | |
| 880 | #undef DECLARE_REG | |
| 881 | #define DECLARE_REG(regno, abi_name) \ | |
| 882 | {2, regno, "cr<"#regno", 2>", abi_name, REG_SUPPORT_ALL, NULL} | |
| 883 | ||
| 884 | DECLARE_REG (0, "fid"), | |
| 885 | DECLARE_REG (1, "fcr"), | |
| 886 | DECLARE_REG (2, "fesr"), | |
| 887 | ||
| 888 | /* Bank3. */ | |
| 889 | #undef DECLARE_REG | |
| 890 | #define DECLARE_REG(regno, abi_name) \ | |
| 891 | {3, regno, "cr<"#regno", 3>", abi_name, REG_SUPPORT_ALL, NULL} | |
| 892 | DECLARE_REG (8, "dcr"), | |
| 893 | DECLARE_REG (8, "sedcr"), | |
| 894 | DECLARE_REG (9, "pcr"), | |
| 895 | DECLARE_REG (9, "sepcr"), | |
| 896 | ||
| 897 | /* Bank15. */ | |
| 898 | #undef DECLARE_REG | |
| 899 | #define DECLARE_REG(regno, abi_name) \ | |
| 900 | {15, regno, "cr<"#regno", 15>", abi_name, REG_SUPPORT_ALL, NULL} | |
| 901 | ||
| 902 | DECLARE_REG (0, "mir"), | |
| 903 | DECLARE_REG (2, "mel0"), | |
| 904 | DECLARE_REG (3, "mel1"), | |
| 905 | DECLARE_REG (4, "meh"), | |
| 906 | DECLARE_REG (6, "mpr"), | |
| 907 | DECLARE_REG (8, "mcir"), | |
| 908 | DECLARE_REG (28, "mpgd0"), | |
| 909 | DECLARE_REG (29, "mpgd"), | |
| 910 | DECLARE_REG (29, "mpgd1"), | |
| 911 | DECLARE_REG (30, "msa0"), | |
| 912 | DECLARE_REG (31, "msa1"), | |
| 913 | #undef DECLARE_REG | |
| 914 | {-1, -1, NULL, NULL, 0, NULL}, | |
| b8891f8d AJ |
915 | }; |
| 916 | ||
| afdcafe8 CQ |
917 | /* Get register name according to giving parameters, |
| 918 | IS_ABI controls whether is ABI name or not. */ | |
| 919 | static inline const char * | |
| 920 | get_register_name (struct csky_reg_def *reg_table, | |
| 921 | int arch, int bank, int regno, int is_abi) | |
| b8891f8d | 922 | { |
| afdcafe8 CQ |
923 | static char regname[64] = {0}; |
| 924 | unsigned int i = 0; | |
| 925 | while (reg_table[i].name != NULL) | |
| 926 | { | |
| 927 | if (reg_table[i].bank == bank | |
| 928 | && reg_table[i].regno == regno | |
| 929 | && (reg_table[i].arch_flag & (1 << arch))) | |
| 930 | { | |
| 931 | if (is_abi && reg_table[i].abi_name) | |
| 932 | return reg_table[i].abi_name; | |
| 933 | else | |
| 934 | return reg_table[i].name; | |
| 935 | } | |
| 936 | i++; | |
| 937 | } | |
| b8891f8d | 938 | |
| afdcafe8 CQ |
939 | if (bank & 0x80000000) |
| 940 | return "unkown register"; | |
| 941 | ||
| 942 | sprintf (regname, "cr<%d, %d>", regno, bank); | |
| 943 | ||
| 944 | return regname; | |
| 945 | } | |
| 946 | ||
| 947 | /* Get register number according to giving parameters. | |
| 948 | If not found, return -1. */ | |
| 949 | static inline int | |
| 950 | get_register_number (struct csky_reg_def *reg_table, | |
| 951 | int arch, char *s, char **end, int *bank) | |
| b8891f8d | 952 | { |
| afdcafe8 CQ |
953 | unsigned int i = 0; |
| 954 | int len = 0; | |
| 955 | while (reg_table[i].name != NULL) | |
| 956 | { | |
| 957 | len = strlen (reg_table[i].name); | |
| 958 | if ((strncasecmp (reg_table[i].name, s, len) == 0) | |
| 959 | && !(ISDIGIT (s[len])) | |
| 960 | && (reg_table[i].arch_flag & (1 << arch))) | |
| 961 | { | |
| 962 | *end = s + len; | |
| 963 | *bank = reg_table[i].bank; | |
| 964 | return reg_table[i].regno; | |
| 965 | } | |
| 966 | ||
| 967 | if (reg_table[i].abi_name == NULL) | |
| 968 | { | |
| 969 | i++; | |
| 970 | continue; | |
| 971 | } | |
| 972 | ||
| 973 | len = strlen (reg_table[i].abi_name); | |
| 974 | if ((strncasecmp (reg_table[i].abi_name, s, len) == 0) | |
| 975 | && !(ISALNUM (s[len])) | |
| 976 | && (reg_table[i].arch_flag & (1 << arch))) | |
| 977 | { | |
| 978 | *end = s + len; | |
| 979 | *bank = reg_table[i].bank; | |
| 980 | return reg_table[i].regno; | |
| 981 | } | |
| 982 | i++; | |
| 983 | } | |
| 984 | return -1; | |
| 985 | } | |
| 986 | ||
| 987 | /* Return general register's name. */ | |
| 988 | static inline const char * | |
| 989 | csky_get_general_reg_name (int arch, int regno, int is_abi) | |
| b8891f8d | 990 | { |
| afdcafe8 CQ |
991 | struct csky_reg_def *reg_table; |
| 992 | ||
| 993 | if (IS_CSKY_ARCH_V1(arch)) | |
| 994 | reg_table = csky_abiv1_general_regs; | |
| 995 | else | |
| 996 | reg_table = csky_abiv2_general_regs; | |
| 997 | ||
| 998 | return get_register_name (reg_table, arch, | |
| 999 | GENARAL_REG_BANK, regno, is_abi); | |
| 1000 | } | |
| 1001 | ||
| 1002 | /* Return general register's number. */ | |
| 1003 | static inline int | |
| 1004 | csky_get_general_regno(int arch, char *s, char **end) | |
| b8891f8d | 1005 | { |
| afdcafe8 CQ |
1006 | struct csky_reg_def *reg_table; |
| 1007 | int bank = 0; | |
| 1008 | ||
| 1009 | if (IS_CSKY_ARCH_V1(arch)) | |
| 1010 | reg_table = csky_abiv1_general_regs; | |
| 1011 | else | |
| 1012 | reg_table = csky_abiv2_general_regs; | |
| b8891f8d | 1013 | |
| afdcafe8 CQ |
1014 | return get_register_number (reg_table, arch, s, end, &bank); |
| 1015 | } | |
| 1016 | ||
| 1017 | /* Return control register's name. */ | |
| 1018 | static inline const char * | |
| 1019 | csky_get_control_reg_name (int arch, int bank, int regno, int is_abi) | |
| 1020 | { | |
| 1021 | struct csky_reg_def *reg_table; | |
| 1022 | ||
| 1023 | if (IS_CSKY_ARCH_V1(arch)) | |
| 1024 | reg_table = csky_abiv1_control_regs; | |
| 1025 | else | |
| 1026 | reg_table = csky_abiv2_control_regs; | |
| 1027 | ||
| 1028 | return get_register_name (reg_table, arch, bank, | |
| 1029 | regno, is_abi); | |
| 1030 | } | |
| 1031 | ||
| 1032 | /* Return control register's number. */ | |
| 1033 | static inline int | |
| 1034 | csky_get_control_regno(int arch, char *s, char **end, int *bank) | |
| 1035 | { | |
| 1036 | struct csky_reg_def *reg_table; | |
| 1037 | ||
| 1038 | if (IS_CSKY_ARCH_V1(arch)) | |
| 1039 | reg_table = csky_abiv1_control_regs; | |
| 1040 | else | |
| 1041 | reg_table = csky_abiv2_control_regs; | |
| 1042 | ||
| 1043 | return get_register_number (reg_table, arch, s, end, bank); | |
| 1044 | } | |
| b8891f8d AJ |
1045 | |
| 1046 | /* C-SKY V1 opcodes. */ | |
| 1047 | const struct csky_opcode csky_v1_opcodes[] = | |
| 1048 | { | |
| 1049 | #define _TRANSFER 0 | |
| 1050 | #define _RELOC16 0 | |
| 1051 | #define _RELOC32 0 | |
| 1052 | #define _RELAX 0 | |
| 1053 | OP16 ("bkpt", | |
| 1054 | OPCODE_INFO0 (0x0000), | |
| 1055 | CSKYV1_ISA_E1), | |
| 1056 | OP16 ("sync", | |
| 1057 | OPCODE_INFO0 (0x0001), | |
| 1058 | CSKYV1_ISA_E1), | |
| 1059 | #undef _TRANSFER | |
| 1060 | #define _TRANSFER 2 | |
| 1061 | OP16 ("rfi", | |
| 1062 | OPCODE_INFO0 (0x0003), | |
| 1063 | CSKYV1_ISA_E1), | |
| 1064 | #undef _TRANSFER | |
| 1065 | #define _TRANSFER 0 | |
| 1066 | OP16 ("stop", | |
| 1067 | OPCODE_INFO0 (0x0004), | |
| 1068 | CSKYV1_ISA_E1), | |
| 1069 | OP16 ("wait", | |
| 1070 | OPCODE_INFO0 (0x0005), | |
| 1071 | CSKYV1_ISA_E1), | |
| 1072 | OP16 ("doze", | |
| 1073 | OPCODE_INFO0 (0x0006), | |
| 1074 | CSKYV1_ISA_E1), | |
| 1075 | OP16 ("idly4", | |
| 1076 | OPCODE_INFO0 (0x0007), | |
| 1077 | CSKYV1_ISA_E1), | |
| 1078 | OP16 ("trap", | |
| 1079 | OPCODE_INFO1 (0x0008, | |
| 1080 | (0_1, IMM2b, OPRND_SHIFT_0_BIT)), | |
| 1081 | CSKYV1_ISA_E1), | |
| 1082 | OP16 ("mvtc", | |
| 1083 | OPCODE_INFO0 (0x000c), | |
| 1084 | CSKY_ISA_DSP), | |
| 1085 | OP16 ("cprc", | |
| 1086 | OPCODE_INFO0 (0x000d), | |
| 1087 | CSKY_ISA_CP), | |
| 1088 | OP16 ("cpseti", | |
| 1089 | OPCODE_INFO1 (0x0010, | |
| 1090 | (0_3, CPIDX, OPRND_SHIFT_0_BIT)), | |
| 1091 | CSKY_ISA_CP), | |
| 1092 | OP16 ("mvc", | |
| 1093 | OPCODE_INFO1 (0x0020, | |
| 1094 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1095 | CSKYV1_ISA_E1), | |
| 1096 | OP16 ("mvcv", | |
| 1097 | OPCODE_INFO1 (0x0030, | |
| 1098 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1099 | CSKYV1_ISA_E1), | |
| 1100 | OP16 ("ldq", | |
| 1101 | OPCODE_INFO2 (0x0040, | |
| 1102 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), | |
| 1103 | (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), | |
| 1104 | CSKYV1_ISA_E1), | |
| 1105 | OP16 ("stq", | |
| 1106 | OPCODE_INFO2 (0x0050, | |
| 1107 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), | |
| 1108 | (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), | |
| 1109 | CSKYV1_ISA_E1), | |
| 1110 | OP16 ("ldm", | |
| 1111 | OPCODE_INFO2 (0x0060, | |
| 1112 | (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 1113 | (NONE, REGbsp, OPRND_SHIFT_0_BIT)), | |
| 1114 | CSKYV1_ISA_E1), | |
| 1115 | OP16 ("stm", | |
| 1116 | OPCODE_INFO2 (0x0070, | |
| 1117 | (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 1118 | (NONE, REGbsp, OPRND_SHIFT_0_BIT)), | |
| 1119 | CSKYV1_ISA_E1), | |
| 1120 | DOP16 ("dect", | |
| 1121 | OPCODE_INFO3 (0x0080, | |
| 1122 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1123 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1124 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1125 | OPCODE_INFO1 (0x0080, | |
| 1126 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1127 | CSKYV1_ISA_E1), | |
| 1128 | DOP16 ("decf", | |
| 1129 | OPCODE_INFO3 (0x0090, | |
| 1130 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1131 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1132 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1133 | OPCODE_INFO1 (0x0090, | |
| 1134 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1135 | CSKYV1_ISA_E1), | |
| 1136 | DOP16 ("inct", | |
| 1137 | OPCODE_INFO3 (0x00a0, | |
| 1138 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1139 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1140 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1141 | OPCODE_INFO1 (0x00a0, | |
| 1142 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1143 | CSKYV1_ISA_E1), | |
| 1144 | DOP16 ("incf", | |
| 1145 | OPCODE_INFO3 (0x00b0, | |
| 1146 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1147 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1148 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1149 | OPCODE_INFO1 (0x00b0, | |
| 1150 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1151 | CSKYV1_ISA_E1), | |
| 1152 | #undef _TRANSFER | |
| 1153 | #define _TRANSFER 2 | |
| 1154 | OP16 ("jmp", | |
| 1155 | OPCODE_INFO1 (0x00c0, | |
| 1156 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1157 | CSKYV1_ISA_E1), | |
| 1158 | #undef _TRANSFER | |
| 1159 | #define _TRANSFER 0 | |
| 1160 | OP16 ("jsr", | |
| 1161 | OPCODE_INFO1 (0x00d0, | |
| 1162 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1163 | CSKYV1_ISA_E1), | |
| 1164 | DOP16 ("ff1", | |
| 1165 | OPCODE_INFO2 (0x00e0, | |
| 1166 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1167 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
| 1168 | OPCODE_INFO1 (0x00e0, | |
| 1169 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1170 | CSKYV1_ISA_E1), | |
| 1171 | DOP16 ("brev", | |
| 1172 | OPCODE_INFO2 (0x00f0, | |
| 1173 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1174 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
| 1175 | OPCODE_INFO1 (0x00f0, | |
| 1176 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1177 | CSKYV1_ISA_E1), | |
| 1178 | DOP16 ("xtrb3", | |
| 1179 | OPCODE_INFO2 (0x0100, | |
| 1180 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), | |
| 1181 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1182 | OPCODE_INFO1 (0x0100, | |
| 1183 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1184 | CSKYV1_ISA_E1), | |
| 1185 | DOP16 ("xtrb2", | |
| 1186 | OPCODE_INFO2 (0x0110, | |
| 1187 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), | |
| 1188 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1189 | OPCODE_INFO1 (0x0110, | |
| 1190 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1191 | CSKYV1_ISA_E1), | |
| 1192 | DOP16 ("xtrb1", | |
| 1193 | OPCODE_INFO2 (0x0120, | |
| 1194 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), | |
| 1195 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1196 | OPCODE_INFO1 (0x0120, | |
| 1197 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1198 | CSKYV1_ISA_E1), | |
| 1199 | DOP16 ("xtrb0", | |
| 1200 | OPCODE_INFO2 (0x0130, | |
| 1201 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), | |
| 1202 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1203 | OPCODE_INFO1 (0x0130, | |
| 1204 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1205 | CSKYV1_ISA_E1), | |
| 1206 | DOP16 ("zextb", | |
| 1207 | OPCODE_INFO2 (0x0140, | |
| 1208 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1209 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
| 1210 | OPCODE_INFO1 (0x0140, | |
| 1211 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1212 | CSKYV1_ISA_E1), | |
| 1213 | DOP16 ("sextb", | |
| 1214 | OPCODE_INFO2 (0x0150, | |
| 1215 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1216 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
| 1217 | OPCODE_INFO1 (0x0150, | |
| 1218 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1219 | CSKYV1_ISA_E1), | |
| 1220 | DOP16 ("zexth", | |
| 1221 | OPCODE_INFO2 (0x0160, | |
| 1222 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1223 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
| 1224 | OPCODE_INFO1 (0x0160, | |
| 1225 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1226 | CSKYV1_ISA_E1), | |
| 1227 | DOP16 ("sexth", | |
| 1228 | OPCODE_INFO2 (0x0170, | |
| 1229 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1230 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
| 1231 | OPCODE_INFO1 (0x0170, | |
| 1232 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1233 | CSKYV1_ISA_E1), | |
| 1234 | DOP16 ("declt", | |
| 1235 | OPCODE_INFO3 (0x0180, | |
| 1236 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1237 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1238 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1239 | OPCODE_INFO1 (0x0180, | |
| 1240 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1241 | CSKYV1_ISA_E1), | |
| 1242 | OP16 ("tstnbz", | |
| 1243 | OPCODE_INFO1 (0x0190, | |
| 1244 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1245 | CSKYV1_ISA_E1), | |
| 1246 | DOP16 ("decgt", | |
| 1247 | OPCODE_INFO3 (0x01a0, | |
| 1248 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1249 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1250 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1251 | OPCODE_INFO1 (0x01a0, | |
| 1252 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1253 | CSKYV1_ISA_E1), | |
| 1254 | DOP16 ("decne", | |
| 1255 | OPCODE_INFO3 (0x01b0, | |
| 1256 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1257 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1258 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1259 | OPCODE_INFO1 (0x01b0, | |
| 1260 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1261 | CSKYV1_ISA_E1), | |
| 1262 | OP16 ("clrt", | |
| 1263 | OPCODE_INFO1 (0x01c0, | |
| 1264 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1265 | CSKYV1_ISA_E1), | |
| 1266 | OP16 ("clrf", | |
| 1267 | OPCODE_INFO1 (0x01d0, | |
| 1268 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1269 | CSKYV1_ISA_E1), | |
| 1270 | DOP16 ("abs", | |
| 1271 | OPCODE_INFO2 (0x01e0, | |
| 1272 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1273 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
| 1274 | OPCODE_INFO1 (0x01e0, | |
| 1275 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1276 | CSKYV1_ISA_E1), | |
| 1277 | DOP16 ("not", | |
| 1278 | OPCODE_INFO2 (0x01f0, | |
| 1279 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1280 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
| 1281 | OPCODE_INFO1 (0x01f0, | |
| 1282 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1283 | CSKYV1_ISA_E1), | |
| 1284 | OP16 ("movt", | |
| 1285 | OPCODE_INFO2 (0x0200, | |
| 1286 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1287 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1288 | CSKYV1_ISA_E1), | |
| 1289 | DOP16 ("mult", | |
| 1290 | OPCODE_INFO3 (0x0300, | |
| 1291 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1292 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1293 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1294 | OPCODE_INFO2 (0x0300, | |
| 1295 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1296 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1297 | CSKYV1_ISA_E1), | |
| 1298 | OP16 ("mac", | |
| 1299 | OPCODE_INFO2 (0x0400, | |
| 1300 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1301 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1302 | CSKY_ISA_MAC), | |
| 1303 | DOP16 ("subu", | |
| 1304 | OPCODE_INFO3 (0x0500, | |
| 1305 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1306 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1307 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1308 | OPCODE_INFO2 (0x0500, | |
| 1309 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1310 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1311 | CSKYV1_ISA_E1), | |
| 1312 | DOP16 ("sub", | |
| 1313 | OPCODE_INFO3 (0x0500, | |
| 1314 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1315 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1316 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1317 | OPCODE_INFO2 (0x0500, | |
| 1318 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1319 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1320 | CSKYV1_ISA_E1), | |
| 1321 | DOP16 ("addc", | |
| 1322 | OPCODE_INFO3 (0x0600, | |
| 1323 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1324 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1325 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1326 | OPCODE_INFO2 (0x0600, | |
| 1327 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1328 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1329 | CSKYV1_ISA_E1), | |
| 1330 | DOP16 ("subc", | |
| 1331 | OPCODE_INFO3 (0x0700, | |
| 1332 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1333 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1334 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1335 | OPCODE_INFO2 (0x0700, | |
| 1336 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1337 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1338 | CSKYV1_ISA_E1), | |
| 1339 | OP16 ("cprgr", | |
| 1340 | OPCODE_INFO2 (0x0800, | |
| 1341 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1342 | (4_8, CPREG, OPRND_SHIFT_0_BIT)), | |
| 1343 | CSKY_ISA_CP), | |
| 1344 | OP16 ("movf", | |
| 1345 | OPCODE_INFO2 (0x0a00, | |
| 1346 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1347 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1348 | CSKYV1_ISA_E1), | |
| 1349 | DOP16 ("lsr", | |
| 1350 | OPCODE_INFO3 (0x0b00, | |
| 1351 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1352 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1353 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1354 | OPCODE_INFO2 (0x0b00, | |
| 1355 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1356 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1357 | CSKYV1_ISA_E1), | |
| 1358 | OP16 ("cmphs", | |
| 1359 | OPCODE_INFO2 (0x0c00, | |
| 1360 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1361 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1362 | CSKYV1_ISA_E1), | |
| 1363 | OP16 ("cmplt", | |
| 1364 | OPCODE_INFO2 (0x0d00, | |
| 1365 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1366 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1367 | CSKYV1_ISA_E1), | |
| 1368 | OP16 ("tst", | |
| 1369 | OPCODE_INFO2 (0x0e00, | |
| 1370 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1371 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1372 | CSKYV1_ISA_E1), | |
| 1373 | OP16 ("cmpne", | |
| 1374 | OPCODE_INFO2 (0x0f00, | |
| 1375 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1376 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1377 | CSKYV1_ISA_E1), | |
| 1378 | OP16 ("mfcr", | |
| 1379 | OPCODE_INFO2 (0x1000, | |
| 1380 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1381 | (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), | |
| 1382 | CSKYV1_ISA_E1), | |
| 1383 | OP16 ("psrclr", | |
| 1384 | OPCODE_INFO_LIST (0x11f0, | |
| 1385 | (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), | |
| 1386 | CSKYV1_ISA_E1), | |
| 1387 | OP16 ("psrset", | |
| 1388 | OPCODE_INFO_LIST (0x11f8, | |
| 1389 | (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), | |
| 1390 | CSKYV1_ISA_E1), | |
| 1391 | OP16 ("mov", | |
| 1392 | OPCODE_INFO2 (0x1200, | |
| 1393 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1394 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1395 | CSKYV1_ISA_E1), | |
| 1396 | OP16 ("bgenr", | |
| 1397 | OPCODE_INFO2 (0x1300, | |
| 1398 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1399 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1400 | CSKYV1_ISA_E1), | |
| 1401 | DOP16 ("rsub", | |
| 1402 | OPCODE_INFO3 (0x1400, | |
| 1403 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1404 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1405 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1406 | OPCODE_INFO2 (0x1400, | |
| 1407 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1408 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1409 | CSKYV1_ISA_E1), | |
| 1410 | DOP16 ("ixw", | |
| 1411 | OPCODE_INFO3 (0x1500, | |
| 1412 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1413 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1414 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1415 | OPCODE_INFO2 (0x1500, | |
| 1416 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1417 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1418 | CSKYV1_ISA_E1), | |
| 1419 | DOP16 ("and", | |
| 1420 | OPCODE_INFO3 (0x1600, | |
| 1421 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1422 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1423 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1424 | OPCODE_INFO2 (0x1600, | |
| 1425 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1426 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1427 | CSKYV1_ISA_E1), | |
| 1428 | DOP16 ("xor", | |
| 1429 | OPCODE_INFO3 (0x1700, | |
| 1430 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1431 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1432 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1433 | OPCODE_INFO2 (0x1700, | |
| 1434 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1435 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1436 | CSKYV1_ISA_E1), | |
| 1437 | OP16 ("mtcr", | |
| 1438 | OPCODE_INFO2 (0x1800, | |
| 1439 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1440 | (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), | |
| 1441 | CSKYV1_ISA_E1), | |
| 1442 | DOP16 ("asr", | |
| 1443 | OPCODE_INFO3 (0x1a00, | |
| 1444 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1445 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1446 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1447 | OPCODE_INFO2 (0x1a00, | |
| 1448 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1449 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1450 | CSKYV1_ISA_E1), | |
| 1451 | DOP16 ("lsl", | |
| 1452 | OPCODE_INFO3 (0x1b00, | |
| 1453 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1454 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1455 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1456 | OPCODE_INFO2 (0x1b00, | |
| 1457 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1458 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1459 | CSKYV1_ISA_E1), | |
| 1460 | DOP16 ("addu", | |
| 1461 | OPCODE_INFO3 (0x1c00, | |
| 1462 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1463 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1464 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1465 | OPCODE_INFO2 (0x1c00, | |
| 1466 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1467 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1468 | CSKYV1_ISA_E1), | |
| 1469 | OP16 ("add", | |
| 1470 | OPCODE_INFO2 (0x1c00, | |
| 1471 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1472 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1473 | CSKYV1_ISA_E1), | |
| 1474 | DOP16 ("ixh", | |
| 1475 | OPCODE_INFO3 (0x1d00, | |
| 1476 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1477 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1478 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1479 | OPCODE_INFO2 (0x1d00, | |
| 1480 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1481 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1482 | CSKYV1_ISA_E1), | |
| 1483 | DOP16 ("or", | |
| 1484 | OPCODE_INFO3 (0x1e00, | |
| 1485 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1486 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1487 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1488 | OPCODE_INFO2 (0x1e00, | |
| 1489 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1490 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1491 | CSKYV1_ISA_E1), | |
| 1492 | DOP16 ("andn", | |
| 1493 | OPCODE_INFO3 (0x1f00, | |
| 1494 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1495 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1496 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1497 | OPCODE_INFO2 (0x1f00, | |
| 1498 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1499 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1500 | CSKYV1_ISA_E1), | |
| 1501 | DOP16 ("addi", | |
| 1502 | OPCODE_INFO3 (0x2000, | |
| 1503 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1504 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1505 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 1506 | OPCODE_INFO2 (0x2000, | |
| 1507 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1508 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 1509 | CSKYV1_ISA_E1), | |
| 1510 | OP16 ("cmplti", | |
| 1511 | OPCODE_INFO2 (0x2200, | |
| 1512 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1513 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 1514 | CSKYV1_ISA_E1), | |
| 1515 | DOP16 ("subi", | |
| 1516 | OPCODE_INFO3 (0x2400, | |
| 1517 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1518 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1519 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 1520 | OPCODE_INFO2 (0x2400, | |
| 1521 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1522 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 1523 | CSKYV1_ISA_E1), | |
| 1524 | OP16 ("cpwgr", | |
| 1525 | OPCODE_INFO2 (0x2600, | |
| 1526 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1527 | (4_8, CPREG, OPRND_SHIFT_0_BIT)), | |
| 1528 | CSKY_ISA_CP), | |
| 1529 | DOP16 ("rsubi", | |
| 1530 | OPCODE_INFO3 (0x2800, | |
| 1531 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1532 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1533 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1534 | OPCODE_INFO2 (0x2800, | |
| 1535 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1536 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1537 | CSKYV1_ISA_E1), | |
| 1538 | OP16 ("cmpnei", | |
| 1539 | OPCODE_INFO2 (0x2a00, | |
| 1540 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1541 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1542 | CSKYV1_ISA_E1), | |
| 1543 | OP16 ("bmaski", | |
| 1544 | OPCODE_INFO2 (0x2c00, | |
| 1545 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1546 | (4_8, IMM5b_BMASKI, OPRND_SHIFT_0_BIT)), | |
| 1547 | CSKYV1_ISA_E1), | |
| 1548 | DOP16 ("divu", | |
| 1549 | OPCODE_INFO3 (0x2c10, | |
| 1550 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1551 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1552 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), | |
| 1553 | OPCODE_INFO2 (0x2c10, | |
| 1554 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1555 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), | |
| 1556 | CSKYV1_ISA_E1), | |
| 1557 | OP16 ("mflos", | |
| 1558 | OPCODE_INFO1 (0x2c20, | |
| 1559 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1560 | CSKY_ISA_MAC_DSP), | |
| 1561 | OP16 ("mfhis", | |
| 1562 | OPCODE_INFO1 (0x2c30, | |
| 1563 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1564 | CSKY_ISA_MAC_DSP), | |
| 1565 | OP16 ("mtlo", | |
| 1566 | OPCODE_INFO1 (0x2c40, | |
| 1567 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1568 | CSKY_ISA_MAC_DSP), | |
| 1569 | OP16 ("mthi", | |
| 1570 | OPCODE_INFO1 (0x2c50, | |
| 1571 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1572 | CSKY_ISA_MAC_DSP), | |
| 1573 | OP16 ("mflo", | |
| 1574 | OPCODE_INFO1 (0x2c60, | |
| 1575 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1576 | CSKY_ISA_MAC_DSP), | |
| 1577 | OP16 ("mfhi", | |
| 1578 | OPCODE_INFO1 (0x2c70, | |
| 1579 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1580 | CSKY_ISA_MAC_DSP), | |
| 1581 | DOP16 ("andi", | |
| 1582 | OPCODE_INFO3 (0x2e00, | |
| 1583 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1584 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1585 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1586 | OPCODE_INFO2 (0x2e00, | |
| 1587 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1588 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1589 | CSKYV1_ISA_E1), | |
| 1590 | DOP16 ("bclri", | |
| 1591 | OPCODE_INFO3 (0x3000, | |
| 1592 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1593 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1594 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1595 | OPCODE_INFO2 (0x3000, | |
| 1596 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1597 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1598 | CSKYV1_ISA_E1), | |
| 1599 | OP16 ("bgeni", | |
| 1600 | OPCODE_INFO2 (0x3200, | |
| 1601 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1602 | (4_8, IMM5b_7_31, OPRND_SHIFT_0_BIT)), | |
| 1603 | CSKYV1_ISA_E1), | |
| 1604 | OP16 ("cpwir", | |
| 1605 | OPCODE_INFO1 (0x3200, | |
| 1606 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1607 | CSKY_ISA_CP), | |
| 1608 | DOP16 ("divs", | |
| 1609 | OPCODE_INFO3 (0x3210, | |
| 1610 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1611 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1612 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), | |
| 1613 | OPCODE_INFO2 (0x3210, | |
| 1614 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1615 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), | |
| 1616 | CSKYV1_ISA_E1), | |
| 1617 | OP16 ("cprsr", | |
| 1618 | OPCODE_INFO1 (0x3220, | |
| 1619 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1620 | CSKY_ISA_CP), | |
| 1621 | OP16 ("cpwsr", | |
| 1622 | OPCODE_INFO1 (0x3230, | |
| 1623 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1624 | CSKY_ISA_CP), | |
| 1625 | DOP16 ("bseti", | |
| 1626 | OPCODE_INFO3 (0x3400, | |
| 1627 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1628 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1629 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1630 | OPCODE_INFO2 (0x3400, | |
| 1631 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1632 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1633 | CSKYV1_ISA_E1), | |
| 1634 | OP16 ("btsti", | |
| 1635 | OPCODE_INFO2 (0x3600, | |
| 1636 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1637 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 1638 | CSKYV1_ISA_E1), | |
| 1639 | DOP16 ("rotli", | |
| 1640 | OPCODE_INFO3 (0x3800, | |
| 1641 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1642 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1643 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
| 1644 | OPCODE_INFO2 (0x3800, | |
| 1645 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1646 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
| 1647 | CSKYV1_ISA_E1), | |
| 1648 | DOP16 ("xsr", | |
| 1649 | OPCODE_INFO3 (0x3800, | |
| 1650 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1651 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1652 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1653 | OPCODE_INFO1 (0x3800, | |
| 1654 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1655 | CSKYV1_ISA_E1), | |
| 1656 | DOP16 ("asrc", | |
| 1657 | OPCODE_INFO3 (0x3a00, | |
| 1658 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1659 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1660 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1661 | OPCODE_INFO1 (0x3a00, | |
| 1662 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1663 | CSKYV1_ISA_E1), | |
| 1664 | DOP16 ("asri", | |
| 1665 | OPCODE_INFO3 (0x3a00, | |
| 1666 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1667 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1668 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
| 1669 | OPCODE_INFO2 (0x3a00, | |
| 1670 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1671 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
| 1672 | CSKYV1_ISA_E1), | |
| 1673 | DOP16 ("lslc", | |
| 1674 | OPCODE_INFO3 (0x3c00, | |
| 1675 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1676 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1677 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1678 | OPCODE_INFO1 (0x3c00, | |
| 1679 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1680 | CSKYV1_ISA_E1), | |
| 1681 | DOP16 ("lsli", | |
| 1682 | OPCODE_INFO3 (0x3c00, | |
| 1683 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1684 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1685 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
| 1686 | OPCODE_INFO2 (0x3c00, | |
| 1687 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1688 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
| 1689 | CSKYV1_ISA_E1), | |
| 1690 | DOP16 ("lsrc", | |
| 1691 | OPCODE_INFO3 (0x3e00, | |
| 1692 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1693 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1694 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 1695 | OPCODE_INFO1 (0x3e00, | |
| 1696 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1697 | CSKYV1_ISA_E1), | |
| 1698 | DOP16 ("lsri", | |
| 1699 | OPCODE_INFO3 (0x3e00, | |
| 1700 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1701 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1702 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
| 1703 | OPCODE_INFO2 (0x3e00, | |
| 1704 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1705 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
| 1706 | CSKYV1_ISA_E1), | |
| 1707 | OP16 ("ldex", | |
| 1708 | SOPCODE_INFO2 (0x4000, | |
| 1709 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1710 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1711 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1712 | CSKY_ISA_MP), | |
| 1713 | OP16 ("ldex.w", | |
| 1714 | SOPCODE_INFO2 (0x4000, | |
| 1715 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1716 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1717 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1718 | CSKY_ISA_MP), | |
| 1719 | OP16 ("ldwex", | |
| 1720 | SOPCODE_INFO2 (0x4000, | |
| 1721 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1722 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1723 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1724 | CSKY_ISA_MP), | |
| 1725 | OP16 ("stex", | |
| 1726 | SOPCODE_INFO2 (0x5000, | |
| 1727 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1728 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1729 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1730 | CSKY_ISA_MP), | |
| 1731 | OP16 ("stex.w", | |
| 1732 | SOPCODE_INFO2 (0x5000, | |
| 1733 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1734 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1735 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1736 | CSKY_ISA_MP), | |
| 1737 | OP16 ("stwex", | |
| 1738 | SOPCODE_INFO2 (0x5000, | |
| 1739 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1740 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1741 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1742 | CSKY_ISA_MP), | |
| 1743 | OP16 ("omflip0", | |
| 1744 | OPCODE_INFO2 (0x4000, | |
| 1745 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1746 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1747 | CSKY_ISA_MAC), | |
| 1748 | OP16 ("omflip1", | |
| 1749 | OPCODE_INFO2 (0x4100, | |
| 1750 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1751 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1752 | CSKY_ISA_MAC), | |
| 1753 | OP16 ("omflip2", | |
| 1754 | OPCODE_INFO2 (0x4200, | |
| 1755 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1756 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1757 | CSKY_ISA_MAC), | |
| 1758 | OP16 ("omflip3", | |
| 1759 | OPCODE_INFO2 (0x4300, | |
| 1760 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1761 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1762 | CSKY_ISA_MAC), | |
| 1763 | OP16 ("muls", | |
| 1764 | OPCODE_INFO2 (0x5000, | |
| 1765 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1766 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1767 | CSKY_ISA_DSP), | |
| 1768 | OP16 ("mulsa", | |
| 1769 | OPCODE_INFO2 (0x5100, | |
| 1770 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1771 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1772 | CSKY_ISA_DSP), | |
| 1773 | OP16 ("mulss", | |
| 1774 | OPCODE_INFO2 (0x5200, | |
| 1775 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1776 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1777 | CSKY_ISA_DSP), | |
| 1778 | OP16 ("mulu", | |
| 1779 | OPCODE_INFO2 (0x5400, | |
| 1780 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1781 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1782 | CSKY_ISA_DSP), | |
| 1783 | OP16 ("mulua", | |
| 1784 | OPCODE_INFO2 (0x5500, | |
| 1785 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1786 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1787 | CSKY_ISA_DSP), | |
| 1788 | OP16 ("mulus", | |
| 1789 | OPCODE_INFO2 (0x5600, | |
| 1790 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1791 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1792 | CSKY_ISA_DSP), | |
| 1793 | OP16 ("vmulsh", | |
| 1794 | OPCODE_INFO2 (0x5800, | |
| 1795 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1796 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1797 | CSKY_ISA_DSP), | |
| 1798 | OP16 ("vmulsha", | |
| 1799 | OPCODE_INFO2 (0x5900, | |
| 1800 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1801 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1802 | CSKY_ISA_DSP), | |
| 1803 | OP16 ("vmulshs", | |
| 1804 | OPCODE_INFO2 (0x5a00, | |
| 1805 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1806 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1807 | CSKY_ISA_DSP), | |
| 1808 | OP16 ("vmulsw", | |
| 1809 | OPCODE_INFO2 (0x5c00, | |
| 1810 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1811 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1812 | CSKY_ISA_DSP), | |
| 1813 | OP16 ("vmulswa", | |
| 1814 | OPCODE_INFO2 (0x5d00, | |
| 1815 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1816 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1817 | CSKY_ISA_DSP), | |
| 1818 | OP16 ("vmulsws", | |
| 1819 | OPCODE_INFO2 (0x5e00, | |
| 1820 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1821 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1822 | CSKY_ISA_DSP), | |
| 1823 | OP16 ("movi", | |
| 1824 | OPCODE_INFO2 (0x6000, | |
| 1825 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1826 | (4_10, IMM7b, OPRND_SHIFT_0_BIT)), | |
| 1827 | CSKYV1_ISA_E1), | |
| 1828 | DOP16 ("mulsh", | |
| 1829 | OPCODE_INFO3 (0x6800, | |
| 1830 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1831 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1832 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1833 | OPCODE_INFO2 (0x6800, | |
| 1834 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1835 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1836 | CSKYV1_ISA_E1), | |
| 1837 | DOP16 ("mulsh.h", | |
| 1838 | OPCODE_INFO3 (0x6800, | |
| 1839 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1840 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 1841 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1842 | OPCODE_INFO2 (0x6800, | |
| 1843 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1844 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1845 | CSKYV1_ISA_E1), | |
| 1846 | OP16 ("mulsha", | |
| 1847 | OPCODE_INFO2 (0x6900, | |
| 1848 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1849 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1850 | CSKY_ISA_DSP), | |
| 1851 | OP16 ("mulshs", | |
| 1852 | OPCODE_INFO2 (0x6a00, | |
| 1853 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1854 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1855 | CSKY_ISA_DSP), | |
| 1856 | OP16 ("cprcr", | |
| 1857 | OPCODE_INFO2 (0x6b00, | |
| 1858 | (0_2, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 1859 | (3_7, CPCREG, OPRND_SHIFT_0_BIT)), | |
| 1860 | CSKY_ISA_CP), | |
| 1861 | OP16 ("mulsw", | |
| 1862 | OPCODE_INFO2 (0x6c00, | |
| 1863 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1864 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1865 | CSKY_ISA_DSP), | |
| 1866 | OP16 ("mulswa", | |
| 1867 | OPCODE_INFO2 (0x6d00, | |
| 1868 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1869 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1870 | CSKY_ISA_DSP), | |
| 1871 | OP16 ("mulsws", | |
| 1872 | OPCODE_INFO2 (0x6e00, | |
| 1873 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1874 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 1875 | CSKY_ISA_DSP), | |
| 1876 | OP16 ("cpwcr", | |
| 1877 | OPCODE_INFO2 (0x6f00, | |
| 1878 | (0_2, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 1879 | (3_7, CPCREG, OPRND_SHIFT_0_BIT)), | |
| 1880 | CSKY_ISA_CP), | |
| 1881 | #undef _RELOC16 | |
| 1882 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM8BY4 | |
| 1883 | #undef _TRANSFER | |
| 1884 | #define _TRANSFER 1 | |
| 1885 | OP16 ("jmpi", | |
| 1886 | OPCODE_INFO1 (0x7000, | |
| 1887 | (0_7, OFF8b, OPRND_SHIFT_2_BIT)), | |
| 1888 | CSKYV1_ISA_E1), | |
| 1889 | #undef _TRANSFER | |
| 1890 | #define _TRANSFER 0 | |
| 1891 | OP16 ("jsri", | |
| 1892 | OPCODE_INFO1 (0x7f00, | |
| 1893 | (0_7, OFF8b, OPRND_SHIFT_2_BIT)), | |
| 1894 | CSKYV1_ISA_E1), | |
| 1895 | OP16_WITH_WORK ("lrw", | |
| 1896 | OPCODE_INFO2 (0x7000, | |
| 1897 | (8_11, REGnsplr, OPRND_SHIFT_0_BIT), | |
| 1898 | (0_7, CONSTANT, OPRND_SHIFT_2_BIT)), | |
| 1899 | CSKYV1_ISA_E1, | |
| 1900 | v1_work_lrw), | |
| 1901 | #undef _RELOC16 | |
| 1902 | #define _RELOC16 0 | |
| 1903 | DOP16 ("ld.w", | |
| 1904 | SOPCODE_INFO2 (0x8000, | |
| 1905 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1906 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1907 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 1908 | OPCODE_INFO2 (0x8000, | |
| 1909 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1910 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1911 | CSKYV1_ISA_E1), | |
| 1912 | DOP16 ("ldw", | |
| 1913 | SOPCODE_INFO2 (0x8000, | |
| 1914 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1915 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1916 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 1917 | OPCODE_INFO2 (0x8000, | |
| 1918 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1919 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1920 | CSKYV1_ISA_E1), | |
| 1921 | DOP16 ("ld", | |
| 1922 | SOPCODE_INFO2 (0x8000, | |
| 1923 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1924 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1925 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 1926 | OPCODE_INFO2 (0x8000, | |
| 1927 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1928 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1929 | CSKYV1_ISA_E1), | |
| 1930 | DOP16 ("st.w", | |
| 1931 | SOPCODE_INFO2 (0x9000, | |
| 1932 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1933 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1934 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 1935 | OPCODE_INFO2 (0x9000, | |
| 1936 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1937 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1938 | CSKYV1_ISA_E1), | |
| 1939 | DOP16 ("stw", | |
| 1940 | SOPCODE_INFO2 (0x9000, | |
| 1941 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1942 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1943 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 1944 | OPCODE_INFO2 (0x9000, | |
| 1945 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1946 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1947 | CSKYV1_ISA_E1), | |
| 1948 | DOP16 ("st", | |
| 1949 | SOPCODE_INFO2 (0x9000, | |
| 1950 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1951 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1952 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 1953 | OPCODE_INFO2 (0x9000, | |
| 1954 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1955 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1956 | CSKYV1_ISA_E1), | |
| 1957 | DOP16 ("ld.b", | |
| 1958 | SOPCODE_INFO2 (0xa000, | |
| 1959 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1960 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1961 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1962 | OPCODE_INFO2 (0xa000, | |
| 1963 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1964 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1965 | CSKYV1_ISA_E1), | |
| 1966 | DOP16 ("ldb", | |
| 1967 | SOPCODE_INFO2 (0xa000, | |
| 1968 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1969 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1970 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1971 | OPCODE_INFO2 (0xa000, | |
| 1972 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1973 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1974 | CSKYV1_ISA_E1), | |
| 1975 | DOP16 ("st.b", | |
| 1976 | SOPCODE_INFO2 (0xb000, | |
| 1977 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1978 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1979 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1980 | OPCODE_INFO2 (0xb000, | |
| 1981 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1982 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1983 | CSKYV1_ISA_E1), | |
| 1984 | DOP16 ("stb", | |
| 1985 | SOPCODE_INFO2 (0xb000, | |
| 1986 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1987 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1988 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 1989 | OPCODE_INFO2 (0xb000, | |
| 1990 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1991 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 1992 | CSKYV1_ISA_E1), | |
| 1993 | DOP16 ("ld.h", | |
| 1994 | SOPCODE_INFO2 (0xc000, | |
| 1995 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1996 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 1997 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 1998 | OPCODE_INFO2 (0xc000, | |
| 1999 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2000 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 2001 | CSKYV1_ISA_E1), | |
| 2002 | DOP16 ("ldh", | |
| 2003 | SOPCODE_INFO2 (0xc000, | |
| 2004 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2005 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2006 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 2007 | OPCODE_INFO2 (0xc000, | |
| 2008 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2009 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 2010 | CSKYV1_ISA_E1), | |
| 2011 | DOP16 ("st.h", | |
| 2012 | SOPCODE_INFO2 (0xd000, | |
| 2013 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2014 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2015 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 2016 | OPCODE_INFO2 (0xd000, | |
| 2017 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2018 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 2019 | CSKYV1_ISA_E1), | |
| 2020 | DOP16 ("sth", | |
| 2021 | SOPCODE_INFO2 (0xd000, | |
| 2022 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2023 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2024 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 2025 | OPCODE_INFO2 (0xd000, | |
| 2026 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2027 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 2028 | CSKYV1_ISA_E1), | |
| 2029 | ||
| 2030 | #undef _RELOC16 | |
| 2031 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM11BY2 | |
| 2032 | OP16 ("bt", | |
| 2033 | OPCODE_INFO1 (0xe000, | |
| 2034 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), | |
| 2035 | CSKYV1_ISA_E1), | |
| 2036 | OP16 ("bf", | |
| 2037 | OPCODE_INFO1 (0xe800, | |
| 2038 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), | |
| 2039 | CSKYV1_ISA_E1), | |
| 2040 | #undef _TRANSFER | |
| 2041 | #define _TRANSFER 1 | |
| 2042 | OP16 ("br", | |
| 2043 | OPCODE_INFO1 (0xf000, | |
| 2044 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), | |
| 2045 | CSKYV1_ISA_E1), | |
| 2046 | #undef _TRANSFER | |
| 2047 | #define _TRANSFER 0 | |
| 2048 | OP16 ("bsr", | |
| 2049 | OPCODE_INFO1 (0xf800, | |
| 2050 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), | |
| 2051 | CSKYV1_ISA_E1), | |
| 2052 | #undef _RELOC16 | |
| 2053 | #define _RELOC16 0 | |
| 2054 | ||
| 2055 | #undef _RELAX | |
| 2056 | #define _RELAX 1 | |
| 2057 | OP16 ("jbt", | |
| 2058 | OPCODE_INFO1 (0xe000, | |
| 2059 | (0_10, JBTF, OPRND_SHIFT_0_BIT)), | |
| 2060 | CSKYV1_ISA_E1), | |
| 2061 | OP16 ("jbf", | |
| 2062 | OPCODE_INFO1 (0xe800, | |
| 2063 | (0_10, JBTF, OPRND_SHIFT_0_BIT)), | |
| 2064 | CSKYV1_ISA_E1), | |
| 2065 | #undef _TRANSFER | |
| 2066 | #define _TRANSFER 1 | |
| 2067 | OP16 ("jbr", | |
| 2068 | OPCODE_INFO1 (0xf000, | |
| 2069 | (0_10, JBR, OPRND_SHIFT_0_BIT)), | |
| 2070 | CSKYV1_ISA_E1), | |
| 2071 | #undef _TRANSFER | |
| 2072 | #define _TRANSFER 0 | |
| 2073 | #undef _RELAX | |
| 2074 | #define _RELAX 0 | |
| 2075 | ||
| 2076 | OP16_WITH_WORK ("jbsr", | |
| 2077 | OPCODE_INFO1 (0xf800, | |
| 2078 | (0_10, JBSR, OPRND_SHIFT_0_BIT)), | |
| 2079 | CSKYV1_ISA_E1, | |
| 2080 | v1_work_jbsr), | |
| 2081 | ||
| 2082 | /* The following are aliases for other instructions. */ | |
| 2083 | /* rts -> jmp r15. */ | |
| 2084 | #undef _TRANSFER | |
| 2085 | #define _TRANSFER 2 | |
| 2086 | OP16 ("rts", | |
| 2087 | OPCODE_INFO0 (0x00CF), | |
| 2088 | CSKYV1_ISA_E1), | |
| 2089 | OP16 ("rte", | |
| 2090 | OPCODE_INFO0 (0x0002), | |
| 2091 | CSKYV1_ISA_E1), | |
| 2092 | OP16 ("rfe", | |
| 2093 | OPCODE_INFO0 (0x0002), | |
| 2094 | CSKYV1_ISA_E1), | |
| 2095 | #undef _TRANSFER | |
| 2096 | #define _TRANSFER 0 | |
| 2097 | ||
| 2098 | /* cmphs r0,r0 */ | |
| 2099 | OP16 ("setc", | |
| 2100 | OPCODE_INFO0 (0x0c00), | |
| 2101 | CSKYV1_ISA_E1), | |
| 2102 | /* cmpne r0,r0 */ | |
| 2103 | OP16 ("clrc", | |
| 2104 | OPCODE_INFO0 (0x0f00), | |
| 2105 | CSKYV1_ISA_E1), | |
| 2106 | /* cmplti rd,1 */ | |
| 2107 | OP16 ("tstle", | |
| 2108 | OPCODE_INFO1 (0x2200, | |
| 2109 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2110 | CSKYV1_ISA_E1), | |
| 2111 | /* cmplei rd,X -> cmplti rd,X+1 */ | |
| 2112 | OP16 ("cmplei", | |
| 2113 | OPCODE_INFO2 (0x2200, | |
| 2114 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2115 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2116 | CSKYV1_ISA_E1), | |
| 2117 | /* rsubi rd,0 */ | |
| 2118 | OP16 ("neg", | |
| 2119 | OPCODE_INFO1 (0x2800, | |
| 2120 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2121 | CSKYV1_ISA_E1), | |
| 2122 | /* cmpnei rd,0. */ | |
| 2123 | OP16 ("tstne", | |
| 2124 | OPCODE_INFO1 (0x2a00, | |
| 2125 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2126 | CSKYV1_ISA_E1), | |
| 2127 | /* btsti rx,31. */ | |
| 2128 | OP16 ("tstlt", | |
| 2129 | OPCODE_INFO1 (0x37f0, | |
| 2130 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2131 | CSKYV1_ISA_E1), | |
| 2132 | /* bclri rx,log2(imm). */ | |
| 2133 | OP16 ("mclri", | |
| 2134 | OPCODE_INFO2 (0x3000, | |
| 2135 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2136 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), | |
| 2137 | CSKYV1_ISA_E1), | |
| 2138 | /* bgeni rx,log2(imm). */ | |
| 2139 | OP16 ("mgeni", | |
| 2140 | OPCODE_INFO2 (0x3200, | |
| 2141 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2142 | (4_8, IMM5b_7_31_POWER, OPRND_SHIFT_0_BIT)), | |
| 2143 | CSKYV1_ISA_E1), | |
| 2144 | /* bseti rx,log2(imm). */ | |
| 2145 | OP16 ("mseti", | |
| 2146 | OPCODE_INFO2 (0x3400, | |
| 2147 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2148 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), | |
| 2149 | CSKYV1_ISA_E1), | |
| 2150 | /* btsti rx,log2(imm). */ | |
| 2151 | OP16 ("mtsti", | |
| 2152 | OPCODE_INFO2 (0x3600, | |
| 2153 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2154 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), | |
| 2155 | CSKYV1_ISA_E1), | |
| 2156 | OP16 ("rori", | |
| 2157 | OPCODE_INFO2 (0x3800, | |
| 2158 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2159 | (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
| 2160 | CSKYV1_ISA_E1), | |
| 2161 | OP16 ("rotri", | |
| 2162 | OPCODE_INFO2 (0x3800, | |
| 2163 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2164 | (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
| 2165 | CSKYV1_ISA_E1), | |
| 2166 | /* mov r0, r0. */ | |
| 2167 | OP16 ("nop", | |
| 2168 | OPCODE_INFO0 (0x1200), | |
| 2169 | CSKYV1_ISA_E1), | |
| 2170 | ||
| 2171 | /* Float instruction with work. */ | |
| 2172 | OP16_WITH_WORK ("fabss", | |
| 2173 | OPCODE_INFO3 (0xffe04400, | |
| 2174 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2175 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2176 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2177 | CSKY_ISA_FLOAT_E1, | |
| 2178 | v1_work_fpu_fo), | |
| 2179 | OP16_WITH_WORK ("fnegs", | |
| 2180 | OPCODE_INFO3 (0xffe04c00, | |
| 2181 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2182 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2183 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2184 | CSKY_ISA_FLOAT_E1, | |
| 2185 | v1_work_fpu_fo), | |
| 2186 | OP16_WITH_WORK ("fsqrts", | |
| 2187 | OPCODE_INFO3 (0xffe05400, | |
| 2188 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2189 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2190 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2191 | CSKY_ISA_FLOAT_E1, | |
| 2192 | v1_work_fpu_fo), | |
| 2193 | OP16_WITH_WORK ("frecips", | |
| 2194 | OPCODE_INFO3 (0xffe05c00, | |
| 2195 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2196 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2197 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2198 | CSKY_ISA_FLOAT_E1, | |
| 2199 | v1_work_fpu_fo), | |
| 2200 | OP16_WITH_WORK ("fadds", | |
| 2201 | OPCODE_INFO4 (0xffe38000, | |
| 2202 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2203 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2204 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2205 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2206 | CSKY_ISA_FLOAT_E1, | |
| 2207 | v1_work_fpu_fo), | |
| 2208 | OP16_WITH_WORK ("fsubs", | |
| 2209 | OPCODE_INFO4 (0xffe48000, | |
| 2210 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2211 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2212 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2213 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2214 | CSKY_ISA_FLOAT_E1, v1_work_fpu_fo), | |
| 2215 | OP16_WITH_WORK ("fmacs", | |
| 2216 | OPCODE_INFO4 (0xffe58000, | |
| 2217 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2218 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2219 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2220 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2221 | CSKY_ISA_FLOAT_E1, | |
| 2222 | v1_work_fpu_fo), | |
| 2223 | OP16_WITH_WORK ("fmscs", | |
| 2224 | OPCODE_INFO4 (0xffe68000, | |
| 2225 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2226 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2227 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2228 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2229 | CSKY_ISA_FLOAT_E1, | |
| 2230 | v1_work_fpu_fo), | |
| 2231 | OP16_WITH_WORK ("fmuls", | |
| 2232 | OPCODE_INFO4 (0xffe78000, | |
| 2233 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2234 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2235 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2236 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2237 | CSKY_ISA_FLOAT_E1, | |
| 2238 | v1_work_fpu_fo), | |
| 2239 | OP16_WITH_WORK ("fdivs", | |
| 2240 | OPCODE_INFO4 (0xffe88000, | |
| 2241 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2242 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2243 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2244 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2245 | CSKY_ISA_FLOAT_E1, | |
| 2246 | v1_work_fpu_fo), | |
| 2247 | OP16_WITH_WORK ("fnmacs", | |
| 2248 | OPCODE_INFO4 (0xffe98000, | |
| 2249 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2250 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2251 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2252 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2253 | CSKY_ISA_FLOAT_E1, | |
| 2254 | v1_work_fpu_fo), | |
| 2255 | OP16_WITH_WORK ("fnmscs", | |
| 2256 | OPCODE_INFO4 (0xffea8000, | |
| 2257 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2258 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2259 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2260 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2261 | CSKY_ISA_FLOAT_E1, | |
| 2262 | v1_work_fpu_fo), | |
| 2263 | OP16_WITH_WORK ("fnmuls", | |
| 2264 | OPCODE_INFO4 (0xffeb8000, | |
| 2265 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2266 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2267 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
| 2268 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2269 | CSKY_ISA_FLOAT_E1, | |
| 2270 | v1_work_fpu_fo), | |
| 2271 | OP16_WITH_WORK ("fabsd", | |
| 2272 | OPCODE_INFO3 (0xffe04000, | |
| 2273 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2274 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2275 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2276 | CSKY_ISA_FLOAT_E1, | |
| 2277 | v1_work_fpu_fo), | |
| 2278 | OP16_WITH_WORK ("fnegd", | |
| 2279 | OPCODE_INFO3 (0xffe04800, | |
| 2280 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2281 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2282 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2283 | CSKY_ISA_FLOAT_E1, | |
| 2284 | v1_work_fpu_fo), | |
| 2285 | OP16_WITH_WORK ("fsqrtd", | |
| 2286 | OPCODE_INFO3 (0xffe05000, | |
| 2287 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2288 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2289 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2290 | CSKY_ISA_FLOAT_E1, | |
| 2291 | v1_work_fpu_fo), | |
| 2292 | OP16_WITH_WORK ("frecipd", | |
| 2293 | OPCODE_INFO3 (0xffe05800, | |
| 2294 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2295 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2296 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2297 | CSKY_ISA_FLOAT_E1, | |
| 2298 | v1_work_fpu_fo), | |
| 2299 | OP16_WITH_WORK ("faddd", | |
| 2300 | OPCODE_INFO4 (0xffe30000, | |
| 2301 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2302 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2303 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2304 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2305 | CSKY_ISA_FLOAT_E1, | |
| 2306 | v1_work_fpu_fo), | |
| 2307 | OP16_WITH_WORK ("fsubd", | |
| 2308 | OPCODE_INFO4 (0xffe40000, | |
| 2309 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2310 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2311 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2312 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2313 | CSKY_ISA_FLOAT_E1, | |
| 2314 | v1_work_fpu_fo), | |
| 2315 | OP16_WITH_WORK ("fmacd", | |
| 2316 | OPCODE_INFO4 (0xffe50000, | |
| 2317 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2318 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2319 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2320 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2321 | CSKY_ISA_FLOAT_E1, | |
| 2322 | v1_work_fpu_fo), | |
| 2323 | OP16_WITH_WORK ("fmscd", | |
| 2324 | OPCODE_INFO4 (0xffe60000, | |
| 2325 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2326 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2327 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2328 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2329 | CSKY_ISA_FLOAT_E1, | |
| 2330 | v1_work_fpu_fo), | |
| 2331 | OP16_WITH_WORK ("fmuld", | |
| 2332 | OPCODE_INFO4 (0xffe70000, | |
| 2333 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2334 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2335 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2336 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2337 | CSKY_ISA_FLOAT_E1, | |
| 2338 | v1_work_fpu_fo), | |
| 2339 | OP16_WITH_WORK ("fdivd", | |
| 2340 | OPCODE_INFO4 (0xffe80000, | |
| 2341 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2342 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2343 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2344 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2345 | CSKY_ISA_FLOAT_E1, | |
| 2346 | v1_work_fpu_fo), | |
| 2347 | OP16_WITH_WORK ("fnmacd", | |
| 2348 | OPCODE_INFO4 (0xffe90000, | |
| 2349 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2350 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2351 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2352 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2353 | CSKY_ISA_FLOAT_E1, | |
| 2354 | v1_work_fpu_fo), | |
| 2355 | OP16_WITH_WORK ("fnmscd", | |
| 2356 | OPCODE_INFO4 (0xffea0000, | |
| 2357 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2358 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2359 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2360 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2361 | CSKY_ISA_FLOAT_E1, | |
| 2362 | v1_work_fpu_fo), | |
| 2363 | OP16_WITH_WORK ("fnmuld", | |
| 2364 | OPCODE_INFO4 (0xffeb0000, | |
| 2365 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2366 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2367 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2368 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2369 | CSKY_ISA_FLOAT_E1, | |
| 2370 | v1_work_fpu_fo), | |
| 2371 | OP16_WITH_WORK ("fabsm", | |
| 2372 | OPCODE_INFO3 (0xffe06000, | |
| 2373 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2374 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2375 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2376 | CSKY_ISA_FLOAT_E1, | |
| 2377 | v1_work_fpu_fo), | |
| 2378 | OP16_WITH_WORK ("fnegm", | |
| 2379 | OPCODE_INFO3 (0xffe06400, | |
| 2380 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2381 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2382 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2383 | CSKY_ISA_FLOAT_E1, | |
| 2384 | v1_work_fpu_fo), | |
| 2385 | OP16_WITH_WORK ("faddm", | |
| 2386 | OPCODE_INFO4 (0xffec0000, | |
| 2387 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2388 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2389 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2390 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2391 | CSKY_ISA_FLOAT_E1, | |
| 2392 | v1_work_fpu_fo), | |
| 2393 | OP16_WITH_WORK ("fsubm", | |
| 2394 | OPCODE_INFO4 (0xffec8000, | |
| 2395 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2396 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2397 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2398 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2399 | CSKY_ISA_FLOAT_E1, | |
| 2400 | v1_work_fpu_fo), | |
| 2401 | OP16_WITH_WORK ("fmacm", | |
| 2402 | OPCODE_INFO4 (0xffed8000, | |
| 2403 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2404 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2405 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2406 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2407 | CSKY_ISA_FLOAT_E1, | |
| 2408 | v1_work_fpu_fo), | |
| 2409 | OP16_WITH_WORK ("fmscm", | |
| 2410 | OPCODE_INFO4 (0xffee0000, | |
| 2411 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2412 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2413 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2414 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2415 | CSKY_ISA_FLOAT_E1, | |
| 2416 | v1_work_fpu_fo), | |
| 2417 | OP16_WITH_WORK ("fmulm", | |
| 2418 | OPCODE_INFO4 (0xffed0000, | |
| 2419 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2420 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2421 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2422 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2423 | CSKY_ISA_FLOAT_E1, | |
| 2424 | v1_work_fpu_fo), | |
| 2425 | OP16_WITH_WORK ("fnmacm", | |
| 2426 | OPCODE_INFO4 (0xffee8000, | |
| 2427 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2428 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2429 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2430 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2431 | CSKY_ISA_FLOAT_E1, | |
| 2432 | v1_work_fpu_fo), | |
| 2433 | OP16_WITH_WORK ("fnmscm", | |
| 2434 | OPCODE_INFO4 (0xffef0000, | |
| 2435 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2436 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2437 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2438 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2439 | CSKY_ISA_FLOAT_E1, | |
| 2440 | v1_work_fpu_fo), | |
| 2441 | OP16_WITH_WORK ("fnmulm", | |
| 2442 | OPCODE_INFO4 (0xffef8000, | |
| 2443 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2444 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2445 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
| 2446 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2447 | CSKY_ISA_FLOAT_E1, | |
| 2448 | v1_work_fpu_fo), | |
| 2449 | OP16_WITH_WORK ("fcmphsd", | |
| 2450 | OPCODE_INFO3 (0xffe00800, | |
| 2451 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2452 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2453 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2454 | CSKY_ISA_FLOAT_E1, | |
| 2455 | v1_work_fpu_fo_fc), | |
| 2456 | OP16_WITH_WORK ("fcmpltd", | |
| 2457 | OPCODE_INFO3 (0xffe00c00, | |
| 2458 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2459 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2460 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2461 | CSKY_ISA_FLOAT_E1, | |
| 2462 | v1_work_fpu_fo_fc), | |
| 2463 | OP16_WITH_WORK ("fcmpned", | |
| 2464 | OPCODE_INFO3 (0xffe01000, | |
| 2465 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2466 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2467 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2468 | CSKY_ISA_FLOAT_E1, | |
| 2469 | v1_work_fpu_fo_fc), | |
| 2470 | OP16_WITH_WORK ("fcmpuod", | |
| 2471 | OPCODE_INFO3 (0xffe01400, | |
| 2472 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2473 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2474 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2475 | CSKY_ISA_FLOAT_E1, | |
| 2476 | v1_work_fpu_fo_fc), | |
| 2477 | OP16_WITH_WORK ("fcmphss", | |
| 2478 | OPCODE_INFO3 (0xffe01800, | |
| 2479 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2480 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2481 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2482 | CSKY_ISA_FLOAT_E1, | |
| 2483 | v1_work_fpu_fo_fc), | |
| 2484 | OP16_WITH_WORK ("fcmplts", | |
| 2485 | OPCODE_INFO3 (0xffe01c00, | |
| 2486 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2487 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2488 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2489 | CSKY_ISA_FLOAT_E1, | |
| 2490 | v1_work_fpu_fo_fc), | |
| 2491 | OP16_WITH_WORK ("fcmpnes", | |
| 2492 | OPCODE_INFO3 (0xffe02000, | |
| 2493 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2494 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2495 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2496 | CSKY_ISA_FLOAT_E1, | |
| 2497 | v1_work_fpu_fo_fc), | |
| 2498 | OP16_WITH_WORK ("fcmpuos", | |
| 2499 | OPCODE_INFO3 (0xffe02400, | |
| 2500 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2501 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2502 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2503 | CSKY_ISA_FLOAT_E1, | |
| 2504 | v1_work_fpu_fo_fc), | |
| 2505 | OP16_WITH_WORK ("fcmpzhsd", | |
| 2506 | OPCODE_INFO2 (0xffe00400, | |
| 2507 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2508 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2509 | CSKY_ISA_FLOAT_E1, | |
| 2510 | v1_work_fpu_fo_fc), | |
| 2511 | OP16_WITH_WORK ("fcmpzltd", | |
| 2512 | OPCODE_INFO2 (0xffe00480, | |
| 2513 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2514 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2515 | CSKY_ISA_FLOAT_E1, | |
| 2516 | v1_work_fpu_fo_fc), | |
| 2517 | OP16_WITH_WORK ("fcmpzned", | |
| 2518 | OPCODE_INFO2 (0xffe00500, | |
| 2519 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2520 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2521 | CSKY_ISA_FLOAT_E1, | |
| 2522 | v1_work_fpu_fo_fc), | |
| 2523 | OP16_WITH_WORK ("fcmpzuod", | |
| 2524 | OPCODE_INFO2 (0xffe00580, | |
| 2525 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2526 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2527 | CSKY_ISA_FLOAT_E1, | |
| 2528 | v1_work_fpu_fo_fc), | |
| 2529 | OP16_WITH_WORK ("fcmpzhss", | |
| 2530 | OPCODE_INFO2 (0xffe00600, | |
| 2531 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2532 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2533 | CSKY_ISA_FLOAT_E1, | |
| 2534 | v1_work_fpu_fo_fc), | |
| 2535 | OP16_WITH_WORK ("fcmpzlts", | |
| 2536 | OPCODE_INFO2 (0xffe00680, | |
| 2537 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2538 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2539 | CSKY_ISA_FLOAT_E1, | |
| 2540 | v1_work_fpu_fo_fc), | |
| 2541 | OP16_WITH_WORK ("fcmpznes", | |
| 2542 | OPCODE_INFO2 (0xffe00700, | |
| 2543 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2544 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2545 | CSKY_ISA_FLOAT_E1, | |
| 2546 | v1_work_fpu_fo_fc), | |
| 2547 | OP16_WITH_WORK ("fcmpzuos", | |
| 2548 | OPCODE_INFO2 (0xffe00780, | |
| 2549 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2550 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2551 | CSKY_ISA_FLOAT_E1, | |
| 2552 | v1_work_fpu_fo_fc), | |
| 2553 | OP16_WITH_WORK ("fstod", | |
| 2554 | OPCODE_INFO3 (0xffe02800, | |
| 2555 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2556 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2557 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2558 | CSKY_ISA_FLOAT_E1, | |
| 2559 | v1_work_fpu_fo), | |
| 2560 | OP16_WITH_WORK ("fdtos", | |
| 2561 | OPCODE_INFO3 (0xffe02c00, | |
| 2562 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2563 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2564 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2565 | CSKY_ISA_FLOAT_E1, | |
| 2566 | v1_work_fpu_fo), | |
| 2567 | OP16_WITH_WORK ("fsitos", | |
| 2568 | OPCODE_INFO3 (0xffe03400, | |
| 2569 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2570 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2571 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2572 | CSKY_ISA_FLOAT_E1, | |
| 2573 | v1_work_fpu_fo), | |
| 2574 | OP16_WITH_WORK ("fsitod", | |
| 2575 | OPCODE_INFO3 (0xffe03000, | |
| 2576 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2577 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2578 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2579 | CSKY_ISA_FLOAT_E1, | |
| 2580 | v1_work_fpu_fo), | |
| 2581 | OP16_WITH_WORK ("fuitos", | |
| 2582 | OPCODE_INFO3 (0xffe03c00, | |
| 2583 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2584 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2585 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2586 | CSKY_ISA_FLOAT_E1, | |
| 2587 | v1_work_fpu_fo), | |
| 2588 | OP16_WITH_WORK ("fuitod", | |
| 2589 | OPCODE_INFO3 (0xffe03800, | |
| 2590 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2591 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2592 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2593 | CSKY_ISA_FLOAT_E1, | |
| 2594 | v1_work_fpu_fo), | |
| 2595 | OP16_WITH_WORK ("fstosi", | |
| 2596 | OPCODE_INFO4 (0xffe10000, | |
| 2597 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2598 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2599 | (13_17, RM, OPRND_SHIFT_0_BIT), | |
| 2600 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2601 | CSKY_ISA_FLOAT_E1, | |
| 2602 | v1_work_fpu_fo), | |
| 2603 | OP16_WITH_WORK ("fdtosi", | |
| 2604 | OPCODE_INFO4 (0xffe08000, | |
| 2605 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2606 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2607 | (13_17, RM, OPRND_SHIFT_0_BIT), | |
| 2608 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2609 | CSKY_ISA_FLOAT_E1, | |
| 2610 | v1_work_fpu_fo), | |
| 2611 | OP16_WITH_WORK ("fstoui", | |
| 2612 | OPCODE_INFO4 (0xffe20000, | |
| 2613 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2614 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2615 | (13_17, RM, OPRND_SHIFT_0_BIT), | |
| 2616 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2617 | CSKY_ISA_FLOAT_E1, | |
| 2618 | v1_work_fpu_fo), | |
| 2619 | OP16_WITH_WORK ("fdtoui", | |
| 2620 | OPCODE_INFO4 (0xffe18000, | |
| 2621 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2622 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
| 2623 | (13_17, RM, OPRND_SHIFT_0_BIT), | |
| 2624 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2625 | CSKY_ISA_FLOAT_E1, | |
| 2626 | v1_work_fpu_fo), | |
| 2627 | OP16_WITH_WORK ("fmovd", | |
| 2628 | OPCODE_INFO3 (0xffe06800, | |
| 2629 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
| 2630 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2631 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2632 | CSKY_ISA_FLOAT_E1, | |
| 2633 | v1_work_fpu_fo), | |
| 2634 | OP16_WITH_WORK ("fmovs", | |
| 2635 | OPCODE_INFO3 (0xffe06c00, | |
| 2636 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
| 2637 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 2638 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 2639 | CSKY_ISA_FLOAT_E1, | |
| 2640 | v1_work_fpu_fo), | |
| 2641 | OP16_WITH_WORK ("fmts", | |
| 2642 | OPCODE_INFO2 (0x00000000, | |
| 2643 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2644 | (NONE, FREG, OPRND_SHIFT_0_BIT)), | |
| 2645 | CSKY_ISA_FLOAT_E1, | |
| 2646 | v1_work_fpu_write), | |
| 2647 | OP16_WITH_WORK ("fmfs", | |
| 2648 | OPCODE_INFO2 (0x00000000, | |
| 2649 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2650 | (NONE, FREG, OPRND_SHIFT_0_BIT)), | |
| 2651 | CSKY_ISA_FLOAT_E1, | |
| 2652 | v1_work_fpu_read), | |
| 2653 | OP16_WITH_WORK ("fmtd", | |
| 2654 | OPCODE_INFO2 (0x00000000, | |
| 2655 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2656 | (NONE, FEREG, OPRND_SHIFT_0_BIT)), | |
| 2657 | CSKY_ISA_FLOAT_E1, | |
| 2658 | v1_work_fpu_writed), | |
| 2659 | OP16_WITH_WORK ("fmfd", | |
| 2660 | OPCODE_INFO2 (0x00000000, | |
| 2661 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 2662 | (NONE, FEREG, OPRND_SHIFT_0_BIT)), | |
| 2663 | CSKY_ISA_FLOAT_E1, | |
| 2664 | v1_work_fpu_readd), | |
| f24ff6e9 | 2665 | {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL} |
| b8891f8d AJ |
2666 | }; |
| 2667 | ||
| 2668 | #undef _TRANSFER | |
| 2669 | #undef _RELOC16 | |
| 2670 | #undef _RELOC32 | |
| 2671 | #undef _RELAX | |
| 2672 | ||
| 2673 | /* C-SKY v2 opcodes. */ | |
| 2674 | const struct csky_opcode csky_v2_opcodes[] = | |
| 2675 | { | |
| 2676 | #define _TRANSFER 0 | |
| 2677 | #define _RELOC16 0 | |
| 2678 | #define _RELOC32 0 | |
| 2679 | #define _RELAX 0 | |
| 2680 | OP16 ("bkpt", | |
| 2681 | OPCODE_INFO0 (0x0000), | |
| 2682 | CSKYV2_ISA_E1), | |
| 2683 | OP16_WITH_WORK ("nie", | |
| 2684 | OPCODE_INFO0 (0x1460), | |
| 2685 | CSKYV2_ISA_E1, | |
| 2686 | v2_work_istack), | |
| 2687 | OP16_WITH_WORK ("nir", | |
| 2688 | OPCODE_INFO0 (0x1461), | |
| 2689 | CSKYV2_ISA_E1, | |
| 2690 | v2_work_istack), | |
| 2691 | OP16_WITH_WORK ("ipush", | |
| 2692 | OPCODE_INFO0 (0x1462), | |
| 2693 | CSKYV2_ISA_E1, | |
| 2694 | v2_work_istack), | |
| 2695 | OP16_WITH_WORK ("ipop", | |
| 2696 | OPCODE_INFO0 (0x1463), | |
| 2697 | CSKYV2_ISA_E1, | |
| 2698 | v2_work_istack), | |
| 2699 | OP16 ("bpop.h", | |
| 2700 | OPCODE_INFO1 (0x14a0, | |
| 2701 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 2702 | CSKY_ISA_JAVA), | |
| 2703 | OP16 ("bpop.w", | |
| 2704 | OPCODE_INFO1 (0x14a2, | |
| 2705 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 2706 | CSKY_ISA_JAVA), | |
| 2707 | OP16 ("bpush.h", | |
| 2708 | OPCODE_INFO1 (0x14e0, | |
| 2709 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 2710 | CSKY_ISA_JAVA), | |
| 2711 | OP16 ("bpush.w", | |
| 2712 | OPCODE_INFO1 (0x14e2, | |
| 2713 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 2714 | CSKY_ISA_JAVA), | |
| 2715 | OP32 ("bmset", | |
| 2716 | OPCODE_INFO0 (0xc0001020), | |
| 2717 | CSKY_ISA_JAVA), | |
| 2718 | OP32 ("bmclr", | |
| 2719 | OPCODE_INFO0 (0xc0001420), | |
| 2720 | CSKY_ISA_JAVA), | |
| 2721 | OP32 ("sce", | |
| 2722 | OPCODE_INFO1 (0xc0001820, | |
| 2723 | (21_24, IMM4b, OPRND_SHIFT_0_BIT)), | |
| 2724 | CSKY_ISA_MP), | |
| 2725 | OP32 ("trap", | |
| 2726 | OPCODE_INFO1 (0xc0002020, | |
| 2727 | (10_11, IMM2b, OPRND_SHIFT_0_BIT)), | |
| 2728 | CSKYV2_ISA_E1), | |
| 2729 | /* Secure/nsecure world switch. */ | |
| 2730 | OP32 ("wsc", | |
| 2731 | OPCODE_INFO0 (0xc0003c20), | |
| 2732 | CSKY_ISA_TRUST), | |
| 2733 | OP32 ("mtcr", | |
| 2734 | OPCODE_INFO2 (0xc0006420, | |
| 2735 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2736 | (0_4or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), | |
| 2737 | CSKYV2_ISA_E1), | |
| 2738 | OP32 ("mfcr", | |
| 2739 | OPCODE_INFO2 (0xc0006020, | |
| 2740 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2741 | (16_20or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), | |
| 2742 | CSKYV2_ISA_E1), | |
| 2743 | #undef _TRANSFER | |
| 2744 | #define _TRANSFER 2 | |
| 2745 | OP32 ("rte", | |
| 2746 | OPCODE_INFO0 (0xc0004020), | |
| 2747 | CSKYV2_ISA_E1), | |
| 2748 | OP32 ("rfi", | |
| 2749 | OPCODE_INFO0 (0xc0004420), | |
| 2750 | CSKYV2_ISA_2E3), | |
| 2751 | #undef _TRANSFER | |
| 2752 | #define _TRANSFER 0 | |
| 2753 | OP32 ("stop", | |
| 2754 | OPCODE_INFO0 (0xc0004820), | |
| 2755 | CSKYV2_ISA_E1), | |
| 2756 | OP32 ("wait", | |
| 2757 | OPCODE_INFO0 (0xc0004c20), | |
| 2758 | CSKYV2_ISA_E1), | |
| 2759 | OP32 ("doze", | |
| 2760 | OPCODE_INFO0 (0xc0005020), | |
| 2761 | CSKYV2_ISA_E1), | |
| 2762 | OP32 ("we", | |
| 2763 | OPCODE_INFO0 (0xc0005420), | |
| 2764 | CSKY_ISA_MP_1E2), | |
| 2765 | OP32 ("se", | |
| 2766 | OPCODE_INFO0 (0xc0005820), | |
| 2767 | CSKY_ISA_MP_1E2), | |
| 2768 | OP32 ("psrclr", | |
| 2769 | OPCODE_INFO_LIST (0xc0007020, | |
| 2770 | (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), | |
| 2771 | CSKYV2_ISA_E1), | |
| 2772 | OP32 ("psrset", | |
| 2773 | OPCODE_INFO_LIST (0xc0007420, | |
| 2774 | (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), | |
| 2775 | CSKYV2_ISA_E1), | |
| 2776 | DOP32 ("abs", | |
| 2777 | OPCODE_INFO2 (0xc4000200, | |
| 2778 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2779 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2780 | OPCODE_INFO1 (0xc4000200, | |
| 2781 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 2782 | CSKYV2_ISA_2E3), | |
| 2783 | OP32 ("mvc", | |
| 2784 | OPCODE_INFO1 (0xc4000500, | |
| 2785 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
| 2786 | CSKYV2_ISA_1E2), | |
| 2787 | OP32 ("incf", | |
| 2788 | OPCODE_INFO3 (0xc4000c20, | |
| 2789 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 2790 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2791 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2792 | CSKYV2_ISA_1E2), | |
| 2793 | OP32 ("movf", | |
| 2794 | OPCODE_INFO2 (0xc4000c20, | |
| 2795 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 2796 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2797 | CSKYV2_ISA_1E2), | |
| 2798 | OP32 ("inct", | |
| 2799 | OPCODE_INFO3 (0xc4000c40, | |
| 2800 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 2801 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2802 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2803 | CSKYV2_ISA_1E2), | |
| 2804 | OP32 ("movt", | |
| 2805 | OPCODE_INFO2 (0xc4000c40, | |
| 2806 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 2807 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2808 | CSKYV2_ISA_1E2), | |
| 2809 | OP32 ("decf", | |
| 2810 | OPCODE_INFO3 (0xc4000c80, | |
| 2811 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 2812 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2813 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2814 | CSKYV2_ISA_1E2), | |
| 2815 | OP32 ("dect", | |
| 2816 | OPCODE_INFO3 (0xc4000d00, | |
| 2817 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 2818 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2819 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2820 | CSKYV2_ISA_1E2), | |
| 2821 | OP32 ("decgt", | |
| 2822 | OPCODE_INFO3 (0xc4001020, | |
| 2823 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2824 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2825 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2826 | CSKYV2_ISA_2E3), | |
| 2827 | OP32 ("declt", | |
| 2828 | OPCODE_INFO3 (0xc4001040, | |
| 2829 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2830 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2831 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2832 | CSKYV2_ISA_2E3), | |
| 2833 | OP32 ("decne", | |
| 2834 | OPCODE_INFO3 (0xc4001080, | |
| 2835 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2836 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2837 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2838 | CSKYV2_ISA_2E3), | |
| 2839 | OP32 ("clrf", | |
| 2840 | OPCODE_INFO1 (0xc4002c20, | |
| 2841 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2842 | CSKYV2_ISA_2E3), | |
| 2843 | OP32 ("clrt", | |
| 2844 | OPCODE_INFO1 (0xc4002c40, | |
| 2845 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2846 | CSKYV2_ISA_2E3), | |
| 2847 | DOP32 ("rotli", | |
| 2848 | OPCODE_INFO3 (0xc4004900, | |
| 2849 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2850 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2851 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2852 | OPCODE_INFO2 (0xc4004900, | |
| 2853 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 2854 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 2855 | CSKYV2_ISA_1E2), | |
| 2856 | OP32 ("lslc", | |
| 2857 | OPCODE_INFO3 (0xc4004c20, | |
| 2858 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2859 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2860 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 2861 | CSKYV2_ISA_1E2), | |
| 2862 | OP32 ("lsrc", | |
| 2863 | OPCODE_INFO3 (0xc4004c40, | |
| 2864 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2865 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2866 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 2867 | CSKYV2_ISA_1E2), | |
| 2868 | DOP32 ("asrc", | |
| 2869 | OPCODE_INFO3 (0xc4004c80, | |
| 2870 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2871 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2872 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 2873 | OPCODE_INFO1 (0xc4004c80, | |
| 2874 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 2875 | CSKYV2_ISA_1E2), | |
| 2876 | OP32 ("xsr", | |
| 2877 | OPCODE_INFO3 (0xc4004d00, | |
| 2878 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2879 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2880 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 2881 | CSKYV2_ISA_1E2), | |
| 2882 | OP32 ("bgenr", | |
| 2883 | OPCODE_INFO2 (0xc4005040, | |
| 2884 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2885 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2886 | CSKYV2_ISA_2E3), | |
| 2887 | DOP32 ("brev", | |
| 2888 | OPCODE_INFO2 (0xc4006200, | |
| 2889 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2890 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2891 | OPCODE_INFO1 (0xc4006200, | |
| 2892 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 2893 | CSKYV2_ISA_2E3), | |
| 2894 | OP32 ("xtrb0", | |
| 2895 | OPCODE_INFO2 (0xc4007020, | |
| 2896 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2897 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2898 | CSKYV2_ISA_1E2), | |
| 2899 | OP32 ("xtrb1", | |
| 2900 | OPCODE_INFO2 (0xc4007040, | |
| 2901 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2902 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2903 | CSKYV2_ISA_1E2), | |
| 2904 | OP32 ("xtrb2", | |
| 2905 | OPCODE_INFO2 (0xc4007080, | |
| 2906 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2907 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2908 | CSKYV2_ISA_1E2), | |
| 2909 | OP32 ("xtrb3", | |
| 2910 | OPCODE_INFO2 (0xc4007100, | |
| 2911 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2912 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2913 | CSKYV2_ISA_1E2), | |
| 2914 | OP32 ("ff0", | |
| 2915 | OPCODE_INFO2 (0xc4007c20, | |
| 2916 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2917 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2918 | CSKYV2_ISA_1E2), | |
| 2919 | DOP32 ("ff1", | |
| 2920 | OPCODE_INFO2 (0xc4007c40, | |
| 2921 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 2922 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2923 | OPCODE_INFO1 (0xc4007c40, | |
| 2924 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 2925 | CSKYV2_ISA_1E2), | |
| 2926 | OP32 ("mulu", | |
| 2927 | OPCODE_INFO2 (0xc4008820, | |
| 2928 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2929 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2930 | CSKY_ISA_DSP), | |
| 2931 | OP32 ("mulua", | |
| 2932 | OPCODE_INFO2 (0xc4008840, | |
| 2933 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2934 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2935 | CSKY_ISA_DSP), | |
| 2936 | OP32 ("mulus", | |
| 2937 | OPCODE_INFO2 (0xc4008880, | |
| 2938 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2939 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2940 | CSKY_ISA_DSP), | |
| 2941 | OP32 ("muls", | |
| 2942 | OPCODE_INFO2 (0xc4008c20, | |
| 2943 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2944 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2945 | CSKY_ISA_DSP), | |
| 2946 | OP32 ("mulsa", | |
| 2947 | OPCODE_INFO2 (0xc4008c40, | |
| 2948 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2949 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2950 | CSKY_ISA_DSP), | |
| 2951 | OP32 ("mulss", | |
| 2952 | OPCODE_INFO2 (0xc4008c80, | |
| 2953 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2954 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2955 | CSKY_ISA_DSP), | |
| 2956 | OP32 ("mulsha", | |
| 2957 | OPCODE_INFO2 (0xc4009040, | |
| 2958 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2959 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2960 | CSKY_ISA_DSP), | |
| 2961 | OP32 ("mulshs", | |
| 2962 | OPCODE_INFO2 (0xc4009080, | |
| 2963 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2964 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2965 | CSKY_ISA_DSP), | |
| 2966 | OP32 ("mulswa", | |
| 2967 | OPCODE_INFO2 (0xc4009440, | |
| 2968 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 2969 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2970 | CSKY_ISA_DSP), | |
| 2971 | OP32 ("mulsws", | |
| 8119cc38 | 2972 | OPCODE_INFO2 (0xc4009500, |
| b8891f8d AJ |
2973 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2974 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 2975 | CSKY_ISA_DSP), | |
| 2976 | OP32 ("mfhis", | |
| 2977 | OPCODE_INFO1 (0xc4009820, | |
| 2978 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
| 2979 | CSKY_ISA_DSP), | |
| 2980 | OP32 ("mflos", | |
| 2981 | OPCODE_INFO1 (0xc4009880, | |
| 2982 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
| 2983 | CSKY_ISA_DSP), | |
| 2984 | OP32 ("mvtc", | |
| 2985 | OPCODE_INFO0 (0xc4009a00), | |
| 6a1ed910 | 2986 | CSKY_ISA_DSPE60), |
| b8891f8d AJ |
2987 | OP32 ("mfhi", |
| 2988 | OPCODE_INFO1 (0xc4009c20, | |
| 2989 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
| 2990 | CSKY_ISA_DSP), | |
| 2991 | OP32 ("mthi", | |
| 2992 | OPCODE_INFO1 (0xc4009c40, | |
| 2993 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 2994 | CSKY_ISA_DSP), | |
| 2995 | OP32 ("mflo", | |
| 2996 | OPCODE_INFO1 (0xc4009c80, | |
| 2997 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
| 2998 | CSKY_ISA_DSP), | |
| 2999 | OP32 ("mtlo", | |
| 3000 | OPCODE_INFO1 (0xc4009d00, | |
| 3001 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 3002 | CSKY_ISA_DSP), | |
| 3003 | OP32 ("vmulsh", | |
| 3004 | OPCODE_INFO2 (0xc400b020, | |
| 3005 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3006 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3007 | CSKY_ISA_DSP_1E2), | |
| 3008 | OP32 ("vmulsha", | |
| 3009 | OPCODE_INFO2 (0xc400b040, | |
| 3010 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3011 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3012 | CSKY_ISA_DSP_1E2), | |
| 3013 | OP32 ("vmulshs", | |
| 3014 | OPCODE_INFO2 (0xc400b080, | |
| 3015 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3016 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3017 | CSKY_ISA_DSP_1E2), | |
| 3018 | OP32 ("vmulsw", | |
| 3019 | OPCODE_INFO2 (0xc400b420, | |
| 3020 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3021 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3022 | CSKY_ISA_DSP_1E2), | |
| 3023 | OP32 ("vmulswa", | |
| 3024 | OPCODE_INFO2 (0xc400b440, | |
| 3025 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3026 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3027 | CSKY_ISA_DSP_1E2), | |
| 3028 | OP32 ("vmulsws", | |
| 3029 | OPCODE_INFO2 (0xc400b480, | |
| 3030 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3031 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3032 | CSKY_ISA_DSP_1E2), | |
| 3033 | OP32 ("ldr.b", | |
| 3034 | SOPCODE_INFO2 (0xd0000000, | |
| 3035 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3036 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3037 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
| 3038 | CSKYV2_ISA_2E3), | |
| 3039 | OP32 ("ldr.bs", | |
| 3040 | SOPCODE_INFO2 (0xd0001000, | |
| 3041 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3042 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3043 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
| 3044 | CSKYV2_ISA_2E3), | |
| 3045 | OP32 ("ldr.h", | |
| 3046 | SOPCODE_INFO2 (0xd0000400, | |
| 3047 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3048 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3049 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
| 3050 | CSKYV2_ISA_2E3), | |
| 3051 | OP32 ("ldr.hs", | |
| 3052 | SOPCODE_INFO2 (0xd0001400, | |
| 3053 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3054 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3055 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
| 3056 | CSKYV2_ISA_2E3), | |
| 3057 | OP32 ("ldr.w", | |
| 3058 | SOPCODE_INFO2 (0xd0000800, | |
| 3059 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3060 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3061 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
| 3062 | CSKYV2_ISA_2E3), | |
| 3063 | OP32 ("ldm", | |
| 3064 | OPCODE_INFO2 (0xd0001c20, | |
| 3065 | (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 3066 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3067 | CSKYV2_ISA_1E2), | |
| 3068 | OP32 ("ldq", | |
| 3069 | OPCODE_INFO2 (0xd0801c23, | |
| 3070 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), | |
| 3071 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3072 | CSKYV2_ISA_2E3), | |
| 3073 | OP32 ("str.b", | |
| 3074 | SOPCODE_INFO2 (0xd4000000, | |
| 3075 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3076 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3077 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
| 3078 | CSKYV2_ISA_2E3), | |
| 3079 | OP32 ("str.h", | |
| 3080 | SOPCODE_INFO2 (0xd4000400, | |
| 3081 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3082 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3083 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
| 3084 | CSKYV2_ISA_2E3), | |
| 3085 | OP32 ("str.w", | |
| 3086 | SOPCODE_INFO2 (0xd4000800, | |
| 3087 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3088 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3089 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
| 3090 | CSKYV2_ISA_2E3), | |
| 3091 | OP32 ("stm", | |
| 3092 | OPCODE_INFO2 (0xd4001c20, | |
| 3093 | (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 3094 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3095 | CSKYV2_ISA_1E2), | |
| 3096 | OP32 ("stq", | |
| 3097 | OPCODE_INFO2 (0xd4801c23, | |
| 3098 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), | |
| 3099 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3100 | CSKYV2_ISA_2E3), | |
| 3101 | OP32 ("ld.bs", | |
| 3102 | SOPCODE_INFO2 (0xd8004000, | |
| 3103 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3104 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3105 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 3106 | CSKYV2_ISA_1E2), | |
| 3107 | OP32 ("ldbs", | |
| 3108 | SOPCODE_INFO2 (0xd8004000, | |
| 3109 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3110 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3111 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 3112 | CSKYV2_ISA_1E2), | |
| 3113 | OP32 ("ld.hs", | |
| 3114 | SOPCODE_INFO2 (0xd8005000, | |
| 3115 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3116 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3117 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 3118 | CSKYV2_ISA_1E2), | |
| 3119 | OP32 ("ldhs", | |
| 3120 | SOPCODE_INFO2 (0xd8005000, | |
| 3121 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3122 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3123 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 3124 | CSKYV2_ISA_1E2), | |
| 3125 | OP32 ("ld.d", | |
| 3126 | SOPCODE_INFO2 (0xd8003000, | |
| 3127 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3128 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3129 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3130 | CSKYV2_ISA_3E7), | |
| 3131 | OP32 ("ldex.w", | |
| 3132 | SOPCODE_INFO2 (0xd8007000, | |
| 3133 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3134 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3135 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3136 | CSKY_ISA_MP_1E2), | |
| 3137 | OP32 ("ldexw", | |
| 3138 | SOPCODE_INFO2 (0xd8007000, | |
| 3139 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3140 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3141 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3142 | CSKY_ISA_MP_1E2), | |
| 3143 | OP32 ("ldex", | |
| 3144 | SOPCODE_INFO2 (0xd8007000, | |
| 3145 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3146 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3147 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3148 | CSKY_ISA_MP_1E2), | |
| 3149 | OP32 ("st.d", | |
| 3150 | SOPCODE_INFO2 (0xdc003000, | |
| 3151 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3152 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3153 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3154 | CSKYV2_ISA_3E7), | |
| 3155 | OP32 ("stex.w", | |
| 3156 | SOPCODE_INFO2 (0xdc007000, | |
| 3157 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3158 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3159 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3160 | CSKY_ISA_MP_1E2), | |
| 3161 | OP32 ("stexw", | |
| 3162 | SOPCODE_INFO2 (0xdc007000, | |
| 3163 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3164 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3165 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3166 | CSKY_ISA_MP_1E2), | |
| 3167 | OP32 ("stex", | |
| 3168 | SOPCODE_INFO2 (0xdc007000, | |
| 3169 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3170 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3171 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3172 | CSKY_ISA_MP_1E2), | |
| 3173 | DOP32 ("andi", | |
| 3174 | OPCODE_INFO3 (0xe4002000, | |
| 3175 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3176 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3177 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), | |
| 3178 | OPCODE_INFO2 (0xe4002000, | |
| 3179 | (16_20or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3180 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), | |
| 3181 | CSKYV2_ISA_1E2), | |
| 3182 | OP32 ("andni", | |
| 3183 | OPCODE_INFO3 (0xe4003000, | |
| 3184 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3185 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3186 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), | |
| 3187 | CSKYV2_ISA_1E2), | |
| 3188 | OP32 ("xori", | |
| 3189 | OPCODE_INFO3 (0xe4004000, | |
| 3190 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3191 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3192 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), | |
| 3193 | CSKYV2_ISA_1E2), | |
| 3194 | OP32 ("ins", | |
| 3195 | OPCODE_INFO4 (0xc4005c00, | |
| 3196 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3197 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3198 | (5_9, MSB2SIZE, OPRND_SHIFT_0_BIT), | |
| 3199 | (0_4, LSB2SIZE, OPRND_SHIFT_0_BIT)), | |
| 3200 | CSKYV2_ISA_2E3), | |
| 3201 | #undef _TRANSFER | |
| 3202 | #undef _RELOC32 | |
| 3203 | #define _TRANSFER 1 | |
| 3204 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 | |
| 3205 | OP32 ("jmpi", | |
| 3206 | OPCODE_INFO1 (0xeac00000, | |
| 3207 | (0_15, OFF16b, OPRND_SHIFT_2_BIT)), | |
| 3208 | CSKYV2_ISA_2E3), | |
| 3209 | #undef _TRANSFER | |
| 3210 | #undef _RELOC32 | |
| 3211 | #define _TRANSFER 0 | |
| 3212 | #define _RELOC32 0 | |
| 3213 | ||
| 3214 | OP32 ("fadds", | |
| 3215 | OPCODE_INFO3 (0xf4000000, | |
| 3216 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3217 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3218 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3219 | CSKY_ISA_FLOAT_E1), | |
| 3220 | OP32 ("fsubs", | |
| 3221 | OPCODE_INFO3 (0xf4000020, | |
| 3222 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3223 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3224 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3225 | CSKY_ISA_FLOAT_E1), | |
| 3226 | OP32 ("fmovs", | |
| 3227 | OPCODE_INFO2 (0xf4000080, | |
| 3228 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3229 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3230 | CSKY_ISA_FLOAT_E1), | |
| 3231 | OP32 ("fabss", | |
| 3232 | OPCODE_INFO2 (0xf40000c0, | |
| 3233 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3234 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3235 | CSKY_ISA_FLOAT_E1), | |
| 3236 | OP32 ("fnegs", | |
| 3237 | OPCODE_INFO2 (0xf40000e0, | |
| 3238 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3239 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3240 | CSKY_ISA_FLOAT_E1), | |
| 3241 | OP32 ("fcmpzhss", | |
| 3242 | OPCODE_INFO1 (0xf4000100, | |
| 3243 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3244 | CSKY_ISA_FLOAT_E1), | |
| 3245 | OP32 ("fcmpzlss", | |
| 3246 | OPCODE_INFO1 (0xf4000120, | |
| 3247 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3248 | CSKY_ISA_FLOAT_E1), | |
| 3249 | OP32 ("fcmpznes", | |
| 3250 | OPCODE_INFO1 (0xf4000140, | |
| 3251 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3252 | CSKY_ISA_FLOAT_E1), | |
| 3253 | OP32 ("fcmpzuos", | |
| 3254 | OPCODE_INFO1 (0xf4000160, | |
| 3255 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3256 | CSKY_ISA_FLOAT_E1), | |
| 3257 | OP32 ("fcmphss", | |
| 3258 | OPCODE_INFO2 (0xf4000180, | |
| 3259 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3260 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3261 | CSKY_ISA_FLOAT_E1), | |
| 3262 | OP32 ("fcmplts", | |
| 3263 | OPCODE_INFO2 (0xf40001a0, | |
| 3264 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3265 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3266 | CSKY_ISA_FLOAT_E1), | |
| 3267 | OP32 ("fcmpnes", | |
| 3268 | OPCODE_INFO2 (0xf40001c0, | |
| 3269 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3270 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3271 | CSKY_ISA_FLOAT_E1), | |
| 3272 | OP32 ("fcmpuos", | |
| 3273 | OPCODE_INFO2 (0xf40001e0, | |
| 3274 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3275 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3276 | CSKY_ISA_FLOAT_E1), | |
| 3277 | OP32 ("fmuls", | |
| 3278 | OPCODE_INFO3 (0xf4000200, | |
| 3279 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3280 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3281 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3282 | CSKY_ISA_FLOAT_E1), | |
| 3283 | OP32 ("fmacs", | |
| 3284 | OPCODE_INFO3 (0xf4000280, | |
| 3285 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3286 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3287 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3288 | CSKY_ISA_FLOAT_E1), | |
| 3289 | OP32 ("fmscs", | |
| 3290 | OPCODE_INFO3 (0xf40002a0, | |
| 3291 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3292 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3293 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3294 | CSKY_ISA_FLOAT_E1), | |
| 3295 | OP32 ("fnmacs", | |
| 3296 | OPCODE_INFO3 (0xf40002c0, | |
| 3297 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3298 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3299 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3300 | CSKY_ISA_FLOAT_E1), | |
| 3301 | OP32 ("fnmscs", | |
| 3302 | OPCODE_INFO3 (0xf40002e0, | |
| 3303 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3304 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3305 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3306 | CSKY_ISA_FLOAT_E1), | |
| 3307 | OP32 ("fnmuls", | |
| 3308 | OPCODE_INFO3 (0xf4000220, | |
| 3309 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3310 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3311 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3312 | CSKY_ISA_FLOAT_E1), | |
| 3313 | OP32 ("fdivs", | |
| 3314 | OPCODE_INFO3 (0xf4000300, | |
| 3315 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3316 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3317 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3318 | CSKY_ISA_FLOAT_E1), | |
| 3319 | OP32 ("frecips", | |
| 3320 | OPCODE_INFO2 (0xf4000320, | |
| 3321 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3322 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3323 | CSKY_ISA_FLOAT_E1), | |
| 3324 | OP32 ("fsqrts", | |
| 3325 | OPCODE_INFO2 (0xf4000340, | |
| 3326 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3327 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3328 | CSKY_ISA_FLOAT_E1), | |
| 3329 | OP32 ("faddd", | |
| 3330 | OPCODE_INFO3 (0xf4000800, | |
| 3331 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3332 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3333 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3334 | CSKY_ISA_FLOAT_1E2), | |
| 3335 | OP32 ("fsubd", | |
| 3336 | OPCODE_INFO3 (0xf4000820, | |
| 3337 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3338 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3339 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3340 | CSKY_ISA_FLOAT_1E2), | |
| 3341 | OP32 ("fmovd", | |
| 3342 | OPCODE_INFO2 (0xf4000880, | |
| 3343 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3344 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3345 | CSKY_ISA_FLOAT_1E2), | |
| 3346 | OP32 ("fabsd", | |
| 3347 | OPCODE_INFO2 (0xf40008c0, | |
| 3348 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3349 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3350 | CSKY_ISA_FLOAT_1E2), | |
| 3351 | OP32 ("fnegd", | |
| 3352 | OPCODE_INFO2 (0xf40008e0, | |
| 3353 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3354 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3355 | CSKY_ISA_FLOAT_1E2), | |
| 3356 | OP32 ("fcmpzhsd", | |
| 3357 | OPCODE_INFO1 (0xf4000900, | |
| 3358 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3359 | CSKY_ISA_FLOAT_1E2), | |
| 3360 | OP32 ("fcmpzlsd", | |
| 3361 | OPCODE_INFO1 (0xf4000920, | |
| 3362 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3363 | CSKY_ISA_FLOAT_1E2), | |
| 3364 | OP32 ("fcmpzned", | |
| 3365 | OPCODE_INFO1 (0xf4000940, | |
| 3366 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3367 | CSKY_ISA_FLOAT_1E2), | |
| 3368 | OP32 ("fcmpzuod", | |
| 3369 | OPCODE_INFO1 (0xf4000960, | |
| 3370 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3371 | CSKY_ISA_FLOAT_1E2), | |
| 3372 | OP32 ("fcmphsd", | |
| 3373 | OPCODE_INFO2 (0xf4000980, | |
| 3374 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3375 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3376 | CSKY_ISA_FLOAT_1E2), | |
| 3377 | OP32 ("fcmpltd", | |
| 3378 | OPCODE_INFO2 (0xf40009a0, | |
| 3379 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3380 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3381 | CSKY_ISA_FLOAT_1E2), | |
| 3382 | OP32 ("fcmpned", | |
| 3383 | OPCODE_INFO2 (0xf40009c0, | |
| 3384 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3385 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3386 | CSKY_ISA_FLOAT_1E2), | |
| 3387 | OP32 ("fcmpuod", | |
| 3388 | OPCODE_INFO2 (0xf40009e0, | |
| 3389 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3390 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3391 | CSKY_ISA_FLOAT_1E2), | |
| 3392 | OP32 ("fmuld", | |
| 3393 | OPCODE_INFO3 (0xf4000a00, | |
| 3394 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3395 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3396 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3397 | CSKY_ISA_FLOAT_1E2), | |
| 3398 | OP32 ("fnmuld", | |
| 3399 | OPCODE_INFO3 (0xf4000a20, | |
| 3400 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3401 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3402 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3403 | CSKY_ISA_FLOAT_1E2), | |
| 3404 | OP32 ("fmacd", | |
| 3405 | OPCODE_INFO3 (0xf4000a80, | |
| 3406 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3407 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3408 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3409 | CSKY_ISA_FLOAT_1E2), | |
| 3410 | OP32 ("fmscd", | |
| 3411 | OPCODE_INFO3 (0xf4000aa0, | |
| 3412 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3413 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3414 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3415 | CSKY_ISA_FLOAT_1E2), | |
| 3416 | OP32 ("fnmacd", | |
| 3417 | OPCODE_INFO3 (0xf4000ac0, | |
| 3418 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3419 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3420 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3421 | CSKY_ISA_FLOAT_1E2), | |
| 3422 | OP32 ("fnmscd", | |
| 3423 | OPCODE_INFO3 (0xf4000ae0, | |
| 3424 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3425 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3426 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3427 | CSKY_ISA_FLOAT_1E2), | |
| 3428 | OP32 ("fdivd", | |
| 3429 | OPCODE_INFO3 (0xf4000b00, | |
| 3430 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3431 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3432 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3433 | CSKY_ISA_FLOAT_1E2), | |
| 3434 | OP32 ("frecipd", | |
| 3435 | OPCODE_INFO2 (0xf4000b20, | |
| 3436 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3437 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3438 | CSKY_ISA_FLOAT_1E2), | |
| 3439 | OP32 ("fsqrtd", | |
| 3440 | OPCODE_INFO2 (0xf4000b40, | |
| 3441 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3442 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3443 | CSKY_ISA_FLOAT_1E2), | |
| 3444 | OP32 ("faddm", | |
| 3445 | OPCODE_INFO3 (0xf4001000, | |
| 3446 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3447 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3448 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3449 | CSKY_ISA_FLOAT_1E2), | |
| 3450 | OP32 ("fsubm", | |
| 3451 | OPCODE_INFO3 (0xf4001020, | |
| 3452 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3453 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3454 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3455 | CSKY_ISA_FLOAT_1E2), | |
| 3456 | OP32 ("fmovm", | |
| 3457 | OPCODE_INFO2 (0xf4001080, | |
| 3458 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3459 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3460 | CSKY_ISA_FLOAT_1E2), | |
| 3461 | OP32 ("fabsm", | |
| 3462 | OPCODE_INFO2 (0xf40010c0, | |
| 3463 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3464 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3465 | CSKY_ISA_FLOAT_1E2), | |
| 3466 | OP32 ("fnegm", | |
| 3467 | OPCODE_INFO2 (0xf40010e0, | |
| 3468 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3469 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3470 | CSKY_ISA_FLOAT_1E2), | |
| 3471 | OP32 ("fmulm", | |
| 3472 | OPCODE_INFO3 (0xf4001200, | |
| 3473 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3474 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3475 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3476 | CSKY_ISA_FLOAT_1E2), | |
| 3477 | OP32 ("fnmulm", | |
| 3478 | OPCODE_INFO3 (0xf4001220, | |
| 3479 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3480 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3481 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3482 | CSKY_ISA_FLOAT_1E2), | |
| 3483 | OP32 ("fmacm", | |
| 3484 | OPCODE_INFO3 (0xf4001280, | |
| 3485 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3486 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3487 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3488 | CSKY_ISA_FLOAT_1E2), | |
| 3489 | OP32 ("fmscm", | |
| 3490 | OPCODE_INFO3 (0xf40012a0, | |
| 3491 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3492 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3493 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3494 | CSKY_ISA_FLOAT_1E2), | |
| 3495 | OP32 ("fnmacm", | |
| 3496 | OPCODE_INFO3 (0xf40012c0, | |
| 3497 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3498 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3499 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3500 | CSKY_ISA_FLOAT_1E2), | |
| 3501 | OP32 ("fnmscm", | |
| 3502 | OPCODE_INFO3 (0xf40012e0, | |
| 3503 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3504 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
| 3505 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
| 3506 | CSKY_ISA_FLOAT_1E2), | |
| 3507 | OP32 ("fstosi.rn", | |
| 3508 | OPCODE_INFO2 (0xf4001800, | |
| 3509 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3510 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3511 | CSKY_ISA_FLOAT_E1), | |
| 3512 | OP32 ("fstosi.rz", | |
| 3513 | OPCODE_INFO2 (0xf4001820, | |
| 3514 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3515 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3516 | CSKY_ISA_FLOAT_E1), | |
| 3517 | OP32 ("fstosi.rpi", | |
| 3518 | OPCODE_INFO2 (0xf4001840, | |
| 3519 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3520 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3521 | CSKY_ISA_FLOAT_E1), | |
| 3522 | OP32 ("fstosi.rni", | |
| 3523 | OPCODE_INFO2 (0xf4001860, | |
| 3524 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3525 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3526 | CSKY_ISA_FLOAT_E1), | |
| 3527 | OP32 ("fstoui.rn", | |
| 3528 | OPCODE_INFO2 (0xf4001880, | |
| 3529 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3530 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3531 | CSKY_ISA_FLOAT_E1), | |
| 3532 | OP32 ("fstoui.rz", | |
| 3533 | OPCODE_INFO2 (0xf40018a0, | |
| 3534 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3535 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3536 | CSKY_ISA_FLOAT_E1), | |
| 3537 | OP32 ("fstoui.rpi", | |
| 3538 | OPCODE_INFO2 (0xf40018c0, | |
| 3539 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3540 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3541 | CSKY_ISA_FLOAT_E1), | |
| 3542 | OP32 ("fstoui.rni", | |
| 3543 | OPCODE_INFO2 (0xf40018e0, | |
| 3544 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3545 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3546 | CSKY_ISA_FLOAT_E1), | |
| 3547 | OP32 ("fdtosi.rn", | |
| 3548 | OPCODE_INFO2 (0xf4001900, | |
| 3549 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3550 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3551 | CSKY_ISA_FLOAT_1E2), | |
| 3552 | OP32 ("fdtosi.rz", | |
| 3553 | OPCODE_INFO2 (0xf4001920, | |
| 3554 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3555 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3556 | CSKY_ISA_FLOAT_1E2), | |
| 3557 | OP32 ("fdtosi.rpi", | |
| 3558 | OPCODE_INFO2 (0xf4001940, | |
| 3559 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3560 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3561 | CSKY_ISA_FLOAT_1E2), | |
| 3562 | OP32 ("fdtosi.rni", | |
| 3563 | OPCODE_INFO2 (0xf4001960, | |
| 3564 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3565 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3566 | CSKY_ISA_FLOAT_1E2), | |
| 3567 | OP32 ("fdtoui.rn", | |
| 3568 | OPCODE_INFO2 (0xf4001980, | |
| 3569 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3570 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3571 | CSKY_ISA_FLOAT_1E2), | |
| 3572 | OP32 ("fdtoui.rz", | |
| 3573 | OPCODE_INFO2 (0xf40019a0, | |
| 3574 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3575 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3576 | CSKY_ISA_FLOAT_1E2), | |
| 3577 | OP32 ("fdtoui.rpi", | |
| 3578 | OPCODE_INFO2 (0xf40019c0, | |
| 3579 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3580 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3581 | CSKY_ISA_FLOAT_1E2), | |
| 3582 | OP32 ("fdtoui.rni", | |
| 3583 | OPCODE_INFO2 (0xf40019e0, | |
| 3584 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3585 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3586 | CSKY_ISA_FLOAT_1E2), | |
| 3587 | OP32 ("fsitos", | |
| 3588 | OPCODE_INFO2 (0xf4001a00, | |
| 3589 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3590 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3591 | CSKY_ISA_FLOAT_E1), | |
| 3592 | OP32 ("fuitos", | |
| 3593 | OPCODE_INFO2 (0xf4001a20, | |
| 3594 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3595 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3596 | CSKY_ISA_FLOAT_E1), | |
| 3597 | OP32 ("fsitod", | |
| 3598 | OPCODE_INFO2 (0xf4001a80, | |
| 3599 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3600 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3601 | CSKY_ISA_FLOAT_1E2), | |
| 3602 | OP32 ("fuitod", | |
| 3603 | OPCODE_INFO2 (0xf4001aa0, | |
| 3604 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3605 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3606 | CSKY_ISA_FLOAT_1E2), | |
| 3607 | OP32 ("fdtos", | |
| 3608 | OPCODE_INFO2 (0xf4001ac0, | |
| 3609 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3610 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3611 | CSKY_ISA_FLOAT_1E2), | |
| 3612 | OP32 ("fstod", | |
| 3613 | OPCODE_INFO2 (0xf4001ae0, | |
| 3614 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3615 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3616 | CSKY_ISA_FLOAT_1E2), | |
| 3617 | OP32 ("fmfvrh", | |
| 3618 | OPCODE_INFO2 (0xf4001b00, | |
| 3619 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3620 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3621 | CSKY_ISA_FLOAT_1E2), | |
| 3622 | OP32 ("fmfvrl", | |
| 3623 | OPCODE_INFO2 (0xf4001b20, | |
| 3624 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3625 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
| 3626 | CSKY_ISA_FLOAT_E1), | |
| 3627 | OP32 ("fmtvrh", | |
| 3628 | OPCODE_INFO2 (0xf4001b40, | |
| 3629 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3630 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 3631 | CSKY_ISA_FLOAT_1E2), | |
| 3632 | OP32 ("fmtvrl", | |
| 3633 | OPCODE_INFO2 (0xf4001b60, | |
| 3634 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3635 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 3636 | CSKY_ISA_FLOAT_E1), | |
| 3637 | OP32 ("flds", | |
| 3638 | SOPCODE_INFO2 (0xf4002000, | |
| 3639 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3640 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3641 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), | |
| 3642 | CSKY_ISA_FLOAT_E1), | |
| 3643 | OP32 ("fldd", | |
| 3644 | SOPCODE_INFO2 (0xf4002100, | |
| 3645 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3646 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3647 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), | |
| 3648 | CSKY_ISA_FLOAT_1E2), | |
| 3649 | OP32 ("fldm", | |
| 3650 | SOPCODE_INFO2 (0xf4002200, | |
| 3651 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3652 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3653 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
| 3654 | CSKY_ISA_FLOAT_1E2), | |
| 3655 | OP32 ("fsts", | |
| 3656 | SOPCODE_INFO2 (0xf4002400, | |
| 3657 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3658 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3659 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), | |
| 3660 | CSKY_ISA_FLOAT_E1), | |
| 3661 | OP32 ("fstd", | |
| 3662 | SOPCODE_INFO2 (0xf4002500, | |
| 3663 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3664 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3665 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), | |
| 3666 | CSKY_ISA_FLOAT_1E2), | |
| 3667 | OP32 ("fstm", | |
| 3668 | SOPCODE_INFO2 (0xf4002600, | |
| 3669 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3670 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3671 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
| 3672 | CSKY_ISA_FLOAT_1E2), | |
| 3673 | OP32 ("fldrs", | |
| 3674 | SOPCODE_INFO2 (0xf4002800, | |
| 3675 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3676 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3677 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 3678 | CSKY_ISA_FLOAT_E1), | |
| 3679 | OP32 ("fstrs", | |
| 3680 | SOPCODE_INFO2 (0xf4002c00, | |
| 3681 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3682 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3683 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 3684 | CSKY_ISA_FLOAT_E1), | |
| 3685 | OP32 ("fldrd", | |
| 3686 | SOPCODE_INFO2 (0xf4002900, | |
| 3687 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3688 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3689 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 3690 | CSKY_ISA_FLOAT_1E2), | |
| 3691 | OP32 ("fldrm", | |
| 3692 | SOPCODE_INFO2 (0xf4002a00, | |
| 3693 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3694 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3695 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 3696 | CSKY_ISA_FLOAT_1E2), | |
| 3697 | OP32 ("fstrd", | |
| 3698 | SOPCODE_INFO2 (0xf4002d00, | |
| 3699 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3700 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3701 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 3702 | CSKY_ISA_FLOAT_1E2), | |
| 3703 | OP32 ("fstrm", | |
| 3704 | SOPCODE_INFO2 (0xf4002e00, | |
| 3705 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 3706 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3707 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 3708 | CSKY_ISA_FLOAT_1E2), | |
| 3709 | OP32 ("fldms", | |
| 3710 | OPCODE_INFO2 (0xf4003000, | |
| 3711 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 3712 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3713 | CSKY_ISA_FLOAT_E1), | |
| 3714 | OP32 ("fldmd", | |
| 3715 | OPCODE_INFO2 (0xf4003100, | |
| 3716 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 3717 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3718 | CSKY_ISA_FLOAT_1E2), | |
| 3719 | OP32 ("fldmm", | |
| 3720 | OPCODE_INFO2 (0xf4003200, | |
| 3721 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 3722 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3723 | CSKY_ISA_FLOAT_1E2), | |
| 3724 | OP32 ("fstms", | |
| 3725 | OPCODE_INFO2 (0xf4003400, | |
| 3726 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 3727 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3728 | CSKY_ISA_FLOAT_E1), | |
| 3729 | OP32 ("fstmd", | |
| 3730 | OPCODE_INFO2 (0xf4003500, | |
| 3731 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 3732 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3733 | CSKY_ISA_FLOAT_1E2), | |
| 3734 | OP32 ("fstmm", | |
| 3735 | OPCODE_INFO2 (0xf4003600, | |
| 3736 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 3737 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 3738 | CSKY_ISA_FLOAT_1E2), | |
| b8891f8d AJ |
3739 | DOP32 ("idly", |
| 3740 | OPCODE_INFO1 (0xc0001c20, | |
| 3741 | (21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)), | |
| 3742 | OPCODE_INFO0 (0xc0601c20), | |
| 3743 | CSKYV2_ISA_E1), | |
| 3744 | ||
| 3745 | #undef _RELOC32 | |
| 3746 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM18BY2 | |
| 3747 | OP32 ("grs", | |
| 3748 | OPCODE_INFO2 (0xcc0c0000, | |
| 3749 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 3750 | (0_17, IMM_OFF18b, OPRND_SHIFT_1_BIT)), | |
| 3751 | CSKYV2_ISA_2E3), | |
| 3752 | #undef _RELOC32 | |
| 3753 | #define _RELOC32 0 | |
| 3754 | DOP32 ("ixh", | |
| 3755 | OPCODE_INFO3 (0xc4000820, | |
| 3756 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3757 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3758 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3759 | OPCODE_INFO2 (0xc4000820, | |
| 3760 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3761 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3762 | CSKYV2_ISA_1E2), | |
| 3763 | DOP32 ("ixw", | |
| 3764 | OPCODE_INFO3 (0xc4000840, | |
| 3765 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3766 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3767 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3768 | OPCODE_INFO2 (0xc4000840, | |
| 3769 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3770 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3771 | CSKYV2_ISA_1E2), | |
| 3772 | OP32 ("ixd", | |
| 3773 | OPCODE_INFO3 (0xc4000880, | |
| 3774 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3775 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3776 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3777 | CSKYV2_ISA_2E3), | |
| 3778 | DOP32 ("divu", | |
| 3779 | OPCODE_INFO3 (0xc4008020, | |
| 3780 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3781 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3782 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3783 | OPCODE_INFO2 (0xc4008020, | |
| 3784 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3785 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3786 | CSKYV2_ISA_2E3), | |
| 3787 | DOP32 ("divs", | |
| 3788 | OPCODE_INFO3 (0xc4008040, | |
| 3789 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3790 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3791 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3792 | OPCODE_INFO2 (0xc4008040, | |
| 3793 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3794 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 3795 | CSKYV2_ISA_2E3), | |
| 3796 | OP32 ("pldr", | |
| 3797 | SOPCODE_INFO1 (0xd8006000, | |
| 3798 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3799 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3800 | CSKY_ISA_CACHE), | |
| 3801 | OP32 ("pldw", | |
| 3802 | SOPCODE_INFO1 (0xdc006000, | |
| 3803 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3804 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 3805 | CSKY_ISA_CACHE), | |
| 3806 | OP32 ("cprgr", | |
| 3807 | SOPCODE_INFO2 (0xfc000000, | |
| 3808 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3809 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
| 3810 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), | |
| 3811 | CSKYV2_ISA_E1), | |
| 3812 | OP32 ("cpwgr", | |
| 3813 | SOPCODE_INFO2 (0xfc001000, | |
| 3814 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3815 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
| 3816 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), | |
| 3817 | CSKYV2_ISA_E1), | |
| 3818 | OP32 ("cprcr", | |
| 3819 | SOPCODE_INFO2 (0xfc002000, | |
| 3820 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3821 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
| 3822 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), | |
| 3823 | CSKYV2_ISA_E1), | |
| 3824 | OP32 ("cpwcr", | |
| 3825 | SOPCODE_INFO2 (0xfc003000, | |
| 3826 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3827 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
| 3828 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), | |
| 3829 | CSKYV2_ISA_E1), | |
| 3830 | OP32 ("cprc", | |
| 3831 | SOPCODE_INFO1 (0xfc004000, | |
| 3832 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
| 3833 | (0_11, IMM12b, OPRND_SHIFT_0_BIT))), | |
| 3834 | CSKYV2_ISA_E1), | |
| 3835 | OP32 ("cpop", | |
| 3836 | SOPCODE_INFO1 (0xfc008000, | |
| 3837 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
| 3838 | (0_14or16_20 , IMM15b, OPRND_SHIFT_0_BIT))), | |
| 3839 | CSKYV2_ISA_E1), | |
| 3840 | ||
| 3841 | OP16_OP32 ("push", | |
| 3842 | OPCODE_INFO_LIST (0x14c0, | |
| 3843 | (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), | |
| 3844 | CSKYV2_ISA_E1, | |
| 3845 | OPCODE_INFO_LIST (0xebe00000, | |
| 3846 | (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), | |
| 3847 | CSKYV2_ISA_2E3), | |
| 3848 | #undef _TRANSFER | |
| 3849 | #define _TRANSFER 2 | |
| 3850 | OP16_OP32 ("pop", | |
| 3851 | OPCODE_INFO_LIST (0x1480, | |
| 3852 | (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), | |
| 3853 | CSKYV2_ISA_E1, | |
| 3854 | OPCODE_INFO_LIST (0xebc00000, | |
| 3855 | (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), | |
| 3856 | CSKYV2_ISA_2E3), | |
| 3857 | #undef _TRANSFER | |
| 3858 | #define _TRANSFER 0 | |
| 3859 | OP16_OP32 ("movi", | |
| 3860 | OPCODE_INFO2 (0x3000, | |
| 3861 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3862 | (0_7, IMM8b, OPRND_SHIFT_0_BIT)), | |
| 3863 | CSKYV2_ISA_E1, | |
| 3864 | OPCODE_INFO2 (0xea000000, | |
| 3865 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3866 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), | |
| 3867 | CSKYV2_ISA_1E2), | |
| 3868 | /* bmaski will transfer to movi when imm < 17. */ | |
| 3869 | OP16_OP32 ("bmaski", | |
| 3870 | OPCODE_INFO2 (0x3000, | |
| 3871 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3872 | (0_7, IMM8b_BMASKI, OPRND_SHIFT_0_BIT)), | |
| 3873 | CSKYV2_ISA_1E2, | |
| 3874 | OPCODE_INFO2 (0xc4005020, | |
| 3875 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3876 | (21_25, OIMM5b_BMASKI, OPRND_SHIFT_0_BIT)), | |
| 3877 | CSKYV2_ISA_1E2), | |
| 3878 | OP16_OP32 ("cmphsi", | |
| 3879 | OPCODE_INFO2 (0x3800, | |
| 3880 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3881 | (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 3882 | CSKYV2_ISA_E1, | |
| 3883 | OPCODE_INFO2 (0xeb000000, | |
| 3884 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3885 | (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), | |
| 3886 | CSKYV2_ISA_1E2), | |
| 3887 | OP16_OP32 ("cmplti", | |
| 3888 | OPCODE_INFO2 (0x3820, | |
| 3889 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3890 | (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 3891 | CSKYV2_ISA_E1, | |
| 3892 | OPCODE_INFO2 (0xeb200000, | |
| 3893 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3894 | (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), | |
| 3895 | CSKYV2_ISA_1E2), | |
| 3896 | OP16_OP32 ("cmpnei", | |
| 3897 | OPCODE_INFO2 (0x3840, | |
| 3898 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3899 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3900 | CSKYV2_ISA_E1, | |
| 3901 | OPCODE_INFO2 (0xeb400000, | |
| 3902 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3903 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), | |
| 3904 | CSKYV2_ISA_1E2), | |
| 3905 | #undef _TRANSFER | |
| 3906 | #define _TRANSFER 1 | |
| 3907 | OP16_OP32 ("jmpix", | |
| 3908 | OPCODE_INFO2 (0x38e0, | |
| 3909 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3910 | (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), | |
| 3911 | CSKY_ISA_JAVA, | |
| 3912 | OPCODE_INFO2 (0xe9e00000, | |
| 3913 | (16_20, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3914 | (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), | |
| 3915 | CSKY_ISA_JAVA), | |
| 3916 | #undef _TRANSFER | |
| 3917 | #define _TRANSFER 0 | |
| 3918 | DOP16_DOP32 ("bclri", | |
| afdcafe8 | 3919 | OPCODE_INFO2 (0x3880, |
| b8891f8d | 3920 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| b8891f8d | 3921 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| afdcafe8 | 3922 | OPCODE_INFO3 (0x3880, |
| b8891f8d | 3923 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| afdcafe8 | 3924 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| b8891f8d AJ |
3925 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3926 | CSKYV2_ISA_E1, | |
| 3927 | OPCODE_INFO3 (0xc4002820, | |
| 3928 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3929 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3930 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3931 | OPCODE_INFO2 (0xc4002820, | |
| 3932 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3933 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3934 | CSKYV2_ISA_1E2), | |
| 3935 | DOP16_DOP32 ("bseti", | |
| afdcafe8 | 3936 | OPCODE_INFO2 (0x38a0, |
| b8891f8d | 3937 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| b8891f8d | 3938 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| afdcafe8 | 3939 | OPCODE_INFO3 (0x38a0, |
| b8891f8d | 3940 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| afdcafe8 | 3941 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| b8891f8d AJ |
3942 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3943 | CSKYV2_ISA_E1, | |
| 3944 | OPCODE_INFO3 (0xc4002840, | |
| 3945 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3946 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3947 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3948 | OPCODE_INFO2 (0xc4002840, | |
| 3949 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3950 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3951 | CSKYV2_ISA_1E2), | |
| 3952 | OP16_OP32_WITH_WORK ("btsti", | |
| 3953 | OPCODE_INFO2 (0x38c0, | |
| 3954 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3955 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3956 | CSKYV2_ISA_E1, | |
| 3957 | OPCODE_INFO2 (0xc4002880, | |
| 3958 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3959 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3960 | CSKYV2_ISA_1E2, v2_work_btsti), | |
| 3961 | DOP16_DOP32 ("lsli", | |
| 3962 | OPCODE_INFO3 (0x4000, | |
| 3963 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3964 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3965 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3966 | OPCODE_INFO2 (0x4000, | |
| 3967 | (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3968 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3969 | CSKYV2_ISA_E1, | |
| 3970 | OPCODE_INFO3 (0xc4004820, | |
| 3971 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3972 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3973 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3974 | OPCODE_INFO2 (0xc4004820, | |
| 3975 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3976 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3977 | CSKYV2_ISA_1E2), | |
| 3978 | DOP16_DOP32 ("lsri", | |
| 3979 | OPCODE_INFO3 (0x4800, | |
| 3980 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3981 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3982 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3983 | OPCODE_INFO2 (0x4800, | |
| 3984 | (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3985 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3986 | CSKYV2_ISA_E1, | |
| 3987 | OPCODE_INFO3 (0xc4004840, | |
| 3988 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 3989 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 3990 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3991 | OPCODE_INFO2 (0xc4004840, | |
| 3992 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 3993 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 3994 | CSKYV2_ISA_1E2), | |
| 3995 | OP16_OP32 ("asri", | |
| 3996 | OPCODE_INFO3 (0x5000, | |
| 3997 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3998 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 3999 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 4000 | CSKYV2_ISA_E1, | |
| 4001 | OPCODE_INFO3 (0xc4004880, | |
| 4002 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4003 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4004 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 4005 | CSKYV2_ISA_1E2), | |
| afdcafe8 CQ |
4006 | DOP16_DOP32_WITH_WORK ("addc", |
| 4007 | OPCODE_INFO2 (0x6001, | |
| 4008 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4009 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4010 | OPCODE_INFO3 (0x6001, | |
| 4011 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4012 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4013 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4014 | CSKYV2_ISA_E1, | |
| 4015 | OPCODE_INFO3 (0xc4000040, | |
| 4016 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4017 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4018 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4019 | OPCODE_INFO2 (0xc4000040, | |
| 4020 | (0_4or16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4021 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4022 | CSKYV2_ISA_1E2, | |
| 4023 | v2_work_addc), | |
| b8891f8d AJ |
4024 | DOP16_DOP32 ("subc", |
| 4025 | OPCODE_INFO2 (0x6003, | |
| 4026 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4027 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4028 | OPCODE_INFO3 (0x6003, | |
| 4029 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4030 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 4031 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4032 | CSKYV2_ISA_E1, | |
| 4033 | OPCODE_INFO3 (0xc4000100, | |
| 4034 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4035 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4036 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4037 | OPCODE_INFO2 (0xc4000100, | |
| 4038 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4039 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4040 | CSKYV2_ISA_1E2), | |
| 4041 | OP16_OP32 ("cmphs", | |
| 4042 | OPCODE_INFO2 (0x6400, | |
| 4043 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4044 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4045 | CSKYV2_ISA_E1, | |
| 4046 | OPCODE_INFO2 (0xc4000420, | |
| 4047 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4048 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4049 | CSKYV2_ISA_2E3), | |
| 4050 | OP16_OP32 ("cmplt", | |
| 4051 | OPCODE_INFO2 (0x6401, | |
| 4052 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4053 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4054 | CSKYV2_ISA_E1, | |
| 4055 | OPCODE_INFO2 (0xc4000440, | |
| 4056 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4057 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4058 | CSKYV2_ISA_2E3), | |
| 4059 | OP16_OP32 ("cmpne", | |
| 4060 | OPCODE_INFO2 (0x6402, | |
| 4061 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4062 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4063 | CSKYV2_ISA_E1, | |
| 4064 | OPCODE_INFO2 (0xc4000480, | |
| 4065 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4066 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4067 | CSKYV2_ISA_2E3), | |
| 4068 | OP16_OP32 ("mvcv", | |
| 4069 | OPCODE_INFO1 (0x6403, | |
| 4070 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4071 | CSKYV2_ISA_E1, | |
| 4072 | OPCODE_INFO1 (0xc4000600, | |
| 4073 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
| 4074 | CSKYV2_ISA_2E3), | |
| 4075 | DOP16_DOP32 ("and", | |
| 4076 | OPCODE_INFO2 (0x6800, | |
| 4077 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4078 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4079 | OPCODE_INFO3 (0x6800, | |
| 4080 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4081 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
| 4082 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
| 4083 | CSKYV2_ISA_E1, | |
| 4084 | OPCODE_INFO3 (0xc4002020, | |
| 4085 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4086 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4087 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4088 | OPCODE_INFO2 (0xc4002020, | |
| 4089 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4090 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4091 | CSKYV2_ISA_1E2), | |
| 4092 | DOP16_DOP32 ("andn", | |
| 4093 | OPCODE_INFO2 (0x6801, | |
| 4094 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4095 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4096 | OPCODE_INFO3 (0x6801, | |
| 4097 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4098 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 4099 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4100 | CSKYV2_ISA_E1, | |
| 4101 | OPCODE_INFO3 (0xc4002040, | |
| 4102 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4103 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4104 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4105 | OPCODE_INFO2 (0xc4002040, | |
| 4106 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4107 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4108 | CSKYV2_ISA_1E2), | |
| 4109 | OP16_OP32 ("tst", | |
| 4110 | OPCODE_INFO2 (0x6802, | |
| 4111 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4112 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4113 | CSKYV2_ISA_E1, | |
| 4114 | OPCODE_INFO2 (0xc4002080, | |
| 4115 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4116 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4117 | CSKYV2_ISA_2E3), | |
| 4118 | OP16_OP32 ("tstnbz", | |
| 4119 | OPCODE_INFO1 (0x6803, | |
| 4120 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4121 | CSKYV2_ISA_E1, | |
| 4122 | OPCODE_INFO1 (0xc4002100, | |
| 4123 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4124 | CSKYV2_ISA_2E3), | |
| 4125 | DOP16_DOP32 ("or", | |
| 4126 | OPCODE_INFO2 (0x6c00, | |
| 4127 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4128 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4129 | OPCODE_INFO3 (0x6c00, | |
| 4130 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4131 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
| 4132 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
| 4133 | CSKYV2_ISA_E1, | |
| 4134 | OPCODE_INFO3 (0xc4002420, | |
| 4135 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4136 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4137 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4138 | OPCODE_INFO2 (0xc4002420, | |
| 4139 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4140 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4141 | CSKYV2_ISA_1E2), | |
| 4142 | DOP16_DOP32 ("xor", | |
| 4143 | OPCODE_INFO2 (0x6c01, | |
| 4144 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4145 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4146 | OPCODE_INFO3 (0x6c01, | |
| 4147 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4148 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
| 4149 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
| 4150 | CSKYV2_ISA_E1, | |
| 4151 | OPCODE_INFO3 (0xc4002440, | |
| 4152 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4153 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4154 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4155 | OPCODE_INFO2 (0xc4002440, | |
| 4156 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4157 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4158 | CSKYV2_ISA_1E2), | |
| 4159 | DOP16_DOP32 ("nor", | |
| 4160 | OPCODE_INFO2 (0x6c02, | |
| 4161 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4162 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4163 | OPCODE_INFO3 (0x6c02, | |
| 4164 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4165 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
| 4166 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
| 4167 | CSKYV2_ISA_E1, | |
| 4168 | OPCODE_INFO3 (0xc4002480, | |
| 4169 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4170 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4171 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4172 | OPCODE_INFO2 (0xc4002480, | |
| 4173 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4174 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4175 | CSKYV2_ISA_1E2), | |
| 4176 | OP16_OP32 ("mov", | |
| 4177 | OPCODE_INFO2 (0x6c03, | |
| 4178 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4179 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4180 | CSKYV2_ISA_E1, | |
| 4181 | OPCODE_INFO2 (0xc4004820, | |
| 4182 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4183 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4184 | CSKYV2_ISA_1E2), | |
| 4185 | OP16_OP32 ("nop", | |
| 4186 | OPCODE_INFO0 (0x6c03), | |
| 4187 | CSKYV2_ISA_E1, | |
| 4188 | OPCODE_INFO0 (0xc4004820), | |
| 4189 | CSKYV2_ISA_E1), | |
| 4190 | DOP16_DOP32 ("lsl", | |
| 4191 | OPCODE_INFO2 (0x7000, | |
| 4192 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4193 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4194 | OPCODE_INFO3 (0x7000, | |
| 4195 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4196 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 4197 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4198 | CSKYV2_ISA_E1, | |
| 4199 | OPCODE_INFO3 (0xc4004020, | |
| 4200 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4201 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4202 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4203 | OPCODE_INFO2 (0xc4004020, | |
| 4204 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4205 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4206 | CSKYV2_ISA_1E2), | |
| 4207 | DOP16_DOP32 ("lsr", | |
| 4208 | OPCODE_INFO2 (0x7001, | |
| 4209 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4210 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4211 | OPCODE_INFO3 (0x7001, | |
| 4212 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4213 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 4214 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4215 | CSKYV2_ISA_E1, | |
| 4216 | OPCODE_INFO3 (0xc4004040, | |
| 4217 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4218 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4219 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4220 | OPCODE_INFO2 (0xc4004040, | |
| 4221 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4222 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4223 | CSKYV2_ISA_1E2), | |
| 4224 | DOP16_DOP32 ("asr", | |
| 4225 | OPCODE_INFO2 (0x7002, | |
| 4226 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4227 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4228 | OPCODE_INFO3 (0x7002, | |
| 4229 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4230 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 4231 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4232 | CSKYV2_ISA_E1, | |
| 4233 | OPCODE_INFO3 (0xc4004080, | |
| 4234 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4235 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4236 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4237 | OPCODE_INFO2 (0xc4004080, | |
| 4238 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4239 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4240 | CSKYV2_ISA_1E2), | |
| 4241 | DOP16_DOP32 ("rotl", | |
| 4242 | OPCODE_INFO2 (0x7003, | |
| 4243 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4244 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4245 | OPCODE_INFO3 (0x7003, | |
| 4246 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4247 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
| 4248 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4249 | CSKYV2_ISA_E1, | |
| 4250 | OPCODE_INFO3 (0xc4004100, | |
| 4251 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4252 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4253 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4254 | OPCODE_INFO2 (0xc4004100, | |
| 4255 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4256 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4257 | CSKYV2_ISA_1E2), | |
| 4258 | DOP16_DOP32 ("zextb", | |
| 4259 | OPCODE_INFO2 (0x7400, | |
| 4260 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4261 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4262 | OPCODE_INFO1 (0x7400, | |
| 4263 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4264 | CSKYV2_ISA_E1, | |
| 4265 | OPCODE_INFO2 (0xc40054e0, | |
| 4266 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4267 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4268 | OPCODE_INFO1 (0xc40054e0, | |
| 4269 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 4270 | CSKYV2_ISA_2E3), | |
| 4271 | DOP16_DOP32 ("zexth", | |
| 4272 | OPCODE_INFO2 (0x7401, | |
| 4273 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4274 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4275 | OPCODE_INFO1 (0x7401, | |
| 4276 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4277 | CSKYV2_ISA_E1, | |
| 4278 | OPCODE_INFO2 (0xc40055e0, | |
| 4279 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4280 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4281 | OPCODE_INFO1 (0xc40055e0, | |
| 4282 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 4283 | CSKYV2_ISA_2E3), | |
| 4284 | DOP16_DOP32 ("sextb", | |
| 4285 | OPCODE_INFO2 (0x7402, | |
| 4286 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4287 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4288 | OPCODE_INFO1 (0x7402, | |
| 4289 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4290 | CSKYV2_ISA_E1, | |
| 4291 | OPCODE_INFO2 (0xc40058e0, | |
| 4292 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4293 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4294 | OPCODE_INFO1 (0xc40058e0, | |
| 4295 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 4296 | CSKYV2_ISA_2E3), | |
| 4297 | DOP16_DOP32 ("sexth", | |
| 4298 | OPCODE_INFO2 (0x7403, | |
| 4299 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4300 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4301 | OPCODE_INFO1 (0x7403, | |
| 4302 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4303 | CSKYV2_ISA_E1, | |
| 4304 | OPCODE_INFO2 (0xc40059e0, | |
| 4305 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4306 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4307 | OPCODE_INFO1 (0xc40059e0, | |
| 4308 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 4309 | CSKYV2_ISA_2E3), | |
| 4310 | OP32 ("zext", | |
| 4311 | OPCODE_INFO4 (0xc4005400, | |
| 4312 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4313 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4314 | (5_9, IMM5b, OPRND_SHIFT_0_BIT), | |
| afdcafe8 | 4315 | (21_25, IMM5b_LS, OPRND_SHIFT_0_BIT)), |
| b8891f8d AJ |
4316 | CSKYV2_ISA_2E3), |
| 4317 | OP32 ("sext", | |
| 4318 | OPCODE_INFO4 (0xc4005800, | |
| 4319 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4320 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4321 | (5_9, IMM5b, OPRND_SHIFT_0_BIT), | |
| afdcafe8 | 4322 | (21_25, IMM5b_LS, OPRND_SHIFT_0_BIT)), |
| b8891f8d AJ |
4323 | CSKYV2_ISA_2E3), |
| 4324 | #undef _TRANSFER | |
| 4325 | #define _TRANSFER 2 | |
| 4326 | OP16_OP32 ("rts", | |
| 4327 | OPCODE_INFO0 (0x783c), | |
| 4328 | CSKYV2_ISA_E1, | |
| 4329 | OPCODE_INFO0 (0xe8cf0000), | |
| 4330 | CSKYV2_ISA_E1), | |
| 4331 | #undef _TRANSFER | |
| 4332 | #define _TRANSFER 1 | |
| 4333 | OP16_OP32 ("jmp", | |
| 4334 | OPCODE_INFO1 (0x7800, | |
| 4335 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4336 | CSKYV2_ISA_E1, | |
| 4337 | OPCODE_INFO1 (0xe8c00000, | |
| 4338 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4339 | CSKYV2_ISA_2E3), | |
| 4340 | #undef _TRANSFER | |
| 4341 | #define _TRANSFER 0 | |
| 4342 | OP16_OP32 ("revb", | |
| 4343 | OPCODE_INFO2 (0x7802, | |
| 4344 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4345 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4346 | CSKYV2_ISA_1E2, | |
| 4347 | OPCODE_INFO2 (0xc4006080, | |
| 4348 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4349 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4350 | CSKYV2_ISA_2E3), | |
| 4351 | OP16_OP32 ("revh", | |
| 4352 | OPCODE_INFO2 (0x7803, | |
| 4353 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4354 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4355 | CSKYV2_ISA_1E2, | |
| 4356 | OPCODE_INFO2 (0xc4006100, | |
| 4357 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4358 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4359 | CSKYV2_ISA_2E3), | |
| 4360 | OP16_OP32 ("jsr", | |
| 4361 | OPCODE_INFO1 (0x7bc1, | |
| 4362 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4363 | CSKYV2_ISA_E1, | |
| 4364 | OPCODE_INFO1 (0xe8e00000, | |
| 4365 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 4366 | CSKYV2_ISA_2E3), | |
| 4367 | DOP16_DOP32 ("mult", | |
| 4368 | OPCODE_INFO2 (0x7c00, | |
| 4369 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4370 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4371 | OPCODE_INFO3 (0x7c00, | |
| 4372 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4373 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
| 4374 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
| 4375 | CSKYV2_ISA_E1, | |
| 4376 | OPCODE_INFO3 (0xc4008420, | |
| 4377 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4378 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4379 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4380 | OPCODE_INFO2 (0xc4008420, | |
| 4381 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4382 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4383 | CSKYV2_ISA_1E2), | |
| 4384 | OP16 ("mul", | |
| 4385 | OPCODE_INFO2 (0x7c00, | |
| 4386 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4387 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4388 | CSKYV2_ISA_E1), | |
| 4389 | DOP16_DOP32 ("mulsh", | |
| 4390 | OPCODE_INFO2 (0x7c01, | |
| 4391 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4392 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4393 | OPCODE_INFO3 (0x7c01, | |
| 4394 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4395 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
| 4396 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
| 4397 | CSKYV2_ISA_2E3, | |
| 4398 | OPCODE_INFO3 (0xc4009020, | |
| 4399 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4400 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4401 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4402 | OPCODE_INFO2 (0xc4009020, | |
| 4403 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4404 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4405 | CSKYV2_ISA_2E3), | |
| 4406 | OP16 ("muls.h", | |
| 4407 | OPCODE_INFO2 (0x7c01, | |
| 4408 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4409 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4410 | CSKYV2_ISA_2E3), | |
| 4411 | DOP32 ("mulsw", | |
| 4412 | OPCODE_INFO3 (0xc4009420, | |
| 4413 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4414 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4415 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4416 | OPCODE_INFO2 (0xc4009420, | |
| 4417 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4418 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6a1ed910 | 4419 | CSKY_ISA_DSPE60), |
| b8891f8d AJ |
4420 | OP16_OP32 ("ld.b", |
| 4421 | SOPCODE_INFO2 (0x8000, | |
| 4422 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4423 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4424 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4425 | CSKYV2_ISA_E1, | |
| 4426 | SOPCODE_INFO2 (0xd8000000, | |
| 4427 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4428 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4429 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4430 | CSKYV2_ISA_E1), | |
| 4431 | OP16_OP32 ("ldb", | |
| 4432 | SOPCODE_INFO2 (0x8000, | |
| 4433 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4434 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4435 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4436 | CSKYV2_ISA_E1, | |
| 4437 | SOPCODE_INFO2 (0xd8000000, | |
| 4438 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4439 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4440 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4441 | CSKYV2_ISA_E1), | |
| 4442 | OP16_OP32 ("st.b", | |
| 4443 | SOPCODE_INFO2 (0xa000, | |
| 4444 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4445 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4446 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4447 | CSKYV2_ISA_E1, | |
| 4448 | SOPCODE_INFO2 (0xdc000000, | |
| 4449 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4450 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4451 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4452 | CSKYV2_ISA_E1), | |
| 4453 | OP16_OP32 ("stb", | |
| 4454 | SOPCODE_INFO2 (0xa000, | |
| 4455 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4456 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4457 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4458 | CSKYV2_ISA_E1, | |
| 4459 | SOPCODE_INFO2 (0xdc000000, | |
| 4460 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4461 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4462 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4463 | CSKYV2_ISA_E1), | |
| 4464 | ||
| 4465 | OP16_OP32 ("ld.h", | |
| 4466 | SOPCODE_INFO2 (0x8800, | |
| 4467 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4468 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4469 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 4470 | CSKYV2_ISA_E1, | |
| 4471 | SOPCODE_INFO2 (0xd8001000, | |
| 4472 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4473 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4474 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 4475 | CSKYV2_ISA_E1), | |
| 4476 | OP16_OP32 ("ldh", | |
| 4477 | SOPCODE_INFO2 (0x8800, | |
| 4478 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4479 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4480 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 4481 | CSKYV2_ISA_E1, | |
| 4482 | SOPCODE_INFO2 (0xd8001000, | |
| 4483 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4484 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4485 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 4486 | CSKYV2_ISA_E1), | |
| 4487 | OP16_OP32 ("st.h", | |
| 4488 | SOPCODE_INFO2 (0xa800, | |
| 4489 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4490 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4491 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 4492 | CSKYV2_ISA_E1, | |
| 4493 | SOPCODE_INFO2 (0xdc001000, | |
| 4494 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4495 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4496 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 4497 | CSKYV2_ISA_E1), | |
| 4498 | OP16_OP32 ("sth", | |
| 4499 | SOPCODE_INFO2 (0xa800, | |
| 4500 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4501 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4502 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 4503 | CSKYV2_ISA_E1, | |
| 4504 | SOPCODE_INFO2 (0xdc001000, | |
| 4505 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4506 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4507 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
| 4508 | CSKYV2_ISA_E1), | |
| 4509 | DOP16_OP32 ("ld.w", | |
| 4510 | SOPCODE_INFO2 (0x9000, | |
| 4511 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4512 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4513 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4514 | SOPCODE_INFO2 (0x9800, | |
| 4515 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4516 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4517 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4518 | CSKYV2_ISA_E1, | |
| 4519 | SOPCODE_INFO2 (0xd8002000, | |
| 4520 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4521 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4522 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4523 | CSKYV2_ISA_E1), | |
| 4524 | DOP16_OP32 ("ldw", | |
| 4525 | SOPCODE_INFO2 (0x9000, | |
| 4526 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4527 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4528 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4529 | SOPCODE_INFO2 (0x9800, | |
| 4530 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4531 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4532 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4533 | CSKYV2_ISA_E1, | |
| 4534 | SOPCODE_INFO2 (0xd8002000, | |
| 4535 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4536 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4537 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4538 | CSKYV2_ISA_E1), | |
| 4539 | DOP16_OP32 ("ld", | |
| 4540 | SOPCODE_INFO2 (0x9000, | |
| 4541 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4542 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4543 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
| 4544 | SOPCODE_INFO2 (0x9800, | |
| 4545 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4546 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4547 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4548 | CSKYV2_ISA_E1, | |
| 4549 | SOPCODE_INFO2 (0xd8002000, | |
| 4550 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4551 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4552 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4553 | CSKYV2_ISA_E1), | |
| 4554 | DOP16_OP32 ("st.w", | |
| 4555 | SOPCODE_INFO2 (0xb000, | |
| 4556 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4557 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4558 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4559 | SOPCODE_INFO2 (0xb800, | |
| 4560 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4561 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4562 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4563 | CSKYV2_ISA_E1, | |
| 4564 | SOPCODE_INFO2 (0xdc002000, | |
| 4565 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4566 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4567 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4568 | CSKYV2_ISA_E1), | |
| 4569 | DOP16_OP32 ("stw", | |
| 4570 | SOPCODE_INFO2 (0xb000, | |
| 4571 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4572 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4573 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4574 | SOPCODE_INFO2 (0xb800, | |
| 4575 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4576 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4577 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4578 | CSKYV2_ISA_E1, | |
| 4579 | SOPCODE_INFO2 (0xdc002000, | |
| 4580 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4581 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4582 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4583 | CSKYV2_ISA_E1), | |
| 4584 | DOP16_OP32 ("st", | |
| 4585 | SOPCODE_INFO2 (0xb000, | |
| 4586 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4587 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4588 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4589 | SOPCODE_INFO2 (0xb800, | |
| 4590 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4591 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4592 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4593 | CSKYV2_ISA_E1, | |
| 4594 | SOPCODE_INFO2 (0xdc002000, | |
| 4595 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4596 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4597 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
| 4598 | CSKYV2_ISA_E1), | |
| 4599 | #ifdef BUILD_AS | |
| 4600 | DOP16_DOP32_WITH_WORK ("addi", | |
| 4601 | OPCODE_INFO2 (0x2000, | |
| 4602 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4603 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
| 4604 | OPCODE_INFO3 (0x2000, | |
| 4605 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4606 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4607 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
| 4608 | CSKYV2_ISA_E1, | |
| 4609 | OPCODE_INFO2 (0xe4000000, | |
| 4610 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4611 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
| 4612 | OPCODE_INFO3 (0xe4000000, | |
| 4613 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4614 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4615 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
| 4616 | CSKYV2_ISA_1E2, | |
| 4617 | v2_work_addi), | |
| 4618 | #else | |
| 4619 | DOP16 ("addi", | |
| 4620 | OPCODE_INFO2 (0x2000, | |
| 4621 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4622 | (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), | |
| 4623 | OPCODE_INFO3 (0x5802, | |
| 4624 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4625 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4626 | (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), | |
| 4627 | CSKYV2_ISA_E1), | |
| 4628 | DOP16 ("addi", | |
| 4629 | OPCODE_INFO3 (0x1800, | |
| 4630 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4631 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4632 | (0_7, IMM8b_LS2, OPRND_SHIFT_0_BIT)), | |
| 4633 | OPCODE_INFO3 (0x1400, | |
| 4634 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4635 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4636 | (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), | |
| 4637 | CSKYV2_ISA_E1), | |
| 4638 | DOP32 ("addi", | |
| 4639 | OPCODE_INFO3 (0xe4000000, | |
| 4640 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4641 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4642 | (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), | |
| 4643 | OPCODE_INFO3 (0xcc1c0000, | |
| 4644 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4645 | (NONE, REG_r28, OPRND_SHIFT_0_BIT), | |
| 4646 | (0_17, OIMM18b, OPRND_SHIFT_0_BIT)), | |
| 4647 | CSKYV2_ISA_1E2), | |
| 4648 | #endif | |
| 4649 | #ifdef BUILD_AS | |
| 4650 | DOP16_DOP32_WITH_WORK ("subi", | |
| 4651 | OPCODE_INFO2 (0x2800, | |
| 4652 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4653 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
| 4654 | OPCODE_INFO3 (0x2800, | |
| 4655 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4656 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4657 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
| 4658 | CSKYV2_ISA_E1, | |
| 4659 | OPCODE_INFO2 (0xe4001000, | |
| 4660 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4661 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
| 4662 | OPCODE_INFO3 (0xe4001000, | |
| 4663 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4664 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 4665 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
| 4666 | CSKYV2_ISA_1E2, v2_work_subi), | |
| 4667 | #else | |
| 4668 | DOP16 ("subi", | |
| 4669 | OPCODE_INFO2 (0x2800, | |
| 4670 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4671 | (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), | |
| 4672 | OPCODE_INFO3 (0x5803, | |
| 4673 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4674 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4675 | (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), | |
| 4676 | CSKYV2_ISA_E1), | |
| 4677 | OP32 ("subi", | |
| 4678 | OPCODE_INFO3 (0xe4001000, | |
| 4679 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4680 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4681 | (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), | |
| 4682 | CSKYV2_ISA_1E2), | |
| 4683 | OP16 ("subi", | |
| 4684 | OPCODE_INFO3 (0x1420, | |
| 4685 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4686 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
| 4687 | (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), | |
| 4688 | CSKYV2_ISA_E1), | |
| 4689 | #endif | |
| 4690 | DOP16_DOP32_WITH_WORK ("addu", | |
| 4691 | OPCODE_INFO2 (0x6000, | |
| 4692 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4693 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4694 | OPCODE_INFO3 (0x5800, | |
| 4695 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4696 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4697 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 4698 | CSKYV2_ISA_E1, | |
| 4699 | OPCODE_INFO3 (0xc4000020, | |
| 4700 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4701 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4702 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4703 | OPCODE_INFO2 (0xc4000020, | |
| 4704 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4705 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4706 | CSKYV2_ISA_E1, | |
| 4707 | v2_work_add_sub), | |
| 4708 | DOP16_DOP32_WITH_WORK ("add", | |
| 4709 | OPCODE_INFO2 (0x6000, | |
| 4710 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4711 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4712 | OPCODE_INFO3 (0x5800, | |
| 4713 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4714 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4715 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 4716 | CSKYV2_ISA_E1, | |
| 4717 | OPCODE_INFO3 (0xc4000020, | |
| 4718 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4719 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4720 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4721 | OPCODE_INFO2 (0xc4000020, | |
| 4722 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4723 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4724 | CSKYV2_ISA_E1, | |
| 4725 | v2_work_add_sub), | |
| 4726 | DOP16_DOP32_WITH_WORK ("subu", | |
| 4727 | OPCODE_INFO2 (0x6002, | |
| 4728 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4729 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4730 | OPCODE_INFO3 (0x5801, | |
| 4731 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4732 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4733 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 4734 | CSKYV2_ISA_E1, | |
| 4735 | OPCODE_INFO3 (0xc4000080, | |
| 4736 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4737 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4738 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4739 | OPCODE_INFO2 (0xc4000080, | |
| 4740 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4741 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4742 | CSKYV2_ISA_E1, | |
| 4743 | v2_work_add_sub), | |
| 4744 | DOP16_DOP32_WITH_WORK ("sub", | |
| 4745 | OPCODE_INFO2 (0x6002, | |
| 4746 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 4747 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 4748 | OPCODE_INFO3 (0x5801, | |
| 4749 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4750 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4751 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 4752 | CSKYV2_ISA_E1, | |
| 4753 | OPCODE_INFO3 (0xc4000080, | |
| 4754 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 4755 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4756 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4757 | OPCODE_INFO2 (0xc4000080, | |
| 4758 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 4759 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4760 | CSKYV2_ISA_E1, | |
| 4761 | v2_work_add_sub), | |
| 4762 | OP32_WITH_WORK ("fmovis", | |
| 4763 | OPCODE_INFO2 (0xf4001c00, | |
| 4764 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 4765 | (4_7or16_24, SFLOAT, OPRND_SHIFT_2_BIT)), | |
| 4766 | CSKY_ISA_FLOAT_1E3, | |
| 4767 | float_work_fmovi), | |
| 4768 | OP32_WITH_WORK ("fmovid", | |
| 4769 | OPCODE_INFO2 (0xf4001e00, | |
| 4770 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 4771 | (4_7or16_24, DFLOAT, OPRND_SHIFT_2_BIT)), | |
| 4772 | CSKY_ISA_FLOAT_3E4, | |
| 4773 | float_work_fmovi), | |
| 4774 | #undef _RELOC32 | |
| 4775 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM26BY2 | |
| 4776 | OP32 ("bsr", | |
| 4777 | OPCODE_INFO1 (0xe0000000, | |
| 4778 | (0_25, OFF26b, OPRND_SHIFT_1_BIT)), | |
| 4779 | CSKYV2_ISA_E1), | |
| 4780 | #undef _RELOC32 | |
| 4781 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18 | |
| 4782 | OP32 ("lrs.b", | |
| 4783 | OPCODE_INFO2 (0xcc000000, | |
| 4784 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4785 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 4786 | CSKYV2_ISA_2E3), | |
| 4787 | OP32 ("srs.b", | |
| 4788 | OPCODE_INFO2 (0xcc100000, | |
| 4789 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4790 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 4791 | CSKYV2_ISA_2E3), | |
| 4792 | #undef _RELOC32 | |
| 4793 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 | |
| 4794 | OP32 ("lrs.h", | |
| 4795 | OPCODE_INFO2 (0xcc040000, | |
| 4796 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4797 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 4798 | CSKYV2_ISA_2E3), | |
| 4799 | OP32 ("srs.h", | |
| 4800 | OPCODE_INFO2 (0xcc140000, | |
| 4801 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4802 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 4803 | CSKYV2_ISA_2E3), | |
| 4804 | #undef _RELOC32 | |
| 4805 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 | |
| 4806 | OP32 ("flrws", | |
| 4807 | OPCODE_INFO2 (0xf4003800, | |
| 4808 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 4809 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
| 4810 | CSKY_ISA_FLOAT_1E3), | |
| 4811 | OP32 ("flrwd", | |
| 4812 | OPCODE_INFO2 (0xf4003900, | |
| 4813 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 4814 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
| 4815 | CSKY_ISA_FLOAT_3E4), | |
| 4816 | #undef _RELOC32 | |
| 4817 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 | |
| 4818 | OP32_WITH_WORK ("lrs.w", | |
| 4819 | OPCODE_INFO2 (0xcc080000, | |
| 4820 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4821 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 4822 | CSKYV2_ISA_2E3, | |
| 4823 | v2_work_lrsrsw), | |
| 4824 | OP32_WITH_WORK ("srs.w", | |
| 4825 | OPCODE_INFO2 (0xcc180000, | |
| 4826 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4827 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 4828 | CSKYV2_ISA_2E3, | |
| 4829 | v2_work_lrsrsw), | |
| 4830 | ||
| 4831 | #undef _RELOC32 | |
| 4832 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 | |
| 4833 | OP32_WITH_WORK ("jsri", | |
| 4834 | OPCODE_INFO1 (0xeae00000, | |
| 4835 | (0_15, OFF16b, OPRND_SHIFT_2_BIT)), | |
| 4836 | CSKYV2_ISA_2E3, | |
| 4837 | v2_work_jsri), | |
| 4838 | #undef _RELOC32 | |
| 4839 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY2 | |
| 4840 | OP32 ("bez", | |
| 4841 | OPCODE_INFO2 (0xe9000000, | |
| 4842 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4843 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
| 4844 | CSKYV2_ISA_2E3), | |
| 4845 | OP32 ("bnez", | |
| 4846 | OPCODE_INFO2 (0xe9200000, | |
| 4847 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4848 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
| 4849 | CSKYV2_ISA_2E3), | |
| 4850 | OP32 ("bhz", | |
| 4851 | OPCODE_INFO2 (0xe9400000, | |
| 4852 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4853 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
| 4854 | CSKYV2_ISA_2E3), | |
| 4855 | OP32 ("blsz", | |
| 4856 | OPCODE_INFO2 (0xe9600000, | |
| 4857 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4858 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
| 4859 | CSKYV2_ISA_2E3), | |
| 4860 | OP32 ("blz", | |
| 4861 | OPCODE_INFO2 (0xe9800000, | |
| 4862 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4863 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
| 4864 | CSKYV2_ISA_2E3), | |
| 4865 | OP32 ("bhsz", | |
| 4866 | OPCODE_INFO2 (0xe9a00000, | |
| 4867 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4868 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
| 4869 | CSKYV2_ISA_2E3), | |
| 4870 | #undef _RELAX | |
| 4871 | #undef _RELOC16 | |
| 4872 | #undef _TRANSFER | |
| 4873 | #define _TRANSFER 1 | |
| 4874 | #define _RELAX 1 | |
| 4875 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM10BY2 | |
| 4876 | OP16_OP32 ("br", | |
| 4877 | OPCODE_INFO1 (0x0400, | |
| 4878 | (0_9, UNCOND10b, OPRND_SHIFT_1_BIT)), | |
| 4879 | CSKYV2_ISA_E1, | |
| 4880 | OPCODE_INFO1 (0xe8000000, | |
| 4881 | (0_15, UNCOND16b, OPRND_SHIFT_1_BIT)), | |
| 4882 | CSKYV2_ISA_E1), | |
| 4883 | #undef _TRANSFER | |
| 4884 | #define _TRANSFER 0 | |
| 4885 | OP16_OP32 ("bt", | |
| 4886 | OPCODE_INFO1 (0x0800, | |
| 4887 | (0_9, COND10b, OPRND_SHIFT_1_BIT)), | |
| 4888 | CSKYV2_ISA_E1, | |
| 4889 | OPCODE_INFO1 (0xe8600000, | |
| 4890 | (0_15, COND16b, OPRND_SHIFT_1_BIT)), | |
| 4891 | CSKYV2_ISA_1E2), | |
| 4892 | OP16_OP32 ("bf", | |
| 4893 | OPCODE_INFO1 (0x0c00, | |
| 4894 | (0_9, COND10b, OPRND_SHIFT_1_BIT)), | |
| 4895 | CSKYV2_ISA_E1, | |
| 4896 | OPCODE_INFO1 (0xe8400000, | |
| 4897 | (0_15, COND16b, OPRND_SHIFT_1_BIT)), | |
| 4898 | CSKYV2_ISA_1E2), | |
| d04aee0f CQ |
4899 | #undef _RELAX |
| 4900 | #undef _RELOC16 | |
| 4901 | #define _RELAX 0 | |
| 4902 | #define _RELOC16 0 | |
| 4903 | OP32 ("bnezad", | |
| 4904 | OPCODE_INFO2 (0xe8200000, | |
| 4905 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4906 | (0_15, COND16b, OPRND_SHIFT_1_BIT)), | |
| 4907 | CSKYV2_ISA_3E3R2), | |
| b8891f8d AJ |
4908 | #undef _RELOC16 |
| 4909 | #undef _RELOC32 | |
| b8891f8d AJ |
4910 | #define _RELOC16 0 |
| 4911 | #define _RELOC32 0 | |
| b8891f8d AJ |
4912 | #undef _TRANSFER |
| 4913 | #define _TRANSFER 1 | |
| 4914 | OP16_WITH_WORK ("jbr", | |
| 4915 | OPCODE_INFO1 (0x0400, | |
| 4916 | (0_10, UNCOND10b, OPRND_SHIFT_1_BIT)), | |
| 4917 | CSKYV2_ISA_E1, | |
| 4918 | v2_work_jbr), | |
| 4919 | #undef _TRANSFER | |
| 4920 | #define _TRANSFER 0 | |
| 4921 | OP16_WITH_WORK ("jbt", | |
| 4922 | OPCODE_INFO1 (0x0800, | |
| 4923 | (0_10, COND10b, OPRND_SHIFT_1_BIT)), | |
| 4924 | CSKYV2_ISA_E1, | |
| 4925 | v2_work_jbtf), | |
| 4926 | OP16_WITH_WORK ("jbf", | |
| 4927 | OPCODE_INFO1 (0x0c00, | |
| 4928 | (0_10, COND10b, OPRND_SHIFT_1_BIT)), | |
| 4929 | CSKYV2_ISA_E1, | |
| 4930 | v2_work_jbtf), | |
| 4931 | OP32_WITH_WORK ("jbsr", | |
| 4932 | OPCODE_INFO1 (0xe0000000, | |
| 4933 | (0_25, OFF26b, OPRND_SHIFT_1_BIT)), | |
| 4934 | CSKYV2_ISA_E1, | |
| 4935 | v2_work_jbsr), | |
| 4936 | OP32_WITH_WORK ("movih", | |
| 4937 | OPCODE_INFO2 (0xea200000, | |
| 4938 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4939 | (0_15, IMM16b_MOVIH, OPRND_SHIFT_0_BIT)), | |
| 4940 | CSKYV2_ISA_1E2, | |
| 4941 | v2_work_movih), | |
| 4942 | OP32_WITH_WORK ("ori", | |
| 4943 | OPCODE_INFO3 (0xec000000, | |
| 4944 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 4945 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4946 | (0_15, IMM16b_ORI, OPRND_SHIFT_0_BIT)), | |
| 4947 | CSKYV2_ISA_1E2, | |
| 4948 | v2_work_ori), | |
| 4949 | DOP32_WITH_WORK ("bgeni", | |
| 4950 | OPCODE_INFO2 (0xea000000, | |
| 4951 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4952 | (0_4, IMM4b, OPRND_SHIFT_0_BIT)), | |
| 4953 | OPCODE_INFO2 (0xea200000, | |
| 4954 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4955 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 4956 | CSKYV2_ISA_E1, | |
| 4957 | v2_work_bgeni), | |
| 4958 | #undef _RELOC16 | |
| 4959 | #undef _RELOC32 | |
| 4960 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM7BY4 | |
| 4961 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 | |
| 4962 | DOP16_OP32_WITH_WORK ("lrw", | |
| 4963 | OPCODE_INFO2 (0x1000, | |
| 4964 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4965 | (0_4or8_9, CONSTANT, OPRND_SHIFT_2_BIT)), | |
| 4966 | OPCODE_INFO2 (0x0000, | |
| 4967 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 4968 | (0_4or8_9, ELRW_CONSTANT, OPRND_SHIFT_2_BIT)), | |
| 4969 | CSKYV2_ISA_E1, | |
| 4970 | OPCODE_INFO2 (0xea800000, | |
| 4971 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4972 | (0_15, CONSTANT, OPRND_SHIFT_2_BIT)), | |
| 4973 | CSKYV2_ISA_E1, | |
| 4974 | v2_work_lrw), | |
| 4975 | #undef _RELOC16 | |
| 4976 | #undef _RELOC32 | |
| 4977 | #define _RELOC16 0 | |
| 4978 | #define _RELOC32 0 | |
| 4979 | ||
| 4980 | #undef _RELAX | |
| 4981 | #define _RELAX 1 | |
| 4982 | OP32 ("jbez", | |
| 4983 | OPCODE_INFO2 (0xe9000000, | |
| 4984 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4985 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
| 4986 | CSKYV2_ISA_2E3), | |
| 4987 | OP32 ("jbnez", | |
| 4988 | OPCODE_INFO2 (0xe9200000, | |
| 4989 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4990 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
| 4991 | CSKYV2_ISA_2E3), | |
| 4992 | OP32 ("jbhz", | |
| 4993 | OPCODE_INFO2 (0xe9400000, | |
| 4994 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 4995 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
| 4996 | CSKYV2_ISA_2E3), | |
| 4997 | OP32 ("jblsz", | |
| 4998 | OPCODE_INFO2 (0xe9600000, | |
| 4999 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5000 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
| 5001 | CSKYV2_ISA_2E3), | |
| 5002 | OP32 ("jblz", | |
| 5003 | OPCODE_INFO2 (0xe9800000, | |
| 5004 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5005 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
| 5006 | CSKYV2_ISA_2E3), | |
| 5007 | OP32 ("jbhsz", | |
| 5008 | OPCODE_INFO2 (0xe9a00000, | |
| 5009 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5010 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
| 5011 | CSKYV2_ISA_2E3), | |
| 5012 | #undef _RELAX | |
| 5013 | #define _RELAX 0 | |
| 5014 | ||
| 531c73a3 | 5015 | /* CK860 instructions. */ |
| 79c8d443 CQ |
5016 | OP32 ("sync.is", |
| 5017 | OPCODE_INFO0 (0xc2200420), | |
| 5018 | CSKYV2_ISA_10E60), | |
| 5019 | OP32 ("sync.i", | |
| 5020 | OPCODE_INFO0 (0xc0200420), | |
| 5021 | CSKYV2_ISA_10E60), | |
| 5022 | OP32 ("sync.s", | |
| 5023 | OPCODE_INFO0 (0xc2000420), | |
| 5024 | CSKYV2_ISA_10E60), | |
| 5025 | OP32 ("bar.brwarw", | |
| 5026 | OPCODE_INFO0 (0xc000842f), | |
| 5027 | CSKYV2_ISA_10E60), | |
| 5028 | OP32 ("bar.brwarws", | |
| 5029 | OPCODE_INFO0 (0xc200842f), | |
| 5030 | CSKYV2_ISA_10E60), | |
| 5031 | OP32 ("bar.brar", | |
| 5032 | OPCODE_INFO0 (0xc0008425), | |
| 5033 | CSKYV2_ISA_10E60), | |
| 5034 | OP32 ("bar.brars", | |
| 5035 | OPCODE_INFO0 (0xc2008425), | |
| 5036 | CSKYV2_ISA_10E60), | |
| 5037 | OP32 ("bar.bwaw", | |
| 5038 | OPCODE_INFO0 (0xc000842a), | |
| 5039 | CSKYV2_ISA_10E60), | |
| 5040 | OP32 ("bar.bwaws", | |
| 5041 | OPCODE_INFO0 (0xc200842a), | |
| 5042 | CSKYV2_ISA_10E60), | |
| 5043 | OP32 ("icache.iall", | |
| 5044 | OPCODE_INFO0 (0xc1009020), | |
| 5045 | CSKYV2_ISA_10E60), | |
| 5046 | OP32 ("icache.ialls", | |
| 5047 | OPCODE_INFO0 (0xc3009020), | |
| 5048 | CSKYV2_ISA_10E60), | |
| 5049 | OP32 ("l2cache.iall", | |
| 5050 | OPCODE_INFO0 (0xc1009820), | |
| 5051 | CSKYV2_ISA_10E60), | |
| 5052 | OP32 ("l2cache.call", | |
| 5053 | OPCODE_INFO0 (0xc0809820), | |
| 5054 | CSKYV2_ISA_10E60), | |
| 5055 | OP32 ("l2cache.ciall", | |
| 5056 | OPCODE_INFO0 (0xc1809820), | |
| 5057 | CSKYV2_ISA_10E60), | |
| 5058 | OP32 ("icache.iva", | |
| 5059 | OPCODE_INFO1 (0xc1609020, | |
| 5060 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5061 | CSKYV2_ISA_10E60), | |
| 5062 | OP32 ("dcache.iall", | |
| 5063 | OPCODE_INFO0 (0xc1009420), | |
| 5064 | CSKYV2_ISA_10E60), | |
| 5065 | OP32 ("dcache.iva", | |
| 5066 | OPCODE_INFO1 (0xc1609420, | |
| 5067 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5068 | CSKYV2_ISA_10E60), | |
| 5069 | OP32 ("dcache.isw", | |
| 5070 | OPCODE_INFO1 (0xc1409420, | |
| 5071 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5072 | CSKYV2_ISA_10E60), | |
| 5073 | OP32 ("dcache.call", | |
| 5074 | OPCODE_INFO0 (0xc0809420), | |
| 5075 | CSKYV2_ISA_10E60), | |
| 5076 | OP32 ("dcache.cva", | |
| 5077 | OPCODE_INFO1 (0xc0e09420, | |
| 5078 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5079 | CSKYV2_ISA_10E60), | |
| 5080 | OP32 ("dcache.cval1", | |
| 5081 | OPCODE_INFO1 (0xc2e09420, | |
| 5082 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5083 | CSKYV2_ISA_10E60), | |
| 5084 | OP32 ("dcache.csw", | |
| 5085 | OPCODE_INFO1 (0xc0c09420, | |
| 5086 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5087 | CSKYV2_ISA_10E60), | |
| 5088 | OP32 ("dcache.ciall", | |
| 5089 | OPCODE_INFO0 (0xc1809420), | |
| 5090 | CSKYV2_ISA_10E60), | |
| 5091 | OP32 ("dcache.civa", | |
| 5092 | OPCODE_INFO1 (0xc1e09420, | |
| 5093 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5094 | CSKYV2_ISA_10E60), | |
| 5095 | OP32 ("dcache.cisw", | |
| 5096 | OPCODE_INFO1 (0xc1c09420, | |
| 5097 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5098 | CSKYV2_ISA_10E60), | |
| 5099 | OP32 ("tlbi.vaa", | |
| 5100 | OPCODE_INFO1 (0xc0408820, | |
| 5101 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5102 | CSKYV2_ISA_10E60), | |
| 5103 | OP32 ("tlbi.vaas", | |
| 5104 | OPCODE_INFO1 (0xc2408820, | |
| 5105 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5106 | CSKYV2_ISA_10E60), | |
| 5107 | OP32 ("tlbi.asid", | |
| 5108 | OPCODE_INFO1 (0xc0208820, | |
| 5109 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5110 | CSKYV2_ISA_10E60), | |
| 5111 | OP32 ("tlbi.asids", | |
| 5112 | OPCODE_INFO1 (0xc2208820, | |
| 5113 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5114 | CSKYV2_ISA_10E60), | |
| 5115 | OP32 ("tlbi.va", | |
| 5116 | OPCODE_INFO1 (0xc0608820, | |
| 5117 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5118 | CSKYV2_ISA_10E60), | |
| 5119 | OP32 ("tlbi.vas", | |
| 5120 | OPCODE_INFO1 (0xc2608820, | |
| 5121 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5122 | CSKYV2_ISA_10E60), | |
| 5123 | OP32 ("tlbi.all", | |
| 5124 | OPCODE_INFO0 (0xc0008820), | |
| 5125 | CSKYV2_ISA_10E60), | |
| 5126 | OP32 ("tlbi.alls", | |
| 5127 | OPCODE_INFO0 (0xc2008820), | |
| 5128 | CSKYV2_ISA_10E60), | |
| 5129 | DOP32 ("sync", | |
| 5130 | OPCODE_INFO0 (0xc0000420), | |
| 5131 | OPCODE_INFO1 (0xc0000420, | |
| 5132 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 5133 | CSKYV2_ISA_E1), | |
| 531c73a3 | 5134 | |
| b8891f8d | 5135 | /* The followings are enhance DSP instructions. */ |
| d285ba8d CQ |
5136 | DOP32_WITH_WORK ("bloop", |
| 5137 | OPCODE_INFO3 (0xe9c00000, | |
| b8891f8d AJ |
5138 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5139 | (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT), | |
| 5140 | (12_15, BLOOP_OFF4b, OPRND_SHIFT_1_BIT)), | |
| d285ba8d CQ |
5141 | OPCODE_INFO2 (0xe9c00000, |
| 5142 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5143 | (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT)), | |
| 5144 | CSKY_ISA_DSP_ENHANCE, | |
| 5145 | dsp_work_bloop), | |
| b8891f8d AJ |
5146 | /* The followings are ld/st instructions. */ |
| 5147 | OP32 ("ldbi.b", | |
| 5148 | OPCODE_INFO2 (0xd0008000, | |
| 5149 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5150 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5151 | CSKY_ISA_DSP_ENHANCE), | |
| 5152 | OP32 ("ldbi.h", | |
| 5153 | OPCODE_INFO2 (0xd0008400, | |
| 5154 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5155 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5156 | CSKY_ISA_DSP_ENHANCE), | |
| 5157 | OP32 ("ldbi.w", | |
| 5158 | OPCODE_INFO2 (0xd0008800, | |
| 5159 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5160 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5161 | CSKY_ISA_DSP_ENHANCE), | |
| 5162 | OP32 ("pldbi.d", | |
| 5163 | OPCODE_INFO2 (0xd0008c00, | |
| 5164 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5165 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5166 | CSKY_ISA_DSP_ENHANCE), | |
| 5167 | OP32 ("ldbi.hs", | |
| 5168 | OPCODE_INFO2 (0xd0009000, | |
| 5169 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5170 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5171 | CSKY_ISA_DSP_ENHANCE), | |
| 5172 | OP32 ("ldbi.bs", | |
| 5173 | OPCODE_INFO2 (0xd0009400, | |
| 5174 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5175 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5176 | CSKY_ISA_DSP_ENHANCE), | |
| 5177 | OP32 ("stbi.b", | |
| 5178 | OPCODE_INFO2 (0xd4008000, | |
| 5179 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5180 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5181 | CSKY_ISA_DSP_ENHANCE), | |
| 5182 | OP32 ("stbi.h", | |
| 5183 | OPCODE_INFO2 (0xd4008400, | |
| 5184 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5185 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5186 | CSKY_ISA_DSP_ENHANCE), | |
| 5187 | OP32 ("stbi.w", | |
| 5188 | OPCODE_INFO2 (0xd4008800, | |
| 5189 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5190 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
| 5191 | CSKY_ISA_DSP_ENHANCE), | |
| 5192 | OP32 ("ldbir.b", | |
| 5193 | OPCODE_INFO3 (0xd000a000, | |
| 5194 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5195 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5196 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5197 | CSKY_ISA_DSP_ENHANCE), | |
| 5198 | OP32 ("ldbir.h", | |
| 5199 | OPCODE_INFO3 (0xd000a400, | |
| 5200 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5201 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5202 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5203 | CSKY_ISA_DSP_ENHANCE), | |
| 5204 | OP32 ("ldbir.w", | |
| 5205 | OPCODE_INFO3 (0xd000a800, | |
| 5206 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5207 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5208 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5209 | CSKY_ISA_DSP_ENHANCE), | |
| 5210 | OP32 ("pldbir.d", | |
| 5211 | OPCODE_INFO3 (0xd000ac00, | |
| 5212 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5213 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5214 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5215 | CSKY_ISA_DSP_ENHANCE), | |
| 5216 | OP32 ("ldbir.bs", | |
| 5217 | OPCODE_INFO3 (0xd000b000, | |
| 5218 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5219 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5220 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5221 | CSKY_ISA_DSP_ENHANCE), | |
| 5222 | OP32 ("ldbir.hs", | |
| 5223 | OPCODE_INFO3 (0xd000b400, | |
| 5224 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5225 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5226 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5227 | CSKY_ISA_DSP_ENHANCE), | |
| 5228 | OP32 ("stbir.b", | |
| 5229 | OPCODE_INFO3 (0xd400a000, | |
| 5230 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5231 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5232 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5233 | CSKY_ISA_DSP_ENHANCE), | |
| 5234 | OP32 ("stbir.h", | |
| 5235 | OPCODE_INFO3 (0xd400a400, | |
| 5236 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5237 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5238 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5239 | CSKY_ISA_DSP_ENHANCE), | |
| 5240 | OP32 ("stbir.w", | |
| 5241 | OPCODE_INFO3 (0xd400a800, | |
| 5242 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5243 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
| 5244 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5245 | CSKY_ISA_DSP_ENHANCE), | |
| 5246 | /* The followings are add/sub instructions. */ | |
| 5247 | OP32 ("padd.8", | |
| 5248 | OPCODE_INFO3 (0xf800c040, | |
| 5249 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5250 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5251 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5252 | CSKY_ISA_DSP_ENHANCE), | |
| 5253 | OP32 ("padd.16", | |
| 5254 | OPCODE_INFO3 (0xf800c000, | |
| 5255 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5256 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5257 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5258 | CSKY_ISA_DSP_ENHANCE), | |
| 5259 | OP32 ("padd.u8.s", | |
| 5260 | OPCODE_INFO3 (0xf800c140, | |
| 5261 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5262 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5263 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5264 | CSKY_ISA_DSP_ENHANCE), | |
| 5265 | OP32 ("padd.s8.s", | |
| 5266 | OPCODE_INFO3 (0xf800c1c0, | |
| 5267 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5268 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5269 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5270 | CSKY_ISA_DSP_ENHANCE), | |
| 5271 | OP32 ("padd.u16.s", | |
| 5272 | OPCODE_INFO3 (0xf800c100, | |
| 5273 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5274 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5275 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5276 | CSKY_ISA_DSP_ENHANCE), | |
| 5277 | OP32 ("padd.s16.s", | |
| 5278 | OPCODE_INFO3 (0xf800c180, | |
| 5279 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5280 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5281 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5282 | CSKY_ISA_DSP_ENHANCE), | |
| 5283 | OP32 ("add.u32.s", | |
| 5284 | OPCODE_INFO3 (0xf800c120, | |
| 5285 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5286 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5287 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5288 | CSKY_ISA_DSP_ENHANCE), | |
| 5289 | OP32 ("add.s32.s", | |
| 5290 | OPCODE_INFO3 (0xf800c1a0, | |
| 5291 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5292 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5293 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5294 | CSKY_ISA_DSP_ENHANCE), | |
| 5295 | OP32 ("psub.8", | |
| 5296 | OPCODE_INFO3 (0xf800c440, | |
| 5297 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5298 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5299 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5300 | CSKY_ISA_DSP_ENHANCE), | |
| 5301 | OP32 ("psub.16", | |
| 5302 | OPCODE_INFO3 (0xf800c400, | |
| 5303 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5304 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5305 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5306 | CSKY_ISA_DSP_ENHANCE), | |
| 5307 | OP32 ("psub.u8.s", | |
| 5308 | OPCODE_INFO3 (0xf800c540, | |
| 5309 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5310 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5311 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5312 | CSKY_ISA_DSP_ENHANCE), | |
| 5313 | OP32 ("psub.s8.s", | |
| 5314 | OPCODE_INFO3 (0xf800c5c0, | |
| 5315 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5316 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5317 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5318 | CSKY_ISA_DSP_ENHANCE), | |
| 5319 | OP32 ("psub.u16.s", | |
| 5320 | OPCODE_INFO3 (0xf800c500, | |
| 5321 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5322 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5323 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5324 | CSKY_ISA_DSP_ENHANCE), | |
| 5325 | OP32 ("psub.s16.s", | |
| 5326 | OPCODE_INFO3 (0xf800c580, | |
| 5327 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5328 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5329 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5330 | CSKY_ISA_DSP_ENHANCE), | |
| 5331 | OP32 ("sub.u32.s", | |
| 5332 | OPCODE_INFO3 (0xf800c520, | |
| 5333 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5334 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5335 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5336 | CSKY_ISA_DSP_ENHANCE), | |
| 5337 | OP32 ("sub.s32.s", | |
| 5338 | OPCODE_INFO3 (0xf800c5a0, | |
| 5339 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5340 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5341 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5342 | CSKY_ISA_DSP_ENHANCE), | |
| 5343 | OP32 ("paddh.u8", | |
| 5344 | OPCODE_INFO3 (0xf800c240, | |
| 5345 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5346 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5347 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5348 | CSKY_ISA_DSP_ENHANCE), | |
| 5349 | OP32 ("paddh.s8", | |
| 5350 | OPCODE_INFO3 (0xf800c2c0, | |
| 5351 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5352 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5353 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5354 | CSKY_ISA_DSP_ENHANCE), | |
| 5355 | OP32 ("paddh.u16", | |
| 5356 | OPCODE_INFO3 (0xf800c200, | |
| 5357 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5358 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5359 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5360 | CSKY_ISA_DSP_ENHANCE), | |
| 5361 | OP32 ("paddh.s16", | |
| 5362 | OPCODE_INFO3 (0xf800c280, | |
| 5363 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5364 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5365 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5366 | CSKY_ISA_DSP_ENHANCE), | |
| 5367 | OP32 ("addh.u32", | |
| 5368 | OPCODE_INFO3 (0xf800c220, | |
| 5369 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5370 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5371 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5372 | CSKY_ISA_DSP_ENHANCE), | |
| 5373 | OP32 ("addh.s32", | |
| 5374 | OPCODE_INFO3 (0xf800c2a0, | |
| 5375 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5376 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5377 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5378 | CSKY_ISA_DSP_ENHANCE), | |
| 5379 | OP32 ("psubh.u8", | |
| 5380 | OPCODE_INFO3 (0xf800c640, | |
| 5381 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5382 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5383 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5384 | CSKY_ISA_DSP_ENHANCE), | |
| 5385 | OP32 ("psubh.s8", | |
| 5386 | OPCODE_INFO3 (0xf800c6c0, | |
| 5387 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5388 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5389 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5390 | CSKY_ISA_DSP_ENHANCE), | |
| 5391 | OP32 ("psubh.u16", | |
| 5392 | OPCODE_INFO3 (0xf800c600, | |
| 5393 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5394 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5395 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5396 | CSKY_ISA_DSP_ENHANCE), | |
| 5397 | OP32 ("psubh.s16", | |
| 5398 | OPCODE_INFO3 (0xf800c680, | |
| 5399 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5400 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5401 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5402 | CSKY_ISA_DSP_ENHANCE), | |
| 5403 | OP32 ("subh.u32", | |
| 5404 | OPCODE_INFO3 (0xf800c620, | |
| 5405 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5406 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5407 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5408 | CSKY_ISA_DSP_ENHANCE), | |
| 5409 | OP32 ("subh.s32", | |
| 5410 | OPCODE_INFO3 (0xf800c6a0, | |
| 5411 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5412 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5413 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5414 | CSKY_ISA_DSP_ENHANCE), | |
| 5415 | OP32 ("add.64", | |
| 5416 | OPCODE_INFO3 (0xf800c060, | |
| 5417 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5418 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5419 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5420 | CSKY_ISA_DSP_ENHANCE), | |
| 5421 | OP32 ("sub.64", | |
| 5422 | OPCODE_INFO3 (0xf800c460, | |
| 5423 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5424 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5425 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5426 | CSKY_ISA_DSP_ENHANCE), | |
| 5427 | OP32 ("add.u64.s", | |
| 5428 | OPCODE_INFO3 (0xf800c160, | |
| 5429 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5430 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5431 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5432 | CSKY_ISA_DSP_ENHANCE), | |
| 5433 | OP32 ("add.s64.s", | |
| 5434 | OPCODE_INFO3 (0xf800c1e0, | |
| 5435 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5436 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5437 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5438 | CSKY_ISA_DSP_ENHANCE), | |
| 5439 | OP32 ("sub.u64.s", | |
| 5440 | OPCODE_INFO3 (0xf800c560, | |
| 5441 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5442 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5443 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5444 | CSKY_ISA_DSP_ENHANCE), | |
| 5445 | OP32 ("sub.s64.s", | |
| 5446 | OPCODE_INFO3 (0xf800c5e0, | |
| 5447 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5448 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5449 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5450 | CSKY_ISA_DSP_ENHANCE), | |
| 5451 | /* The following are comparison instructions. */ | |
| 5452 | OP32 ("pasx.16", | |
| 5453 | OPCODE_INFO3 (0xf800c860, | |
| 5454 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5455 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5456 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5457 | CSKY_ISA_DSP_ENHANCE), | |
| 5458 | OP32 ("psax.16", | |
| 5459 | OPCODE_INFO3 (0xf800cc60, | |
| 5460 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5461 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5462 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5463 | CSKY_ISA_DSP_ENHANCE), | |
| 5464 | OP32 ("pasx.u16.s", | |
| 5465 | OPCODE_INFO3 (0xf800c960, | |
| 5466 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5467 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5468 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5469 | CSKY_ISA_DSP_ENHANCE), | |
| 5470 | OP32 ("pasx.s16.s", | |
| 5471 | OPCODE_INFO3 (0xf800c9e0, | |
| 5472 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5473 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5474 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5475 | CSKY_ISA_DSP_ENHANCE), | |
| 5476 | OP32 ("psax.u16.s", | |
| 5477 | OPCODE_INFO3 (0xf800cd60, | |
| 5478 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5479 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5480 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5481 | CSKY_ISA_DSP_ENHANCE), | |
| 5482 | OP32 ("psax.s16.s", | |
| 5483 | OPCODE_INFO3 (0xf800cde0, | |
| 5484 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5485 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5486 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5487 | CSKY_ISA_DSP_ENHANCE), | |
| 5488 | OP32 ("pasxh.u16", | |
| 5489 | OPCODE_INFO3 (0xf800ca60, | |
| 5490 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5491 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5492 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5493 | CSKY_ISA_DSP_ENHANCE), | |
| 5494 | OP32 ("pasxh.s16", | |
| 5495 | OPCODE_INFO3 (0xf800cae0, | |
| 5496 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5497 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5498 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5499 | CSKY_ISA_DSP_ENHANCE), | |
| 5500 | OP32 ("psaxh.u16", | |
| 5501 | OPCODE_INFO3 (0xf800ce60, | |
| 5502 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5503 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5504 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5505 | CSKY_ISA_DSP_ENHANCE), | |
| 5506 | OP32 ("psaxh.s16", | |
| 5507 | OPCODE_INFO3 (0xf800cee0, | |
| 5508 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5509 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5510 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5511 | CSKY_ISA_DSP_ENHANCE), | |
| 5512 | OP32 ("pcmpne.8", | |
| 5513 | OPCODE_INFO3 (0xf800c840, | |
| 5514 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5515 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5516 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5517 | CSKY_ISA_DSP_ENHANCE), | |
| 5518 | OP32 ("pcmpne.16", | |
| 5519 | OPCODE_INFO3 (0xf800c800, | |
| 5520 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5521 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5522 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5523 | CSKY_ISA_DSP_ENHANCE), | |
| 5524 | OP32 ("pcmphs.u8", | |
| 5525 | OPCODE_INFO3 (0xf800c940, | |
| 5526 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5527 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5528 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5529 | CSKY_ISA_DSP_ENHANCE), | |
| 5530 | OP32 ("pcmphs.s8", | |
| 5531 | OPCODE_INFO3 (0xf800c9c0, | |
| 5532 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5533 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5534 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5535 | CSKY_ISA_DSP_ENHANCE), | |
| 5536 | OP32 ("pcmphs.u16", | |
| 5537 | OPCODE_INFO3 (0xf800c900, | |
| 5538 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5539 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5540 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5541 | CSKY_ISA_DSP_ENHANCE), | |
| 5542 | OP32 ("pcmphs.s16", | |
| 5543 | OPCODE_INFO3 (0xf800c980, | |
| 5544 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5545 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5546 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5547 | CSKY_ISA_DSP_ENHANCE), | |
| 5548 | OP32 ("pcmplt.u8", | |
| 5549 | OPCODE_INFO3 (0xf800ca40, | |
| 5550 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5551 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5552 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5553 | CSKY_ISA_DSP_ENHANCE), | |
| 5554 | OP32 ("pcmplt.s8", | |
| 5555 | OPCODE_INFO3 (0xf800cac0, | |
| 5556 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5557 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5558 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5559 | CSKY_ISA_DSP_ENHANCE), | |
| 5560 | OP32 ("pcmplt.u16", | |
| 5561 | OPCODE_INFO3 (0xf800ca00, | |
| 5562 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5563 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5564 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5565 | CSKY_ISA_DSP_ENHANCE), | |
| 5566 | OP32 ("pcmplt.s16", | |
| 5567 | OPCODE_INFO3 (0xf800ca80, | |
| 5568 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5569 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5570 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5571 | CSKY_ISA_DSP_ENHANCE), | |
| 5572 | OP32 ("pmax.u8", | |
| 5573 | OPCODE_INFO3 (0xf800cc40, | |
| 5574 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5575 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5576 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5577 | CSKY_ISA_DSP_ENHANCE), | |
| 5578 | OP32 ("pmax.s8", | |
| 5579 | OPCODE_INFO3 (0xf800ccc0, | |
| 5580 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5581 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5582 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5583 | CSKY_ISA_DSP_ENHANCE), | |
| 5584 | OP32 ("pmax.u16", | |
| 5585 | OPCODE_INFO3 (0xf800cc00, | |
| 5586 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5587 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5588 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5589 | CSKY_ISA_DSP_ENHANCE), | |
| 5590 | OP32 ("pmax.s16", | |
| 5591 | OPCODE_INFO3 (0xf800cc80, | |
| 5592 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5593 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5594 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5595 | CSKY_ISA_DSP_ENHANCE), | |
| 5596 | OP32 ("max.u32", | |
| 5597 | OPCODE_INFO3 (0xf800cc20, | |
| 5598 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5599 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5600 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5601 | CSKY_ISA_DSP_ENHANCE), | |
| 5602 | OP32 ("max.s32", | |
| 5603 | OPCODE_INFO3 (0xf800cca0, | |
| 5604 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5605 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5606 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5607 | CSKY_ISA_DSP_ENHANCE), | |
| 5608 | OP32 ("pmin.u8", | |
| 5609 | OPCODE_INFO3 (0xf800cd40, | |
| 5610 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5611 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5612 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5613 | CSKY_ISA_DSP_ENHANCE), | |
| 5614 | OP32 ("pmin.s8", | |
| 5615 | OPCODE_INFO3 (0xf800cdc0, | |
| 5616 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5617 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5618 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5619 | CSKY_ISA_DSP_ENHANCE), | |
| 5620 | OP32 ("pmin.u16", | |
| 5621 | OPCODE_INFO3 (0xf800cd00, | |
| 5622 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5623 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5624 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5625 | CSKY_ISA_DSP_ENHANCE), | |
| 5626 | OP32 ("pmin.s16", | |
| 5627 | OPCODE_INFO3 (0xf800cd80, | |
| 5628 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5629 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5630 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5631 | CSKY_ISA_DSP_ENHANCE), | |
| 5632 | OP32 ("min.u32", | |
| 5633 | OPCODE_INFO3 (0xf800cd20, | |
| 5634 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5635 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5636 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5637 | CSKY_ISA_DSP_ENHANCE), | |
| 5638 | OP32 ("min.s32", | |
| 5639 | OPCODE_INFO3 (0xf800cda0, | |
| 5640 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5641 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5642 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5643 | CSKY_ISA_DSP_ENHANCE), | |
| 5644 | OP32 ("sel", | |
| 5645 | OPCODE_INFO4 (0xf8009000, | |
| 5646 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5647 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5648 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 5649 | (5_9, AREG, OPRND_SHIFT_0_BIT)), | |
| 5650 | CSKY_ISA_DSP_ENHANCE), | |
| 5651 | /* The followings are miscs. */ | |
| 5652 | OP32 ("psabsa.u8", | |
| 5653 | OPCODE_INFO3 (0xf800e040, | |
| 5654 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5655 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5656 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5657 | CSKY_ISA_DSP_ENHANCE), | |
| 5658 | OP32 ("psabsaa.u8", | |
| 5659 | OPCODE_INFO3 (0xf800e140, | |
| 5660 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5661 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5662 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5663 | CSKY_ISA_DSP_ENHANCE), | |
| 5664 | OP32 ("divul", | |
| 5665 | OPCODE_INFO3 (0xf800e260, | |
| 5666 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5667 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5668 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4211a340 | 5669 | CSKYV2_ISA_3E3R3), |
| b8891f8d AJ |
5670 | OP32 ("divsl", |
| 5671 | OPCODE_INFO3 (0xf800e2e0, | |
| 5672 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5673 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5674 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 4211a340 | 5675 | CSKYV2_ISA_3E3R3), |
| b8891f8d AJ |
5676 | OP32 ("mulaca.s8", |
| 5677 | OPCODE_INFO3 (0xf800e4c0, | |
| 5678 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5679 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5680 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5681 | CSKY_ISA_DSP_ENHANCE), | |
| 5682 | /* The followings are shift instructions. */ | |
| 5683 | OP32 ("asri.s32.r", | |
| 5684 | OPCODE_INFO3 (0xf800d1a0, | |
| 5685 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5686 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5687 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 5688 | CSKY_ISA_DSP_ENHANCE), | |
| 5689 | OP32 ("asr.s32.r", | |
| 5690 | OPCODE_INFO3 (0xf800d1e0, | |
| 5691 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5692 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5693 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5694 | CSKY_ISA_DSP_ENHANCE), | |
| 5695 | OP32 ("lsri.u32.r", | |
| 5696 | OPCODE_INFO3 (0xf800d320, | |
| 5697 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5698 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5699 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 5700 | CSKY_ISA_DSP_ENHANCE), | |
| 5701 | OP32 ("lsr.u32.r", | |
| 5702 | OPCODE_INFO3 (0xf800d360, | |
| 5703 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5704 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5705 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5706 | CSKY_ISA_DSP_ENHANCE), | |
| 5707 | OP32 ("lsli.u32.s", | |
| 5708 | OPCODE_INFO3 (0xf800d520, | |
| 5709 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5710 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5711 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 5712 | CSKY_ISA_DSP_ENHANCE), | |
| 5713 | OP32 ("lsli.s32.s", | |
| 5714 | OPCODE_INFO3 (0xf800d5a0, | |
| 5715 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5716 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5717 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 5718 | CSKY_ISA_DSP_ENHANCE), | |
| 5719 | OP32 ("lsl.u32.s", | |
| 5720 | OPCODE_INFO3 (0xf800d560, | |
| 5721 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5722 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5723 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5724 | CSKY_ISA_DSP_ENHANCE), | |
| 5725 | OP32 ("lsl.s32.s", | |
| 5726 | OPCODE_INFO3 (0xf800d5e0, | |
| 5727 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5728 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5729 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5730 | CSKY_ISA_DSP_ENHANCE), | |
| 5731 | OP32 ("pasri.s16", | |
| 5732 | OPCODE_INFO3 (0xf800d080, | |
| 5733 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5734 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5735 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5736 | CSKY_ISA_DSP_ENHANCE), | |
| 5737 | OP32 ("pasr.s16", | |
| 5738 | OPCODE_INFO3 (0xf800d0c0, | |
| 5739 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5740 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5741 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5742 | CSKY_ISA_DSP_ENHANCE), | |
| 5743 | OP32 ("pasri.s16.r", | |
| 5744 | OPCODE_INFO3 (0xf800d180, | |
| 5745 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5746 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5747 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5748 | CSKY_ISA_DSP_ENHANCE), | |
| 5749 | OP32 ("pasr.s16.r", | |
| 5750 | OPCODE_INFO3 (0xf800d1c0, | |
| 5751 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5752 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5753 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5754 | CSKY_ISA_DSP_ENHANCE), | |
| 5755 | OP32 ("plsri.u16", | |
| 5756 | OPCODE_INFO3 (0xf800d200, | |
| 5757 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5758 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5759 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5760 | CSKY_ISA_DSP_ENHANCE), | |
| 5761 | OP32 ("plsr.u16", | |
| 5762 | OPCODE_INFO3 (0xf800d240, | |
| 5763 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5764 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5765 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5766 | CSKY_ISA_DSP_ENHANCE), | |
| 5767 | OP32 ("plsri.u16.r", | |
| 5768 | OPCODE_INFO3 (0xf800d300, | |
| 5769 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5770 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5771 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5772 | CSKY_ISA_DSP_ENHANCE), | |
| 5773 | OP32 ("plsr.u16.r", | |
| 5774 | OPCODE_INFO3 (0xf800d340, | |
| 5775 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5776 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5777 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5778 | CSKY_ISA_DSP_ENHANCE), | |
| 531c73a3 | 5779 | OP32 ("plsli.16", |
| b8891f8d AJ |
5780 | OPCODE_INFO3 (0xf800d400, |
| 5781 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5782 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5783 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5784 | CSKY_ISA_DSP_ENHANCE), | |
| 5785 | OP32 ("plsl.u16", | |
| 5786 | OPCODE_INFO3 (0xf800d440, | |
| 5787 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5788 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5789 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5790 | CSKY_ISA_DSP_ENHANCE), | |
| 5791 | OP32 ("plsli.u16.s", | |
| 5792 | OPCODE_INFO3 (0xf800d500, | |
| 5793 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5794 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5795 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5796 | CSKY_ISA_DSP_ENHANCE), | |
| 5797 | OP32 ("plsli.s16.s", | |
| 5798 | OPCODE_INFO3 (0xf800d580, | |
| 5799 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5800 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5801 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5802 | CSKY_ISA_DSP_ENHANCE), | |
| 5803 | OP32 ("plsl.u16.s", | |
| 5804 | OPCODE_INFO3 (0xf800d540, | |
| 5805 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5806 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5807 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5808 | CSKY_ISA_DSP_ENHANCE), | |
| 5809 | OP32 ("plsl.s16.s", | |
| 5810 | OPCODE_INFO3 (0xf800d5c0, | |
| 5811 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5812 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5813 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5814 | CSKY_ISA_DSP_ENHANCE), | |
| 5815 | /* The following are package & unpackage instructions. */ | |
| 5816 | OP32 ("pkg", | |
| 5817 | OPCODE_INFO5 (0xf800a000, | |
| 5818 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5819 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5820 | (5_8, IMM4b, OPRND_SHIFT_0_BIT), | |
| 5821 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 5822 | (9_12, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5823 | CSKY_ISA_DSP_ENHANCE), | |
| 5824 | OP32 ("dexti", | |
| 5825 | OPCODE_INFO4 (0xf8009800, | |
| 5826 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5827 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5828 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 5829 | (5_9, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 5830 | CSKY_ISA_DSP_ENHANCE), | |
| 5831 | OP32 ("dext", | |
| 5832 | OPCODE_INFO4 (0xf8009c00, | |
| 5833 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5834 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5835 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 5836 | (5_9, AREG, OPRND_SHIFT_0_BIT)), | |
| 5837 | CSKY_ISA_DSP_ENHANCE), | |
| 5838 | OP32 ("pkgll", | |
| 5839 | OPCODE_INFO3 (0xf800d840, | |
| 5840 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5841 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5842 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5843 | CSKY_ISA_DSP_ENHANCE), | |
| 5844 | OP32 ("pkghh", | |
| 5845 | OPCODE_INFO3 (0xf800d860, | |
| 5846 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5847 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5848 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5849 | CSKY_ISA_DSP_ENHANCE), | |
| 5850 | OP32 ("pext.u8.e", | |
| 5851 | OPCODE_INFO2 (0xf800d900, | |
| 5852 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5853 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5854 | CSKY_ISA_DSP_ENHANCE), | |
| 5855 | OP32 ("pext.s8.e", | |
| 5856 | OPCODE_INFO2 (0xf800d980, | |
| 5857 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5858 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5859 | CSKY_ISA_DSP_ENHANCE), | |
| 5860 | OP32 ("pextx.u8.e", | |
| 5861 | OPCODE_INFO2 (0xf800d920, | |
| 5862 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5863 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5864 | CSKY_ISA_DSP_ENHANCE), | |
| 5865 | OP32 ("pextx.s8.e", | |
| 5866 | OPCODE_INFO2 (0xf800d9a0, | |
| 5867 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5868 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5869 | CSKY_ISA_DSP_ENHANCE), | |
| 5870 | OP32 ("narl", | |
| 5871 | OPCODE_INFO3 (0xf800da00, | |
| 5872 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5873 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5874 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5875 | CSKY_ISA_DSP_ENHANCE), | |
| 5876 | OP32 ("narh", | |
| 5877 | OPCODE_INFO3 (0xf800da20, | |
| 5878 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5879 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5880 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5881 | CSKY_ISA_DSP_ENHANCE), | |
| 5882 | OP32 ("narlx", | |
| 5883 | OPCODE_INFO3 (0xf800da40, | |
| 5884 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5885 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5886 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5887 | CSKY_ISA_DSP_ENHANCE), | |
| 5888 | OP32 ("narhx", | |
| 5889 | OPCODE_INFO3 (0xf800da60, | |
| 5890 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5891 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5892 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5893 | CSKY_ISA_DSP_ENHANCE), | |
| 5894 | OP32 ("clipi.u32", | |
| 5895 | OPCODE_INFO3 (0xf800db00, | |
| 5896 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5897 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5898 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 5899 | CSKY_ISA_DSP_ENHANCE), | |
| 5900 | OP32 ("clipi.s32", | |
| 5901 | OPCODE_INFO3 (0xf800db80, | |
| 5902 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5903 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5904 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
| 5905 | CSKY_ISA_DSP_ENHANCE), | |
| 5906 | OP32 ("clip.u32", | |
| 5907 | OPCODE_INFO3 (0xf800db20, | |
| 5908 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5909 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5910 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5911 | CSKY_ISA_DSP_ENHANCE), | |
| 5912 | OP32 ("clip.s32", | |
| 5913 | OPCODE_INFO3 (0xf800dba0, | |
| 5914 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5915 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5916 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5917 | CSKY_ISA_DSP_ENHANCE), | |
| 5918 | OP32 ("pclipi.u16", | |
| 5919 | OPCODE_INFO3 (0xf800db40, | |
| 5920 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5921 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5922 | (21_25, IMM4b, OPRND_SHIFT_0_BIT)), | |
| 5923 | CSKY_ISA_DSP_ENHANCE), | |
| 5924 | OP32 ("pclipi.s16", | |
| 5925 | OPCODE_INFO3 (0xf800dbc0, | |
| 5926 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5927 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5928 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
| 5929 | CSKY_ISA_DSP_ENHANCE), | |
| 5930 | OP32 ("pclip.u16", | |
| 5931 | OPCODE_INFO3 (0xf800db60, | |
| 5932 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5933 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5934 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5935 | CSKY_ISA_DSP_ENHANCE), | |
| 5936 | OP32 ("pclip.s16", | |
| 5937 | OPCODE_INFO3 (0xf800dbe0, | |
| 5938 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5939 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5940 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5941 | CSKY_ISA_DSP_ENHANCE), | |
| 5942 | OP32 ("pabs.s8.s", | |
| 5943 | OPCODE_INFO2 (0xf800dc80, | |
| 5944 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5945 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5946 | CSKY_ISA_DSP_ENHANCE), | |
| 5947 | OP32 ("pabs.s16.s", | |
| 5948 | OPCODE_INFO2 (0xf800dca0, | |
| 5949 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5950 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5951 | CSKY_ISA_DSP_ENHANCE), | |
| 5952 | OP32 ("abs.s32.s", | |
| 5953 | OPCODE_INFO2 (0xf800dcc0, | |
| 5954 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5955 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5956 | CSKY_ISA_DSP_ENHANCE), | |
| 5957 | OP32 ("pneg.s8.s", | |
| 5958 | OPCODE_INFO2 (0xf800dd80, | |
| 5959 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5960 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5961 | CSKY_ISA_DSP_ENHANCE), | |
| 5962 | OP32 ("pneg.s16.s", | |
| 5963 | OPCODE_INFO2 (0xf800dda0, | |
| 5964 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5965 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5966 | CSKY_ISA_DSP_ENHANCE), | |
| 5967 | OP32 ("neg.s32.s", | |
| 5968 | OPCODE_INFO2 (0xf800ddc0, | |
| 5969 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5970 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 5971 | CSKY_ISA_DSP_ENHANCE), | |
| 5972 | OP32 ("dup.8", | |
| 5973 | OPCODE_INFO3 (0xf800de00, | |
| 5974 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5975 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5976 | (5_6, IMM2b, OPRND_SHIFT_0_BIT)), | |
| 5977 | CSKY_ISA_DSP_ENHANCE), | |
| 5978 | OP32 ("dup.16", | |
| 5979 | OPCODE_INFO3 (0xf800df00, | |
| 5980 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5981 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5982 | (5_6, IMM1b, OPRND_SHIFT_0_BIT)), | |
| 5983 | CSKY_ISA_DSP_ENHANCE), | |
| 5984 | /* The followings are multiplication instructions. */ | |
| 5985 | OP32 ("mul.u32", | |
| 5986 | OPCODE_INFO3 (0xf8008000, | |
| 5987 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5988 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5989 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5990 | CSKYV2_ISA_3E3R1), | |
| 5991 | OP32 ("mul.s32", | |
| 5992 | OPCODE_INFO3 (0xf8008200, | |
| 5993 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 5994 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 5995 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 5996 | CSKYV2_ISA_3E3R1), | |
| 5997 | OP32 ("mula.u32", | |
| 5998 | OPCODE_INFO3 (0xf8008080, | |
| 5999 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6000 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6001 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6002 | CSKYV2_ISA_3E3R1), | |
| 6003 | OP32 ("mula.s32", | |
| 6004 | OPCODE_INFO3 (0xf8008280, | |
| 6005 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6006 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6007 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6008 | CSKYV2_ISA_3E3R1), | |
| 6009 | OP32 ("mula.32.l", | |
| 6010 | OPCODE_INFO3 (0xf8008440, | |
| 6011 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6012 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6013 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6014 | CSKYV2_ISA_3E3R1), | |
| 6015 | OP32 ("mulall.s16.s", | |
| 6016 | OPCODE_INFO3 (0xf80081a0, | |
| 6017 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6018 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6019 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6020 | CSKYV2_ISA_3E3R1), | |
| 6021 | OP32 ("muls.u32", | |
| 6022 | OPCODE_INFO3 (0xf80080c0, | |
| 6023 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6024 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6025 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6026 | CSKY_ISA_DSP_ENHANCE), | |
| 6027 | OP32 ("muls.s32", | |
| 6028 | OPCODE_INFO3 (0xf80082c0, | |
| 6029 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6030 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6031 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6032 | CSKY_ISA_DSP_ENHANCE), | |
| 6033 | OP32 ("mula.u32.s", | |
| 6034 | OPCODE_INFO3 (0xf8008180, | |
| 6035 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6036 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6037 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6038 | CSKY_ISA_DSP_ENHANCE), | |
| 6039 | OP32 ("mula.s32.s", | |
| 6040 | OPCODE_INFO3 (0xf8008380, | |
| 6041 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6042 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6043 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6044 | CSKY_ISA_DSP_ENHANCE), | |
| 6045 | OP32 ("muls.u32.s", | |
| 6046 | OPCODE_INFO3 (0xf80081c0, | |
| 6047 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6048 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6049 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6050 | CSKY_ISA_DSP_ENHANCE), | |
| 6051 | OP32 ("muls.s32.s", | |
| 6052 | OPCODE_INFO3 (0xf80083c0, | |
| 6053 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6054 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6055 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6056 | CSKY_ISA_DSP_ENHANCE), | |
| 6057 | OP32 ("mul.s32.h", | |
| 6058 | OPCODE_INFO3 (0xf8008400, | |
| 6059 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6060 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6061 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6062 | CSKY_ISA_DSP_ENHANCE), | |
| 6063 | OP32 ("mul.s32.rh", | |
| 6064 | OPCODE_INFO3 (0xf8008600, | |
| 6065 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6066 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6067 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6068 | CSKY_ISA_DSP_ENHANCE), | |
| 6069 | OP32 ("rmul.s32.h", | |
| 6070 | OPCODE_INFO3 (0xf8008500, | |
| 6071 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6072 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6073 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6074 | CSKY_ISA_DSP_ENHANCE), | |
| 6075 | OP32 ("rmul.s32.rh", | |
| 6076 | OPCODE_INFO3 (0xf8008700, | |
| 6077 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6078 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6079 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6080 | CSKY_ISA_DSP_ENHANCE), | |
| 6081 | OP32 ("mula.s32.hs", | |
| 6082 | OPCODE_INFO3 (0xf8008580, | |
| 6083 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6084 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6085 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6086 | CSKY_ISA_DSP_ENHANCE), | |
| 6087 | OP32 ("muls.s32.hs", | |
| 6088 | OPCODE_INFO3 (0xf80085c0, | |
| 6089 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6090 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6091 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6092 | CSKY_ISA_DSP_ENHANCE), | |
| 6093 | OP32 ("mula.s32.rhs", | |
| 6094 | OPCODE_INFO3 (0xf8008780, | |
| 6095 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6096 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6097 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6098 | CSKY_ISA_DSP_ENHANCE), | |
| 6099 | OP32 ("muls.s32.rhs", | |
| 6100 | OPCODE_INFO3 (0xf80087c0, | |
| 6101 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6102 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6103 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6104 | CSKY_ISA_DSP_ENHANCE), | |
| 6105 | OP32 ("mulxl.s32", | |
| 6106 | OPCODE_INFO3 (0xf8008800, | |
| 6107 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6108 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6109 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6110 | CSKY_ISA_DSP_ENHANCE), | |
| 6111 | OP32 ("mulxl.s32.r", | |
| 6112 | OPCODE_INFO3 (0xf8008a00, | |
| 6113 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6114 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6115 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6116 | CSKY_ISA_DSP_ENHANCE), | |
| 6117 | OP32 ("mulxh.s32", | |
| 6118 | OPCODE_INFO3 (0xf8008c00, | |
| 6119 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6120 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6121 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6122 | CSKY_ISA_DSP_ENHANCE), | |
| 6123 | OP32 ("mulxh.s32.r", | |
| 6124 | OPCODE_INFO3 (0xf8008e00, | |
| 6125 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6126 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6127 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6128 | CSKY_ISA_DSP_ENHANCE), | |
| 6129 | OP32 ("rmulxl.s32", | |
| 6130 | OPCODE_INFO3 (0xf8008900, | |
| 6131 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6132 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6133 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6134 | CSKY_ISA_DSP_ENHANCE), | |
| 6135 | OP32 ("rmulxl.s32.r", | |
| 6136 | OPCODE_INFO3 (0xf8008b00, | |
| 6137 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6138 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6139 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6140 | CSKY_ISA_DSP_ENHANCE), | |
| 6141 | OP32 ("rmulxh.s32", | |
| 6142 | OPCODE_INFO3 (0xf8008d00, | |
| 6143 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6144 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6145 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6146 | CSKY_ISA_DSP_ENHANCE), | |
| 6147 | OP32 ("rmulxh.s32.r", | |
| 6148 | OPCODE_INFO3 (0xf8008f00, | |
| 6149 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6150 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6151 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6152 | CSKY_ISA_DSP_ENHANCE), | |
| 6153 | OP32 ("mulaxl.s32.s", | |
| 6154 | OPCODE_INFO3 (0xf8008980, | |
| 6155 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6156 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6157 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6158 | CSKY_ISA_DSP_ENHANCE), | |
| 6159 | OP32 ("mulaxl.s32.rs", | |
| 6160 | OPCODE_INFO3 (0xf8008b80, | |
| 6161 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6162 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6163 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6164 | CSKY_ISA_DSP_ENHANCE), | |
| 6165 | OP32 ("mulaxh.s32.s", | |
| 6166 | OPCODE_INFO3 (0xf8008d80, | |
| 6167 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6168 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6169 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6170 | CSKY_ISA_DSP_ENHANCE), | |
| 6171 | OP32 ("mulaxh.s32.rs", | |
| 6172 | OPCODE_INFO3 (0xf8008f80, | |
| 6173 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6174 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6175 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6176 | CSKY_ISA_DSP_ENHANCE), | |
| 6177 | OP32 ("mulll.s16", | |
| 6178 | OPCODE_INFO3 (0xf8008020, | |
| 6179 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6180 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6181 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6182 | CSKY_ISA_DSP_ENHANCE), | |
| 6183 | OP32 ("mulhh.s16", | |
| 6184 | OPCODE_INFO3 (0xf8008260, | |
| 6185 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6186 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6187 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6188 | CSKY_ISA_DSP_ENHANCE), | |
| 6189 | OP32 ("mulhl.s16", | |
| 6190 | OPCODE_INFO3 (0xf8008220, | |
| 6191 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6192 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6193 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6194 | CSKY_ISA_DSP_ENHANCE), | |
| 6195 | OP32 ("rmulll.s16", | |
| 6196 | OPCODE_INFO3 (0xf8008120, | |
| 6197 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6198 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6199 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6200 | CSKY_ISA_DSP_ENHANCE), | |
| 6201 | OP32 ("rmulhh.s16", | |
| 6202 | OPCODE_INFO3 (0xf8008360, | |
| 6203 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6204 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6205 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6206 | CSKY_ISA_DSP_ENHANCE), | |
| 6207 | OP32 ("rmulhl.s16", | |
| 6208 | OPCODE_INFO3 (0xf8008320, | |
| 6209 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6210 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6211 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6212 | CSKY_ISA_DSP_ENHANCE), | |
| 6213 | OP32 ("mulahh.s16.s", | |
| 6214 | OPCODE_INFO3 (0xf80083e0, | |
| 6215 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6216 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6217 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6218 | CSKY_ISA_DSP_ENHANCE), | |
| 6219 | OP32 ("mulahl.s16.s", | |
| 6220 | OPCODE_INFO3 (0xf80083a0, | |
| 6221 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6222 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6223 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6224 | CSKY_ISA_DSP_ENHANCE), | |
| 6225 | OP32 ("mulall.s16.e", | |
| 6226 | OPCODE_INFO3 (0xf80080a0, | |
| 6227 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6228 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6229 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6230 | CSKY_ISA_DSP_ENHANCE), | |
| 6231 | OP32 ("mulahh.s16.e", | |
| 6232 | OPCODE_INFO3 (0xf80082e0, | |
| 6233 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6234 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6235 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6236 | CSKY_ISA_DSP_ENHANCE), | |
| 6237 | OP32 ("mulahl.s16.e", | |
| 6238 | OPCODE_INFO3 (0xf80080e0, | |
| 6239 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6240 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6241 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6242 | CSKY_ISA_DSP_ENHANCE), | |
| 6243 | OP32 ("pmul.u16", | |
| 6244 | OPCODE_INFO3 (0xf80084a0, | |
| 6245 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6246 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6247 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6248 | CSKY_ISA_DSP_ENHANCE), | |
| 6249 | OP32 ("pmulx.u16", | |
| 6250 | OPCODE_INFO3 (0xf80084e0, | |
| 6251 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6252 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6253 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6254 | CSKY_ISA_DSP_ENHANCE), | |
| 6255 | OP32 ("pmul.s16", | |
| 6256 | OPCODE_INFO3 (0xf8008420, | |
| 6257 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6258 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6259 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6260 | CSKY_ISA_DSP_ENHANCE), | |
| 6261 | OP32 ("pmulx.s16", | |
| 6262 | OPCODE_INFO3 (0xf8008460, | |
| 6263 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6264 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6265 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6266 | CSKY_ISA_DSP_ENHANCE), | |
| 6267 | OP32 ("prmul.s16", | |
| 6268 | OPCODE_INFO3 (0xf8008520, | |
| 6269 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6270 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6271 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6272 | CSKY_ISA_DSP_ENHANCE), | |
| 6273 | OP32 ("prmulx.s16", | |
| 6274 | OPCODE_INFO3 (0xf8008560, | |
| 6275 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6276 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6277 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6278 | CSKY_ISA_DSP_ENHANCE), | |
| 6279 | OP32 ("prmul.s16.h", | |
| 6280 | OPCODE_INFO3 (0xf80085a0, | |
| 6281 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6282 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6283 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6284 | CSKY_ISA_DSP_ENHANCE), | |
| 6285 | OP32 ("prmul.s16.rh", | |
| 6286 | OPCODE_INFO3 (0xf80087a0, | |
| 6287 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6288 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6289 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6290 | CSKY_ISA_DSP_ENHANCE), | |
| 6291 | OP32 ("prmulx.s16.h", | |
| 6292 | OPCODE_INFO3 (0xf80085e0, | |
| 6293 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6294 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6295 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6296 | CSKY_ISA_DSP_ENHANCE), | |
| 6297 | OP32 ("prmulx.s16.rh", | |
| 6298 | OPCODE_INFO3 (0xf80087e0, | |
| 6299 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6300 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6301 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6302 | CSKY_ISA_DSP_ENHANCE), | |
| 6303 | OP32 ("mulca.s16.s", | |
| 6304 | OPCODE_INFO3 (0xf8008920, | |
| 6305 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6306 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6307 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6308 | CSKY_ISA_DSP_ENHANCE), | |
| 6309 | OP32 ("mulcax.s16.s", | |
| 6310 | OPCODE_INFO3 (0xf8008960, | |
| 6311 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6312 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6313 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6314 | CSKY_ISA_DSP_ENHANCE), | |
| 6315 | OP32 ("mulcs.s16", | |
| 6316 | OPCODE_INFO3 (0xf8008a20, | |
| 6317 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6318 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6319 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6320 | CSKY_ISA_DSP_ENHANCE), | |
| 6321 | OP32 ("mulcsr.s16", | |
| 6322 | OPCODE_INFO3 (0xf8008a60, | |
| 6323 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6324 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6325 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6326 | CSKY_ISA_DSP_ENHANCE), | |
| 6327 | OP32 ("mulcsx.s16", | |
| 6328 | OPCODE_INFO3 (0xf8008c20, | |
| 6329 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6330 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6331 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6332 | CSKY_ISA_DSP_ENHANCE), | |
| 6333 | OP32 ("mulaca.s16.s", | |
| 6334 | OPCODE_INFO3 (0xf80089a0, | |
| 6335 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6336 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6337 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6338 | CSKY_ISA_DSP_ENHANCE), | |
| 6339 | OP32 ("mulacax.s16.s", | |
| 6340 | OPCODE_INFO3 (0xf80089e0, | |
| 6341 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6342 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6343 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6344 | CSKY_ISA_DSP_ENHANCE), | |
| 6345 | OP32 ("mulacs.s16.s", | |
| 6346 | OPCODE_INFO3 (0xf8008ba0, | |
| 6347 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6348 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6349 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6350 | CSKY_ISA_DSP_ENHANCE), | |
| 6351 | OP32 ("mulacsr.s16.s", | |
| 6352 | OPCODE_INFO3 (0xf8008be0, | |
| 6353 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6354 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6355 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6356 | CSKY_ISA_DSP_ENHANCE), | |
| 6357 | OP32 ("mulacsx.s16.s", | |
| 6358 | OPCODE_INFO3 (0xf8008da0, | |
| 6359 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6360 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6361 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6362 | CSKY_ISA_DSP_ENHANCE), | |
| 6363 | OP32 ("mulsca.s16.s", | |
| 6364 | OPCODE_INFO3 (0xf8008de0, | |
| 6365 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6366 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6367 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6368 | CSKY_ISA_DSP_ENHANCE), | |
| 6369 | OP32 ("mulscax.s16.s", | |
| 6370 | OPCODE_INFO3 (0xf8008fa0, | |
| 6371 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6372 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6373 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6374 | CSKY_ISA_DSP_ENHANCE), | |
| 6375 | OP32 ("mulaca.s16.e", | |
| 6376 | OPCODE_INFO3 (0xf80088a0, | |
| 6377 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6378 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6379 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6380 | CSKY_ISA_DSP_ENHANCE), | |
| 6381 | OP32 ("mulacax.s16.e", | |
| 6382 | OPCODE_INFO3 (0xf80088e0, | |
| 6383 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6384 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6385 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6386 | CSKY_ISA_DSP_ENHANCE), | |
| 6387 | OP32 ("mulacs.s16.e", | |
| 6388 | OPCODE_INFO3 (0xf8008aa0, | |
| 6389 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6390 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6391 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6392 | CSKY_ISA_DSP_ENHANCE), | |
| 6393 | OP32 ("mulacsr.s16.e", | |
| 6394 | OPCODE_INFO3 (0xf8008ae0, | |
| 6395 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6396 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6397 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6398 | CSKY_ISA_DSP_ENHANCE), | |
| 6399 | OP32 ("mulacsx.s16.e", | |
| 6400 | OPCODE_INFO3 (0xf8008ca0, | |
| 6401 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6402 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6403 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6404 | CSKY_ISA_DSP_ENHANCE), | |
| 6405 | OP32 ("mulsca.s16.e", | |
| 6406 | OPCODE_INFO3 (0xf8008ce0, | |
| 6407 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6408 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6409 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6410 | CSKY_ISA_DSP_ENHANCE), | |
| 6411 | OP32 ("mulscax.s16.e", | |
| 6412 | OPCODE_INFO3 (0xf8008ea0, | |
| 6413 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6414 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6415 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
| 6416 | CSKY_ISA_DSP_ENHANCE), | |
| 6417 | ||
| 6418 | /* The followings are vdsp instructions for ck810. */ | |
| 6419 | OP32 ("vdup.8", | |
| 6420 | OPCODE_INFO2 (0xf8000e80, | |
| 6421 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6422 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
| 6423 | CSKY_ISA_VDSP), | |
| 6424 | OP32 ("vdup.16", | |
| 6425 | OPCODE_INFO2 (0xf8100e80, | |
| 6426 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6427 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
| 6428 | CSKY_ISA_VDSP), | |
| 6429 | OP32 ("vdup.32", | |
| 6430 | OPCODE_INFO2 (0xfa000e80, | |
| 6431 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6432 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
| 6433 | CSKY_ISA_VDSP), | |
| 6434 | OP32 ("vmfvr.u8", | |
| 6435 | OPCODE_INFO2 (0xf8001200, | |
| 6436 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6437 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
| 6438 | CSKY_ISA_VDSP), | |
| 6439 | OP32 ("vmfvr.u16", | |
| 6440 | OPCODE_INFO2 (0xf8001220, | |
| 6441 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6442 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
| 6443 | CSKY_ISA_VDSP), | |
| 6444 | OP32 ("vmfvr.u32", | |
| 6445 | OPCODE_INFO2 (0xf8001240, | |
| 6446 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6447 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
| 6448 | CSKY_ISA_VDSP), | |
| 6449 | OP32 ("vmfvr.s8", | |
| 6450 | OPCODE_INFO2 (0xf8001280, | |
| 6451 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6452 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
| 6453 | CSKY_ISA_VDSP), | |
| 6454 | OP32 ("vmfvr.s16", | |
| 6455 | OPCODE_INFO2 (0xf80012a0, | |
| 6456 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 6457 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
| 6458 | CSKY_ISA_VDSP), | |
| 6459 | OP32 ("vmtvr.u8", | |
| 6460 | OPCODE_INFO2 (0xf8001300, | |
| 6461 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), | |
| 6462 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 6463 | CSKY_ISA_VDSP), | |
| 6464 | OP32 ("vmtvr.u16", | |
| 6465 | OPCODE_INFO2 (0xf8001320, | |
| 6466 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), | |
| 6467 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 6468 | CSKY_ISA_VDSP), | |
| 6469 | OP32 ("vmtvr.u32", | |
| 6470 | OPCODE_INFO2 (0xf8001340, | |
| 6471 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), | |
| 6472 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 6473 | CSKY_ISA_VDSP), | |
| 6474 | OP32 ("vldd.8", | |
| 6475 | SOPCODE_INFO2 (0xf8002000, | |
| 6476 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6477 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6478 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
| 6479 | CSKY_ISA_VDSP), | |
| 6480 | OP32 ("vldd.16", | |
| 6481 | SOPCODE_INFO2 (0xf8002100, | |
| 6482 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6483 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6484 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
| 6485 | CSKY_ISA_VDSP), | |
| 6486 | OP32 ("vldd.32", | |
| 6487 | SOPCODE_INFO2 (0xf8002200, | |
| 6488 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6489 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6490 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
| 6491 | CSKY_ISA_VDSP), | |
| 6492 | OP32 ("vldq.8", | |
| 6493 | SOPCODE_INFO2 (0xf8002400, | |
| 6494 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6495 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6496 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
| 6497 | CSKY_ISA_VDSP), | |
| 6498 | OP32 ("vldq.16", | |
| 6499 | SOPCODE_INFO2 (0xf8002500, | |
| 6500 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6501 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6502 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
| 6503 | CSKY_ISA_VDSP), | |
| 6504 | OP32 ("vldq.32", | |
| 6505 | SOPCODE_INFO2 (0xf8002600, | |
| 6506 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6507 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6508 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
| 6509 | CSKY_ISA_VDSP), | |
| 6510 | OP32 ("vstd.8", | |
| 6511 | SOPCODE_INFO2 (0xf8002800, | |
| 6512 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6513 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6514 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
| 6515 | CSKY_ISA_VDSP), | |
| 6516 | OP32 ("vstd.16", | |
| 6517 | SOPCODE_INFO2 (0xf8002900, | |
| 6518 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6519 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6520 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
| 6521 | CSKY_ISA_VDSP), | |
| 6522 | OP32 ("vstd.32", | |
| 6523 | SOPCODE_INFO2 (0xf8002a00, | |
| 6524 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6525 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6526 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
| 6527 | CSKY_ISA_VDSP), | |
| 6528 | OP32 ("vstq.8", | |
| 6529 | SOPCODE_INFO2 (0xf8002c00, | |
| 6530 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6531 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6532 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
| 6533 | CSKY_ISA_VDSP), | |
| 6534 | OP32 ("vstq.16", | |
| 6535 | SOPCODE_INFO2 (0xf8002d00, | |
| 6536 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6537 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6538 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
| 6539 | CSKY_ISA_VDSP), | |
| 6540 | OP32 ("vstq.32", | |
| 6541 | SOPCODE_INFO2 (0xf8002e00, | |
| 6542 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6543 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6544 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
| 6545 | CSKY_ISA_VDSP), | |
| 6546 | OP32 ("vldrd.8", | |
| 6547 | SOPCODE_INFO2 (0xf8003000, | |
| 6548 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6549 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6550 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6551 | CSKY_ISA_VDSP), | |
| 6552 | OP32 ("vldrd.16", | |
| 6553 | SOPCODE_INFO2 (0xf8003100, | |
| 6554 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6555 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6556 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6557 | CSKY_ISA_VDSP), | |
| 6558 | OP32 ("vldrd.32", | |
| 6559 | SOPCODE_INFO2 (0xf8003200, | |
| 6560 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6561 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6562 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6563 | CSKY_ISA_VDSP), | |
| 6564 | OP32 ("vldrq.8", | |
| 6565 | SOPCODE_INFO2 (0xf8003400, | |
| 6566 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6567 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6568 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6569 | CSKY_ISA_VDSP), | |
| 6570 | OP32 ("vldrq.16", | |
| 6571 | SOPCODE_INFO2 (0xf8003500, | |
| 6572 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6573 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6574 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6575 | CSKY_ISA_VDSP), | |
| 6576 | OP32 ("vldrq.32", | |
| 6577 | SOPCODE_INFO2 (0xf8003600, | |
| 6578 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6579 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6580 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6581 | CSKY_ISA_VDSP), | |
| 6582 | OP32 ("vstrd.8", | |
| 6583 | SOPCODE_INFO2 (0xf8003800, | |
| 6584 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6585 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6586 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6587 | CSKY_ISA_VDSP), | |
| 6588 | OP32 ("vstrd.16", | |
| 6589 | SOPCODE_INFO2 (0xf8003900, | |
| 6590 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6591 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6592 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6593 | CSKY_ISA_VDSP), | |
| 6594 | OP32 ("vstrd.32", | |
| 6595 | SOPCODE_INFO2 (0xf8003a00, | |
| 6596 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6597 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6598 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6599 | CSKY_ISA_VDSP), | |
| 6600 | OP32 ("vstrq.8", | |
| 6601 | SOPCODE_INFO2 (0xf8003c00, | |
| 6602 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6603 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6604 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6605 | CSKY_ISA_VDSP), | |
| 6606 | OP32 ("vstrq.16", | |
| 6607 | SOPCODE_INFO2 (0xf8003d00, | |
| 6608 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6609 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6610 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6611 | CSKY_ISA_VDSP), | |
| 6612 | OP32 ("vstrq.32", | |
| 6613 | SOPCODE_INFO2 (0xf8003e00, | |
| 6614 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
| 6615 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 6616 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
| 6617 | CSKY_ISA_VDSP), | |
| 6618 | OP32 ("vmov", | |
| 6619 | OPCODE_INFO2 (0xf8000c00, | |
| 6620 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6621 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6622 | CSKY_ISA_VDSP), | |
| 6623 | OP32 ("vcadd.eu8", | |
| 6624 | OPCODE_INFO2 (0xf8000060, | |
| 6625 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6626 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6627 | CSKY_ISA_VDSP), | |
| 6628 | OP32 ("vcadd.eu16", | |
| 6629 | OPCODE_INFO2 (0xf8100060, | |
| 6630 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6631 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6632 | CSKY_ISA_VDSP), | |
| 6633 | OP32 ("vcadd.es8", | |
| 6634 | OPCODE_INFO2 (0xf8000070, | |
| 6635 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6636 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6637 | CSKY_ISA_VDSP), | |
| 6638 | OP32 ("vcadd.es16", | |
| 6639 | OPCODE_INFO2 (0xf8100070, | |
| 6640 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6641 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6642 | CSKY_ISA_VDSP), | |
| 6643 | OP32 ("vmov.eu8", | |
| 6644 | OPCODE_INFO2 (0xf8000c20, | |
| 6645 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6646 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6647 | CSKY_ISA_VDSP), | |
| 6648 | OP32 ("vmov.eu16", | |
| 6649 | OPCODE_INFO2 (0xf8100c20, | |
| 6650 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6651 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6652 | CSKY_ISA_VDSP), | |
| 6653 | OP32 ("vmov.es8", | |
| 6654 | OPCODE_INFO2 (0xf8000c30, | |
| 6655 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6656 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6657 | CSKY_ISA_VDSP), | |
| 6658 | OP32 ("vmov.es16", | |
| 6659 | OPCODE_INFO2 (0xf8100c30, | |
| 6660 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6661 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6662 | CSKY_ISA_VDSP), | |
| 6663 | OP32 ("vmov.u16.l", | |
| 6664 | OPCODE_INFO2 (0xf8100d00, | |
| 6665 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6666 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6667 | CSKY_ISA_VDSP), | |
| 6668 | OP32 ("vmov.u32.l", | |
| 6669 | OPCODE_INFO2 (0xfa000d00, | |
| 6670 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6671 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6672 | CSKY_ISA_VDSP), | |
| 6673 | OP32 ("vmov.s16.l", | |
| 6674 | OPCODE_INFO2 (0xf8100d10, | |
| 6675 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6676 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6677 | CSKY_ISA_VDSP), | |
| 6678 | OP32 ("vmov.s32.l", | |
| 6679 | OPCODE_INFO2 (0xfa000d10, | |
| 6680 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6681 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6682 | CSKY_ISA_VDSP), | |
| 6683 | OP32 ("vmov.u16.sl", | |
| 6684 | OPCODE_INFO2 (0xf8100d40, | |
| 6685 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6686 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6687 | CSKY_ISA_VDSP), | |
| 6688 | OP32 ("vmov.u32.sl", | |
| 6689 | OPCODE_INFO2 (0xfa000d40, | |
| 6690 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6691 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6692 | CSKY_ISA_VDSP), | |
| 6693 | OP32 ("vmov.s16.sl", | |
| 6694 | OPCODE_INFO2 (0xf8100d50, | |
| 6695 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6696 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6697 | CSKY_ISA_VDSP), | |
| 6698 | OP32 ("vmov.s32.sl", | |
| 6699 | OPCODE_INFO2 (0xfa000d50, | |
| 6700 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6701 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6702 | CSKY_ISA_VDSP), | |
| 6703 | OP32 ("vmov.u16.h", | |
| 6704 | OPCODE_INFO2 (0xf8100d60, | |
| 6705 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6706 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6707 | CSKY_ISA_VDSP), | |
| 6708 | OP32 ("vmov.u32.h", | |
| 6709 | OPCODE_INFO2 (0xfa000d60, | |
| 6710 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6711 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6712 | CSKY_ISA_VDSP), | |
| 6713 | OP32 ("vmov.s16.h", | |
| 6714 | OPCODE_INFO2 (0xf8100d70, | |
| 6715 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6716 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6717 | CSKY_ISA_VDSP), | |
| 6718 | OP32 ("vmov.s32.h", | |
| 6719 | OPCODE_INFO2 (0xfa000d70, | |
| 6720 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6721 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6722 | CSKY_ISA_VDSP), | |
| 6723 | OP32 ("vmov.u16.rh", | |
| 6724 | OPCODE_INFO2 (0xf8100d80, | |
| 6725 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6726 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6727 | CSKY_ISA_VDSP), | |
| 6728 | OP32 ("vmov.u32.rh", | |
| 6729 | OPCODE_INFO2 (0xfa000d80, | |
| 6730 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6731 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6732 | CSKY_ISA_VDSP), | |
| 6733 | OP32 ("vmov.s16.rh", | |
| 6734 | OPCODE_INFO2 (0xf8100d90, | |
| 6735 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6736 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6737 | CSKY_ISA_VDSP), | |
| 6738 | OP32 ("vmov.s32.rh", | |
| 6739 | OPCODE_INFO2 (0xfa000d90, | |
| 6740 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6741 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6742 | CSKY_ISA_VDSP), | |
| 6743 | OP32 ("vstou.u16.sl", | |
| 6744 | OPCODE_INFO2 (0xf8100dc0, | |
| 6745 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6746 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6747 | CSKY_ISA_VDSP), | |
| 6748 | OP32 ("vstou.u32.sl", | |
| 6749 | OPCODE_INFO2 (0xfa000dc0, | |
| 6750 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6751 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6752 | CSKY_ISA_VDSP), | |
| 6753 | OP32 ("vstou.s16.sl", | |
| 6754 | OPCODE_INFO2 (0xf8100dd0, | |
| 6755 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6756 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6757 | CSKY_ISA_VDSP), | |
| 6758 | OP32 ("vstou.s32.sl", | |
| 6759 | OPCODE_INFO2 (0xfa000dd0, | |
| 6760 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6761 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6762 | CSKY_ISA_VDSP), | |
| 6763 | OP32 ("vrev.8", | |
| 6764 | OPCODE_INFO2 (0xf8000e60, | |
| 6765 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6766 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6767 | CSKY_ISA_VDSP), | |
| 6768 | OP32 ("vrev.16", | |
| 6769 | OPCODE_INFO2 (0xf8100e60, | |
| 6770 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6771 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6772 | CSKY_ISA_VDSP), | |
| 6773 | OP32 ("vrev.32", | |
| 6774 | OPCODE_INFO2 (0xfa000e60, | |
| 6775 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6776 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6777 | CSKY_ISA_VDSP), | |
| 6778 | OP32 ("vcnt1.8", | |
| 6779 | OPCODE_INFO2 (0xf8000ea0, | |
| 6780 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6781 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6782 | CSKY_ISA_VDSP), | |
| 6783 | OP32 ("vclz.8", | |
| 6784 | OPCODE_INFO2 (0xf8000ec0, | |
| 6785 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6786 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6787 | CSKY_ISA_VDSP), | |
| 6788 | OP32 ("vclz.16", | |
| 6789 | OPCODE_INFO2 (0xf8100ec0, | |
| 6790 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6791 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6792 | CSKY_ISA_VDSP), | |
| 6793 | OP32 ("vclz.32", | |
| 6794 | OPCODE_INFO2 (0xfa000ec0, | |
| 6795 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6796 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6797 | CSKY_ISA_VDSP), | |
| 6798 | OP32 ("vcls.u8", | |
| 6799 | OPCODE_INFO2 (0xf8000ee0, | |
| 6800 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6801 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6802 | CSKY_ISA_VDSP), | |
| 6803 | OP32 ("vcls.u16", | |
| 6804 | OPCODE_INFO2 (0xf8100ee0, | |
| 6805 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6806 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6807 | CSKY_ISA_VDSP), | |
| 6808 | OP32 ("vcls.u32", | |
| 6809 | OPCODE_INFO2 (0xfa000ee0, | |
| 6810 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6811 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6812 | CSKY_ISA_VDSP), | |
| 6813 | OP32 ("vcls.s8", | |
| 6814 | OPCODE_INFO2 (0xf8000ef0, | |
| 6815 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6816 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6817 | CSKY_ISA_VDSP), | |
| 6818 | OP32 ("vcls.s16", | |
| 6819 | OPCODE_INFO2 (0xf8100ef0, | |
| 6820 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6821 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6822 | CSKY_ISA_VDSP), | |
| 6823 | OP32 ("vcls.s32", | |
| 6824 | OPCODE_INFO2 (0xfa000ef0, | |
| 6825 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6826 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6827 | CSKY_ISA_VDSP), | |
| 6828 | OP32 ("vabs.s8", | |
| 6829 | OPCODE_INFO2 (0xf8001010, | |
| 6830 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6831 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6832 | CSKY_ISA_VDSP), | |
| 6833 | OP32 ("vabs.s16", | |
| 6834 | OPCODE_INFO2 (0xf8101010, | |
| 6835 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6836 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6837 | CSKY_ISA_VDSP), | |
| 6838 | OP32 ("vabs.s32", | |
| 6839 | OPCODE_INFO2 (0xfa001010, | |
| 6840 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6841 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6842 | CSKY_ISA_VDSP), | |
| 6843 | OP32 ("vabs.u8.s", | |
| 6844 | OPCODE_INFO2 (0xf8001040, | |
| 6845 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6846 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6847 | CSKY_ISA_VDSP), | |
| 6848 | OP32 ("vabs.u16.s", | |
| 6849 | OPCODE_INFO2 (0xf8101040, | |
| 6850 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6851 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6852 | CSKY_ISA_VDSP), | |
| 6853 | OP32 ("vabs.u32.s", | |
| 6854 | OPCODE_INFO2 (0xfa001040, | |
| 6855 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6856 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6857 | CSKY_ISA_VDSP), | |
| 6858 | OP32 ("vabs.s8.s", | |
| 6859 | OPCODE_INFO2 (0xf8001050, | |
| 6860 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6861 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6862 | CSKY_ISA_VDSP), | |
| 6863 | OP32 ("vabs.s16.s", | |
| 6864 | OPCODE_INFO2 (0xf8101050, | |
| 6865 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6866 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6867 | CSKY_ISA_VDSP), | |
| 6868 | OP32 ("vabs.s32.s", | |
| 6869 | OPCODE_INFO2 (0xfa001050, | |
| 6870 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6871 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6872 | CSKY_ISA_VDSP), | |
| 6873 | OP32 ("vneg.u8", | |
| 6874 | OPCODE_INFO2 (0xf8001080, | |
| 6875 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6876 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6877 | CSKY_ISA_VDSP), | |
| 6878 | OP32 ("vneg.u16", | |
| 6879 | OPCODE_INFO2 (0xf8101080, | |
| 6880 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6881 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6882 | CSKY_ISA_VDSP), | |
| 6883 | OP32 ("vneg.u32", | |
| 6884 | OPCODE_INFO2 (0xfa001080, | |
| 6885 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6886 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6887 | CSKY_ISA_VDSP), | |
| 6888 | OP32 ("vneg.s8", | |
| 6889 | OPCODE_INFO2 (0xf8001090, | |
| 6890 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6891 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6892 | CSKY_ISA_VDSP), | |
| 6893 | OP32 ("vneg.s16", | |
| 6894 | OPCODE_INFO2 (0xf8101090, | |
| 6895 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6896 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6897 | CSKY_ISA_VDSP), | |
| 6898 | OP32 ("vneg.s32", | |
| 6899 | OPCODE_INFO2 (0xfa001090, | |
| 6900 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6901 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6902 | CSKY_ISA_VDSP), | |
| 6903 | OP32 ("vneg.u8.s", | |
| 6904 | OPCODE_INFO2 (0xf80010c0, | |
| 6905 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6906 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6907 | CSKY_ISA_VDSP), | |
| 6908 | OP32 ("vneg.u16.s", | |
| 6909 | OPCODE_INFO2 (0xf81010c0, | |
| 6910 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6911 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6912 | CSKY_ISA_VDSP), | |
| 6913 | OP32 ("vneg.u32.s", | |
| 6914 | OPCODE_INFO2 (0xfa0010c0, | |
| 6915 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6916 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6917 | CSKY_ISA_VDSP), | |
| 6918 | OP32 ("vneg.s8.s", | |
| 6919 | OPCODE_INFO2 (0xf80010d0, | |
| 6920 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6921 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6922 | CSKY_ISA_VDSP), | |
| 6923 | OP32 ("vneg.s16.s", | |
| 6924 | OPCODE_INFO2 (0xf81010d0, | |
| 6925 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6926 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6927 | CSKY_ISA_VDSP), | |
| 6928 | OP32 ("vneg.s32.s", | |
| 6929 | OPCODE_INFO2 (0xfa0010d0, | |
| 6930 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6931 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6932 | CSKY_ISA_VDSP), | |
| 6933 | OP32 ("vcmphsz.u8", | |
| 6934 | OPCODE_INFO2 (0xf8000880, | |
| 6935 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6936 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6937 | CSKY_ISA_VDSP), | |
| 6938 | OP32 ("vcmphsz.u16", | |
| 6939 | OPCODE_INFO2 (0xf8100880, | |
| 6940 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6941 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6942 | CSKY_ISA_VDSP), | |
| 6943 | OP32 ("vcmphsz.u32", | |
| 6944 | OPCODE_INFO2 (0xfa000880, | |
| 6945 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6946 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6947 | CSKY_ISA_VDSP), | |
| 6948 | OP32 ("vcmphsz.s8", | |
| 6949 | OPCODE_INFO2 (0xf8000890, | |
| 6950 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6951 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6952 | CSKY_ISA_VDSP), | |
| 6953 | OP32 ("vcmphsz.s16", | |
| 6954 | OPCODE_INFO2 (0xf8100890, | |
| 6955 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6956 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6957 | CSKY_ISA_VDSP), | |
| 6958 | OP32 ("vcmphsz.s32", | |
| 6959 | OPCODE_INFO2 (0xfa000890, | |
| 6960 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6961 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6962 | CSKY_ISA_VDSP), | |
| 6963 | OP32 ("vcmpltz.u8", | |
| 6964 | OPCODE_INFO2 (0xf80008a0, | |
| 6965 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6966 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6967 | CSKY_ISA_VDSP), | |
| 6968 | OP32 ("vcmpltz.u16", | |
| 6969 | OPCODE_INFO2 (0xf81008a0, | |
| 6970 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6971 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6972 | CSKY_ISA_VDSP), | |
| 6973 | OP32 ("vcmpltz.u32", | |
| 6974 | OPCODE_INFO2 (0xfa0008a0, | |
| 6975 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6976 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6977 | CSKY_ISA_VDSP), | |
| 6978 | OP32 ("vcmpltz.s8", | |
| 6979 | OPCODE_INFO2 (0xf80008b0, | |
| 6980 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6981 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6982 | CSKY_ISA_VDSP), | |
| 6983 | OP32 ("vcmpltz.s16", | |
| 6984 | OPCODE_INFO2 (0xf81008b0, | |
| 6985 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6986 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6987 | CSKY_ISA_VDSP), | |
| 6988 | OP32 ("vcmpltz.s32", | |
| 6989 | OPCODE_INFO2 (0xfa0008b0, | |
| 6990 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6991 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6992 | CSKY_ISA_VDSP), | |
| 6993 | OP32 ("vcmpnez.u8", | |
| 6994 | OPCODE_INFO2 (0xf80008c0, | |
| 6995 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 6996 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 6997 | CSKY_ISA_VDSP), | |
| 6998 | OP32 ("vcmpnez.u16", | |
| 6999 | OPCODE_INFO2 (0xf81008c0, | |
| 7000 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7001 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 7002 | CSKY_ISA_VDSP), | |
| 7003 | OP32 ("vcmpnez.u32", | |
| 7004 | OPCODE_INFO2 (0xfa0008c0, | |
| 7005 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7006 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 7007 | CSKY_ISA_VDSP), | |
| 7008 | OP32 ("vcmpnez.s8", | |
| 7009 | OPCODE_INFO2 (0xf80008d0, | |
| 7010 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7011 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 7012 | CSKY_ISA_VDSP), | |
| 7013 | OP32 ("vcmpnez.s16", | |
| 7014 | OPCODE_INFO2 (0xf81008d0, | |
| 7015 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7016 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 7017 | CSKY_ISA_VDSP), | |
| 7018 | OP32 ("vcmpnez.s32", | |
| 7019 | OPCODE_INFO2 (0xfa0008d0, | |
| 7020 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7021 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
| 7022 | CSKY_ISA_VDSP), | |
| 7023 | OP32 ("vtrch.8", | |
| 7024 | OPCODE_INFO3 (0xf8000f40, | |
| 7025 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7026 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7027 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7028 | CSKY_ISA_VDSP), | |
| 7029 | OP32 ("vtrch.16", | |
| 7030 | OPCODE_INFO3 (0xf8100f40, | |
| 7031 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7032 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7033 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7034 | CSKY_ISA_VDSP), | |
| 7035 | OP32 ("vtrch.32", | |
| 7036 | OPCODE_INFO3 (0xfa000f40, | |
| 7037 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7038 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7039 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7040 | CSKY_ISA_VDSP), | |
| 7041 | OP32 ("vtrcl.8", | |
| 7042 | OPCODE_INFO3 (0xf8000f60, | |
| 7043 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7044 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7045 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7046 | CSKY_ISA_VDSP), | |
| 7047 | OP32 ("vtrcl.16", | |
| 7048 | OPCODE_INFO3 (0xf8100f60, | |
| 7049 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7050 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7051 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7052 | CSKY_ISA_VDSP), | |
| 7053 | OP32 ("vtrcl.32", | |
| 7054 | OPCODE_INFO3 (0xfa000f60, | |
| 7055 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7056 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7057 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7058 | CSKY_ISA_VDSP), | |
| 7059 | OP32 ("vadd.u8", | |
| 7060 | OPCODE_INFO3 (0xf8000000, | |
| 7061 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7062 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7063 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7064 | CSKY_ISA_VDSP), | |
| 7065 | OP32 ("vadd.u16", | |
| 7066 | OPCODE_INFO3 (0xf8100000, | |
| 7067 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7068 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7069 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7070 | CSKY_ISA_VDSP), | |
| 7071 | OP32 ("vadd.u32", | |
| 7072 | OPCODE_INFO3 (0xfa000000, | |
| 7073 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7074 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7075 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7076 | CSKY_ISA_VDSP), | |
| 7077 | OP32 ("vadd.s8", | |
| 7078 | OPCODE_INFO3 (0xf8000010, | |
| 7079 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7080 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7081 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7082 | CSKY_ISA_VDSP), | |
| 7083 | OP32 ("vadd.s16", | |
| 7084 | OPCODE_INFO3 (0xf8100010, | |
| 7085 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7086 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7087 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7088 | CSKY_ISA_VDSP), | |
| 7089 | OP32 ("vadd.s32", | |
| 7090 | OPCODE_INFO3 (0xfa000010, | |
| 7091 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7092 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7093 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7094 | CSKY_ISA_VDSP), | |
| 7095 | OP32 ("vadd.eu8", | |
| 7096 | OPCODE_INFO3 (0xf8000020, | |
| 7097 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7098 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7099 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7100 | CSKY_ISA_VDSP), | |
| 7101 | OP32 ("vadd.eu16", | |
| 7102 | OPCODE_INFO3 (0xf8100020, | |
| 7103 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7104 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7105 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7106 | CSKY_ISA_VDSP), | |
| 7107 | OP32 ("vadd.es8", | |
| 7108 | OPCODE_INFO3 (0xf8000030, | |
| 7109 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7110 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7111 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7112 | CSKY_ISA_VDSP), | |
| 7113 | OP32 ("vadd.es16", | |
| 7114 | OPCODE_INFO3 (0xf8100030, | |
| 7115 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7116 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7117 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7118 | CSKY_ISA_VDSP), | |
| 7119 | OP32 ("vcadd.u8", | |
| 7120 | OPCODE_INFO3 (0xf8000040, | |
| 7121 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7122 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7123 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7124 | CSKY_ISA_VDSP), | |
| 7125 | OP32 ("vcadd.u16", | |
| 7126 | OPCODE_INFO3 (0xf8100040, | |
| 7127 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7128 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7129 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7130 | CSKY_ISA_VDSP), | |
| 7131 | OP32 ("vcadd.u32", | |
| 7132 | OPCODE_INFO3 (0xfa000040, | |
| 7133 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7134 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7135 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7136 | CSKY_ISA_VDSP), | |
| 7137 | OP32 ("vcadd.s8", | |
| 7138 | OPCODE_INFO3 (0xf8000050, | |
| 7139 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7140 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7141 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7142 | CSKY_ISA_VDSP), | |
| 7143 | OP32 ("vcadd.s16", | |
| 7144 | OPCODE_INFO3 (0xf8100050, | |
| 7145 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7146 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7147 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7148 | CSKY_ISA_VDSP), | |
| 7149 | OP32 ("vcadd.s32", | |
| 7150 | OPCODE_INFO3 (0xfa000050, | |
| 7151 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7152 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7153 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7154 | CSKY_ISA_VDSP), | |
| 7155 | OP32 ("vadd.xu16.sl", | |
| 7156 | OPCODE_INFO3 (0xf8100140, | |
| 7157 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7158 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7159 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7160 | CSKY_ISA_VDSP), | |
| 7161 | OP32 ("vadd.xu32.sl", | |
| 7162 | OPCODE_INFO3 (0xfa000140, | |
| 7163 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7164 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7165 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7166 | CSKY_ISA_VDSP), | |
| 7167 | OP32 ("vadd.xs16.sl", | |
| 7168 | OPCODE_INFO3 (0xf8100150, | |
| 7169 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7170 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7171 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7172 | CSKY_ISA_VDSP), | |
| 7173 | OP32 ("vadd.xs32.sl", | |
| 7174 | OPCODE_INFO3 (0xfa000150, | |
| 7175 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7176 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7177 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7178 | CSKY_ISA_VDSP), | |
| 7179 | OP32 ("vadd.xu16", | |
| 7180 | OPCODE_INFO3 (0xf8100160, | |
| 7181 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7182 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7183 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7184 | CSKY_ISA_VDSP), | |
| 7185 | OP32 ("vadd.xu32", | |
| 7186 | OPCODE_INFO3 (0xfa000160, | |
| 7187 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7188 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7189 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7190 | CSKY_ISA_VDSP), | |
| 7191 | OP32 ("vadd.xs16", | |
| 7192 | OPCODE_INFO3 (0xf8100170, | |
| 7193 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7194 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7195 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7196 | CSKY_ISA_VDSP), | |
| 7197 | OP32 ("vadd.xs32", | |
| 7198 | OPCODE_INFO3 (0xfa000170, | |
| 7199 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7200 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7201 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7202 | CSKY_ISA_VDSP), | |
| 7203 | OP32 ("vaddh.u8", | |
| 7204 | OPCODE_INFO3 (0xf8000180, | |
| 7205 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7206 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7207 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7208 | CSKY_ISA_VDSP), | |
| 7209 | OP32 ("vaddh.u16", | |
| 7210 | OPCODE_INFO3 (0xf8100180, | |
| 7211 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7212 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7213 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7214 | CSKY_ISA_VDSP), | |
| 7215 | OP32 ("vaddh.u32", | |
| 7216 | OPCODE_INFO3 (0xfa000180, | |
| 7217 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7218 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7219 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7220 | CSKY_ISA_VDSP), | |
| 7221 | OP32 ("vaddh.s8", | |
| 7222 | OPCODE_INFO3 (0xf8000190, | |
| 7223 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7224 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7225 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7226 | CSKY_ISA_VDSP), | |
| 7227 | OP32 ("vaddh.s16", | |
| 7228 | OPCODE_INFO3 (0xf8100190, | |
| 7229 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7230 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7231 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7232 | CSKY_ISA_VDSP), | |
| 7233 | OP32 ("vaddh.s32", | |
| 7234 | OPCODE_INFO3 (0xfa000190, | |
| 7235 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7236 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7237 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7238 | CSKY_ISA_VDSP), | |
| 7239 | OP32 ("vaddh.u8.r", | |
| 7240 | OPCODE_INFO3 (0xf80001a0, | |
| 7241 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7242 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7243 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7244 | CSKY_ISA_VDSP), | |
| 7245 | OP32 ("vaddh.u16.r", | |
| 7246 | OPCODE_INFO3 (0xf81001a0, | |
| 7247 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7248 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7249 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7250 | CSKY_ISA_VDSP), | |
| 7251 | OP32 ("vaddh.u32.r", | |
| 7252 | OPCODE_INFO3 (0xfa0001a0, | |
| 7253 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7254 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7255 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7256 | CSKY_ISA_VDSP), | |
| 7257 | OP32 ("vaddh.s8.r", | |
| 7258 | OPCODE_INFO3 (0xf80001b0, | |
| 7259 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7260 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7261 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7262 | CSKY_ISA_VDSP), | |
| 7263 | OP32 ("vaddh.s16.r", | |
| 7264 | OPCODE_INFO3 (0xf81001b0, | |
| 7265 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7266 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7267 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7268 | CSKY_ISA_VDSP), | |
| 7269 | OP32 ("vaddh.s32.r", | |
| 7270 | OPCODE_INFO3 (0xfa0001b0, | |
| 7271 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7272 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7273 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7274 | CSKY_ISA_VDSP), | |
| 7275 | OP32 ("vadd.u8.s", | |
| 7276 | OPCODE_INFO3 (0xf80001c0, | |
| 7277 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7278 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7279 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7280 | CSKY_ISA_VDSP), | |
| 7281 | OP32 ("vadd.u16.s", | |
| 7282 | OPCODE_INFO3 (0xf81001c0, | |
| 7283 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7284 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7285 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7286 | CSKY_ISA_VDSP), | |
| 7287 | OP32 ("vadd.u32.s", | |
| 7288 | OPCODE_INFO3 (0xfa0001c0, | |
| 7289 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7290 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7291 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7292 | CSKY_ISA_VDSP), | |
| 7293 | OP32 ("vadd.s8.s", | |
| 7294 | OPCODE_INFO3 (0xf80001d0, | |
| 7295 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7296 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7297 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7298 | CSKY_ISA_VDSP), | |
| 7299 | OP32 ("vadd.s16.s", | |
| 7300 | OPCODE_INFO3 (0xf81001d0, | |
| 7301 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7302 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7303 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7304 | CSKY_ISA_VDSP), | |
| 7305 | OP32 ("vadd.s32.s", | |
| 7306 | OPCODE_INFO3 (0xfa0001d0, | |
| 7307 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7308 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7309 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7310 | CSKY_ISA_VDSP), | |
| 7311 | OP32 ("vsub.u8", | |
| 7312 | OPCODE_INFO3 (0xf8000200, | |
| 7313 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7314 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7315 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7316 | CSKY_ISA_VDSP), | |
| 7317 | OP32 ("vsub.u16", | |
| 7318 | OPCODE_INFO3 (0xf8100200, | |
| 7319 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7320 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7321 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7322 | CSKY_ISA_VDSP), | |
| 7323 | OP32 ("vsub.u32", | |
| 7324 | OPCODE_INFO3 (0xfa000200, | |
| 7325 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7326 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7327 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7328 | CSKY_ISA_VDSP), | |
| 7329 | OP32 ("vsub.s8", | |
| 7330 | OPCODE_INFO3 (0xf8000210, | |
| 7331 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7332 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7333 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7334 | CSKY_ISA_VDSP), | |
| 7335 | OP32 ("vsub.s16", | |
| 7336 | OPCODE_INFO3 (0xf8100210, | |
| 7337 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7338 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7339 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7340 | CSKY_ISA_VDSP), | |
| 7341 | OP32 ("vsub.s32", | |
| 7342 | OPCODE_INFO3 (0xfa000210, | |
| 7343 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7344 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7345 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7346 | CSKY_ISA_VDSP), | |
| 7347 | OP32 ("vsub.eu8", | |
| 7348 | OPCODE_INFO3 (0xf8000220, | |
| 7349 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7350 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7351 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7352 | CSKY_ISA_VDSP), | |
| 7353 | OP32 ("vsub.eu16", | |
| 7354 | OPCODE_INFO3 (0xf8100220, | |
| 7355 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7356 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7357 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7358 | CSKY_ISA_VDSP), | |
| 7359 | OP32 ("vsub.eu32", | |
| 7360 | OPCODE_INFO3 (0xfa000220, | |
| 7361 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7362 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7363 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7364 | CSKY_ISA_VDSP), | |
| 7365 | OP32 ("vsub.es8", | |
| 7366 | OPCODE_INFO3 (0xf8000230, | |
| 7367 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7368 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7369 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7370 | CSKY_ISA_VDSP), | |
| 7371 | OP32 ("vsub.es16", | |
| 7372 | OPCODE_INFO3 (0xf8100230, | |
| 7373 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7374 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7375 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7376 | CSKY_ISA_VDSP), | |
| 7377 | OP32 ("vsub.es32", | |
| 7378 | OPCODE_INFO3 (0xfa000230, | |
| 7379 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7380 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7381 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7382 | CSKY_ISA_VDSP), | |
| 7383 | OP32 ("vsabs.u8", | |
| 7384 | OPCODE_INFO3 (0xf8000240, | |
| 7385 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7386 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7387 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7388 | CSKY_ISA_VDSP), | |
| 7389 | OP32 ("vsabs.u16", | |
| 7390 | OPCODE_INFO3 (0xf8100240, | |
| 7391 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7392 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7393 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7394 | CSKY_ISA_VDSP), | |
| 7395 | OP32 ("vsabs.u32", | |
| 7396 | OPCODE_INFO3 (0xfa000240, | |
| 7397 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7398 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7399 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7400 | CSKY_ISA_VDSP), | |
| 7401 | OP32 ("vsabs.s8", | |
| 7402 | OPCODE_INFO3 (0xf8000250, | |
| 7403 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7404 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7405 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7406 | CSKY_ISA_VDSP), | |
| 7407 | OP32 ("vsabs.s16", | |
| 7408 | OPCODE_INFO3 (0xf8100250, | |
| 7409 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7410 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7411 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7412 | CSKY_ISA_VDSP), | |
| 7413 | OP32 ("vsabs.s32", | |
| 7414 | OPCODE_INFO3 (0xfa000250, | |
| 7415 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7416 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7417 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7418 | CSKY_ISA_VDSP), | |
| 7419 | OP32 ("vsabs.eu8", | |
| 7420 | OPCODE_INFO3 (0xf8000260, | |
| 7421 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7422 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7423 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7424 | CSKY_ISA_VDSP), | |
| 7425 | OP32 ("vsabs.eu16", | |
| 7426 | OPCODE_INFO3 (0xf8100260, | |
| 7427 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7428 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7429 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7430 | CSKY_ISA_VDSP), | |
| 7431 | OP32 ("vsabs.es8", | |
| 7432 | OPCODE_INFO3 (0xf8000270, | |
| 7433 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7434 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7435 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7436 | CSKY_ISA_VDSP), | |
| 7437 | OP32 ("vsabs.es16", | |
| 7438 | OPCODE_INFO3 (0xf8100270, | |
| 7439 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7440 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7441 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7442 | CSKY_ISA_VDSP), | |
| 7443 | OP32 ("vsabsa.u8", | |
| 7444 | OPCODE_INFO3 (0xf8000280, | |
| 7445 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7446 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7447 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7448 | CSKY_ISA_VDSP), | |
| 7449 | OP32 ("vsabsa.u16", | |
| 7450 | OPCODE_INFO3 (0xf8100280, | |
| 7451 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7452 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7453 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7454 | CSKY_ISA_VDSP), | |
| 7455 | OP32 ("vsabsa.u32", | |
| 7456 | OPCODE_INFO3 (0xfa000280, | |
| 7457 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7458 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7459 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7460 | CSKY_ISA_VDSP), | |
| 7461 | OP32 ("vsabsa.s8", | |
| 7462 | OPCODE_INFO3 (0xf8000290, | |
| 7463 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7464 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7465 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7466 | CSKY_ISA_VDSP), | |
| 7467 | OP32 ("vsabsa.s16", | |
| 7468 | OPCODE_INFO3 (0xf8100290, | |
| 7469 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7470 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7471 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7472 | CSKY_ISA_VDSP), | |
| 7473 | OP32 ("vsabsa.s32", | |
| 7474 | OPCODE_INFO3 (0xfa000290, | |
| 7475 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7476 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7477 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7478 | CSKY_ISA_VDSP), | |
| 7479 | OP32 ("vsabsa.eu8", | |
| 7480 | OPCODE_INFO3 (0xf80002a0, | |
| 7481 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7482 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7483 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7484 | CSKY_ISA_VDSP), | |
| 7485 | OP32 ("vsabsa.eu16", | |
| 7486 | OPCODE_INFO3 (0xf81002a0, | |
| 7487 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7488 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7489 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7490 | CSKY_ISA_VDSP), | |
| 7491 | OP32 ("vsabsa.es8", | |
| 7492 | OPCODE_INFO3 (0xf80002b0, | |
| 7493 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7494 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7495 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7496 | CSKY_ISA_VDSP), | |
| 7497 | OP32 ("vsabsa.es16", | |
| 7498 | OPCODE_INFO3 (0xf81002b0, | |
| 7499 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7500 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7501 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7502 | CSKY_ISA_VDSP), | |
| 7503 | OP32 ("vsub.xu16", | |
| 7504 | OPCODE_INFO3 (0xf8100360, | |
| 7505 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7506 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7507 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7508 | CSKY_ISA_VDSP), | |
| 7509 | OP32 ("vsub.xu32", | |
| 7510 | OPCODE_INFO3 (0xfa000360, | |
| 7511 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7512 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7513 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7514 | CSKY_ISA_VDSP), | |
| 7515 | OP32 ("vsub.xs16", | |
| 7516 | OPCODE_INFO3 (0xf8100370, | |
| 7517 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7518 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7519 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7520 | CSKY_ISA_VDSP), | |
| 7521 | OP32 ("vsub.xs32", | |
| 7522 | OPCODE_INFO3 (0xfa000370, | |
| 7523 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7524 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7525 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7526 | CSKY_ISA_VDSP), | |
| 7527 | OP32 ("vsubh.u8", | |
| 7528 | OPCODE_INFO3 (0xf8000380, | |
| 7529 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7530 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7531 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7532 | CSKY_ISA_VDSP), | |
| 7533 | OP32 ("vsubh.u16", | |
| 7534 | OPCODE_INFO3 (0xf8100380, | |
| 7535 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7536 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7537 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7538 | CSKY_ISA_VDSP), | |
| 7539 | OP32 ("vsubh.u32", | |
| 7540 | OPCODE_INFO3 (0xfa000380, | |
| 7541 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7542 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7543 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7544 | CSKY_ISA_VDSP), | |
| 7545 | OP32 ("vsubh.s8", | |
| 7546 | OPCODE_INFO3 (0xf8000390, | |
| 7547 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7548 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7549 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7550 | CSKY_ISA_VDSP), | |
| 7551 | OP32 ("vsubh.s16", | |
| 7552 | OPCODE_INFO3 (0xf8100390, | |
| 7553 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7554 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7555 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7556 | CSKY_ISA_VDSP), | |
| 7557 | OP32 ("vsubh.s32", | |
| 7558 | OPCODE_INFO3 (0xfa000390, | |
| 7559 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7560 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7561 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7562 | CSKY_ISA_VDSP), | |
| 7563 | OP32 ("vsubh.u8.r", | |
| 7564 | OPCODE_INFO3 (0xf80003a0, | |
| 7565 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7566 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7567 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7568 | CSKY_ISA_VDSP), | |
| 7569 | OP32 ("vsubh.u16.r", | |
| 7570 | OPCODE_INFO3 (0xf81003a0, | |
| 7571 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7572 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7573 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7574 | CSKY_ISA_VDSP), | |
| 7575 | OP32 ("vsubh.u32.r", | |
| 7576 | OPCODE_INFO3 (0xfa0003a0, | |
| 7577 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7578 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7579 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7580 | CSKY_ISA_VDSP), | |
| 7581 | OP32 ("vsubh.s8.r", | |
| 7582 | OPCODE_INFO3 (0xf80003b0, | |
| 7583 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7584 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7585 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7586 | CSKY_ISA_VDSP), | |
| 7587 | OP32 ("vsubh.s16.r", | |
| 7588 | OPCODE_INFO3 (0xf81003b0, | |
| 7589 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7590 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7591 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7592 | CSKY_ISA_VDSP), | |
| 7593 | OP32 ("vsubh.s32.r", | |
| 7594 | OPCODE_INFO3 (0xfa0003b0, | |
| 7595 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7596 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7597 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7598 | CSKY_ISA_VDSP), | |
| 7599 | OP32 ("vsub.u8.s", | |
| 7600 | OPCODE_INFO3 (0xf80003c0, | |
| 7601 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7602 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7603 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7604 | CSKY_ISA_VDSP), | |
| 7605 | OP32 ("vsub.u16.s", | |
| 7606 | OPCODE_INFO3 (0xf81003c0, | |
| 7607 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7608 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7609 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7610 | CSKY_ISA_VDSP), | |
| 7611 | OP32 ("vsub.u32.s", | |
| 7612 | OPCODE_INFO3 (0xfa0003c0, | |
| 7613 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7614 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7615 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7616 | CSKY_ISA_VDSP), | |
| 7617 | OP32 ("vsub.s8.s", | |
| 7618 | OPCODE_INFO3 (0xf80003d0, | |
| 7619 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7620 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7621 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7622 | CSKY_ISA_VDSP), | |
| 7623 | OP32 ("vsub.s16.s", | |
| 7624 | OPCODE_INFO3 (0xf81003d0, | |
| 7625 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7626 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7627 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7628 | CSKY_ISA_VDSP), | |
| 7629 | OP32 ("vsub.s32.s", | |
| 7630 | OPCODE_INFO3 (0xfa0003d0, | |
| 7631 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7632 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7633 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7634 | CSKY_ISA_VDSP), | |
| 7635 | OP32 ("vmul.u8", | |
| 7636 | OPCODE_INFO3 (0xf8000400, | |
| 7637 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7638 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7639 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7640 | CSKY_ISA_VDSP), | |
| 7641 | OP32 ("vmul.u16", | |
| 7642 | OPCODE_INFO3 (0xf8100400, | |
| 7643 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7644 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7645 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7646 | CSKY_ISA_VDSP), | |
| 7647 | OP32 ("vmul.u32", | |
| 7648 | OPCODE_INFO3 (0xfa000400, | |
| 7649 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7650 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7651 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7652 | CSKY_ISA_VDSP), | |
| 7653 | OP32 ("vmul.s8", | |
| 7654 | OPCODE_INFO3 (0xf8000410, | |
| 7655 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7656 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7657 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7658 | CSKY_ISA_VDSP), | |
| 7659 | OP32 ("vmul.s16", | |
| 7660 | OPCODE_INFO3 (0xf8100410, | |
| 7661 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7662 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7663 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7664 | CSKY_ISA_VDSP), | |
| 7665 | OP32 ("vmul.s32", | |
| 7666 | OPCODE_INFO3 (0xfa000410, | |
| 7667 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7668 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7669 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7670 | CSKY_ISA_VDSP), | |
| 7671 | OP32 ("vmul.eu8", | |
| 7672 | OPCODE_INFO3 (0xf8000420, | |
| 7673 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7674 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7675 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7676 | CSKY_ISA_VDSP), | |
| 7677 | OP32 ("vmul.eu16", | |
| 7678 | OPCODE_INFO3 (0xf8100420, | |
| 7679 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7680 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7681 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7682 | CSKY_ISA_VDSP), | |
| 7683 | OP32 ("vmul.es8", | |
| 7684 | OPCODE_INFO3 (0xf8000430, | |
| 7685 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7686 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7687 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7688 | CSKY_ISA_VDSP), | |
| 7689 | OP32 ("vmul.es16", | |
| 7690 | OPCODE_INFO3 (0xf8100430, | |
| 7691 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7692 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7693 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7694 | CSKY_ISA_VDSP), | |
| 7695 | OP32 ("vmula.u8", | |
| 7696 | OPCODE_INFO3 (0xf8000440, | |
| 7697 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7698 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7699 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7700 | CSKY_ISA_VDSP), | |
| 7701 | OP32 ("vmula.u16", | |
| 7702 | OPCODE_INFO3 (0xf8100440, | |
| 7703 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7704 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7705 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7706 | CSKY_ISA_VDSP), | |
| 7707 | OP32 ("vmula.u32", | |
| 7708 | OPCODE_INFO3 (0xfa000440, | |
| 7709 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7710 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7711 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7712 | CSKY_ISA_VDSP), | |
| 7713 | OP32 ("vmula.s8", | |
| 7714 | OPCODE_INFO3 (0xf8000450, | |
| 7715 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7716 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7717 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7718 | CSKY_ISA_VDSP), | |
| 7719 | OP32 ("vmula.s16", | |
| 7720 | OPCODE_INFO3 (0xf8100450, | |
| 7721 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7722 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7723 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7724 | CSKY_ISA_VDSP), | |
| 7725 | OP32 ("vmula.s32", | |
| 7726 | OPCODE_INFO3 (0xfa000450, | |
| 7727 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7728 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7729 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7730 | CSKY_ISA_VDSP), | |
| 7731 | OP32 ("vmula.eu8", | |
| 7732 | OPCODE_INFO3 (0xf8000460, | |
| 7733 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7734 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7735 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7736 | CSKY_ISA_VDSP), | |
| 7737 | OP32 ("vmula.eu16", | |
| 7738 | OPCODE_INFO3 (0xf8100460, | |
| 7739 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7740 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7741 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7742 | CSKY_ISA_VDSP), | |
| 7743 | OP32 ("vmula.eu32", | |
| 7744 | OPCODE_INFO3 (0xfa000460, | |
| 7745 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7746 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7747 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7748 | CSKY_ISA_VDSP), | |
| 7749 | OP32 ("vmula.es8", | |
| 7750 | OPCODE_INFO3 (0xf8000470, | |
| 7751 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7752 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7753 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7754 | CSKY_ISA_VDSP), | |
| 7755 | OP32 ("vmula.es16", | |
| 7756 | OPCODE_INFO3 (0xf8100470, | |
| 7757 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7758 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7759 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7760 | CSKY_ISA_VDSP), | |
| 7761 | OP32 ("vmula.es32", | |
| 7762 | OPCODE_INFO3 (0xfa000470, | |
| 7763 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7764 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7765 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7766 | CSKY_ISA_VDSP), | |
| 7767 | OP32 ("vmuls.u8", | |
| 7768 | OPCODE_INFO3 (0xf8000480, | |
| 7769 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7770 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7771 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7772 | CSKY_ISA_VDSP), | |
| 7773 | OP32 ("vmuls.u16", | |
| 7774 | OPCODE_INFO3 (0xf8100480, | |
| 7775 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7776 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7777 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7778 | CSKY_ISA_VDSP), | |
| 7779 | OP32 ("vmuls.u32", | |
| 7780 | OPCODE_INFO3 (0xfa000480, | |
| 7781 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7782 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7783 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7784 | CSKY_ISA_VDSP), | |
| 7785 | OP32 ("vmuls.s8", | |
| 7786 | OPCODE_INFO3 (0xf8000490, | |
| 7787 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7788 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7789 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7790 | CSKY_ISA_VDSP), | |
| 7791 | OP32 ("vmuls.s16", | |
| 7792 | OPCODE_INFO3 (0xf8100490, | |
| 7793 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7794 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7795 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7796 | CSKY_ISA_VDSP), | |
| 7797 | OP32 ("vmuls.s32", | |
| 7798 | OPCODE_INFO3 (0xfa000490, | |
| 7799 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7800 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7801 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7802 | CSKY_ISA_VDSP), | |
| 7803 | OP32 ("vmuls.eu8", | |
| 7804 | OPCODE_INFO3 (0xf80004a0, | |
| 7805 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7806 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7807 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7808 | CSKY_ISA_VDSP), | |
| 7809 | OP32 ("vmuls.eu16", | |
| 7810 | OPCODE_INFO3 (0xf81004a0, | |
| 7811 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7812 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7813 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7814 | CSKY_ISA_VDSP), | |
| 7815 | OP32 ("vmuls.es8", | |
| 7816 | OPCODE_INFO3 (0xf80004b0, | |
| 7817 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7818 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7819 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7820 | CSKY_ISA_VDSP), | |
| 7821 | OP32 ("vmuls.es16", | |
| 7822 | OPCODE_INFO3 (0xf81004b0, | |
| 7823 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7824 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7825 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7826 | CSKY_ISA_VDSP), | |
| 7827 | OP32 ("vshr.u8", | |
| 7828 | OPCODE_INFO3 (0xf8000680, | |
| 7829 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7830 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7831 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7832 | CSKY_ISA_VDSP), | |
| 7833 | OP32 ("vshr.u16", | |
| 7834 | OPCODE_INFO3 (0xf8100680, | |
| 7835 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7836 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7837 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7838 | CSKY_ISA_VDSP), | |
| 7839 | OP32 ("vshr.u32", | |
| 7840 | OPCODE_INFO3 (0xfa000680, | |
| 7841 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7842 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7843 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7844 | CSKY_ISA_VDSP), | |
| 7845 | OP32 ("vshr.s8", | |
| 7846 | OPCODE_INFO3 (0xf8000690, | |
| 7847 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7848 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7849 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7850 | CSKY_ISA_VDSP), | |
| 7851 | OP32 ("vshr.s16", | |
| 7852 | OPCODE_INFO3 (0xf8100690, | |
| 7853 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7854 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7855 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7856 | CSKY_ISA_VDSP), | |
| 7857 | OP32 ("vshr.s32", | |
| 7858 | OPCODE_INFO3 (0xfa000690, | |
| 7859 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7860 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7861 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7862 | CSKY_ISA_VDSP), | |
| 7863 | OP32 ("vshr.u8.r", | |
| 7864 | OPCODE_INFO3 (0xf80006c0, | |
| 7865 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7866 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7867 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7868 | CSKY_ISA_VDSP), | |
| 7869 | OP32 ("vshr.u16.r", | |
| 7870 | OPCODE_INFO3 (0xf81006c0, | |
| 7871 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7872 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7873 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7874 | CSKY_ISA_VDSP), | |
| 7875 | OP32 ("vshr.u32.r", | |
| 7876 | OPCODE_INFO3 (0xfa0006c0, | |
| 7877 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7878 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7879 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7880 | CSKY_ISA_VDSP), | |
| 7881 | OP32 ("vshr.s8.r", | |
| 7882 | OPCODE_INFO3 (0xf80006d0, | |
| 7883 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7884 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7885 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7886 | CSKY_ISA_VDSP), | |
| 7887 | OP32 ("vshr.s16.r", | |
| 7888 | OPCODE_INFO3 (0xf81006d0, | |
| 7889 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7890 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7891 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7892 | CSKY_ISA_VDSP), | |
| 7893 | OP32 ("vshr.s32.r", | |
| 7894 | OPCODE_INFO3 (0xfa0006d0, | |
| 7895 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7896 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7897 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7898 | CSKY_ISA_VDSP), | |
| 7899 | OP32 ("vshl.u8", | |
| 7900 | OPCODE_INFO3 (0xf8000780, | |
| 7901 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7902 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7903 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7904 | CSKY_ISA_VDSP), | |
| 7905 | OP32 ("vshl.u16", | |
| 7906 | OPCODE_INFO3 (0xf8100780, | |
| 7907 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7908 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7909 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7910 | CSKY_ISA_VDSP), | |
| 7911 | OP32 ("vshl.u32", | |
| 7912 | OPCODE_INFO3 (0xfa000780, | |
| 7913 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7914 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7915 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7916 | CSKY_ISA_VDSP), | |
| 7917 | OP32 ("vshl.s8", | |
| 7918 | OPCODE_INFO3 (0xf8000790, | |
| 7919 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7920 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7921 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7922 | CSKY_ISA_VDSP), | |
| 7923 | OP32 ("vshl.s16", | |
| 7924 | OPCODE_INFO3 (0xf8100790, | |
| 7925 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7926 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7927 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7928 | CSKY_ISA_VDSP), | |
| 7929 | OP32 ("vshl.s32", | |
| 7930 | OPCODE_INFO3 (0xfa000790, | |
| 7931 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7932 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7933 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7934 | CSKY_ISA_VDSP), | |
| 7935 | OP32 ("vshl.u8.s", | |
| 7936 | OPCODE_INFO3 (0xf80007c0, | |
| 7937 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7938 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7939 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7940 | CSKY_ISA_VDSP), | |
| 7941 | OP32 ("vshl.u16.s", | |
| 7942 | OPCODE_INFO3 (0xf81007c0, | |
| 7943 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7944 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7945 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7946 | CSKY_ISA_VDSP), | |
| 7947 | OP32 ("vshl.u32.s", | |
| 7948 | OPCODE_INFO3 (0xfa0007c0, | |
| 7949 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7950 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7951 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7952 | CSKY_ISA_VDSP), | |
| 7953 | OP32 ("vshl.s8.s", | |
| 7954 | OPCODE_INFO3 (0xf80007d0, | |
| 7955 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7956 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7957 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7958 | CSKY_ISA_VDSP), | |
| 7959 | OP32 ("vshl.s16.s", | |
| 7960 | OPCODE_INFO3 (0xf81007d0, | |
| 7961 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7962 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7963 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7964 | CSKY_ISA_VDSP), | |
| 7965 | OP32 ("vshl.s32.s", | |
| 7966 | OPCODE_INFO3 (0xfa0007d0, | |
| 7967 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7968 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7969 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7970 | CSKY_ISA_VDSP), | |
| 7971 | OP32 ("vcmphs.u8", | |
| 7972 | OPCODE_INFO3 (0xf8000800, | |
| 7973 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7974 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7975 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7976 | CSKY_ISA_VDSP), | |
| 7977 | OP32 ("vcmphs.u16", | |
| 7978 | OPCODE_INFO3 (0xf8100800, | |
| 7979 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7980 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7981 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7982 | CSKY_ISA_VDSP), | |
| 7983 | OP32 ("vcmphs.u32", | |
| 7984 | OPCODE_INFO3 (0xfa000800, | |
| 7985 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7986 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7987 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7988 | CSKY_ISA_VDSP), | |
| 7989 | OP32 ("vcmphs.s8", | |
| 7990 | OPCODE_INFO3 (0xf8000810, | |
| 7991 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7992 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7993 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 7994 | CSKY_ISA_VDSP), | |
| 7995 | OP32 ("vcmphs.s16", | |
| 7996 | OPCODE_INFO3 (0xf8100810, | |
| 7997 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 7998 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 7999 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8000 | CSKY_ISA_VDSP), | |
| 8001 | OP32 ("vcmphs.s32", | |
| 8002 | OPCODE_INFO3 (0xfa000810, | |
| 8003 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8004 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8005 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8006 | CSKY_ISA_VDSP), | |
| 8007 | OP32 ("vcmplt.u8", | |
| 8008 | OPCODE_INFO3 (0xf8000820, | |
| 8009 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8010 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8011 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8012 | CSKY_ISA_VDSP), | |
| 8013 | OP32 ("vcmplt.u16", | |
| 8014 | OPCODE_INFO3 (0xf8100820, | |
| 8015 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8016 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8017 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8018 | CSKY_ISA_VDSP), | |
| 8019 | OP32 ("vcmplt.u32", | |
| 8020 | OPCODE_INFO3 (0xfa000820, | |
| 8021 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8022 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8023 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8024 | CSKY_ISA_VDSP), | |
| 8025 | OP32 ("vcmplt.s8", | |
| 8026 | OPCODE_INFO3 (0xf8000830, | |
| 8027 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8028 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8029 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8030 | CSKY_ISA_VDSP), | |
| 8031 | OP32 ("vcmplt.s16", | |
| 8032 | OPCODE_INFO3 (0xf8100830, | |
| 8033 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8034 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8035 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8036 | CSKY_ISA_VDSP), | |
| 8037 | OP32 ("vcmplt.s32", | |
| 8038 | OPCODE_INFO3 (0xfa000830, | |
| 8039 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8040 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8041 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8042 | CSKY_ISA_VDSP), | |
| 8043 | OP32 ("vcmpne.u8", | |
| 8044 | OPCODE_INFO3 (0xf8000840, | |
| 8045 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8046 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8047 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8048 | CSKY_ISA_VDSP), | |
| 8049 | OP32 ("vcmpne.u16", | |
| 8050 | OPCODE_INFO3 (0xf8100840, | |
| 8051 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8052 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8053 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8054 | CSKY_ISA_VDSP), | |
| 8055 | OP32 ("vcmpne.u32", | |
| 8056 | OPCODE_INFO3 (0xfa000840, | |
| 8057 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8058 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8059 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8060 | CSKY_ISA_VDSP), | |
| 8061 | OP32 ("vcmpne.s8", | |
| 8062 | OPCODE_INFO3 (0xf8000850, | |
| 8063 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8064 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8065 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8066 | CSKY_ISA_VDSP), | |
| 8067 | OP32 ("vcmpne.s16", | |
| 8068 | OPCODE_INFO3 (0xf8100850, | |
| 8069 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8070 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8071 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8072 | CSKY_ISA_VDSP), | |
| 8073 | OP32 ("vcmpne.s32", | |
| 8074 | OPCODE_INFO3 (0xfa000850, | |
| 8075 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8076 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8077 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8078 | CSKY_ISA_VDSP), | |
| 8079 | OP32 ("vmax.u8", | |
| 8080 | OPCODE_INFO3 (0xf8000900, | |
| 8081 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8082 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8083 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8084 | CSKY_ISA_VDSP), | |
| 8085 | OP32 ("vmax.u16", | |
| 8086 | OPCODE_INFO3 (0xf8100900, | |
| 8087 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8088 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8089 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8090 | CSKY_ISA_VDSP), | |
| 8091 | OP32 ("vmax.u32", | |
| 8092 | OPCODE_INFO3 (0xfa000900, | |
| 8093 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8094 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8095 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8096 | CSKY_ISA_VDSP), | |
| 8097 | OP32 ("vmax.s8", | |
| 8098 | OPCODE_INFO3 (0xf8000910, | |
| 8099 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8100 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8101 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8102 | CSKY_ISA_VDSP), | |
| 8103 | OP32 ("vmax.s16", | |
| 8104 | OPCODE_INFO3 (0xf8100910, | |
| 8105 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8106 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8107 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8108 | CSKY_ISA_VDSP), | |
| 8109 | OP32 ("vmax.s32", | |
| 8110 | OPCODE_INFO3 (0xfa000910, | |
| 8111 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8112 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8113 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8114 | CSKY_ISA_VDSP), | |
| 8115 | OP32 ("vmin.u8", | |
| 8116 | OPCODE_INFO3 (0xf8000920, | |
| 8117 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8118 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8119 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8120 | CSKY_ISA_VDSP), | |
| 8121 | OP32 ("vmin.u16", | |
| 8122 | OPCODE_INFO3 (0xf8100920, | |
| 8123 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8124 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8125 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8126 | CSKY_ISA_VDSP), | |
| 8127 | OP32 ("vmin.u32", | |
| 8128 | OPCODE_INFO3 (0xfa000920, | |
| 8129 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8130 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8131 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8132 | CSKY_ISA_VDSP), | |
| 8133 | OP32 ("vmin.s8", | |
| 8134 | OPCODE_INFO3 (0xf8000930, | |
| 8135 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8136 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8137 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8138 | CSKY_ISA_VDSP), | |
| 8139 | OP32 ("vmin.s16", | |
| 8140 | OPCODE_INFO3 (0xf8100930, | |
| 8141 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8142 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8143 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8144 | CSKY_ISA_VDSP), | |
| 8145 | OP32 ("vmin.s32", | |
| 8146 | OPCODE_INFO3 (0xfa000930, | |
| 8147 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8148 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8149 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8150 | CSKY_ISA_VDSP), | |
| 8151 | OP32 ("vcmax.u8", | |
| 8152 | OPCODE_INFO3 (0xf8000980, | |
| 8153 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8154 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8155 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8156 | CSKY_ISA_VDSP), | |
| 8157 | OP32 ("vcmax.u16", | |
| 8158 | OPCODE_INFO3 (0xf8100980, | |
| 8159 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8160 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8161 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8162 | CSKY_ISA_VDSP), | |
| 8163 | OP32 ("vcmax.u32", | |
| 8164 | OPCODE_INFO3 (0xfa000980, | |
| 8165 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8166 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8167 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8168 | CSKY_ISA_VDSP), | |
| 8169 | OP32 ("vcmax.s8", | |
| 8170 | OPCODE_INFO3 (0xf8000990, | |
| 8171 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8172 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8173 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8174 | CSKY_ISA_VDSP), | |
| 8175 | OP32 ("vcmax.s16", | |
| 8176 | OPCODE_INFO3 (0xf8100990, | |
| 8177 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8178 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8179 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8180 | CSKY_ISA_VDSP), | |
| 8181 | OP32 ("vcmax.s32", | |
| 8182 | OPCODE_INFO3 (0xfa000990, | |
| 8183 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8184 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8185 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8186 | CSKY_ISA_VDSP), | |
| 8187 | OP32 ("vcmin.u8", | |
| 8188 | OPCODE_INFO3 (0xf80009a0, | |
| 8189 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8190 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8191 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8192 | CSKY_ISA_VDSP), | |
| 8193 | OP32 ("vcmin.u16", | |
| 8194 | OPCODE_INFO3 (0xf81009a0, | |
| 8195 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8196 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8197 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8198 | CSKY_ISA_VDSP), | |
| 8199 | OP32 ("vcmin.u32", | |
| 8200 | OPCODE_INFO3 (0xfa0009a0, | |
| 8201 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8202 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8203 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8204 | CSKY_ISA_VDSP), | |
| 8205 | OP32 ("vcmin.s8", | |
| 8206 | OPCODE_INFO3 (0xf80009b0, | |
| 8207 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8208 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8209 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8210 | CSKY_ISA_VDSP), | |
| 8211 | OP32 ("vcmin.s16", | |
| 8212 | OPCODE_INFO3 (0xf81009b0, | |
| 8213 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8214 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8215 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8216 | CSKY_ISA_VDSP), | |
| 8217 | OP32 ("vcmin.s32", | |
| 8218 | OPCODE_INFO3 (0xfa0009b0, | |
| 8219 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8220 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8221 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8222 | CSKY_ISA_VDSP), | |
| 8223 | OP32 ("vand.8", | |
| 8224 | OPCODE_INFO3 (0xf8000a00, | |
| 8225 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8226 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8227 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8228 | CSKY_ISA_VDSP), | |
| 8229 | OP32 ("vand.16", | |
| 8230 | OPCODE_INFO3 (0xf8100a00, | |
| 8231 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8232 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8233 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8234 | CSKY_ISA_VDSP), | |
| 8235 | OP32 ("vand.32", | |
| 8236 | OPCODE_INFO3 (0xfa000a00, | |
| 8237 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8238 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8239 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8240 | CSKY_ISA_VDSP), | |
| 8241 | OP32 ("vandn.8", | |
| 8242 | OPCODE_INFO3 (0xf8000a20, | |
| 8243 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8244 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8245 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8246 | CSKY_ISA_VDSP), | |
| 8247 | OP32 ("vandn.16", | |
| 8248 | OPCODE_INFO3 (0xf8100a20, | |
| 8249 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8250 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8251 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8252 | CSKY_ISA_VDSP), | |
| 8253 | OP32 ("vandn.32", | |
| 8254 | OPCODE_INFO3 (0xfa000a20, | |
| 8255 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8256 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8257 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8258 | CSKY_ISA_VDSP), | |
| 8259 | OP32 ("vor.8", | |
| 8260 | OPCODE_INFO3 (0xf8000a40, | |
| 8261 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8262 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8263 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8264 | CSKY_ISA_VDSP), | |
| 8265 | OP32 ("vor.16", | |
| 8266 | OPCODE_INFO3 (0xf8100a40, | |
| 8267 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8268 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8269 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8270 | CSKY_ISA_VDSP), | |
| 8271 | OP32 ("vor.32", | |
| 8272 | OPCODE_INFO3 (0xfa000a40, | |
| 8273 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8274 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8275 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8276 | CSKY_ISA_VDSP), | |
| 8277 | OP32 ("vnor.8", | |
| 8278 | OPCODE_INFO3 (0xf8000a60, | |
| 8279 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8280 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8281 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8282 | CSKY_ISA_VDSP), | |
| 8283 | OP32 ("vnor.16", | |
| 8284 | OPCODE_INFO3 (0xf8100a60, | |
| 8285 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8286 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8287 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8288 | CSKY_ISA_VDSP), | |
| 8289 | OP32 ("vnor.32", | |
| 8290 | OPCODE_INFO3 (0xfa000a60, | |
| 8291 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8292 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8293 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8294 | CSKY_ISA_VDSP), | |
| 8295 | OP32 ("vxor.8", | |
| 8296 | OPCODE_INFO3 (0xf8000a80, | |
| 8297 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8298 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8299 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8300 | CSKY_ISA_VDSP), | |
| 8301 | OP32 ("vxor.16", | |
| 8302 | OPCODE_INFO3 (0xf8100a80, | |
| 8303 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8304 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8305 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8306 | CSKY_ISA_VDSP), | |
| 8307 | OP32 ("vxor.32", | |
| 8308 | OPCODE_INFO3 (0xfa000a80, | |
| 8309 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8310 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8311 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8312 | CSKY_ISA_VDSP), | |
| 8313 | OP32 ("vtst.8", | |
| 8314 | OPCODE_INFO3 (0xf8000b20, | |
| 8315 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8316 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8317 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8318 | CSKY_ISA_VDSP), | |
| 8319 | OP32 ("vtst.16", | |
| 8320 | OPCODE_INFO3 (0xf8100b20, | |
| 8321 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8322 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8323 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8324 | CSKY_ISA_VDSP), | |
| 8325 | OP32 ("vtst.32", | |
| 8326 | OPCODE_INFO3 (0xfa000b20, | |
| 8327 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8328 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8329 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8330 | CSKY_ISA_VDSP), | |
| 8331 | OP32 ("vbpermz.8", | |
| 8332 | OPCODE_INFO3 (0xf8000f00, | |
| 8333 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8334 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8335 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8336 | CSKY_ISA_VDSP), | |
| 8337 | OP32 ("vbpermz.16", | |
| 8338 | OPCODE_INFO3 (0xf8100f00, | |
| 8339 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8340 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8341 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8342 | CSKY_ISA_VDSP), | |
| 8343 | OP32 ("vbpermz.32", | |
| 8344 | OPCODE_INFO3 (0xfa000f00, | |
| 8345 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8346 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8347 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8348 | CSKY_ISA_VDSP), | |
| 8349 | OP32 ("vbperm.8", | |
| 8350 | OPCODE_INFO3 (0xf8000f20, | |
| 8351 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8352 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8353 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8354 | CSKY_ISA_VDSP), | |
| 8355 | OP32 ("vbperm.16", | |
| 8356 | OPCODE_INFO3 (0xf8100f20, | |
| 8357 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8358 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8359 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8360 | CSKY_ISA_VDSP), | |
| 8361 | OP32 ("vbperm.32", | |
| 8362 | OPCODE_INFO3 (0xfa000f20, | |
| 8363 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8364 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8365 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8366 | CSKY_ISA_VDSP), | |
| 8367 | OP32 ("vdch.8", | |
| 8368 | OPCODE_INFO3 (0xf8000fc0, | |
| 8369 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8370 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8371 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8372 | CSKY_ISA_VDSP), | |
| 8373 | OP32 ("vdch.16", | |
| 8374 | OPCODE_INFO3 (0xf8100fc0, | |
| 8375 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8376 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8377 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8378 | CSKY_ISA_VDSP), | |
| 8379 | OP32 ("vdch.32", | |
| 8380 | OPCODE_INFO3 (0xfa000fc0, | |
| 8381 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8382 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8383 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8384 | CSKY_ISA_VDSP), | |
| 8385 | OP32 ("vdcl.8", | |
| 8386 | OPCODE_INFO3 (0xf8000fe0, | |
| 8387 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8388 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8389 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8390 | CSKY_ISA_VDSP), | |
| 8391 | OP32 ("vdcl.16", | |
| 8392 | OPCODE_INFO3 (0xf8100fe0, | |
| 8393 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8394 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8395 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8396 | CSKY_ISA_VDSP), | |
| 8397 | OP32 ("vdcl.32", | |
| 8398 | OPCODE_INFO3 (0xfa000fe0, | |
| 8399 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8400 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8401 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8402 | CSKY_ISA_VDSP), | |
| 8403 | OP32 ("vich.8", | |
| 8404 | OPCODE_INFO3 (0xf8000f80, | |
| 8405 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8406 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8407 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8408 | CSKY_ISA_VDSP), | |
| 8409 | OP32 ("vich.16", | |
| 8410 | OPCODE_INFO3 (0xf8100f80, | |
| 8411 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8412 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8413 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8414 | CSKY_ISA_VDSP), | |
| 8415 | OP32 ("vich.32", | |
| 8416 | OPCODE_INFO3 (0xfa000f80, | |
| 8417 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8418 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8419 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8420 | CSKY_ISA_VDSP), | |
| 8421 | OP32 ("vicl.8", | |
| 8422 | OPCODE_INFO3 (0xf8000fa0, | |
| 8423 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8424 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8425 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8426 | CSKY_ISA_VDSP), | |
| 8427 | OP32 ("vicl.16", | |
| 8428 | OPCODE_INFO3 (0xf8100fa0, | |
| 8429 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8430 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8431 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8432 | CSKY_ISA_VDSP), | |
| 8433 | OP32 ("vicl.32", | |
| 8434 | OPCODE_INFO3 (0xfa000fa0, | |
| 8435 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
| 8436 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
| 8437 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
| 8438 | CSKY_ISA_VDSP), | |
| 8439 | ||
| 1feede9b CQ |
8440 | #define OPRND_SHIFT0(mask, type) (mask, type, OPRND_SHIFT_0_BIT) |
| 8441 | #define OPRND_SHIFT1(mask, type) (mask, type, OPRND_SHIFT_1_BIT) | |
| 8442 | #define OPRND_SHIFT2(mask, type) (mask, type, OPRND_SHIFT_2_BIT) | |
| 8443 | #define OPRND_SHIFT3(mask, type) (mask, type, OPRND_SHIFT_3_BIT) | |
| 8444 | #define OPRND_SHIFT4(mask, type) (mask, type, OPRND_SHIFT_4_BIT) | |
| 8445 | ||
| 8446 | /* The followings are 860 floating instructions. */ | |
| 8447 | OP32 ("fadd.16", | |
| 8448 | OPCODE_INFO3 (0xf400c800, | |
| 8449 | OPRND_SHIFT0 (0_4, FREG), | |
| 8450 | OPRND_SHIFT0 (16_20, FREG), | |
| 8451 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8452 | CSKY_ISA_FLOAT_7E60), | |
| 8453 | OP32 ("faddh", | |
| 8454 | OPCODE_INFO3 (0xf400c800, | |
| 8455 | OPRND_SHIFT0 (0_4, FREG), | |
| 8456 | OPRND_SHIFT0 (16_20, FREG), | |
| 8457 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8458 | CSKY_ISA_FLOAT_7E60), | |
| 8459 | OP32 ("fsub.16", | |
| 8460 | OPCODE_INFO3 (0xf400c820, | |
| 8461 | OPRND_SHIFT0 (0_4, FREG), | |
| 8462 | OPRND_SHIFT0 (16_20, FREG), | |
| 8463 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8464 | CSKY_ISA_FLOAT_7E60), | |
| 8465 | OP32 ("fsubh", | |
| 8466 | OPCODE_INFO3 (0xf400c820, | |
| 8467 | OPRND_SHIFT0 (0_4, FREG), | |
| 8468 | OPRND_SHIFT0 (16_20, FREG), | |
| 8469 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8470 | CSKY_ISA_FLOAT_7E60), | |
| 8471 | OP32 ("fmov.16", | |
| 8472 | OPCODE_INFO2 (0xf400c880, | |
| 8473 | OPRND_SHIFT0 (0_4, FREG), | |
| 8474 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8475 | CSKY_ISA_FLOAT_7E60), | |
| 8476 | OP32 ("fmovh", | |
| 8477 | OPCODE_INFO2 (0xf400c880, | |
| 8478 | OPRND_SHIFT0 (0_4, FREG), | |
| 8479 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8480 | CSKY_ISA_FLOAT_7E60), | |
| 8481 | OP32 ("fabs.16", | |
| 8482 | OPCODE_INFO2 (0xf400c8c0, | |
| 8483 | OPRND_SHIFT0 (0_4, FREG), | |
| 8484 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8485 | CSKY_ISA_FLOAT_7E60), | |
| 8486 | OP32 ("fabsh", | |
| 8487 | OPCODE_INFO2 (0xf400c8c0, | |
| 8488 | OPRND_SHIFT0 (0_4, FREG), | |
| 8489 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8490 | CSKY_ISA_FLOAT_7E60), | |
| 8491 | OP32 ("fneg.16", | |
| 8492 | OPCODE_INFO2 (0xf400c8e0, | |
| 8493 | OPRND_SHIFT0 (0_4, FREG), | |
| 8494 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8495 | CSKY_ISA_FLOAT_7E60), | |
| 8496 | OP32 ("fnegh", | |
| 8497 | OPCODE_INFO2 (0xf400c8e0, | |
| 8498 | OPRND_SHIFT0 (0_4, FREG), | |
| 8499 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8500 | CSKY_ISA_FLOAT_7E60), | |
| 8501 | OP32 ("fcmphsz.16", | |
| 8502 | OPCODE_INFO1 (0xf400c900, | |
| 8503 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8504 | CSKY_ISA_FLOAT_7E60), | |
| 8505 | OP32 ("fcmpzhsh", | |
| 8506 | OPCODE_INFO1 (0xf400c900, | |
| 8507 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8508 | CSKY_ISA_FLOAT_7E60), | |
| 8509 | OP32 ("fcmpltz.16", | |
| 8510 | OPCODE_INFO1 (0xf400c920, | |
| 8511 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8512 | CSKY_ISA_FLOAT_7E60), | |
| 8513 | OP32 ("fcmpzlth", | |
| 8514 | OPCODE_INFO1 (0xf400c920, | |
| 8515 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8516 | CSKY_ISA_FLOAT_7E60), | |
| 8517 | OP32 ("fcmpnez.16", | |
| 8518 | OPCODE_INFO1 (0xf400c940, | |
| 8519 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8520 | CSKY_ISA_FLOAT_7E60), | |
| 8521 | OP32 ("fcmpzneh", | |
| 8522 | OPCODE_INFO1 (0xf400c940, | |
| 8523 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8524 | CSKY_ISA_FLOAT_7E60), | |
| 8525 | OP32 ("fcmpuoz.16", | |
| 8526 | OPCODE_INFO1 (0xf400c960, | |
| 8527 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8528 | CSKY_ISA_FLOAT_7E60), | |
| 8529 | OP32 ("fcmpzuoh", | |
| 8530 | OPCODE_INFO1 (0xf400c960, | |
| 8531 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8532 | CSKY_ISA_FLOAT_7E60), | |
| 8533 | OP32 ("fcmphs.16", | |
| 8534 | OPCODE_INFO2 (0xf400c980, | |
| 8535 | OPRND_SHIFT0 (16_20, FREG), | |
| 8536 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8537 | CSKY_ISA_FLOAT_7E60), | |
| 8538 | OP32 ("fcmphsh", | |
| 8539 | OPCODE_INFO2 (0xf400c980, | |
| 8540 | OPRND_SHIFT0 (16_20, FREG), | |
| 8541 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8542 | CSKY_ISA_FLOAT_7E60), | |
| 8543 | OP32 ("fcmplt.16", | |
| 8544 | OPCODE_INFO2 (0xf400c9a0, | |
| 8545 | OPRND_SHIFT0 (16_20, FREG), | |
| 8546 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8547 | CSKY_ISA_FLOAT_7E60), | |
| 8548 | OP32 ("fcmpne.16", | |
| 8549 | OPCODE_INFO2 (0xf400c9c0, | |
| 8550 | OPRND_SHIFT0 (16_20, FREG), | |
| 8551 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8552 | CSKY_ISA_FLOAT_7E60), | |
| 8553 | OP32 ("fcmpneh", | |
| 8554 | OPCODE_INFO2 (0xf400c9c0, | |
| 8555 | OPRND_SHIFT0 (16_20, FREG), | |
| 8556 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8557 | CSKY_ISA_FLOAT_7E60), | |
| 8558 | OP32 ("fcmpuo.16", | |
| 8559 | OPCODE_INFO2 (0xf400c9e0, | |
| 8560 | OPRND_SHIFT0 (16_20, FREG), | |
| 8561 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8562 | CSKY_ISA_FLOAT_7E60), | |
| 8563 | OP32 ("fcmpuoh", | |
| 8564 | OPCODE_INFO2 (0xf400c9e0, | |
| 8565 | OPRND_SHIFT0 (16_20, FREG), | |
| 8566 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8567 | CSKY_ISA_FLOAT_7E60), | |
| 8568 | OP32 ("fmaxnm.16", | |
| 8569 | OPCODE_INFO3 (0xf400cd00, | |
| 8570 | OPRND_SHIFT0 (0_4, FREG), | |
| 8571 | OPRND_SHIFT0 (16_20, FREG), | |
| 8572 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8573 | CSKY_ISA_FLOAT_7E60), | |
| 8574 | OP32 ("fminnm.16", | |
| 8575 | OPCODE_INFO3 (0xf400cd20, | |
| 8576 | OPRND_SHIFT0 (0_4, FREG), | |
| 8577 | OPRND_SHIFT0 (16_20, FREG), | |
| 8578 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8579 | CSKY_ISA_FLOAT_7E60), | |
| 8580 | OP32 ("fcmphz.16", | |
| 8581 | OPCODE_INFO1 (0xf400cd40, | |
| 8582 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8583 | CSKY_ISA_FLOAT_7E60), | |
| 8584 | OP32 ("fcmplsz.16", | |
| 8585 | OPCODE_INFO1 (0xf400cd60, | |
| 8586 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8587 | CSKY_ISA_FLOAT_7E60), | |
| 8588 | OP32 ("fmul.16", | |
| 8589 | OPCODE_INFO3 (0xf400ca00, | |
| 8590 | OPRND_SHIFT0 (0_4, FREG), | |
| 8591 | OPRND_SHIFT0 (16_20, FREG), | |
| 8592 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8593 | CSKY_ISA_FLOAT_7E60), | |
| 8594 | OP32 ("fmulh", | |
| 8595 | OPCODE_INFO3 (0xf400ca00, | |
| 8596 | OPRND_SHIFT0 (0_4, FREG), | |
| 8597 | OPRND_SHIFT0 (16_20, FREG), | |
| 8598 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8599 | CSKY_ISA_FLOAT_7E60), | |
| 8600 | OP32 ("fnmul.16", | |
| 8601 | OPCODE_INFO3 (0xf400ca20, | |
| 8602 | OPRND_SHIFT0 (0_4, FREG), | |
| 8603 | OPRND_SHIFT0 (16_20, FREG), | |
| 8604 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8605 | CSKY_ISA_FLOAT_7E60), | |
| 8606 | OP32 ("fnmulh", | |
| 8607 | OPCODE_INFO3 (0xf400ca20, | |
| 8608 | OPRND_SHIFT0 (0_4, FREG), | |
| 8609 | OPRND_SHIFT0 (16_20, FREG), | |
| 8610 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8611 | CSKY_ISA_FLOAT_7E60), | |
| 8612 | OP32 ("fmula.16", | |
| 8613 | OPCODE_INFO3 (0xf400ca80, | |
| 8614 | OPRND_SHIFT0 (0_4, FREG), | |
| 8615 | OPRND_SHIFT0 (16_20, FREG), | |
| 8616 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8617 | CSKY_ISA_FLOAT_7E60), | |
| 8618 | OP32 ("fmach", | |
| 8619 | OPCODE_INFO3 (0xf400ca80, | |
| 8620 | OPRND_SHIFT0 (0_4, FREG), | |
| 8621 | OPRND_SHIFT0 (16_20, FREG), | |
| 8622 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8623 | CSKY_ISA_FLOAT_7E60), | |
| 8624 | OP32 ("fnmuls.16", | |
| 8625 | OPCODE_INFO3 (0xf400caa0, | |
| 8626 | OPRND_SHIFT0 (0_4, FREG), | |
| 8627 | OPRND_SHIFT0 (16_20, FREG), | |
| 8628 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8629 | CSKY_ISA_FLOAT_7E60), | |
| 8630 | OP32 ("fmsch", | |
| 8631 | OPCODE_INFO3 (0xf400caa0, | |
| 8632 | OPRND_SHIFT0 (0_4, FREG), | |
| 8633 | OPRND_SHIFT0 (16_20, FREG), | |
| 8634 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8635 | CSKY_ISA_FLOAT_7E60), | |
| 8636 | OP32 ("fmuls.16", | |
| 8637 | OPCODE_INFO3 (0xf400cac0, | |
| 8638 | OPRND_SHIFT0 (0_4, FREG), | |
| 8639 | OPRND_SHIFT0 (16_20, FREG), | |
| 8640 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8641 | CSKY_ISA_FLOAT_7E60), | |
| 8642 | OP32 ("fnmach", | |
| 8643 | OPCODE_INFO3 (0xf400cac0, | |
| 8644 | OPRND_SHIFT0 (0_4, FREG), | |
| 8645 | OPRND_SHIFT0 (16_20, FREG), | |
| 8646 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8647 | CSKY_ISA_FLOAT_7E60), | |
| 8648 | OP32 ("fnmula.16", | |
| 8649 | OPCODE_INFO3 (0xf400cae0, | |
| 8650 | OPRND_SHIFT0 (0_4, FREG), | |
| 8651 | OPRND_SHIFT0 (16_20, FREG), | |
| 8652 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8653 | CSKY_ISA_FLOAT_7E60), | |
| 8654 | OP32 ("fnmsch", | |
| 8655 | OPCODE_INFO3 (0xf400cae0, | |
| 8656 | OPRND_SHIFT0 (0_4, FREG), | |
| 8657 | OPRND_SHIFT0 (16_20, FREG), | |
| 8658 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8659 | CSKY_ISA_FLOAT_7E60), | |
| 8660 | OP32 ("ffmula.16", | |
| 8661 | OPCODE_INFO3 (0xf400ce00, | |
| 8662 | OPRND_SHIFT0 (0_4, FREG), | |
| 8663 | OPRND_SHIFT0 (16_20, FREG), | |
| 8664 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8665 | CSKY_ISA_FLOAT_7E60), | |
| 8666 | OP32 ("ffmuls.16", | |
| 8667 | OPCODE_INFO3 (0xf400ce20, | |
| 8668 | OPRND_SHIFT0 (0_4, FREG), | |
| 8669 | OPRND_SHIFT0 (16_20, FREG), | |
| 8670 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8671 | CSKY_ISA_FLOAT_7E60), | |
| 8672 | OP32 ("ffnmula.16", | |
| 8673 | OPCODE_INFO3 (0xf400ce40, | |
| 8674 | OPRND_SHIFT0 (0_4, FREG), | |
| 8675 | OPRND_SHIFT0 (16_20, FREG), | |
| 8676 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8677 | CSKY_ISA_FLOAT_7E60), | |
| 8678 | OP32 ("ffnmuls.16", | |
| 8679 | OPCODE_INFO3 (0xf400ce60, | |
| 8680 | OPRND_SHIFT0 (0_4, FREG), | |
| 8681 | OPRND_SHIFT0 (16_20, FREG), | |
| 8682 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8683 | CSKY_ISA_FLOAT_7E60), | |
| 8684 | OP32 ("fdivh", | |
| 8685 | OPCODE_INFO3 (0xf400cb00, | |
| 8686 | OPRND_SHIFT0 (0_4, FREG), | |
| 8687 | OPRND_SHIFT0 (16_20, FREG), | |
| 8688 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8689 | CSKY_ISA_FLOAT_7E60), | |
| 8690 | OP32 ("fdiv.16", | |
| 8691 | OPCODE_INFO3 (0xf400cb00, | |
| 8692 | OPRND_SHIFT0 (0_4, FREG), | |
| 8693 | OPRND_SHIFT0 (16_20, FREG), | |
| 8694 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8695 | CSKY_ISA_FLOAT_7E60), | |
| 8696 | OP32 ("freciph", | |
| 8697 | OPCODE_INFO2 (0xf400cb20, | |
| 8698 | OPRND_SHIFT0 (0_4, FREG), | |
| 8699 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8700 | CSKY_ISA_FLOAT_7E60), | |
| 8701 | OP32 ("frecip.16", | |
| 8702 | OPCODE_INFO2 (0xf400cb20, | |
| 8703 | OPRND_SHIFT0 (0_4, FREG), | |
| 8704 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8705 | CSKY_ISA_FLOAT_7E60), | |
| 8706 | OP32 ("fsqrt.16", | |
| 8707 | OPCODE_INFO2 (0xf400cb40, | |
| 8708 | OPRND_SHIFT0 (0_4, FREG), | |
| 8709 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8710 | CSKY_ISA_FLOAT_7E60), | |
| 8711 | OP32 ("fsqrth", | |
| 8712 | OPCODE_INFO2 (0xf400cb40, | |
| 8713 | OPRND_SHIFT0 (0_4, FREG), | |
| 8714 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8715 | CSKY_ISA_FLOAT_7E60), | |
| 8716 | OP32 ("fsel.16", | |
| 8717 | OPCODE_INFO3 (0xf400cf20, | |
| 8718 | OPRND_SHIFT0 (0_4, FREG), | |
| 8719 | OPRND_SHIFT0 (16_20, FREG), | |
| 8720 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8721 | CSKY_ISA_FLOAT_7E60), | |
| 8722 | /* Single floating. */ | |
| 8723 | OP32 ("fadd.32", | |
| 8724 | OPCODE_INFO3 (0xf4000000, | |
| 8725 | OPRND_SHIFT0 (0_4, FREG), | |
| 8726 | OPRND_SHIFT0 (16_20, FREG), | |
| 8727 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8728 | CSKY_ISA_FLOAT_7E60), | |
| 8729 | OP32 ("fadds", | |
| 8730 | OPCODE_INFO3 (0xf4000000, | |
| 8731 | OPRND_SHIFT0 (0_4, FREG), | |
| 8732 | OPRND_SHIFT0 (16_20, FREG), | |
| 8733 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8734 | CSKY_ISA_FLOAT_7E60), | |
| 8735 | OP32 ("fsub.32", | |
| 8736 | OPCODE_INFO3 (0xf4000020, | |
| 8737 | OPRND_SHIFT0 (0_4, FREG), | |
| 8738 | OPRND_SHIFT0 (16_20, FREG), | |
| 8739 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8740 | CSKY_ISA_FLOAT_7E60), | |
| 8741 | OP32 ("fsubs", | |
| 8742 | OPCODE_INFO3 (0xf4000020, | |
| 8743 | OPRND_SHIFT0 (0_4, FREG), | |
| 8744 | OPRND_SHIFT0 (16_20, FREG), | |
| 8745 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8746 | CSKY_ISA_FLOAT_7E60), | |
| 8747 | OP32 ("fmov.32", | |
| 8748 | OPCODE_INFO2 (0xf4000080, | |
| 8749 | OPRND_SHIFT0 (0_4, FREG), | |
| 8750 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8751 | CSKY_ISA_FLOAT_7E60), | |
| 8752 | OP32 ("fmovs", | |
| 8753 | OPCODE_INFO2 (0xf4000080, | |
| 8754 | OPRND_SHIFT0 (0_4, FREG), | |
| 8755 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8756 | CSKY_ISA_FLOAT_7E60), | |
| 8757 | OP32 ("fabs.32", | |
| 8758 | OPCODE_INFO2 (0xf40000c0, | |
| 8759 | OPRND_SHIFT0 (0_4, FREG), | |
| 8760 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8761 | CSKY_ISA_FLOAT_7E60), | |
| 8762 | OP32 ("fabss", | |
| 8763 | OPCODE_INFO2 (0xf40000c0, | |
| 8764 | OPRND_SHIFT0 (0_4, FREG), | |
| 8765 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8766 | CSKY_ISA_FLOAT_7E60), | |
| 8767 | OP32 ("fneg.32", | |
| 8768 | OPCODE_INFO2 (0xf40000e0, | |
| 8769 | OPRND_SHIFT0 (0_4, FREG), | |
| 8770 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8771 | CSKY_ISA_FLOAT_7E60), | |
| 8772 | OP32 ("fnegs", | |
| 8773 | OPCODE_INFO2 (0xf40000e0, | |
| 8774 | OPRND_SHIFT0 (0_4, FREG), | |
| 8775 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8776 | CSKY_ISA_FLOAT_7E60), | |
| 8777 | OP32 ("fcmphsz.32", | |
| 8778 | OPCODE_INFO1 (0xf4000100, | |
| 8779 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8780 | CSKY_ISA_FLOAT_7E60), | |
| 8781 | OP32 ("fcmpzhss", | |
| 8782 | OPCODE_INFO1 (0xf4000100, | |
| 8783 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8784 | CSKY_ISA_FLOAT_7E60), | |
| 8785 | OP32 ("fcmpltz.32", | |
| 8786 | OPCODE_INFO1 (0xf4000120, | |
| 8787 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8788 | CSKY_ISA_FLOAT_7E60), | |
| 8789 | OP32 ("fcmpzlts", | |
| 8790 | OPCODE_INFO1 (0xf4000120, | |
| 8791 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8792 | CSKY_ISA_FLOAT_7E60), | |
| 8793 | OP32 ("fcmpnez.32", | |
| 8794 | OPCODE_INFO1 (0xf4000140, | |
| 8795 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8796 | CSKY_ISA_FLOAT_7E60), | |
| 8797 | OP32 ("fcmpznes", | |
| 8798 | OPCODE_INFO1 (0xf4000140, | |
| 8799 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8800 | CSKY_ISA_FLOAT_7E60), | |
| 8801 | OP32 ("fcmpuoz.32", | |
| 8802 | OPCODE_INFO1 (0xf4000160, | |
| 8803 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8804 | CSKY_ISA_FLOAT_7E60), | |
| 8805 | OP32 ("fcmpzuos", | |
| 8806 | OPCODE_INFO1 (0xf4000160, | |
| 8807 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8808 | CSKY_ISA_FLOAT_7E60), | |
| 8809 | OP32 ("fcmphs.32", | |
| 8810 | OPCODE_INFO2 (0xf4000180, | |
| 8811 | OPRND_SHIFT0 (16_20, FREG), | |
| 8812 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8813 | CSKY_ISA_FLOAT_7E60), | |
| 8814 | OP32 ("fcmphss", | |
| 8815 | OPCODE_INFO2 (0xf4000180, | |
| 8816 | OPRND_SHIFT0 (16_20, FREG), | |
| 8817 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8818 | CSKY_ISA_FLOAT_7E60), | |
| 8819 | OP32 ("fcmplt.32", | |
| 8820 | OPCODE_INFO2 (0xf40001a0, | |
| 8821 | OPRND_SHIFT0 (16_20, FREG), | |
| 8822 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8823 | CSKY_ISA_FLOAT_7E60), | |
| 8824 | OP32 ("fcmplts", | |
| 8825 | OPCODE_INFO2 (0xf40001a0, | |
| 8826 | OPRND_SHIFT0 (16_20, FREG), | |
| 8827 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8828 | CSKY_ISA_FLOAT_7E60), | |
| 8829 | OP32 ("fcmpne.32", | |
| 8830 | OPCODE_INFO2 (0xf40001c0, | |
| 8831 | OPRND_SHIFT0 (16_20, FREG), | |
| 8832 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8833 | CSKY_ISA_FLOAT_7E60), | |
| 8834 | OP32 ("fcmpnes", | |
| 8835 | OPCODE_INFO2 (0xf40001c0, | |
| 8836 | OPRND_SHIFT0 (16_20, FREG), | |
| 8837 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8838 | CSKY_ISA_FLOAT_7E60), | |
| 8839 | OP32 ("fcmpuo.32", | |
| 8840 | OPCODE_INFO2 (0xf40001e0, | |
| 8841 | OPRND_SHIFT0 (16_20, FREG), | |
| 8842 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8843 | CSKY_ISA_FLOAT_7E60), | |
| 8844 | OP32 ("fcmpuos", | |
| 8845 | OPCODE_INFO2 (0xf40001e0, | |
| 8846 | OPRND_SHIFT0 (16_20, FREG), | |
| 8847 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8848 | CSKY_ISA_FLOAT_7E60), | |
| 8849 | OP32 ("fmaxnm.32", | |
| 8850 | OPCODE_INFO3 (0xf4000500, | |
| 8851 | OPRND_SHIFT0 (0_4, FREG), | |
| 8852 | OPRND_SHIFT0 (16_20, FREG), | |
| 8853 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8854 | CSKY_ISA_FLOAT_7E60), | |
| 8855 | OP32 ("fminnm.32", | |
| 8856 | OPCODE_INFO3 (0xf4000520, | |
| 8857 | OPRND_SHIFT0 (0_4, FREG), | |
| 8858 | OPRND_SHIFT0 (16_20, FREG), | |
| 8859 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8860 | CSKY_ISA_FLOAT_7E60), | |
| 8861 | OP32 ("fcmphz.32", | |
| 8862 | OPCODE_INFO1 (0xf4000540, | |
| 8863 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8864 | CSKY_ISA_FLOAT_7E60), | |
| 8865 | OP32 ("fcmplsz.32", | |
| 8866 | OPCODE_INFO1 (0xf4000560, | |
| 8867 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8868 | CSKY_ISA_FLOAT_7E60), | |
| 8869 | OP32 ("fmul.32", | |
| 8870 | OPCODE_INFO3 (0xf4000200, | |
| 8871 | OPRND_SHIFT0 (0_4, FREG), | |
| 8872 | OPRND_SHIFT0 (16_20, FREG), | |
| 8873 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8874 | CSKY_ISA_FLOAT_7E60), | |
| 8875 | OP32 ("fmuls", | |
| 8876 | OPCODE_INFO3 (0xf4000200, | |
| 8877 | OPRND_SHIFT0 (0_4, FREG), | |
| 8878 | OPRND_SHIFT0 (16_20, FREG), | |
| 8879 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8880 | CSKY_ISA_FLOAT_7E60), | |
| 8881 | OP32 ("fnmul.32", | |
| 8882 | OPCODE_INFO3 (0xf4000220, | |
| 8883 | OPRND_SHIFT0 (0_4, FREG), | |
| 8884 | OPRND_SHIFT0 (16_20, FREG), | |
| 8885 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8886 | CSKY_ISA_FLOAT_7E60), | |
| 8887 | OP32 ("fnmuls", | |
| 8888 | OPCODE_INFO3 (0xf4000220, | |
| 8889 | OPRND_SHIFT0 (0_4, FREG), | |
| 8890 | OPRND_SHIFT0 (16_20, FREG), | |
| 8891 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8892 | CSKY_ISA_FLOAT_7E60), | |
| 8893 | OP32 ("fmula.32", | |
| 8894 | OPCODE_INFO3 (0xf4000280, | |
| 8895 | OPRND_SHIFT0 (0_4, FREG), | |
| 8896 | OPRND_SHIFT0 (16_20, FREG), | |
| 8897 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8898 | CSKY_ISA_FLOAT_7E60), | |
| 8899 | OP32 ("fmacs", | |
| 8900 | OPCODE_INFO3 (0xf4000280, | |
| 8901 | OPRND_SHIFT0 (0_4, FREG), | |
| 8902 | OPRND_SHIFT0 (16_20, FREG), | |
| 8903 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8904 | CSKY_ISA_FLOAT_7E60), | |
| 8905 | OP32 ("fnmuls.32", | |
| 8906 | OPCODE_INFO3 (0xf40002a0, | |
| 8907 | OPRND_SHIFT0 (0_4, FREG), | |
| 8908 | OPRND_SHIFT0 (16_20, FREG), | |
| 8909 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8910 | CSKY_ISA_FLOAT_7E60), | |
| 8911 | OP32 ("fmscs", | |
| 8912 | OPCODE_INFO3 (0xf40002a0, | |
| 8913 | OPRND_SHIFT0 (0_4, FREG), | |
| 8914 | OPRND_SHIFT0 (16_20, FREG), | |
| 8915 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8916 | CSKY_ISA_FLOAT_7E60), | |
| 8917 | OP32 ("fmuls.32", | |
| 8918 | OPCODE_INFO3 (0xf40002c0, | |
| 8919 | OPRND_SHIFT0 (0_4, FREG), | |
| 8920 | OPRND_SHIFT0 (16_20, FREG), | |
| 8921 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8922 | CSKY_ISA_FLOAT_7E60), | |
| 8923 | OP32 ("fnmacs", | |
| 8924 | OPCODE_INFO3 (0xf40002c0, | |
| 8925 | OPRND_SHIFT0 (0_4, FREG), | |
| 8926 | OPRND_SHIFT0 (16_20, FREG), | |
| 8927 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8928 | CSKY_ISA_FLOAT_7E60), | |
| 8929 | OP32 ("fnmula.32", | |
| 8930 | OPCODE_INFO3 (0xf40002e0, | |
| 8931 | OPRND_SHIFT0 (0_4, FREG), | |
| 8932 | OPRND_SHIFT0 (16_20, FREG), | |
| 8933 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8934 | CSKY_ISA_FLOAT_7E60), | |
| 8935 | OP32 ("fnmscs", | |
| 8936 | OPCODE_INFO3 (0xf40002e0, | |
| 8937 | OPRND_SHIFT0 (0_4, FREG), | |
| 8938 | OPRND_SHIFT0 (16_20, FREG), | |
| 8939 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8940 | CSKY_ISA_FLOAT_7E60), | |
| 8941 | OP32 ("ffmula.32", | |
| 8942 | OPCODE_INFO3 (0xf4000600, | |
| 8943 | OPRND_SHIFT0 (0_4, FREG), | |
| 8944 | OPRND_SHIFT0 (16_20, FREG), | |
| 8945 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8946 | CSKY_ISA_FLOAT_7E60), | |
| 8947 | OP32 ("ffmuls.32", | |
| 8948 | OPCODE_INFO3 (0xf4000620, | |
| 8949 | OPRND_SHIFT0 (0_4, FREG), | |
| 8950 | OPRND_SHIFT0 (16_20, FREG), | |
| 8951 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8952 | CSKY_ISA_FLOAT_7E60), | |
| 8953 | OP32 ("ffnmula.32", | |
| 8954 | OPCODE_INFO3 (0xf4000640, | |
| 8955 | OPRND_SHIFT0 (0_4, FREG), | |
| 8956 | OPRND_SHIFT0 (16_20, FREG), | |
| 8957 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8958 | CSKY_ISA_FLOAT_7E60), | |
| 8959 | OP32 ("ffnmuls.32", | |
| 8960 | OPCODE_INFO3 (0xf4000660, | |
| 8961 | OPRND_SHIFT0 (0_4, FREG), | |
| 8962 | OPRND_SHIFT0 (16_20, FREG), | |
| 8963 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8964 | CSKY_ISA_FLOAT_7E60), | |
| 8965 | OP32 ("fdiv.32", | |
| 8966 | OPCODE_INFO3 (0xf4000300, | |
| 8967 | OPRND_SHIFT0 (0_4, FREG), | |
| 8968 | OPRND_SHIFT0 (16_20, FREG), | |
| 8969 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8970 | CSKY_ISA_FLOAT_7E60), | |
| 8971 | OP32 ("fdivs", | |
| 8972 | OPCODE_INFO3 (0xf4000300, | |
| 8973 | OPRND_SHIFT0 (0_4, FREG), | |
| 8974 | OPRND_SHIFT0 (16_20, FREG), | |
| 8975 | OPRND_SHIFT0 (21_25, FREG)), | |
| 8976 | CSKY_ISA_FLOAT_7E60), | |
| 8977 | OP32 ("frecip.32", | |
| 8978 | OPCODE_INFO2 (0xf4000320, | |
| 8979 | OPRND_SHIFT0 (0_4, FREG), | |
| 8980 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8981 | CSKY_ISA_FLOAT_7E60), | |
| 8982 | OP32 ("frecips", | |
| 8983 | OPCODE_INFO2 (0xf4000320, | |
| 8984 | OPRND_SHIFT0 (0_4, FREG), | |
| 8985 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8986 | CSKY_ISA_FLOAT_7E60), | |
| 8987 | OP32 ("fsqrt.32", | |
| 8988 | OPCODE_INFO2 (0xf4000340, | |
| 8989 | OPRND_SHIFT0 (0_4, FREG), | |
| 8990 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8991 | CSKY_ISA_FLOAT_7E60), | |
| 8992 | OP32 ("fsqrts", | |
| 8993 | OPCODE_INFO2 (0xf4000340, | |
| 8994 | OPRND_SHIFT0 (0_4, FREG), | |
| 8995 | OPRND_SHIFT0 (16_20, FREG)), | |
| 8996 | CSKY_ISA_FLOAT_7E60), | |
| 8997 | OP32 ("fsel.32", | |
| 8998 | OPCODE_INFO3 (0xf4000720, | |
| 8999 | OPRND_SHIFT0 (0_4, FREG), | |
| 9000 | OPRND_SHIFT0 (16_20, FREG), | |
| 9001 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9002 | CSKY_ISA_FLOAT_7E60), | |
| 9003 | /* Double floating. */ | |
| 9004 | OP32 ("fadd.64", | |
| 9005 | OPCODE_INFO3 (0xf4000800, | |
| 9006 | OPRND_SHIFT0 (0_4, FREG), | |
| 9007 | OPRND_SHIFT0 (16_20, FREG), | |
| 9008 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9009 | CSKY_ISA_FLOAT_7E60), | |
| 9010 | OP32 ("faddd", | |
| 9011 | OPCODE_INFO3 (0xf4000800, | |
| 9012 | OPRND_SHIFT0 (0_4, FREG), | |
| 9013 | OPRND_SHIFT0 (16_20, FREG), | |
| 9014 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9015 | CSKY_ISA_FLOAT_7E60), | |
| 9016 | OP32 ("fsub.64", | |
| 9017 | OPCODE_INFO3 (0xf4000820, | |
| 9018 | OPRND_SHIFT0 (0_4, FREG), | |
| 9019 | OPRND_SHIFT0 (16_20, FREG), | |
| 9020 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9021 | CSKY_ISA_FLOAT_7E60), | |
| 9022 | OP32 ("fsubd", | |
| 9023 | OPCODE_INFO3 (0xf4000820, | |
| 9024 | OPRND_SHIFT0 (0_4, FREG), | |
| 9025 | OPRND_SHIFT0 (16_20, FREG), | |
| 9026 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9027 | CSKY_ISA_FLOAT_7E60), | |
| 9028 | OP32 ("fmov.64", | |
| 9029 | OPCODE_INFO2 (0xf4000880, | |
| 9030 | OPRND_SHIFT0 (0_4, FREG), | |
| 9031 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9032 | CSKY_ISA_FLOAT_7E60), | |
| 9033 | OP32 ("fmovd", | |
| 9034 | OPCODE_INFO2 (0xf4000880, | |
| 9035 | OPRND_SHIFT0 (0_4, FREG), | |
| 9036 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9037 | CSKY_ISA_FLOAT_7E60), | |
| 9038 | OP32 ("fmovx.32", | |
| 9039 | OPCODE_INFO2 (0xf40008a0, | |
| 9040 | OPRND_SHIFT0 (0_4, FREG), | |
| 9041 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9042 | CSKY_ISA_FLOAT_7E60), | |
| 9043 | OP32 ("fabs.64", | |
| 9044 | OPCODE_INFO2 (0xf40008c0, | |
| 9045 | OPRND_SHIFT0 (0_4, FREG), | |
| 9046 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9047 | CSKY_ISA_FLOAT_7E60), | |
| 9048 | OP32 ("fabsd", | |
| 9049 | OPCODE_INFO2 (0xf40008c0, | |
| 9050 | OPRND_SHIFT0 (0_4, FREG), | |
| 9051 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9052 | CSKY_ISA_FLOAT_7E60), | |
| 9053 | OP32 ("fneg.64", | |
| 9054 | OPCODE_INFO2 (0xf40008e0, | |
| 9055 | OPRND_SHIFT0 (0_4, FREG), | |
| 9056 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9057 | CSKY_ISA_FLOAT_7E60), | |
| 9058 | OP32 ("fnegd", | |
| 9059 | OPCODE_INFO2 (0xf40008e0, | |
| 9060 | OPRND_SHIFT0 (0_4, FREG), | |
| 9061 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9062 | CSKY_ISA_FLOAT_7E60), | |
| 9063 | OP32 ("fcmphsz.64", | |
| 9064 | OPCODE_INFO1 (0xf4000900, | |
| 9065 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9066 | CSKY_ISA_FLOAT_7E60), | |
| 9067 | OP32 ("fcmpzhsd", | |
| 9068 | OPCODE_INFO1 (0xf4000900, | |
| 9069 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9070 | CSKY_ISA_FLOAT_7E60), | |
| 9071 | OP32 ("fcmpltz.64", | |
| 9072 | OPCODE_INFO1 (0xf4000920, | |
| 9073 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9074 | CSKY_ISA_FLOAT_7E60), | |
| 9075 | OP32 ("fcmpzltd", | |
| 9076 | OPCODE_INFO1 (0xf4000920, | |
| 9077 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9078 | CSKY_ISA_FLOAT_7E60), | |
| 9079 | OP32 ("fcmpnez.64", | |
| 9080 | OPCODE_INFO1 (0xf4000940, | |
| 9081 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9082 | CSKY_ISA_FLOAT_7E60), | |
| 9083 | OP32 ("fcmpzned", | |
| 9084 | OPCODE_INFO1 (0xf4000940, | |
| 9085 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9086 | CSKY_ISA_FLOAT_7E60), | |
| 9087 | OP32 ("fcmpuoz.64", | |
| 9088 | OPCODE_INFO1 (0xf4000960, | |
| 9089 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9090 | CSKY_ISA_FLOAT_7E60), | |
| 9091 | OP32 ("fcmpzuod", | |
| 9092 | OPCODE_INFO1 (0xf4000960, | |
| 9093 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9094 | CSKY_ISA_FLOAT_7E60), | |
| 9095 | OP32 ("fcmphs.64", | |
| 9096 | OPCODE_INFO2 (0xf4000980, | |
| 9097 | OPRND_SHIFT0 (16_20, FREG), | |
| 9098 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9099 | CSKY_ISA_FLOAT_7E60), | |
| 9100 | OP32 ("fcmphsd", | |
| 9101 | OPCODE_INFO2 (0xf4000980, | |
| 9102 | OPRND_SHIFT0 (16_20, FREG), | |
| 9103 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9104 | CSKY_ISA_FLOAT_7E60), | |
| 9105 | OP32 ("fcmplt.64", | |
| 9106 | OPCODE_INFO2 (0xf40009a0, | |
| 9107 | OPRND_SHIFT0 (16_20, FREG), | |
| 9108 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9109 | CSKY_ISA_FLOAT_7E60), | |
| 9110 | OP32 ("fcmpltd", | |
| 9111 | OPCODE_INFO2 (0xf40009a0, | |
| 9112 | OPRND_SHIFT0 (16_20, FREG), | |
| 9113 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9114 | CSKY_ISA_FLOAT_7E60), | |
| 9115 | OP32 ("fcmpne.64", | |
| 9116 | OPCODE_INFO2 (0xf40009c0, | |
| 9117 | OPRND_SHIFT0 (16_20, FREG), | |
| 9118 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9119 | CSKY_ISA_FLOAT_7E60), | |
| 9120 | OP32 ("fcmpned", | |
| 9121 | OPCODE_INFO2 (0xf40009c0, | |
| 9122 | OPRND_SHIFT0 (16_20, FREG), | |
| 9123 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9124 | CSKY_ISA_FLOAT_7E60), | |
| 9125 | OP32 ("fcmpuo.64", | |
| 9126 | OPCODE_INFO2 (0xf40009e0, | |
| 9127 | OPRND_SHIFT0 (16_20, FREG), | |
| 9128 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9129 | CSKY_ISA_FLOAT_7E60), | |
| 9130 | OP32 ("fcmpuod", | |
| 9131 | OPCODE_INFO2 (0xf40009e0, | |
| 9132 | OPRND_SHIFT0 (16_20, FREG), | |
| 9133 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9134 | CSKY_ISA_FLOAT_7E60), | |
| 9135 | OP32 ("fmaxnm.64", | |
| 9136 | OPCODE_INFO3 (0xf4000d00, | |
| 9137 | OPRND_SHIFT0 (0_4, FREG), | |
| 9138 | OPRND_SHIFT0 (16_20, FREG), | |
| 9139 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9140 | CSKY_ISA_FLOAT_7E60), | |
| 9141 | OP32 ("fminnm.64", | |
| 9142 | OPCODE_INFO3 (0xf4000d20, | |
| 9143 | OPRND_SHIFT0 (0_4, FREG), | |
| 9144 | OPRND_SHIFT0 (16_20, FREG), | |
| 9145 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9146 | CSKY_ISA_FLOAT_7E60), | |
| 9147 | OP32 ("fcmphz.64", | |
| 9148 | OPCODE_INFO1 (0xf4000d40, | |
| 9149 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9150 | CSKY_ISA_FLOAT_7E60), | |
| 9151 | OP32 ("fcmplsz.64", | |
| 9152 | OPCODE_INFO1 (0xf4000d60, | |
| 9153 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9154 | CSKY_ISA_FLOAT_7E60), | |
| 9155 | OP32 ("fmul.64", | |
| 9156 | OPCODE_INFO3 (0xf4000a00, | |
| 9157 | OPRND_SHIFT0 (0_4, FREG), | |
| 9158 | OPRND_SHIFT0 (16_20, FREG), | |
| 9159 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9160 | CSKY_ISA_FLOAT_7E60), | |
| 9161 | OP32 ("fmuld", | |
| 9162 | OPCODE_INFO3 (0xf4000a00, | |
| 9163 | OPRND_SHIFT0 (0_4, FREG), | |
| 9164 | OPRND_SHIFT0 (16_20, FREG), | |
| 9165 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9166 | CSKY_ISA_FLOAT_7E60), | |
| 9167 | OP32 ("fnmul.64", | |
| 9168 | OPCODE_INFO3 (0xf4000a20, | |
| 9169 | OPRND_SHIFT0 (0_4, FREG), | |
| 9170 | OPRND_SHIFT0 (16_20, FREG), | |
| 9171 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9172 | CSKY_ISA_FLOAT_7E60), | |
| 9173 | OP32 ("fnmuld", | |
| 9174 | OPCODE_INFO3 (0xf4000a20, | |
| 9175 | OPRND_SHIFT0 (0_4, FREG), | |
| 9176 | OPRND_SHIFT0 (16_20, FREG), | |
| 9177 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9178 | CSKY_ISA_FLOAT_7E60), | |
| 9179 | OP32 ("fmula.64", | |
| 9180 | OPCODE_INFO3 (0xf4000a80, | |
| 9181 | OPRND_SHIFT0 (0_4, FREG), | |
| 9182 | OPRND_SHIFT0 (16_20, FREG), | |
| 9183 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9184 | CSKY_ISA_FLOAT_7E60), | |
| 9185 | OP32 ("fmacd", | |
| 9186 | OPCODE_INFO3 (0xf4000a80, | |
| 9187 | OPRND_SHIFT0 (0_4, FREG), | |
| 9188 | OPRND_SHIFT0 (16_20, FREG), | |
| 9189 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9190 | CSKY_ISA_FLOAT_7E60), | |
| 9191 | OP32 ("fnmuls.64", | |
| 9192 | OPCODE_INFO3 (0xf4000aa0, | |
| 9193 | OPRND_SHIFT0 (0_4, FREG), | |
| 9194 | OPRND_SHIFT0 (16_20, FREG), | |
| 9195 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9196 | CSKY_ISA_FLOAT_7E60), | |
| 9197 | OP32 ("fmscd", | |
| 9198 | OPCODE_INFO3 (0xf4000aa0, | |
| 9199 | OPRND_SHIFT0 (0_4, FREG), | |
| 9200 | OPRND_SHIFT0 (16_20, FREG), | |
| 9201 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9202 | CSKY_ISA_FLOAT_7E60), | |
| 9203 | OP32 ("fmuls.64", | |
| 9204 | OPCODE_INFO3 (0xf4000ac0, | |
| 9205 | OPRND_SHIFT0 (0_4, FREG), | |
| 9206 | OPRND_SHIFT0 (16_20, FREG), | |
| 9207 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9208 | CSKY_ISA_FLOAT_7E60), | |
| 9209 | OP32 ("fnmacd", | |
| 9210 | OPCODE_INFO3 (0xf4000ac0, | |
| 9211 | OPRND_SHIFT0 (0_4, FREG), | |
| 9212 | OPRND_SHIFT0 (16_20, FREG), | |
| 9213 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9214 | CSKY_ISA_FLOAT_7E60), | |
| 9215 | OP32 ("fnmula.64", | |
| 9216 | OPCODE_INFO3 (0xf4000ae0, | |
| 9217 | OPRND_SHIFT0 (0_4, FREG), | |
| 9218 | OPRND_SHIFT0 (16_20, FREG), | |
| 9219 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9220 | CSKY_ISA_FLOAT_7E60), | |
| 9221 | OP32 ("fnmscd", | |
| 9222 | OPCODE_INFO3 (0xf4000ae0, | |
| 9223 | OPRND_SHIFT0 (0_4, FREG), | |
| 9224 | OPRND_SHIFT0 (16_20, FREG), | |
| 9225 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9226 | CSKY_ISA_FLOAT_7E60), | |
| 9227 | OP32 ("ffmula.64", | |
| 9228 | OPCODE_INFO3 (0xf4000e00, | |
| 9229 | OPRND_SHIFT0 (0_4, FREG), | |
| 9230 | OPRND_SHIFT0 (16_20, FREG), | |
| 9231 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9232 | CSKY_ISA_FLOAT_7E60), | |
| 9233 | OP32 ("ffmuls.64", | |
| 9234 | OPCODE_INFO3 (0xf4000e20, | |
| 9235 | OPRND_SHIFT0 (0_4, FREG), | |
| 9236 | OPRND_SHIFT0 (16_20, FREG), | |
| 9237 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9238 | CSKY_ISA_FLOAT_7E60), | |
| 9239 | OP32 ("ffnmula.64", | |
| 9240 | OPCODE_INFO3 (0xf4000e40, | |
| 9241 | OPRND_SHIFT0 (0_4, FREG), | |
| 9242 | OPRND_SHIFT0 (16_20, FREG), | |
| 9243 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9244 | CSKY_ISA_FLOAT_7E60), | |
| 9245 | OP32 ("ffnmuls.64", | |
| 9246 | OPCODE_INFO3 (0xf4000e60, | |
| 9247 | OPRND_SHIFT0 (0_4, FREG), | |
| 9248 | OPRND_SHIFT0 (16_20, FREG), | |
| 9249 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9250 | CSKY_ISA_FLOAT_7E60), | |
| 9251 | OP32 ("fdiv.64", | |
| 9252 | OPCODE_INFO3 (0xf4000b00, | |
| 9253 | OPRND_SHIFT0 (0_4, FREG), | |
| 9254 | OPRND_SHIFT0 (16_20, FREG), | |
| 9255 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9256 | CSKY_ISA_FLOAT_7E60), | |
| 9257 | OP32 ("fdivd", | |
| 9258 | OPCODE_INFO3 (0xf4000b00, | |
| 9259 | OPRND_SHIFT0 (0_4, FREG), | |
| 9260 | OPRND_SHIFT0 (16_20, FREG), | |
| 9261 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9262 | CSKY_ISA_FLOAT_7E60), | |
| 9263 | OP32 ("frecip.64", | |
| 9264 | OPCODE_INFO2 (0xf4000b20, | |
| 9265 | OPRND_SHIFT0 (0_4, FREG), | |
| 9266 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9267 | CSKY_ISA_FLOAT_7E60), | |
| 9268 | OP32 ("frecipd", | |
| 9269 | OPCODE_INFO2 (0xf4000b20, | |
| 9270 | OPRND_SHIFT0 (0_4, FREG), | |
| 9271 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9272 | CSKY_ISA_FLOAT_7E60), | |
| 9273 | OP32 ("fsqrt.64", | |
| 9274 | OPCODE_INFO2 (0xf4000b40, | |
| 9275 | OPRND_SHIFT0 (0_4, FREG), | |
| 9276 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9277 | CSKY_ISA_FLOAT_7E60), | |
| 9278 | OP32 ("fsqrtd", | |
| 9279 | OPCODE_INFO2 (0xf4000b40, | |
| 9280 | OPRND_SHIFT0 (0_4, FREG), | |
| 9281 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9282 | CSKY_ISA_FLOAT_7E60), | |
| 9283 | OP32 ("fins.32", | |
| 9284 | OPCODE_INFO2 (0xf4000360, | |
| 9285 | OPRND_SHIFT0 (0_4, FREG), | |
| 9286 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9287 | CSKY_ISA_FLOAT_7E60), | |
| 9288 | OP32 ("fsel.64", | |
| 9289 | OPCODE_INFO3 (0xf4000f20, | |
| 9290 | OPRND_SHIFT0 (0_4, FREG), | |
| 9291 | OPRND_SHIFT0 (16_20, FREG), | |
| 9292 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9293 | CSKY_ISA_FLOAT_7E60), | |
| 9294 | /* SIMD floating. */ | |
| 9295 | OP32 ("fadd.f32", | |
| 9296 | OPCODE_INFO3 (0xf4001000, | |
| 9297 | OPRND_SHIFT0 (0_4, FREG), | |
| 9298 | OPRND_SHIFT0 (16_20, FREG), | |
| 9299 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9300 | CSKY_ISA_FLOAT_7E60), | |
| 9301 | OP32 ("faddm", | |
| 9302 | OPCODE_INFO3 (0xf4001000, | |
| 9303 | OPRND_SHIFT0 (0_4, FREG), | |
| 9304 | OPRND_SHIFT0 (16_20, FREG), | |
| 9305 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9306 | CSKY_ISA_FLOAT_7E60), | |
| 9307 | OP32 ("fsub.f32", | |
| 9308 | OPCODE_INFO3 (0xf4001020, | |
| 9309 | OPRND_SHIFT0 (0_4, FREG), | |
| 9310 | OPRND_SHIFT0 (16_20, FREG), | |
| 9311 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9312 | CSKY_ISA_FLOAT_7E60), | |
| 9313 | OP32 ("fsubm", | |
| 9314 | OPCODE_INFO3 (0xf4001020, | |
| 9315 | OPRND_SHIFT0 (0_4, FREG), | |
| 9316 | OPRND_SHIFT0 (16_20, FREG), | |
| 9317 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9318 | CSKY_ISA_FLOAT_7E60), | |
| 9319 | OP32 ("fmov.f32", | |
| 9320 | OPCODE_INFO2 (0xf4001080, | |
| 9321 | OPRND_SHIFT0 (0_4, FREG), | |
| 9322 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9323 | CSKY_ISA_FLOAT_7E60), | |
| 9324 | OP32 ("fmovm", | |
| 9325 | OPCODE_INFO2 (0xf4001080, | |
| 9326 | OPRND_SHIFT0 (0_4, FREG), | |
| 9327 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9328 | CSKY_ISA_FLOAT_7E60), | |
| 9329 | OP32 ("fabs.f32", | |
| 9330 | OPCODE_INFO2 (0xf40010c0, | |
| 9331 | OPRND_SHIFT0 (0_4, FREG), | |
| 9332 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9333 | CSKY_ISA_FLOAT_7E60), | |
| 9334 | OP32 ("fabsm", | |
| 9335 | OPCODE_INFO2 (0xf40010c0, | |
| 9336 | OPRND_SHIFT0 (0_4, FREG), | |
| 9337 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9338 | CSKY_ISA_FLOAT_7E60), | |
| 9339 | OP32 ("fneg.f32", | |
| 9340 | OPCODE_INFO2 (0xf40010e0, | |
| 9341 | OPRND_SHIFT0 (0_4, FREG), | |
| 9342 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9343 | CSKY_ISA_FLOAT_7E60), | |
| 9344 | OP32 ("fnegm", | |
| 9345 | OPCODE_INFO2 (0xf40010e0, | |
| 9346 | OPRND_SHIFT0 (0_4, FREG), | |
| 9347 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9348 | CSKY_ISA_FLOAT_7E60), | |
| 9349 | OP32 ("fmul.f32", | |
| 9350 | OPCODE_INFO3 (0xf4001200, | |
| 9351 | OPRND_SHIFT0 (0_4, FREG), | |
| 9352 | OPRND_SHIFT0 (16_20, FREG), | |
| 9353 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9354 | CSKY_ISA_FLOAT_7E60), | |
| 9355 | OP32 ("fmulm", | |
| 9356 | OPCODE_INFO3 (0xf4001200, | |
| 9357 | OPRND_SHIFT0 (0_4, FREG), | |
| 9358 | OPRND_SHIFT0 (16_20, FREG), | |
| 9359 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9360 | CSKY_ISA_FLOAT_7E60), | |
| 9361 | OP32 ("fmula.f32", | |
| 9362 | OPCODE_INFO3 (0xf4001280, | |
| 9363 | OPRND_SHIFT0 (0_4, FREG), | |
| 9364 | OPRND_SHIFT0 (16_20, FREG), | |
| 9365 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9366 | CSKY_ISA_FLOAT_7E60), | |
| 9367 | OP32 ("fmuls.f32", | |
| 9368 | OPCODE_INFO3 (0xf40012c0, | |
| 9369 | OPRND_SHIFT0 (0_4, FREG), | |
| 9370 | OPRND_SHIFT0 (16_20, FREG), | |
| 9371 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9372 | CSKY_ISA_FLOAT_7E60), | |
| 9373 | OP32 ("fnmacm", | |
| 9374 | OPCODE_INFO3 (0xf40012c0, | |
| 9375 | OPRND_SHIFT0 (0_4, FREG), | |
| 9376 | OPRND_SHIFT0 (16_20, FREG), | |
| 9377 | OPRND_SHIFT0 (21_25, FREG)), | |
| 9378 | CSKY_ISA_FLOAT_7E60), | |
| 9379 | /* floating formate. */ | |
| 9380 | OP32 ("fftoi.f32.s32.rn", | |
| 9381 | OPCODE_INFO2 (0xf4001800, | |
| 9382 | OPRND_SHIFT0 (0_4, FREG), | |
| 9383 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9384 | CSKY_ISA_FLOAT_7E60), | |
| 9385 | OP32 ("fstosi.rn", | |
| 9386 | OPCODE_INFO2 (0xf4001800, | |
| 9387 | OPRND_SHIFT0 (0_4, FREG), | |
| 9388 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9389 | CSKY_ISA_FLOAT_7E60), | |
| 9390 | OP32 ("fftoi.f32.s32.rz", | |
| 9391 | OPCODE_INFO2 (0xf4001820, | |
| 9392 | OPRND_SHIFT0 (0_4, FREG), | |
| 9393 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9394 | CSKY_ISA_FLOAT_7E60), | |
| 9395 | OP32 ("fstosi.rz", | |
| 9396 | OPCODE_INFO2 (0xf4001820, | |
| 9397 | OPRND_SHIFT0 (0_4, FREG), | |
| 9398 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9399 | CSKY_ISA_FLOAT_7E60), | |
| 9400 | OP32 ("fftoi.f32.s32.rpi", | |
| 9401 | OPCODE_INFO2 (0xf4001840, | |
| 9402 | OPRND_SHIFT0 (0_4, FREG), | |
| 9403 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9404 | CSKY_ISA_FLOAT_7E60), | |
| 9405 | OP32 ("fstosi.rpi", | |
| 9406 | OPCODE_INFO2 (0xf4001840, | |
| 9407 | OPRND_SHIFT0 (0_4, FREG), | |
| 9408 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9409 | CSKY_ISA_FLOAT_7E60), | |
| 9410 | OP32 ("fftoi.f32.s32.rni", | |
| 9411 | OPCODE_INFO2 (0xf4001860, | |
| 9412 | OPRND_SHIFT0 (0_4, FREG), | |
| 9413 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9414 | CSKY_ISA_FLOAT_7E60), | |
| 9415 | OP32 ("fstosi.rni", | |
| 9416 | OPCODE_INFO2 (0xf4001860, | |
| 9417 | OPRND_SHIFT0 (0_4, FREG), | |
| 9418 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9419 | CSKY_ISA_FLOAT_7E60), | |
| 9420 | OP32 ("fftoi.f32.u32.rn", | |
| 9421 | OPCODE_INFO2 (0xf4001880, | |
| 9422 | OPRND_SHIFT0 (0_4, FREG), | |
| 9423 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9424 | CSKY_ISA_FLOAT_7E60), | |
| 9425 | OP32 ("fstoui.rn", | |
| 9426 | OPCODE_INFO2 (0xf4001880, | |
| 9427 | OPRND_SHIFT0 (0_4, FREG), | |
| 9428 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9429 | CSKY_ISA_FLOAT_7E60), | |
| 9430 | OP32 ("fftoi.f32.u32.rz", | |
| 9431 | OPCODE_INFO2 (0xf40018a0, | |
| 9432 | OPRND_SHIFT0 (0_4, FREG), | |
| 9433 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9434 | CSKY_ISA_FLOAT_7E60), | |
| 9435 | OP32 ("fstoui.rz", | |
| 9436 | OPCODE_INFO2 (0xf40018a0, | |
| 9437 | OPRND_SHIFT0 (0_4, FREG), | |
| 9438 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9439 | CSKY_ISA_FLOAT_7E60), | |
| 9440 | OP32 ("fftoi.f32.u32.rpi", | |
| 9441 | OPCODE_INFO2 (0xf40018c0, | |
| 9442 | OPRND_SHIFT0 (0_4, FREG), | |
| 9443 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9444 | CSKY_ISA_FLOAT_7E60), | |
| 9445 | OP32 ("fstoui.rpi", | |
| 9446 | OPCODE_INFO2 (0xf40018c0, | |
| 9447 | OPRND_SHIFT0 (0_4, FREG), | |
| 9448 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9449 | CSKY_ISA_FLOAT_7E60), | |
| 9450 | OP32 ("fftoi.f32.u32.rni", | |
| 9451 | OPCODE_INFO2 (0xf40018e0, | |
| 9452 | OPRND_SHIFT0 (0_4, FREG), | |
| 9453 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9454 | CSKY_ISA_FLOAT_7E60), | |
| 9455 | OP32 ("fstoui.rni", | |
| 9456 | OPCODE_INFO2 (0xf40018e0, | |
| 9457 | OPRND_SHIFT0 (0_4, FREG), | |
| 9458 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9459 | CSKY_ISA_FLOAT_7E60), | |
| 9460 | OP32 ("fftoi.f64.s32.rn", | |
| 9461 | OPCODE_INFO2 (0xf4001900, | |
| 9462 | OPRND_SHIFT0 (0_4, FREG), | |
| 9463 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9464 | CSKY_ISA_FLOAT_7E60), | |
| 9465 | OP32 ("fdtosi.rn", | |
| 9466 | OPCODE_INFO2 (0xf4001900, | |
| 9467 | OPRND_SHIFT0 (0_4, FREG), | |
| 9468 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9469 | CSKY_ISA_FLOAT_7E60), | |
| 9470 | OP32 ("fftoi.f64.s32.rz", | |
| 9471 | OPCODE_INFO2 (0xf4001920, | |
| 9472 | OPRND_SHIFT0 (0_4, FREG), | |
| 9473 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9474 | CSKY_ISA_FLOAT_7E60), | |
| 9475 | OP32 ("fdtosi.rz", | |
| 9476 | OPCODE_INFO2 (0xf4001920, | |
| 9477 | OPRND_SHIFT0 (0_4, FREG), | |
| 9478 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9479 | CSKY_ISA_FLOAT_7E60), | |
| 9480 | OP32 ("fftoi.f64.s32.rpi", | |
| 9481 | OPCODE_INFO2 (0xf4001940, | |
| 9482 | OPRND_SHIFT0 (0_4, FREG), | |
| 9483 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9484 | CSKY_ISA_FLOAT_7E60), | |
| 9485 | OP32 ("fdtosi.rpi", | |
| 9486 | OPCODE_INFO2 (0xf4001940, | |
| 9487 | OPRND_SHIFT0 (0_4, FREG), | |
| 9488 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9489 | CSKY_ISA_FLOAT_7E60), | |
| 9490 | OP32 ("fftoi.f64.s32.rni", | |
| 9491 | OPCODE_INFO2 (0xf4001960, | |
| 9492 | OPRND_SHIFT0 (0_4, FREG), | |
| 9493 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9494 | CSKY_ISA_FLOAT_7E60), | |
| 9495 | OP32 ("fdtosi.rni", | |
| 9496 | OPCODE_INFO2 (0xf4001960, | |
| 9497 | OPRND_SHIFT0 (0_4, FREG), | |
| 9498 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9499 | CSKY_ISA_FLOAT_7E60), | |
| 9500 | OP32 ("fftoi.f64.u32.rn", | |
| 9501 | OPCODE_INFO2 (0xf4001980, | |
| 9502 | OPRND_SHIFT0 (0_4, FREG), | |
| 9503 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9504 | CSKY_ISA_FLOAT_7E60), | |
| 9505 | OP32 ("fdtoui.rn", | |
| 9506 | OPCODE_INFO2 (0xf4001980, | |
| 9507 | OPRND_SHIFT0 (0_4, FREG), | |
| 9508 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9509 | CSKY_ISA_FLOAT_7E60), | |
| 9510 | OP32 ("fftoi.f64.u32.rz", | |
| 9511 | OPCODE_INFO2 (0xf40019a0, | |
| 9512 | OPRND_SHIFT0 (0_4, FREG), | |
| 9513 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9514 | CSKY_ISA_FLOAT_7E60), | |
| 9515 | OP32 ("fdtoui.rz", | |
| 9516 | OPCODE_INFO2 (0xf40019a0, | |
| 9517 | OPRND_SHIFT0 (0_4, FREG), | |
| 9518 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9519 | CSKY_ISA_FLOAT_7E60), | |
| 9520 | OP32 ("fftoi.f64.u32.rpi", | |
| 9521 | OPCODE_INFO2 (0xf40019c0, | |
| 9522 | OPRND_SHIFT0 (0_4, FREG), | |
| 9523 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9524 | CSKY_ISA_FLOAT_7E60), | |
| 9525 | OP32 ("fdtoui.rpi", | |
| 9526 | OPCODE_INFO2 (0xf40019c0, | |
| 9527 | OPRND_SHIFT0 (0_4, FREG), | |
| 9528 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9529 | CSKY_ISA_FLOAT_7E60), | |
| 9530 | OP32 ("fftoi.f64.u32.rni", | |
| 9531 | OPCODE_INFO2 (0xf40019e0, | |
| 9532 | OPRND_SHIFT0 (0_4, FREG), | |
| 9533 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9534 | CSKY_ISA_FLOAT_7E60), | |
| 9535 | OP32 ("fdtoui.rni", | |
| 9536 | OPCODE_INFO2 (0xf40019e0, | |
| 9537 | OPRND_SHIFT0 (0_4, FREG), | |
| 9538 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9539 | CSKY_ISA_FLOAT_7E60), | |
| 9540 | OP32 ("fftoi.f16.s32.rn", | |
| 9541 | OPCODE_INFO2 (0xf4001c00, | |
| 9542 | OPRND_SHIFT0 (0_4, FREG), | |
| 9543 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9544 | CSKY_ISA_FLOAT_7E60), | |
| 9545 | OP32 ("fhtosi.rn", | |
| 9546 | OPCODE_INFO2 (0xf4001c00, | |
| 9547 | OPRND_SHIFT0 (0_4, FREG), | |
| 9548 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9549 | CSKY_ISA_FLOAT_7E60), | |
| 9550 | OP32 ("fftoi.f16.s32.rz", | |
| 9551 | OPCODE_INFO2 (0xf4001c20, | |
| 9552 | OPRND_SHIFT0 (0_4, FREG), | |
| 9553 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9554 | CSKY_ISA_FLOAT_7E60), | |
| 9555 | OP32 ("fhtosi.rz", | |
| 9556 | OPCODE_INFO2 (0xf4001c20, | |
| 9557 | OPRND_SHIFT0 (0_4, FREG), | |
| 9558 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9559 | CSKY_ISA_FLOAT_7E60), | |
| 9560 | OP32 ("fftoi.f16.s32.rpi", | |
| 9561 | OPCODE_INFO2 (0xf4001c40, | |
| 9562 | OPRND_SHIFT0 (0_4, FREG), | |
| 9563 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9564 | CSKY_ISA_FLOAT_7E60), | |
| 9565 | OP32 ("fhtosi.rpi", | |
| 9566 | OPCODE_INFO2 (0xf4001c40, | |
| 9567 | OPRND_SHIFT0 (0_4, FREG), | |
| 9568 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9569 | CSKY_ISA_FLOAT_7E60), | |
| 9570 | OP32 ("fftoi.f16.s32.rni", | |
| 9571 | OPCODE_INFO2 (0xf4001c60, | |
| 9572 | OPRND_SHIFT0 (0_4, FREG), | |
| 9573 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9574 | CSKY_ISA_FLOAT_7E60), | |
| 9575 | OP32 ("fhtosi.rni", | |
| 9576 | OPCODE_INFO2 (0xf4001c60, | |
| 9577 | OPRND_SHIFT0 (0_4, FREG), | |
| 9578 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9579 | CSKY_ISA_FLOAT_7E60), | |
| 9580 | OP32 ("fftoi.f16.u32.rn", | |
| 9581 | OPCODE_INFO2 (0xf4001c80, | |
| 9582 | OPRND_SHIFT0 (0_4, FREG), | |
| 9583 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9584 | CSKY_ISA_FLOAT_7E60), | |
| 9585 | OP32 ("fhtoui.rn", | |
| 9586 | OPCODE_INFO2 (0xf4001c80, | |
| 9587 | OPRND_SHIFT0 (0_4, FREG), | |
| 9588 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9589 | CSKY_ISA_FLOAT_7E60), | |
| 9590 | OP32 ("fftoi.f16.u32.rz", | |
| 9591 | OPCODE_INFO2 (0xf4001ca0, | |
| 9592 | OPRND_SHIFT0 (0_4, FREG), | |
| 9593 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9594 | CSKY_ISA_FLOAT_7E60), | |
| 9595 | OP32 ("fhtoui.rz", | |
| 9596 | OPCODE_INFO2 (0xf4001ca0, | |
| 9597 | OPRND_SHIFT0 (0_4, FREG), | |
| 9598 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9599 | CSKY_ISA_FLOAT_7E60), | |
| 9600 | OP32 ("fftoi.f16.u32.rpi", | |
| 9601 | OPCODE_INFO2 (0xf4001cc0, | |
| 9602 | OPRND_SHIFT0 (0_4, FREG), | |
| 9603 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9604 | CSKY_ISA_FLOAT_7E60), | |
| 9605 | OP32 ("fhtoui.rpi", | |
| 9606 | OPCODE_INFO2 (0xf4001cc0, | |
| 9607 | OPRND_SHIFT0 (0_4, FREG), | |
| 9608 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9609 | CSKY_ISA_FLOAT_7E60), | |
| 9610 | OP32 ("fftoi.f16.u32.rni", | |
| 9611 | OPCODE_INFO2 (0xf4001ce0, | |
| 9612 | OPRND_SHIFT0 (0_4, FREG), | |
| 9613 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9614 | CSKY_ISA_FLOAT_7E60), | |
| 9615 | OP32 ("fhtoui.rni", | |
| 9616 | OPCODE_INFO2 (0xf4001ce0, | |
| 9617 | OPRND_SHIFT0 (0_4, FREG), | |
| 9618 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9619 | CSKY_ISA_FLOAT_7E60), | |
| 9620 | OP32 ("fhtos", | |
| 9621 | OPCODE_INFO2 (0xf4001a40, | |
| 9622 | OPRND_SHIFT0 (0_4, FREG), | |
| 9623 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9624 | CSKY_ISA_FLOAT_7E60), | |
| 9625 | OP32 ("fhtos.f16", | |
| 9626 | OPCODE_INFO2 (0xf4001a40, | |
| 9627 | OPRND_SHIFT0 (0_4, FREG), | |
| 9628 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9629 | CSKY_ISA_FLOAT_7E60), | |
| 9630 | OP32 ("fstoh", | |
| 9631 | OPCODE_INFO2 (0xf4001a60, | |
| 9632 | OPRND_SHIFT0 (0_4, FREG), | |
| 9633 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9634 | CSKY_ISA_FLOAT_7E60), | |
| 9635 | OP32 ("fstoh.f32", | |
| 9636 | OPCODE_INFO2 (0xf4001a60, | |
| 9637 | OPRND_SHIFT0 (0_4, FREG), | |
| 9638 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9639 | CSKY_ISA_FLOAT_7E60), | |
| 9640 | OP32 ("fdtos", | |
| 9641 | OPCODE_INFO2 (0xf4001ac0, | |
| 9642 | OPRND_SHIFT0 (0_4, FREG), | |
| 9643 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9644 | CSKY_ISA_FLOAT_7E60), | |
| 9645 | OP32 ("fdtos.f64", | |
| 9646 | OPCODE_INFO2 (0xf4001ac0, | |
| 9647 | OPRND_SHIFT0 (0_4, FREG), | |
| 9648 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9649 | CSKY_ISA_FLOAT_7E60), | |
| 9650 | OP32 ("fstod", | |
| 9651 | OPCODE_INFO2 (0xf4001ae0, | |
| 9652 | OPRND_SHIFT0 (0_4, FREG), | |
| 9653 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9654 | CSKY_ISA_FLOAT_7E60), | |
| 9655 | OP32 ("fmfvrh", | |
| 9656 | OPCODE_INFO2 (0xf4001b00, | |
| 9657 | OPRND_SHIFT0 (0_4, AREG), | |
| 9658 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9659 | CSKY_ISA_FLOAT_7E60), | |
| 9660 | OP32 ("fmfvr.32.1", | |
| 9661 | OPCODE_INFO2 (0xf4001b20, | |
| 9662 | OPRND_SHIFT0 (0_4, AREG), | |
| 9663 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9664 | CSKY_ISA_FLOAT_7E60), | |
| 9665 | OP32 ("fmfvrl", | |
| 9666 | OPCODE_INFO2 (0xf4001b20, | |
| 9667 | OPRND_SHIFT0 (0_4, AREG), | |
| 9668 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9669 | CSKY_ISA_FLOAT_7E60), | |
| 9670 | OP32 ("fmtvr.16", | |
| 9671 | OPCODE_INFO2 (0xf4001fa0, | |
| 9672 | OPRND_SHIFT0 (0_4, FREG), | |
| 9673 | OPRND_SHIFT0 (16_20, AREG)), | |
| 9674 | CSKY_ISA_FLOAT_7E60), | |
| 9675 | OP32 ("fmfvr.16", | |
| 9676 | OPCODE_INFO2 (0xf4001f20, | |
| 9677 | OPRND_SHIFT0 (0_4, AREG), | |
| 9678 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9679 | CSKY_ISA_FLOAT_7E60), | |
| 9680 | OP32 ("fmtvrh", | |
| 9681 | OPCODE_INFO2 (0xf4001b40, | |
| 9682 | OPRND_SHIFT0 (0_4, FREG), | |
| 9683 | OPRND_SHIFT0 (16_20, AREG)), | |
| 9684 | CSKY_ISA_FLOAT_7E60), | |
| 9685 | OP32 ("fmtvr.32.1", | |
| 9686 | OPCODE_INFO2 (0xf4001b60, | |
| 9687 | OPRND_SHIFT0 (0_4, FREG), | |
| 9688 | OPRND_SHIFT0 (16_20, AREG)), | |
| 9689 | CSKY_ISA_FLOAT_7E60), | |
| 9690 | OP32 ("fmtvrl", | |
| 9691 | OPCODE_INFO2 (0xf4001b60, | |
| 9692 | OPRND_SHIFT0 (0_4, FREG), | |
| 9693 | OPRND_SHIFT0 (16_20, AREG)), | |
| 9694 | CSKY_ISA_FLOAT_7E60), | |
| 9695 | OP32 ("fmtvr.64", | |
| 9696 | OPCODE_INFO3 (0xf4001f80, | |
| 9697 | OPRND_SHIFT0 (0_4, FREG), | |
| 9698 | OPRND_SHIFT0 (16_20, AREG), | |
| 9699 | OPRND_SHIFT0 (21_25, AREG)), | |
| 9700 | CSKY_ISA_FLOAT_7E60), | |
| 9701 | OP32 ("fmfvr.64", | |
| 9702 | OPCODE_INFO3 (0xf4001f00, | |
| 9703 | OPRND_SHIFT0 (0_4, AREG), | |
| 9704 | OPRND_SHIFT0 (21_25, AREG), | |
| 9705 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9706 | CSKY_ISA_FLOAT_7E60), | |
| 9707 | OP32 ("fmtvr.32.2", | |
| 9708 | OPCODE_INFO3 (0xf4001fc0, | |
| 9709 | OPRND_SHIFT0 (0_4, FREG), | |
| 9710 | OPRND_SHIFT0 (16_20, AREG), | |
| 9711 | OPRND_SHIFT0 (21_25, AREG)), | |
| 9712 | CSKY_ISA_FLOAT_7E60), | |
| 9713 | OP32 ("fmfvr.32.2", | |
| 9714 | OPCODE_INFO3 (0xf4001f40, | |
| 9715 | OPRND_SHIFT0 (0_4, AREG), | |
| 9716 | OPRND_SHIFT0 (21_25, AREG), | |
| 9717 | OPRND_SHIFT0 (16_20, FREG)), | |
| 9718 | CSKY_ISA_FLOAT_7E60), | |
| 9719 | /* flsu. */ | |
| 9720 | OP32 ("fld.16", | |
| 9721 | SOPCODE_INFO2 (0xf4002300, | |
| 9722 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9723 | BRACKET_OPRND ((16_20, | |
| 9724 | AREG, | |
| 9725 | OPRND_SHIFT_0_BIT), | |
| 9726 | (4_7or21_24, | |
| 9727 | IMM_FLDST, | |
| 9728 | OPRND_SHIFT_1_BIT))), | |
| 9729 | CSKY_ISA_FLOAT_7E60), | |
| 9730 | OP32 ("fldh", | |
| 9731 | SOPCODE_INFO2 (0xf4002300, | |
| 9732 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9733 | BRACKET_OPRND ((16_20, | |
| 9734 | AREG, | |
| 9735 | OPRND_SHIFT_0_BIT), | |
| 9736 | (4_7or21_24, | |
| 9737 | IMM_FLDST, | |
| 9738 | OPRND_SHIFT_1_BIT))), | |
| 9739 | CSKY_ISA_FLOAT_7E60), | |
| 9740 | OP32_WITH_WORK ("fst.16", | |
| 9741 | SOPCODE_INFO2 (0xf4002700, | |
| 9742 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9743 | BRACKET_OPRND ((16_20, | |
| 9744 | AREG, | |
| 9745 | OPRND_SHIFT_0_BIT), | |
| 9746 | (4_7or21_24, | |
| 9747 | IMM_FLDST, | |
| 9748 | OPRND_SHIFT_1_BIT))), | |
| 9749 | CSKY_ISA_FLOAT_7E60, | |
| 9750 | float_work_fpuv3_fstore), | |
| 9751 | OP32_WITH_WORK ("fsth", | |
| 9752 | SOPCODE_INFO2 (0xf4002700, | |
| 9753 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9754 | BRACKET_OPRND ((16_20, | |
| 9755 | AREG, | |
| 9756 | OPRND_SHIFT_0_BIT), | |
| 9757 | (4_7or21_24, | |
| 9758 | IMM_FLDST, | |
| 9759 | OPRND_SHIFT_1_BIT))), | |
| 9760 | CSKY_ISA_FLOAT_7E60, | |
| 9761 | float_work_fpuv3_fstore), | |
| 9762 | OP32 ("fldr16", | |
| 9763 | SOPCODE_INFO2 (0xf4002b00, | |
| 9764 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 9765 | BRACKET_OPRND ((16_20, | |
| 9766 | AREG, | |
| 9767 | OPRND_SHIFT_0_BIT), | |
| 9768 | (5_6or21_25, | |
| 9769 | AREG_WITH_LSHIFT_FPU, | |
| 9770 | OPRND_SHIFT_0_BIT))), | |
| 9771 | CSKY_ISA_FLOAT_7E60), | |
| 9772 | OP32 ("fldrh", | |
| 9773 | SOPCODE_INFO2 (0xf4002b00, | |
| 9774 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 9775 | BRACKET_OPRND ((16_20, | |
| 9776 | AREG, | |
| 9777 | OPRND_SHIFT_0_BIT), | |
| 9778 | (5_6or21_25, | |
| 9779 | AREG_WITH_LSHIFT_FPU, | |
| 9780 | OPRND_SHIFT_0_BIT))), | |
| 9781 | CSKY_ISA_FLOAT_7E60), | |
| 9782 | OP32_WITH_WORK ("fstr.16", | |
| 9783 | SOPCODE_INFO2 (0xf4002f00, | |
| 9784 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 9785 | BRACKET_OPRND ((16_20, | |
| 9786 | AREG, | |
| 9787 | OPRND_SHIFT_0_BIT), | |
| 9788 | (5_6or21_25, | |
| 9789 | AREG_WITH_LSHIFT_FPU, | |
| 9790 | OPRND_SHIFT_0_BIT))), | |
| 9791 | CSKY_ISA_FLOAT_7E60, | |
| 9792 | float_work_fpuv3_fstore), | |
| 9793 | OP32_WITH_WORK ("fstrh", | |
| 9794 | SOPCODE_INFO2 (0xf4002f00, | |
| 9795 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 9796 | BRACKET_OPRND ((16_20, | |
| 9797 | AREG, | |
| 9798 | OPRND_SHIFT_0_BIT), | |
| 9799 | (5_6or21_25, | |
| 9800 | AREG_WITH_LSHIFT_FPU, | |
| 9801 | OPRND_SHIFT_0_BIT))), | |
| 9802 | CSKY_ISA_FLOAT_7E60, | |
| 9803 | float_work_fpuv3_fstore), | |
| 9804 | OP32 ("fldm.16", | |
| 9805 | OPCODE_INFO2 (0xf4003300, | |
| 9806 | (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 9807 | (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), | |
| 9808 | CSKY_ISA_FLOAT_7E60), | |
| 9809 | OP32 ("fldmh", | |
| 9810 | OPCODE_INFO2 (0xf4003300, | |
| 9811 | (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 9812 | (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), | |
| 9813 | CSKY_ISA_FLOAT_7E60), | |
| 9814 | OP32_WITH_WORK ("fstm.16", | |
| 9815 | OPCODE_INFO2 (0xf4003700, | |
| 9816 | (0_4or21_24, | |
| 9817 | FREGLIST_DASH, | |
| 9818 | OPRND_SHIFT_0_BIT), | |
| 9819 | (16_20, | |
| 9820 | AREG_WITH_BRACKET, | |
| 9821 | OPRND_SHIFT_0_BIT)), | |
| 9822 | CSKY_ISA_FLOAT_7E60, | |
| 9823 | float_work_fpuv3_fstore), | |
| 9824 | OP32_WITH_WORK ("fstmh", | |
| 9825 | OPCODE_INFO2 (0xf4003700, | |
| 9826 | (0_4or21_24, | |
| 9827 | FREGLIST_DASH, | |
| 9828 | OPRND_SHIFT_0_BIT), | |
| 9829 | (16_20, | |
| 9830 | AREG_WITH_BRACKET, | |
| 9831 | OPRND_SHIFT_0_BIT)), | |
| 9832 | CSKY_ISA_FLOAT_7E60, | |
| 9833 | float_work_fpuv3_fstore), | |
| 9834 | OP32 ("fldmu.16", | |
| 9835 | OPCODE_INFO2 (0xf4003380, | |
| 9836 | OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), | |
| 9837 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9838 | CSKY_ISA_FLOAT_7E60), | |
| 9839 | OP32 ("fldmu.h", | |
| 9840 | OPCODE_INFO2 (0xf4003380, | |
| 9841 | OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), | |
| 9842 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9843 | CSKY_ISA_FLOAT_7E60), | |
| 9844 | OP32_WITH_WORK ("fstmu.16", | |
| 9845 | OPCODE_INFO2 (0xf4003780, | |
| 9846 | OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), | |
| 9847 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9848 | CSKY_ISA_FLOAT_7E60, | |
| 9849 | float_work_fpuv3_fstore), | |
| 9850 | OP32_WITH_WORK ("fstmu.h", | |
| 9851 | OPCODE_INFO2 (0xf4003780, | |
| 9852 | OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), | |
| 9853 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9854 | CSKY_ISA_FLOAT_7E60, | |
| 9855 | float_work_fpuv3_fstore), | |
| 9856 | OP32 ("fld.32", | |
| 9857 | SOPCODE_INFO2 (0xf4002000, | |
| 9858 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9859 | BRACKET_OPRND ((16_20, | |
| 9860 | AREG, | |
| 9861 | OPRND_SHIFT_0_BIT), | |
| 9862 | (4_7or21_24, | |
| 9863 | IMM_FLDST, | |
| 9864 | OPRND_SHIFT_2_BIT))), | |
| 9865 | CSKY_ISA_FLOAT_7E60), | |
| 9866 | OP32 ("flds", | |
| 9867 | SOPCODE_INFO2 (0xf4002000, | |
| 9868 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9869 | BRACKET_OPRND ((16_20, | |
| 9870 | AREG, | |
| 9871 | OPRND_SHIFT_0_BIT), | |
| 9872 | (4_7or21_24, | |
| 9873 | IMM_FLDST, | |
| 9874 | OPRND_SHIFT_2_BIT))), | |
| 9875 | CSKY_ISA_FLOAT_7E60), | |
| 9876 | OP32_WITH_WORK ("fst.32", | |
| 9877 | SOPCODE_INFO2 (0xf4002400, | |
| 9878 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9879 | BRACKET_OPRND ((16_20, | |
| 9880 | AREG, | |
| 9881 | OPRND_SHIFT_0_BIT), | |
| 9882 | (4_7or21_24, | |
| 9883 | IMM_FLDST, | |
| 9884 | OPRND_SHIFT_2_BIT))), | |
| 9885 | CSKY_ISA_FLOAT_7E60, | |
| 9886 | float_work_fpuv3_fstore), | |
| 9887 | OP32_WITH_WORK ("fsts", | |
| 9888 | SOPCODE_INFO2 (0xf4002400, | |
| 9889 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9890 | BRACKET_OPRND ((16_20, | |
| 9891 | AREG, | |
| 9892 | OPRND_SHIFT_0_BIT), | |
| 9893 | (4_7or21_24, | |
| 9894 | IMM_FLDST, | |
| 9895 | OPRND_SHIFT_2_BIT))), | |
| 9896 | CSKY_ISA_FLOAT_7E60, | |
| 9897 | float_work_fpuv3_fstore), | |
| 9898 | OP32 ("fldr.32", | |
| 9899 | SOPCODE_INFO2 (0xf4002800, | |
| 9900 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 9901 | BRACKET_OPRND ((16_20, | |
| 9902 | AREG, | |
| 9903 | OPRND_SHIFT_0_BIT), | |
| 9904 | (5_6or21_25, | |
| 9905 | AREG_WITH_LSHIFT_FPU, | |
| 9906 | OPRND_SHIFT_0_BIT))), | |
| 9907 | CSKY_ISA_FLOAT_7E60), | |
| 9908 | OP32 ("fldrs", | |
| 9909 | SOPCODE_INFO2 (0xf4002800, | |
| 9910 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 9911 | BRACKET_OPRND ((16_20, | |
| 9912 | AREG, | |
| 9913 | OPRND_SHIFT_0_BIT), | |
| 9914 | (5_6or21_25, | |
| 9915 | AREG_WITH_LSHIFT_FPU, | |
| 9916 | OPRND_SHIFT_0_BIT))), | |
| 9917 | CSKY_ISA_FLOAT_7E60), | |
| 9918 | OP32_WITH_WORK ("fstr.32", | |
| 9919 | SOPCODE_INFO2 (0xf4002c00, | |
| 9920 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 9921 | BRACKET_OPRND ((16_20, | |
| 9922 | AREG, | |
| 9923 | OPRND_SHIFT_0_BIT), | |
| 9924 | (5_6or21_25, | |
| 9925 | AREG_WITH_LSHIFT_FPU, | |
| 9926 | OPRND_SHIFT_0_BIT))), | |
| 9927 | CSKY_ISA_FLOAT_7E60, | |
| 9928 | float_work_fpuv3_fstore), | |
| 9929 | OP32_WITH_WORK ("fstrs", | |
| 9930 | SOPCODE_INFO2 (0xf4002c00, | |
| 9931 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 9932 | BRACKET_OPRND ((16_20, | |
| 9933 | AREG, | |
| 9934 | OPRND_SHIFT_0_BIT), | |
| 9935 | (5_6or21_25, | |
| 9936 | AREG_WITH_LSHIFT_FPU, | |
| 9937 | OPRND_SHIFT_0_BIT))), | |
| 9938 | CSKY_ISA_FLOAT_7E60, | |
| 9939 | float_work_fpuv3_fstore), | |
| 9940 | OP32 ("fldm.32", | |
| 9941 | OPCODE_INFO2 (0xf4003000, | |
| 9942 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 9943 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9944 | CSKY_ISA_FLOAT_7E60), | |
| 9945 | OP32 ("fldms", | |
| 9946 | OPCODE_INFO2 (0xf4003000, | |
| 9947 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 9948 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9949 | CSKY_ISA_FLOAT_7E60), | |
| 9950 | OP32_WITH_WORK ("fstm.32", | |
| 9951 | OPCODE_INFO2 (0xf4003400, | |
| 9952 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 9953 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9954 | CSKY_ISA_FLOAT_7E60, | |
| 9955 | float_work_fpuv3_fstore), | |
| 9956 | OP32_WITH_WORK ("fstms", | |
| 9957 | OPCODE_INFO2 (0xf4003400, | |
| 9958 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 9959 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9960 | CSKY_ISA_FLOAT_7E60, | |
| 9961 | float_work_fpuv3_fstore), | |
| 9962 | OP32 ("fldmu.32", | |
| 9963 | OPCODE_INFO2 (0xf4003080, | |
| 9964 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 9965 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9966 | CSKY_ISA_FLOAT_7E60), | |
| 9967 | OP32 ("fldmu.s", | |
| 9968 | OPCODE_INFO2 (0xf4003080, | |
| 9969 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 9970 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9971 | CSKY_ISA_FLOAT_7E60), | |
| 9972 | OP32_WITH_WORK ("fstmu.32", | |
| 9973 | OPCODE_INFO2 (0xf4003480, | |
| 9974 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 9975 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9976 | CSKY_ISA_FLOAT_7E60, | |
| 9977 | float_work_fpuv3_fstore), | |
| 9978 | OP32_WITH_WORK ("fstmu.s", | |
| 9979 | OPCODE_INFO2 (0xf4003480, | |
| 9980 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 9981 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 9982 | CSKY_ISA_FLOAT_7E60, | |
| 9983 | float_work_fpuv3_fstore), | |
| 9984 | OP32 ("fld.64", | |
| 9985 | SOPCODE_INFO2 (0xf4002100, | |
| 9986 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9987 | BRACKET_OPRND ((16_20, | |
| 9988 | AREG, | |
| 9989 | OPRND_SHIFT_0_BIT), | |
| 9990 | (4_7or21_24, | |
| 9991 | IMM_FLDST, | |
| 9992 | OPRND_SHIFT_2_BIT))), | |
| 9993 | CSKY_ISA_FLOAT_7E60), | |
| 9994 | OP32 ("fldd", | |
| 9995 | SOPCODE_INFO2 (0xf4002100, | |
| 9996 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 9997 | BRACKET_OPRND ((16_20, | |
| 9998 | AREG, | |
| 9999 | OPRND_SHIFT_0_BIT), | |
| 10000 | (4_7or21_24, | |
| 10001 | IMM_FLDST, | |
| 10002 | OPRND_SHIFT_2_BIT))), | |
| 10003 | CSKY_ISA_FLOAT_7E60), | |
| 10004 | OP32_WITH_WORK ("fst.64", | |
| 10005 | SOPCODE_INFO2 (0xf4002500, | |
| 10006 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 10007 | BRACKET_OPRND ((16_20, | |
| 10008 | AREG, | |
| 10009 | OPRND_SHIFT_0_BIT), | |
| 10010 | (4_7or21_24, | |
| 10011 | IMM_FLDST, | |
| 10012 | OPRND_SHIFT_2_BIT))), | |
| 10013 | CSKY_ISA_FLOAT_7E60, | |
| 10014 | float_work_fpuv3_fstore), | |
| 10015 | OP32_WITH_WORK ("fstd", | |
| 10016 | SOPCODE_INFO2 (0xf4002500, | |
| 10017 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 10018 | BRACKET_OPRND ((16_20, | |
| 10019 | AREG, | |
| 10020 | OPRND_SHIFT_0_BIT), | |
| 10021 | (4_7or21_24, | |
| 10022 | IMM_FLDST, | |
| 10023 | OPRND_SHIFT_2_BIT))), | |
| 10024 | CSKY_ISA_FLOAT_7E60, | |
| 10025 | float_work_fpuv3_fstore), | |
| 10026 | OP32 ("fldr.64", | |
| 10027 | SOPCODE_INFO2 (0xf4002900, | |
| 10028 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 10029 | BRACKET_OPRND ((16_20, | |
| 10030 | AREG, | |
| 10031 | OPRND_SHIFT_0_BIT), | |
| 10032 | (5_6or21_25, | |
| 10033 | AREG_WITH_LSHIFT_FPU, | |
| 10034 | OPRND_SHIFT_0_BIT))), | |
| 10035 | CSKY_ISA_FLOAT_7E60), | |
| 10036 | OP32 ("fldrd", | |
| 10037 | SOPCODE_INFO2 (0xf4002900, | |
| 10038 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 10039 | BRACKET_OPRND ((16_20, | |
| 10040 | AREG, | |
| 10041 | OPRND_SHIFT_0_BIT), | |
| 10042 | (5_6or21_25, | |
| 10043 | AREG_WITH_LSHIFT_FPU, | |
| 10044 | OPRND_SHIFT_0_BIT))), | |
| 10045 | CSKY_ISA_FLOAT_7E60), | |
| 10046 | OP32_WITH_WORK ("fstr.64", | |
| 10047 | SOPCODE_INFO2 (0xf4002d00, | |
| 10048 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 10049 | BRACKET_OPRND ((16_20, | |
| 10050 | AREG, | |
| 10051 | OPRND_SHIFT_0_BIT), | |
| 10052 | (5_6or21_25, | |
| 10053 | AREG_WITH_LSHIFT_FPU, | |
| 10054 | OPRND_SHIFT_0_BIT))), | |
| 10055 | CSKY_ISA_FLOAT_7E60, | |
| 10056 | float_work_fpuv3_fstore), | |
| 10057 | OP32_WITH_WORK ("fstrd", | |
| 10058 | SOPCODE_INFO2 (0xf4002d00, | |
| 10059 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 10060 | BRACKET_OPRND ((16_20, | |
| 10061 | AREG, | |
| 10062 | OPRND_SHIFT_0_BIT), | |
| 10063 | (5_6or21_25, | |
| 10064 | AREG_WITH_LSHIFT_FPU, | |
| 10065 | OPRND_SHIFT_0_BIT))), | |
| 10066 | CSKY_ISA_FLOAT_7E60, | |
| 10067 | float_work_fpuv3_fstore), | |
| 10068 | OP32 ("fldm.64", | |
| 10069 | OPCODE_INFO2 (0xf4003100, | |
| 10070 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 10071 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 10072 | CSKY_ISA_FLOAT_7E60), | |
| 10073 | OP32 ("fldmd", | |
| 10074 | OPCODE_INFO2 (0xf4003100, | |
| 10075 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 10076 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 10077 | CSKY_ISA_FLOAT_7E60), | |
| 10078 | OP32_WITH_WORK ("fstm.64", | |
| 10079 | OPCODE_INFO2 (0xf4003500, | |
| 10080 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 10081 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 10082 | CSKY_ISA_FLOAT_7E60, | |
| 10083 | float_work_fpuv3_fstore), | |
| 10084 | OP32_WITH_WORK ("fstmd", | |
| 10085 | OPCODE_INFO2 (0xf4003500, | |
| 10086 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 10087 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 10088 | CSKY_ISA_FLOAT_7E60, | |
| 10089 | float_work_fpuv3_fstore), | |
| 10090 | OP32 ("fldmu.64", | |
| 10091 | OPCODE_INFO2 (0xf4003180, | |
| 10092 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 10093 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 10094 | CSKY_ISA_FLOAT_7E60), | |
| 10095 | OP32 ("fldmu.d", | |
| 10096 | OPCODE_INFO2 (0xf4003180, | |
| 10097 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 10098 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 10099 | CSKY_ISA_FLOAT_7E60), | |
| 10100 | OP32_WITH_WORK ("fstmu.64", | |
| 10101 | OPCODE_INFO2 (0xf4003580, | |
| 10102 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 10103 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 10104 | CSKY_ISA_FLOAT_7E60, | |
| 10105 | float_work_fpuv3_fstore), | |
| 10106 | OP32_WITH_WORK ("fstmu.d", | |
| 10107 | OPCODE_INFO2 (0xf4003580, | |
| 10108 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
| 10109 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
| 10110 | CSKY_ISA_FLOAT_7E60, | |
| 10111 | float_work_fpuv3_fstore), | |
| 10112 | OP32 ("fldrm", | |
| 10113 | SOPCODE_INFO2 (0xf4002a00, | |
| 10114 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 10115 | BRACKET_OPRND ((16_20, | |
| 10116 | AREG, | |
| 10117 | OPRND_SHIFT_0_BIT), | |
| 10118 | (5_6or21_25, | |
| 10119 | AREG_WITH_LSHIFT_FPU, | |
| 10120 | OPRND_SHIFT_0_BIT))), | |
| 10121 | CSKY_ISA_FLOAT_7E60), | |
| 10122 | OP32_WITH_WORK ("fstrm", | |
| 10123 | SOPCODE_INFO2 (0xf4002e00, | |
| 10124 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
| 10125 | BRACKET_OPRND ((16_20, | |
| 10126 | AREG, | |
| 10127 | OPRND_SHIFT_0_BIT), | |
| 10128 | (5_6or21_25, | |
| 10129 | AREG_WITH_LSHIFT_FPU, | |
| 10130 | OPRND_SHIFT_0_BIT))), | |
| 10131 | CSKY_ISA_FLOAT_7E60, | |
| 10132 | float_work_fpuv3_fstore), | |
| 10133 | OP32 ("fldmm", | |
| 10134 | OPCODE_INFO2 (0xf4003200, | |
| 10135 | (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 10136 | (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), | |
| 10137 | CSKY_ISA_FLOAT_7E60), | |
| 10138 | OP32_WITH_WORK ("fstmm", | |
| 10139 | OPCODE_INFO2 (0xf4003600, | |
| 10140 | (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
| 10141 | (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), | |
| 10142 | CSKY_ISA_FLOAT_7E60, | |
| 10143 | float_work_fpuv3_fstore), | |
| 10144 | OP32 ("fftox.f16.u16", | |
| 10145 | OPCODE_INFO2 (0xf4004000, | |
| 10146 | OPRND_SHIFT0 (0_4, FREG), | |
| 10147 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10148 | CSKY_ISA_FLOAT_7E60), | |
| 10149 | OP32 ("fftox.f16.s16", | |
| 10150 | OPCODE_INFO2 (0xf4004020, | |
| 10151 | OPRND_SHIFT0 (0_4, FREG), | |
| 10152 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10153 | CSKY_ISA_FLOAT_7E60), | |
| 10154 | OP32 ("fftox.f16.u32", | |
| 10155 | OPCODE_INFO2 (0xf4004100, | |
| 10156 | OPRND_SHIFT0 (0_4, FREG), | |
| 10157 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10158 | CSKY_ISA_FLOAT_7E60), | |
| 10159 | OP32 ("fftox.f16.s32", | |
| 10160 | OPCODE_INFO2 (0xf4004120, | |
| 10161 | OPRND_SHIFT0 (0_4, FREG), | |
| 10162 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10163 | CSKY_ISA_FLOAT_7E60), | |
| 10164 | OP32 ("fftox.f32.u32", | |
| 10165 | OPCODE_INFO2 (0xf4004140, | |
| 10166 | OPRND_SHIFT0 (0_4, FREG), | |
| 10167 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10168 | CSKY_ISA_FLOAT_7E60), | |
| 10169 | OP32 ("fftox.f32.s32", | |
| 10170 | OPCODE_INFO2 (0xf4004160, | |
| 10171 | OPRND_SHIFT0 (0_4, FREG), | |
| 10172 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10173 | CSKY_ISA_FLOAT_7E60), | |
| 10174 | OP32 ("fftox.f64.u32", | |
| 10175 | OPCODE_INFO2 (0xf4004180, | |
| 10176 | OPRND_SHIFT0 (0_4, FREG), | |
| 10177 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10178 | CSKY_ISA_FLOAT_7E60), | |
| 10179 | OP32 ("fftox.f64.s32", | |
| 10180 | OPCODE_INFO2 (0xf40041a0, | |
| 10181 | OPRND_SHIFT0 (0_4, FREG), | |
| 10182 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10183 | CSKY_ISA_FLOAT_7E60), | |
| 10184 | OP32 ("fxtof.u16.f16", | |
| 10185 | OPCODE_INFO2 (0xf4004800, | |
| 10186 | OPRND_SHIFT0 (0_4, FREG), | |
| 10187 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10188 | CSKY_ISA_FLOAT_7E60), | |
| 10189 | OP32 ("fxtof.s16.f16", | |
| 10190 | OPCODE_INFO2 (0xf4004820, | |
| 10191 | OPRND_SHIFT0 (0_4, FREG), | |
| 10192 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10193 | CSKY_ISA_FLOAT_7E60), | |
| 10194 | OP32 ("fxtof.u32.f16", | |
| 10195 | OPCODE_INFO2 (0xf4004900, | |
| 10196 | OPRND_SHIFT0 (0_4, FREG), | |
| 10197 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10198 | CSKY_ISA_FLOAT_7E60), | |
| 10199 | OP32 ("fxtof.s32.f16", | |
| 10200 | OPCODE_INFO2 (0xf4004920, | |
| 10201 | OPRND_SHIFT0 (0_4, FREG), | |
| 10202 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10203 | CSKY_ISA_FLOAT_7E60), | |
| 10204 | OP32 ("fxtof.u32.f32", | |
| 10205 | OPCODE_INFO2 (0xf4004940, | |
| 10206 | OPRND_SHIFT0 (0_4, FREG), | |
| 10207 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10208 | CSKY_ISA_FLOAT_7E60), | |
| 10209 | OP32 ("fxtof.s32.f32", | |
| 10210 | OPCODE_INFO2 (0xf4004960, | |
| 10211 | OPRND_SHIFT0 (0_4, FREG), | |
| 10212 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10213 | CSKY_ISA_FLOAT_7E60), | |
| 10214 | OP32 ("fxtof.u32.f64", | |
| 10215 | OPCODE_INFO2 (0xf4004980, | |
| 10216 | OPRND_SHIFT0 (0_4, FREG), | |
| 10217 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10218 | CSKY_ISA_FLOAT_7E60), | |
| 10219 | OP32 ("fxtof.s32.f64", | |
| 10220 | OPCODE_INFO2 (0xf40049a0, | |
| 10221 | OPRND_SHIFT0 (0_4, FREG), | |
| 10222 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10223 | CSKY_ISA_FLOAT_7E60), | |
| 10224 | OP32 ("fftoi.f16.s16", | |
| 10225 | OPCODE_INFO2 (0xf4004220, | |
| 10226 | OPRND_SHIFT0 (0_4, FREG), | |
| 10227 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10228 | CSKY_ISA_FLOAT_7E60), | |
| 10229 | OP32 ("fftoi.f16.u16", | |
| 10230 | OPCODE_INFO2 (0xf4004200, | |
| 10231 | OPRND_SHIFT0 (0_4, FREG), | |
| 10232 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10233 | CSKY_ISA_FLOAT_7E60), | |
| 10234 | OP32 ("fftoi.f16.s32", | |
| 10235 | OPCODE_INFO2 (0xf4004320, | |
| 10236 | OPRND_SHIFT0 (0_4, FREG), | |
| 10237 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10238 | CSKY_ISA_FLOAT_7E60), | |
| 10239 | OP32 ("fftoi.f16.u32", | |
| 10240 | OPCODE_INFO2 (0xf4004300, | |
| 10241 | OPRND_SHIFT0 (0_4, FREG), | |
| 10242 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10243 | CSKY_ISA_FLOAT_7E60), | |
| 10244 | OP32 ("fftoi.f32.s32", | |
| 10245 | OPCODE_INFO2 (0xf4004360, | |
| 10246 | OPRND_SHIFT0 (0_4, FREG), | |
| 10247 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10248 | CSKY_ISA_FLOAT_7E60), | |
| 10249 | OP32 ("fftoi.f32.u32", | |
| 10250 | OPCODE_INFO2 (0xf4004340, | |
| 10251 | OPRND_SHIFT0 (0_4, FREG), | |
| 10252 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10253 | CSKY_ISA_FLOAT_7E60), | |
| 10254 | OP32 ("fftoi.f64.s32", | |
| 10255 | OPCODE_INFO2 (0xf40043a0, | |
| 10256 | OPRND_SHIFT0 (0_4, FREG), | |
| 10257 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10258 | CSKY_ISA_FLOAT_7E60), | |
| 10259 | OP32 ("fftoi.f64.u32", | |
| 10260 | OPCODE_INFO2 (0xf4004380, | |
| 10261 | OPRND_SHIFT0 (0_4, FREG), | |
| 10262 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10263 | CSKY_ISA_FLOAT_7E60), | |
| 10264 | OP32 ("fitof.s16.f16", | |
| 10265 | OPCODE_INFO2 (0xf4004a20, | |
| 10266 | OPRND_SHIFT0 (0_4, FREG), | |
| 10267 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10268 | CSKY_ISA_FLOAT_7E60), | |
| 10269 | OP32 ("fitof.u16.f16", | |
| 10270 | OPCODE_INFO2 (0xf4004a00, | |
| 10271 | OPRND_SHIFT0 (0_4, FREG), | |
| 10272 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10273 | CSKY_ISA_FLOAT_7E60), | |
| 10274 | OP32 ("fitof.s32.f16", | |
| 10275 | OPCODE_INFO2 (0xf4004b20, | |
| 10276 | OPRND_SHIFT0 (0_4, FREG), | |
| 10277 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10278 | CSKY_ISA_FLOAT_7E60), | |
| 10279 | OP32 ("fitof.u32.f16", | |
| 10280 | OPCODE_INFO2 (0xf4004b00, | |
| 10281 | OPRND_SHIFT0 (0_4, FREG), | |
| 10282 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10283 | CSKY_ISA_FLOAT_7E60), | |
| 10284 | OP32 ("fitof.s32.f32", | |
| 10285 | OPCODE_INFO2 (0xf4004b60, | |
| 10286 | OPRND_SHIFT0 (0_4, FREG), | |
| 10287 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10288 | CSKY_ISA_FLOAT_7E60), | |
| 10289 | OP32 ("fsitos", | |
| 10290 | OPCODE_INFO2 (0xf4004b60, | |
| 10291 | OPRND_SHIFT0 (0_4, FREG), | |
| 10292 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10293 | CSKY_ISA_FLOAT_7E60), | |
| 10294 | OP32 ("fitof.u32.f32", | |
| 10295 | OPCODE_INFO2 (0xf4004b40, | |
| 10296 | OPRND_SHIFT0 (0_4, FREG), | |
| 10297 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10298 | CSKY_ISA_FLOAT_7E60), | |
| 10299 | OP32 ("fuitos", | |
| 10300 | OPCODE_INFO2 (0xf4004b40, | |
| 10301 | OPRND_SHIFT0 (0_4, FREG), | |
| 10302 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10303 | CSKY_ISA_FLOAT_7E60), | |
| 10304 | OP32 ("fitof.s32.f64", | |
| 10305 | OPCODE_INFO2 (0xf4004ba0, | |
| 10306 | OPRND_SHIFT0 (0_4, FREG), | |
| 10307 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10308 | CSKY_ISA_FLOAT_7E60), | |
| 10309 | OP32 ("fsitod", | |
| 10310 | OPCODE_INFO2 (0xf4004ba0, | |
| 10311 | OPRND_SHIFT0 (0_4, FREG), | |
| 10312 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10313 | CSKY_ISA_FLOAT_7E60), | |
| 10314 | OP32 ("fitof.u32.f64", | |
| 10315 | OPCODE_INFO2 (0xf4004b80, | |
| 10316 | OPRND_SHIFT0 (0_4, FREG), | |
| 10317 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10318 | CSKY_ISA_FLOAT_7E60), | |
| 10319 | OP32 ("fuitod", | |
| 10320 | OPCODE_INFO2 (0xf4004b80, | |
| 10321 | OPRND_SHIFT0 (0_4, FREG), | |
| 10322 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10323 | CSKY_ISA_FLOAT_7E60), | |
| 10324 | OP32 ("fftofi.f16.rn", | |
| 10325 | OPCODE_INFO2 (0xf4004400, | |
| 10326 | OPRND_SHIFT0 (0_4, FREG), | |
| 10327 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10328 | CSKY_ISA_FLOAT_7E60), | |
| 10329 | OP32 ("fftofi.f16.rz", | |
| 10330 | OPCODE_INFO2 (0xf4004420, | |
| 10331 | OPRND_SHIFT0 (0_4, FREG), | |
| 10332 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10333 | CSKY_ISA_FLOAT_7E60), | |
| 10334 | OP32 ("fftofi.f16.rpi", | |
| 10335 | OPCODE_INFO2 (0xf4004440, | |
| 10336 | OPRND_SHIFT0 (0_4, FREG), | |
| 10337 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10338 | CSKY_ISA_FLOAT_7E60), | |
| 10339 | OP32 ("fftofi.f16.rni", | |
| 10340 | OPCODE_INFO2 (0xf4004460, | |
| 10341 | OPRND_SHIFT0 (0_4, FREG), | |
| 10342 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10343 | CSKY_ISA_FLOAT_7E60), | |
| 10344 | OP32 ("fftofi.f32.rn", | |
| 10345 | OPCODE_INFO2 (0xf4004480, | |
| 10346 | OPRND_SHIFT0 (0_4, FREG), | |
| 10347 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10348 | CSKY_ISA_FLOAT_7E60), | |
| 10349 | OP32 ("fftofi.f32.rz", | |
| 10350 | OPCODE_INFO2 (0xf40044a0, | |
| 10351 | OPRND_SHIFT0 (0_4, FREG), | |
| 10352 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10353 | CSKY_ISA_FLOAT_7E60), | |
| 10354 | OP32 ("fftofi.f32.rpi", | |
| 10355 | OPCODE_INFO2 (0xf40044c0, | |
| 10356 | OPRND_SHIFT0 (0_4, FREG), | |
| 10357 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10358 | CSKY_ISA_FLOAT_7E60), | |
| 10359 | OP32 ("fftofi.f32.rni", | |
| 10360 | OPCODE_INFO2 (0xf40044e0, | |
| 10361 | OPRND_SHIFT0 (0_4, FREG), | |
| 10362 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10363 | CSKY_ISA_FLOAT_7E60), | |
| 10364 | OP32 ("fftofi.f64.rn", | |
| 10365 | OPCODE_INFO2 (0xf4004500, | |
| 10366 | OPRND_SHIFT0 (0_4, FREG), | |
| 10367 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10368 | CSKY_ISA_FLOAT_7E60), | |
| 10369 | OP32 ("fftofi.f64.rz", | |
| 10370 | OPCODE_INFO2 (0xf4004520, | |
| 10371 | OPRND_SHIFT0 (0_4, FREG), | |
| 10372 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10373 | CSKY_ISA_FLOAT_7E60), | |
| 10374 | OP32 ("fftofi.f64.rpi", | |
| 10375 | OPCODE_INFO2 (0xf4004540, | |
| 10376 | OPRND_SHIFT0 (0_4, FREG), | |
| 10377 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10378 | CSKY_ISA_FLOAT_7E60), | |
| 10379 | OP32 ("fftofi.f64.rni", | |
| 10380 | OPCODE_INFO2 (0xf4004560, | |
| 10381 | OPRND_SHIFT0 (0_4, FREG), | |
| 10382 | OPRND_SHIFT0 (16_20, FREG)), | |
| 10383 | CSKY_ISA_FLOAT_7E60), | |
| 10384 | DOP32_WITH_WORK ("fmovi.16", | |
| 10385 | OPCODE_INFO2 (0xf400e400, | |
| 10386 | OPRND_SHIFT0 (0_4, FREG), | |
| 10387 | OPRND_SHIFT0 (5or8_9or16_25, HFLOAT_FMOVI)), | |
| 10388 | OPCODE_INFO3 (0xf400e400, | |
| 10389 | OPRND_SHIFT0 (0_4, FREG), | |
| 10390 | OPRND_SHIFT0 (5or8_9or20_25, IMM9b), | |
| 10391 | OPRND_SHIFT0 (16_19, IMM4b)), | |
| 10392 | CSKY_ISA_FLOAT_7E60, | |
| 10393 | float_work_fpuv3_fmovi), | |
| 10394 | DOP32_WITH_WORK ("fmovi.32", | |
| 10395 | OPCODE_INFO2 (0xf400e440, | |
| 10396 | OPRND_SHIFT0 (0_4, FREG), | |
| 10397 | OPRND_SHIFT0 (5or8_9or16_25, SFLOAT_FMOVI)), | |
| 10398 | OPCODE_INFO3 (0xf400e440, | |
| 10399 | OPRND_SHIFT0 (0_4, FREG), | |
| 10400 | OPRND_SHIFT0 (5or8_9or20_25, IMM9b), | |
| 10401 | OPRND_SHIFT0 (16_19, IMM4b)), | |
| 10402 | CSKY_ISA_FLOAT_7E60, | |
| 10403 | float_work_fpuv3_fmovi), | |
| 10404 | DOP32_WITH_WORK ("fmovi.64", | |
| 10405 | OPCODE_INFO2 (0xf400e480, | |
| 10406 | OPRND_SHIFT0 (0_4, FREG), | |
| 10407 | OPRND_SHIFT0 (5or8_9or16_25, DFLOAT_FMOVI)), | |
| 10408 | OPCODE_INFO3 (0xf400e480, | |
| 10409 | OPRND_SHIFT0 (0_4, FREG), | |
| 10410 | OPRND_SHIFT0 (5or8_9or20_25, IMM9b), | |
| 10411 | OPRND_SHIFT0 (16_19, IMM4b)), | |
| 10412 | CSKY_ISA_FLOAT_7E60, | |
| 10413 | float_work_fpuv3_fmovi), | |
| 10414 | #undef _RELOC32 | |
| 10415 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 | |
| 10416 | OP32 ("flrw.32", | |
| 10417 | OPCODE_INFO2 (0xf4003800, | |
| 10418 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 10419 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
| 10420 | CSKY_ISA_FLOAT_7E60), | |
| 10421 | OP32 ("flrws", | |
| 10422 | OPCODE_INFO2 (0xf4003800, | |
| 10423 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 10424 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
| 10425 | CSKY_ISA_FLOAT_7E60), | |
| 10426 | OP32 ("flrw.64", | |
| 10427 | OPCODE_INFO2 (0xf4003900, | |
| 10428 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 10429 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
| 10430 | CSKY_ISA_FLOAT_7E60), | |
| 10431 | OP32 ("flrwd", | |
| 10432 | OPCODE_INFO2 (0xf4003900, | |
| 10433 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
| 10434 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
| 10435 | CSKY_ISA_FLOAT_7E60), | |
| 10436 | #undef _RELOC32 | |
| 10437 | #define _RELOC32 0 | |
| 10438 | ||
| b8891f8d AJ |
10439 | /* The following are aliases for other instructions. */ |
| 10440 | /* setc -> cmphs r0, r0 */ | |
| 10441 | OP16 ("setc", | |
| 10442 | OPCODE_INFO0 (0x6400), | |
| 10443 | CSKYV2_ISA_E1), | |
| 10444 | /* clrc -> cmpne r0, r0 */ | |
| 10445 | OP16 ("clrc", | |
| 10446 | OPCODE_INFO0 (0x6402), | |
| 10447 | CSKYV2_ISA_E1), | |
| 10448 | /* tstlt rd -> btsti rd,31 */ | |
| 10449 | OP32 ("tstlt", | |
| 10450 | OPCODE_INFO1 (0xc7e02880, | |
| 10451 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10452 | CSKYV2_ISA_1E2), | |
| 10453 | /* idly4 -> idly 4 */ | |
| 10454 | OP32 ("idly4", | |
| 10455 | OPCODE_INFO0 (0xc0601c20), | |
| 10456 | CSKYV2_ISA_E1), | |
| 10457 | /* rsub rz, ry, rx -> subu rz, rx, ry */ | |
| 10458 | DOP32 ("rsub", | |
| 10459 | OPCODE_INFO3 (0xc4000080, | |
| 10460 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10461 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 10462 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10463 | OPCODE_INFO2 (0xc4000080, | |
| 10464 | (0_4or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 10465 | (16_20, AREG, OPRND_SHIFT_0_BIT)), CSKYV2_ISA_1E2), | |
| 10466 | /* cmplei rd,X -> cmplti rd,X+1 */ | |
| 10467 | OP16_OP32 ("cmplei", | |
| 10468 | OPCODE_INFO2 (0x3820, | |
| 10469 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
| 10470 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
| 10471 | CSKYV2_ISA_E1, | |
| 10472 | OPCODE_INFO2 (0xeb200000, | |
| 10473 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 10474 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), | |
| 10475 | CSKYV2_ISA_1E2), | |
| 10476 | /* cmpls -> cmphs */ | |
| 10477 | OP16_OP32 ("cmpls", | |
| 10478 | OPCODE_INFO2 (0x6400, | |
| 10479 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 10480 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 10481 | CSKYV2_ISA_E1, | |
| 10482 | OPCODE_INFO2 (0xc4000420, | |
| 10483 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 10484 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10485 | CSKYV2_ISA_2E3), | |
| 10486 | /* cmpgt -> cmplt */ | |
| 10487 | OP16_OP32 ("cmpgt", | |
| 10488 | OPCODE_INFO2 (0x6401, | |
| 10489 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 10490 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
| 10491 | CSKYV2_ISA_E1, | |
| 10492 | OPCODE_INFO2 (0xc4000440, | |
| 10493 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
| 10494 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10495 | CSKYV2_ISA_2E3), | |
| 10496 | /* tstle rd -> cmplti rd,1 */ | |
| 10497 | OP16_OP32 ("tstle", | |
| 10498 | OPCODE_INFO1 (0x3820, | |
| 10499 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 10500 | CSKYV2_ISA_E1, | |
| 10501 | OPCODE_INFO1 (0xeb200000, | |
| 10502 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10503 | CSKYV2_ISA_1E2), | |
| 10504 | /* tstne rd -> cmpnei rd,0 */ | |
| 10505 | OP16_OP32 ("tstne", | |
| 10506 | OPCODE_INFO1 (0x3840, | |
| 10507 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), | |
| 10508 | CSKYV2_ISA_E1, | |
| 10509 | OPCODE_INFO1 (0xeb400000, | |
| 10510 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10511 | CSKYV2_ISA_1E2), | |
| 10512 | /* rotri rz, rx, imm5 -> rotli rz, rx, 32-imm5 */ | |
| 10513 | DOP32 ("rotri", | |
| 10514 | OPCODE_INFO3 (0xc4004900, | |
| 10515 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10516 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 10517 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
| 10518 | OPCODE_INFO2 (0xc4004900, | |
| 10519 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 10520 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
| 10521 | CSKYV2_ISA_2E3), | |
| 10522 | DOP32 ("rori", | |
| 10523 | OPCODE_INFO3 (0xc4004900, | |
| 10524 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10525 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
| 10526 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
| 10527 | OPCODE_INFO2 (0xc4004900, | |
| 10528 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
| 10529 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
| 10530 | CSKYV2_ISA_2E3), | |
| 10531 | ||
| 10532 | /* rotlc rd -> addc rd, rd/ addc rd, rd, rd */ | |
| 10533 | OP16_OP32_WITH_WORK ("rotlc", | |
| 10534 | OPCODE_INFO2 (0x6001, | |
| 10535 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
| 10536 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 10537 | CSKYV2_ISA_E1, | |
| 10538 | OPCODE_INFO2 (0xc4000040, | |
| 10539 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 10540 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
| 10541 | CSKYV2_ISA_2E3, | |
| 10542 | v2_work_rotlc), | |
| 10543 | /* not rd -> nor rd, rd, not rz, rx -> nor rz, rx, rx */ | |
| 10544 | OP16_OP32_WITH_WORK ("not", | |
| 10545 | OPCODE_INFO1 (0x6c02, | |
| 10546 | (NONE, AREG, OPRND_SHIFT_0_BIT)), | |
| 10547 | CSKYV2_ISA_E1, | |
| 10548 | OPCODE_INFO2 (0xc4002480, | |
| 10549 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
| 10550 | (NONE, AREG, OPRND_SHIFT_0_BIT)), | |
| 10551 | CSKYV2_ISA_E1, v2_work_not), | |
| 10552 | ||
| 10553 | /* Special force 32 bits instruction. */ | |
| 10554 | OP32 ("xtrb0.32", | |
| 10555 | OPCODE_INFO2 (0xc4007020, | |
| 10556 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10557 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10558 | CSKYV2_ISA_1E2), | |
| 10559 | OP32 ("xtrb1.32", | |
| 10560 | OPCODE_INFO2 (0xc4007040, | |
| 10561 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10562 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10563 | CSKYV2_ISA_1E2), | |
| 10564 | OP32 ("xtrb2.32", | |
| 10565 | OPCODE_INFO2 (0xc4007080, | |
| 10566 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10567 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10568 | CSKYV2_ISA_1E2), | |
| 10569 | OP32 ("xtrb3.32", | |
| 10570 | OPCODE_INFO2 (0xc4007100, | |
| 10571 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10572 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10573 | CSKYV2_ISA_1E2), | |
| 10574 | OP32 ("ff0.32", | |
| 10575 | OPCODE_INFO2 (0xc4007c20, | |
| 10576 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10577 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10578 | CSKYV2_ISA_1E2), | |
| 10579 | DOP32 ("ff1.32", | |
| 10580 | OPCODE_INFO2 (0xc4007c40, | |
| 10581 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
| 10582 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
| 10583 | OPCODE_INFO1 (0xc4007c40, | |
| 10584 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
| 10585 | CSKYV2_ISA_1E2), | |
| 1feede9b | 10586 | |
| f24ff6e9 | 10587 | {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL} |
| b8891f8d | 10588 | }; |