[thirdparty/binutils-gdb.git] / opcodes / m32r-opc.h

/* Instruction description for m32r.

This file is machine generated with CGEN.

Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifndef m32r_OPC_H
#define m32r_OPC_H

#define CGEN_ARCH m32r

/* Given symbol S, return m32r_cgen_<s>.  */
#define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)

/* Selected cpu families.  */
#define HAVE_CPU_M32R
/* start-sanitize-m32rx */
#define HAVE_CPU_M32RX
/* end-sanitize-m32rx */

#define CGEN_WORD_BITSIZE 32
#define CGEN_DEFAULT_INSN_BITSIZE 32
#define CGEN_BASE_INSN_BITSIZE 32
#define CGEN_MAX_INSN_BITSIZE 32
#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
#define CGEN_INT_INSN

/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */

/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
   we can't hash on everything up to the space.  */
#define CGEN_MNEMONIC_OPERANDS

/* Enums.  */

/* Enum declaration for insn format enums.  */
typedef enum insn_op1 {
  OP1_0, OP1_1, OP1_2, OP1_3
 , OP1_4, OP1_5, OP1_6, OP1_7
 , OP1_8, OP1_9, OP1_10, OP1_11
 , OP1_12, OP1_13, OP1_14, OP1_15
} INSN_OP1;

/* Enum declaration for op2 enums.  */
typedef enum insn_op2 {
  OP2_0, OP2_1, OP2_2, OP2_3
 , OP2_4, OP2_5, OP2_6, OP2_7
 , OP2_8, OP2_9, OP2_10, OP2_11
 , OP2_12, OP2_13, OP2_14, OP2_15
} INSN_OP2;

/* Enum declaration for m32r operand types.  */
typedef enum cgen_operand_type {
  M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
 , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
 , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
/* start-sanitize-m32rx */
 , M32R_OPERAND_ACCS
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_OPERAND_ACC
/* end-sanitize-m32rx */
 , M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
 , M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
 , M32R_OPERAND_ACCUM
/* start-sanitize-m32rx */
 , M32R_OPERAND_ABORT_PARALLEL_EXECUTION
/* end-sanitize-m32rx */
 , M32R_OPERAND_MAX
} CGEN_OPERAND_TYPE;

/* Non-boolean attributes.  */

/* Enum declaration for machine type selection.  */
typedef enum mach_attr {
  MACH_M32R
/* start-sanitize-m32rx */
 , MACH_M32RX
/* end-sanitize-m32rx */
 , MACH_MAX
} MACH_ATTR;

/* start-sanitize-m32rx */
/* Enum declaration for parallel execution pipeline selection.  */
typedef enum pipe_attr {
  PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
} PIPE_ATTR;

/* end-sanitize-m32rx */
/* Number of architecture variants.  */
#define MAX_MACHS ((int) MACH_MAX)

/* Number of operands.  */
#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)

/* Operand and instruction attribute indices.  */

/* Enum declaration for cgen_operand attrs.  */
typedef enum cgen_operand_attr {
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC
 , CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
 , CGEN_OPERAND_UNSIGNED
} CGEN_OPERAND_ATTR;

/* Number of non-boolean elements in cgen_operand.  */
#define CGEN_OPERAND_MAX_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)

/* Enum declaration for cgen_insn attrs.  */
typedef enum cgen_insn_attr {
  CGEN_INSN_MACH
/* start-sanitize-m32rx */
 , CGEN_INSN_PIPE
/* end-sanitize-m32rx */
 , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL
 , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
} CGEN_INSN_ATTR;

/* Number of non-boolean elements in cgen_insn.  */
#define CGEN_INSN_MAX_ATTRS ((int) CGEN_INSN_ALIAS)

/* Insn types are used by the simulator.  */
/* Enum declaration for m32r instruction types.  */
typedef enum cgen_insn_type {
  M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_ADD3_A
 , M32R_INSN_AND, M32R_INSN_AND3, M32R_INSN_AND3_A, M32R_INSN_OR
 , M32R_INSN_OR3, M32R_INSN_OR3_A, M32R_INSN_XOR, M32R_INSN_XOR3
 , M32R_INSN_XOR3_A, M32R_INSN_ADDI, M32R_INSN_ADDI_A, M32R_INSN_ADDV
 , M32R_INSN_ADDV3, M32R_INSN_ADDV3_A, M32R_INSN_ADDX, M32R_INSN_BC8
 , M32R_INSN_BC8_S, M32R_INSN_BC24, M32R_INSN_BC24_L, M32R_INSN_BEQ
 , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
 , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL8_S
 , M32R_INSN_BL24, M32R_INSN_BL24_L
/* start-sanitize-m32rx */
 , M32R_INSN_BCL8
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_BCL8_S
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_BCL24
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_BCL24_L
/* end-sanitize-m32rx */
 , M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L
 , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24
 , M32R_INSN_BRA24_L
/* start-sanitize-m32rx */
 , M32R_INSN_BNCL8
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_BNCL8_S
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_BNCL24
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_BNCL24_L
/* end-sanitize-m32rx */
 , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPI_A, M32R_INSN_CMPU
 , M32R_INSN_CMPUI, M32R_INSN_CMPUI_A
/* start-sanitize-m32rx */
 , M32R_INSN_CMPEQ
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_CMPZ
/* end-sanitize-m32rx */
 , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
/* start-sanitize-m32rx */
 , M32R_INSN_JC
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_JNC
/* end-sanitize-m32rx */
 , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_2
 , M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB, M32R_INSN_LDB_2
 , M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH, M32R_INSN_LDH_2
 , M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB, M32R_INSN_LDUB_2
 , M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH, M32R_INSN_LDUH_2
 , M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS, M32R_INSN_LD24
 , M32R_INSN_LD24_A, M32R_INSN_LDI8, M32R_INSN_LDI8_A, M32R_INSN_LDI8A
 , M32R_INSN_LDI8A_A, M32R_INSN_LDI16, M32R_INSN_LDI16A, M32R_INSN_LOCK
 , M32R_INSN_MACHI
/* start-sanitize-m32rx */
 , M32R_INSN_MACHI_A
/* end-sanitize-m32rx */
 , M32R_INSN_MACLO
/* start-sanitize-m32rx */
 , M32R_INSN_MACLO_A
/* end-sanitize-m32rx */
 , M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI
/* start-sanitize-m32rx */
 , M32R_INSN_MULHI_A
/* end-sanitize-m32rx */
 , M32R_INSN_MULLO
/* start-sanitize-m32rx */
 , M32R_INSN_MULLO_A
/* end-sanitize-m32rx */
 , M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV, M32R_INSN_MVFACHI
/* start-sanitize-m32rx */
 , M32R_INSN_MVFACHI_A
/* end-sanitize-m32rx */
 , M32R_INSN_MVFACLO
/* start-sanitize-m32rx */
 , M32R_INSN_MVFACLO_A
/* end-sanitize-m32rx */
 , M32R_INSN_MVFACMI
/* start-sanitize-m32rx */
 , M32R_INSN_MVFACMI_A
/* end-sanitize-m32rx */
 , M32R_INSN_MVFC, M32R_INSN_MVTACHI
/* start-sanitize-m32rx */
 , M32R_INSN_MVTACHI_A
/* end-sanitize-m32rx */
 , M32R_INSN_MVTACLO
/* start-sanitize-m32rx */
 , M32R_INSN_MVTACLO_A
/* end-sanitize-m32rx */
 , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
 , M32R_INSN_RAC
/* start-sanitize-m32rx */
 , M32R_INSN_RAC_A
/* end-sanitize-m32rx */
 , M32R_INSN_RACH
/* start-sanitize-m32rx */
 , M32R_INSN_RACH_A
/* end-sanitize-m32rx */
 , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL
 , M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A
 , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRA3_A, M32R_INSN_SRAI
 , M32R_INSN_SRAI_A, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRL3_A
 , M32R_INSN_SRLI, M32R_INSN_SRLI_A, M32R_INSN_ST, M32R_INSN_ST_2
 , M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2
 , M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2
 , M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS
 , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
 , M32R_INSN_TRAP_A, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP
/* start-sanitize-m32rx */
 , M32R_INSN_SATB
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_SATH
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_SAT
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_PCMPBZ
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_SADD
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_MACWU1
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_MSBLO
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_MULWU1
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_MACHL1
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_SC
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
 , M32R_INSN_SNC
/* end-sanitize-m32rx */
 , M32R_INSN_MAX
} CGEN_INSN_TYPE;

/* Index of `illegal' insn place holder.  */
#define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
/* Total number of insns in table.  */
#define MAX_INSNS ((int) M32R_INSN_MAX)

/* cgen.h uses things we just defined.  */
#include "opcode/cgen.h"

/* This struct records data prior to insertion or after extraction.  */
typedef struct cgen_fields 
{
  long f_nil;
  long f_op1;
  long f_op2;
  long f_cond;
  long f_r1;
  long f_r2;
  long f_simm8;
  long f_simm16;
  long f_shift_op2;
  long f_uimm4;
  long f_uimm5;
  long f_uimm16;
  long f_uimm24;
  long f_hi16;
  long f_disp8;
  long f_disp16;
  long f_disp24;
/* start-sanitize-m32rx */
  long f_op23;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
  long f_op3;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
  long f_acc;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
  long f_accs;
/* end-sanitize-m32rx */
  int length;
} CGEN_FIELDS;

/* Attributes.  */
extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];

extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
/* start-sanitize-m32rx */
extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
/* end-sanitize-m32rx */

#define CGEN_INIT_PARSE() \
{\
}
#define CGEN_INIT_INSERT() \
{\
}
#define CGEN_INIT_EXTRACT() \
{\
}
#define CGEN_INIT_PRINT() \
{\
}

/* -- opc.h */

#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
#define CGEN_DIS_HASH(buffer, insn) \
(X (buffer) | \
 (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
  : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
  : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))

/* -- */


#endif /* m32r_OPC_H */
Commit	Line	Data
23cf992f NC	1	/* Instruction description for m32r.
23cf992f NC	2
7c26196f DE	3	This file is machine generated with CGEN.
7c26196f DE	4
5d07b6cf	5	Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
23cf992f NC	6
	7	This file is part of the GNU Binutils and/or GDB, the GNU debugger.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2, or (at your option)
	12	any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License along
	20	with this program; if not, write to the Free Software Foundation, Inc.,
	21	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	22
	23	*/
	24
	25	#ifndef m32r_OPC_H
	26	#define m32r_OPC_H
	27
	28	#define CGEN_ARCH m32r
35e689de	29
23cf992f NC	30	/* Given symbol S, return m32r_cgen_<s>. */
	31	#define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
	32
35e689de DE	33	/* Selected cpu families. */
35e689de DE	34	#define HAVE_CPU_M32R
7c26196f DE	35	/* start-sanitize-m32rx */
	36	#define HAVE_CPU_M32RX
	37	/* end-sanitize-m32rx */
35e689de	38
23cf992f NC	39	#define CGEN_WORD_BITSIZE 32
	40	#define CGEN_DEFAULT_INSN_BITSIZE 32
	41	#define CGEN_BASE_INSN_BITSIZE 32
	42	#define CGEN_MAX_INSN_BITSIZE 32
	43	#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
	44	#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
	45	#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
	46	#define CGEN_INT_INSN
	47
23cf992f NC	48	/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
	49
	50	/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
	51	e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
	52	we can't hash on everything up to the space. */
	53	#define CGEN_MNEMONIC_OPERANDS
	54
23cf992f NC	55	/* Enums. */
	56
	57	/* Enum declaration for insn format enums. */
	58	typedef enum insn_op1 {
7c26196f DE	59	OP1_0, OP1_1, OP1_2, OP1_3
	60	, OP1_4, OP1_5, OP1_6, OP1_7
	61	, OP1_8, OP1_9, OP1_10, OP1_11
	62	, OP1_12, OP1_13, OP1_14, OP1_15
23cf992f NC	63	} INSN_OP1;
	64
	65	/* Enum declaration for op2 enums. */
	66	typedef enum insn_op2 {
7c26196f DE	67	OP2_0, OP2_1, OP2_2, OP2_3
	68	, OP2_4, OP2_5, OP2_6, OP2_7
	69	, OP2_8, OP2_9, OP2_10, OP2_11
	70	, OP2_12, OP2_13, OP2_14, OP2_15
23cf992f NC	71	} INSN_OP2;
	72
	73	/* Enum declaration for m32r operand types. */
	74	typedef enum cgen_operand_type {
7c26196f DE	75	M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
	76	, M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
	77	, M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
	78	/* start-sanitize-m32rx */
	79	, M32R_OPERAND_ACCS
	80	/* end-sanitize-m32rx */
	81	/* start-sanitize-m32rx */
	82	, M32R_OPERAND_ACC
	83	/* end-sanitize-m32rx */
	84	, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
	85	, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
	86	, M32R_OPERAND_ACCUM
	87	/* start-sanitize-m32rx */
	88	, M32R_OPERAND_ABORT_PARALLEL_EXECUTION
	89	/* end-sanitize-m32rx */
	90	, M32R_OPERAND_MAX
23cf992f NC	91	} CGEN_OPERAND_TYPE;
	92
	93	/* Non-boolean attributes. */
	94
	95	/* Enum declaration for machine type selection. */
	96	typedef enum mach_attr {
7c26196f DE	97	MACH_M32R
	98	/* start-sanitize-m32rx */
	99	, MACH_M32RX
	100	/* end-sanitize-m32rx */
	101	, MACH_MAX
23cf992f NC	102	} MACH_ATTR;
23cf992f NC	103
7c26196f DE	104	/* start-sanitize-m32rx */
	105	/* Enum declaration for parallel execution pipeline selection. */
	106	typedef enum pipe_attr {
	107	PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
	108	} PIPE_ATTR;
	109
	110	/* end-sanitize-m32rx */
	111	/* Number of architecture variants. */
	112	#define MAX_MACHS ((int) MACH_MAX)
	113
	114	/* Number of operands. */
	115	#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
	116
23cf992f NC	117	/* Operand and instruction attribute indices. */
	118
	119	/* Enum declaration for cgen_operand attrs. */
	120	typedef enum cgen_operand_attr {
7c26196f DE	121	CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC
	122	, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
	123	, CGEN_OPERAND_UNSIGNED
23cf992f NC	124	} CGEN_OPERAND_ATTR;
23cf992f NC	125
7c26196f DE	126	/* Number of non-boolean elements in cgen_operand. */
	127	#define CGEN_OPERAND_MAX_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
	128
23cf992f NC	129	/* Enum declaration for cgen_insn attrs. */
23cf992f NC	130	typedef enum cgen_insn_attr {
7c26196f DE	131	CGEN_INSN_MACH
	132	/* start-sanitize-m32rx */
	133	, CGEN_INSN_PIPE
	134	/* end-sanitize-m32rx */
	135	, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL
	136	, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
23cf992f NC	137	} CGEN_INSN_ATTR;
23cf992f NC	138
7c26196f DE	139	/* Number of non-boolean elements in cgen_insn. */
	140	#define CGEN_INSN_MAX_ATTRS ((int) CGEN_INSN_ALIAS)
	141
23cf992f NC	142	/* Insn types are used by the simulator. */
	143	/* Enum declaration for m32r instruction types. */
	144	typedef enum cgen_insn_type {
7c26196f DE	145	M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_ADD3_A
	146	, M32R_INSN_AND, M32R_INSN_AND3, M32R_INSN_AND3_A, M32R_INSN_OR
	147	, M32R_INSN_OR3, M32R_INSN_OR3_A, M32R_INSN_XOR, M32R_INSN_XOR3
	148	, M32R_INSN_XOR3_A, M32R_INSN_ADDI, M32R_INSN_ADDI_A, M32R_INSN_ADDV
	149	, M32R_INSN_ADDV3, M32R_INSN_ADDV3_A, M32R_INSN_ADDX, M32R_INSN_BC8
	150	, M32R_INSN_BC8_S, M32R_INSN_BC24, M32R_INSN_BC24_L, M32R_INSN_BEQ
	151	, M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
	152	, M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL8_S
	153	, M32R_INSN_BL24, M32R_INSN_BL24_L
	154	/* start-sanitize-m32rx */
	155	, M32R_INSN_BCL8
	156	/* end-sanitize-m32rx */
	157	/* start-sanitize-m32rx */
	158	, M32R_INSN_BCL8_S
	159	/* end-sanitize-m32rx */
	160	/* start-sanitize-m32rx */
	161	, M32R_INSN_BCL24
	162	/* end-sanitize-m32rx */
	163	/* start-sanitize-m32rx */
	164	, M32R_INSN_BCL24_L
	165	/* end-sanitize-m32rx */
	166	, M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L
	167	, M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24
	168	, M32R_INSN_BRA24_L
	169	/* start-sanitize-m32rx */
	170	, M32R_INSN_BNCL8
	171	/* end-sanitize-m32rx */
	172	/* start-sanitize-m32rx */
	173	, M32R_INSN_BNCL8_S
	174	/* end-sanitize-m32rx */
	175	/* start-sanitize-m32rx */
	176	, M32R_INSN_BNCL24
	177	/* end-sanitize-m32rx */
	178	/* start-sanitize-m32rx */
	179	, M32R_INSN_BNCL24_L
	180	/* end-sanitize-m32rx */
	181	, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPI_A, M32R_INSN_CMPU
	182	, M32R_INSN_CMPUI, M32R_INSN_CMPUI_A
	183	/* start-sanitize-m32rx */
	184	, M32R_INSN_CMPEQ
	185	/* end-sanitize-m32rx */
	186	/* start-sanitize-m32rx */
	187	, M32R_INSN_CMPZ
	188	/* end-sanitize-m32rx */
	189	, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
	190	/* start-sanitize-m32rx */
	191	, M32R_INSN_JC
	192	/* end-sanitize-m32rx */
	193	/* start-sanitize-m32rx */
	194	, M32R_INSN_JNC
	195	/* end-sanitize-m32rx */
	196	, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_2
	197	, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB, M32R_INSN_LDB_2
	198	, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH, M32R_INSN_LDH_2
	199	, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB, M32R_INSN_LDUB_2
	200	, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH, M32R_INSN_LDUH_2
	201	, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS, M32R_INSN_LD24
	202	, M32R_INSN_LD24_A, M32R_INSN_LDI8, M32R_INSN_LDI8_A, M32R_INSN_LDI8A
	203	, M32R_INSN_LDI8A_A, M32R_INSN_LDI16, M32R_INSN_LDI16A, M32R_INSN_LOCK
	204	, M32R_INSN_MACHI
	205	/* start-sanitize-m32rx */
	206	, M32R_INSN_MACHI_A
	207	/* end-sanitize-m32rx */
	208	, M32R_INSN_MACLO
209	/* start-sanitize-m32rx */
210	, M32R_INSN_MACLO_A
211	/* end-sanitize-m32rx */
212	, M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI
213	/* start-sanitize-m32rx */
214	, M32R_INSN_MULHI_A
215	/* end-sanitize-m32rx */
216	, M32R_INSN_MULLO
217	/* start-sanitize-m32rx */
218	, M32R_INSN_MULLO_A
219	/* end-sanitize-m32rx */
220	, M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV, M32R_INSN_MVFACHI
221	/* start-sanitize-m32rx */
222	, M32R_INSN_MVFACHI_A
223	/* end-sanitize-m32rx */
224	, M32R_INSN_MVFACLO
225	/* start-sanitize-m32rx */
226	, M32R_INSN_MVFACLO_A
227	/* end-sanitize-m32rx */
228	, M32R_INSN_MVFACMI
229	/* start-sanitize-m32rx */
230	, M32R_INSN_MVFACMI_A
231	/* end-sanitize-m32rx */
232	, M32R_INSN_MVFC, M32R_INSN_MVTACHI
233	/* start-sanitize-m32rx */
234	, M32R_INSN_MVTACHI_A
235	/* end-sanitize-m32rx */
236	, M32R_INSN_MVTACLO
237	/* start-sanitize-m32rx */
238	, M32R_INSN_MVTACLO_A
239	/* end-sanitize-m32rx */
240	, M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
241	, M32R_INSN_RAC
242	/* start-sanitize-m32rx */
243	, M32R_INSN_RAC_A
244	/* end-sanitize-m32rx */
245	, M32R_INSN_RACH
246	/* start-sanitize-m32rx */
247	, M32R_INSN_RACH_A
248	/* end-sanitize-m32rx */
249	, M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL
250	, M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A
251	, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRA3_A, M32R_INSN_SRAI
252	, M32R_INSN_SRAI_A, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRL3_A
253	, M32R_INSN_SRLI, M32R_INSN_SRLI_A, M32R_INSN_ST, M32R_INSN_ST_2
254	, M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2
255	, M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2
256	, M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS
257	, M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
258	, M32R_INSN_TRAP_A, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP
259	/* start-sanitize-m32rx */
260	, M32R_INSN_SATB
261	/* end-sanitize-m32rx */
262	/* start-sanitize-m32rx */
263	, M32R_INSN_SATH
264	/* end-sanitize-m32rx */
265	/* start-sanitize-m32rx */
266	, M32R_INSN_SAT
267	/* end-sanitize-m32rx */
268	/* start-sanitize-m32rx */
269	, M32R_INSN_PCMPBZ
270	/* end-sanitize-m32rx */
271	/* start-sanitize-m32rx */
272	, M32R_INSN_SADD
273	/* end-sanitize-m32rx */
274	/* start-sanitize-m32rx */
275	, M32R_INSN_MACWU1
276	/* end-sanitize-m32rx */
277	/* start-sanitize-m32rx */
278	, M32R_INSN_MSBLO
279	/* end-sanitize-m32rx */
280	/* start-sanitize-m32rx */
281	, M32R_INSN_MULWU1
282	/* end-sanitize-m32rx */
283	/* start-sanitize-m32rx */
284	, M32R_INSN_MACHL1
285	/* end-sanitize-m32rx */
286	/* start-sanitize-m32rx */
287	, M32R_INSN_SC
288	/* end-sanitize-m32rx */
289	/* start-sanitize-m32rx */
290	, M32R_INSN_SNC
291	/* end-sanitize-m32rx */
292	, M32R_INSN_MAX
23cf992f NC	293	} CGEN_INSN_TYPE;
	294
	295	/* Index of `illegal' insn place holder. */
	296	#define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
	297	/* Total number of insns in table. */
7c26196f	298	#define MAX_INSNS ((int) M32R_INSN_MAX)
23cf992f NC	299
	300	/* cgen.h uses things we just defined. */
	301	#include "opcode/cgen.h"
	302
	303	/* This struct records data prior to insertion or after extraction. */
853713a7	304	typedef struct cgen_fields
5d07b6cf DE	305	{
5d07b6cf DE	306	long f_nil;
23cf992f NC	307	long f_op1;
	308	long f_op2;
	309	long f_cond;
	310	long f_r1;
	311	long f_r2;
	312	long f_simm8;
	313	long f_simm16;
	314	long f_shift_op2;
	315	long f_uimm4;
	316	long f_uimm5;
	317	long f_uimm16;
	318	long f_uimm24;
	319	long f_hi16;
	320	long f_disp8;
	321	long f_disp16;
	322	long f_disp24;
7c26196f DE	323	/* start-sanitize-m32rx */
	324	long f_op23;
	325	/* end-sanitize-m32rx */
	326	/* start-sanitize-m32rx */
	327	long f_op3;
	328	/* end-sanitize-m32rx */
	329	/* start-sanitize-m32rx */
	330	long f_acc;
	331	/* end-sanitize-m32rx */
	332	/* start-sanitize-m32rx */
	333	long f_accs;
	334	/* end-sanitize-m32rx */
23cf992f NC	335	int length;
	336	} CGEN_FIELDS;
	337
	338	/* Attributes. */
	339	extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
	340	extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
	341
23cf992f NC	342	extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
23cf992f NC	343	extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
7c26196f DE	344	/* start-sanitize-m32rx */
	345	extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
	346	/* end-sanitize-m32rx */
23cf992f NC	347
	348	#define CGEN_INIT_PARSE() \
	349	{\
	350	}
	351	#define CGEN_INIT_INSERT() \
	352	{\
	353	}
	354	#define CGEN_INIT_EXTRACT() \
	355	{\
	356	}
	357	#define CGEN_INIT_PRINT() \
	358	{\
	359	}
	360
	361	/* -- opc.h */
	362
	363	#undef CGEN_DIS_HASH_SIZE
	364	#define CGEN_DIS_HASH_SIZE 256
	365	#undef CGEN_DIS_HASH
	366	#define X(b) (((unsigned char *) (b))[0] & 0xf0)
	367	#define CGEN_DIS_HASH(buffer, insn) \
	368	(X (buffer) \| \
	369	(X (buffer) == 0x40 \|\| X (buffer) == 0xe0 \|\| X (buffer) == 0x60 \|\| X (buffer) == 0x50 ? 0 \
	370	: X (buffer) == 0x70 \|\| X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
	371	: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
	372
	373	/* -- */
	374
	375
	376	#endif /* m32r_OPC_H */