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1999-09-15 Ulrich Drepper <drepper@cygnus.com>
[thirdparty/binutils-gdb.git] / opcodes / m32r-opinst.c
CommitLineData
252b5132
RH		 1/* Semantic operand instances for m32r.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include "ansidecl.h"
27#include "bfd.h"
28#include "symcat.h"
29#include "m32r-desc.h"
30#include "m32r-opc.h"
31
32/* Operand references. */
33
34#define INPUT CGEN_OPINST_INPUT
35#define OUTPUT CGEN_OPINST_OUTPUT
36#define END CGEN_OPINST_END
37#define COND_REF CGEN_OPINST_COND_REF
38#define OP_ENT(op) CONCAT2 (M32R_OPERAND_,op)
39
eb1b03df 40static const CGEN_OPINST sfmt_empty_ops[] = {
252b5132
RH		 41 { END }
42};
43
eb1b03df 44static const CGEN_OPINST sfmt_add_ops[] = {
252b5132
RH		 45 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
46 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
47 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
48 { END }
49};
50
eb1b03df 51static const CGEN_OPINST sfmt_add3_ops[] = {
252b5132
RH		 52 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
53 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
54 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
55 { END }
56};
57
eb1b03df 58static const CGEN_OPINST sfmt_and3_ops[] = {
252b5132
RH		 59 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
60 { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
61 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
62 { END }
63};
64
eb1b03df 65static const CGEN_OPINST sfmt_or3_ops[] = {
252b5132
RH		 66 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
67 { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
68 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
69 { END }
70};
71
eb1b03df 72static const CGEN_OPINST sfmt_addi_ops[] = {
252b5132
RH		 73 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
74 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
75 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
76 { END }
77};
78
eb1b03df 79static const CGEN_OPINST sfmt_addv_ops[] = {
252b5132
RH		 80 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
81 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
82 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
83 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
84 { END }
85};
86
eb1b03df 87static const CGEN_OPINST sfmt_addv3_ops[] = {
252b5132
RH		 88 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
89 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
90 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
91 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
92 { END }
93};
94
eb1b03df 95static const CGEN_OPINST sfmt_addx_ops[] = {
252b5132
RH		 96 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
97 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
98 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
99 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
100 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
101 { END }
102};
103
eb1b03df 104static const CGEN_OPINST sfmt_bc8_ops[] = {
252b5132
RH		 105 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
106 { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
107 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
108 { END }
109};
110
eb1b03df 111static const CGEN_OPINST sfmt_bc24_ops[] = {
252b5132
RH		 112 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
113 { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
114 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
115 { END }
116};
117
eb1b03df 118static const CGEN_OPINST sfmt_beq_ops[] = {
252b5132
RH		 119 { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
120 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
121 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
122 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
123 { END }
124};
125
eb1b03df 126static const CGEN_OPINST sfmt_beqz_ops[] = {
252b5132
RH		 127 { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
128 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
129 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
130 { END }
131};
132
eb1b03df 133static const CGEN_OPINST sfmt_bl8_ops[] = {
252b5132
RH		 134 { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
135 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
136 { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
137 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
138 { END }
139};
140
eb1b03df 141static const CGEN_OPINST sfmt_bl24_ops[] = {
252b5132
RH		 142 { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
143 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
144 { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
145 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
146 { END }
147};
148
eb1b03df 149static const CGEN_OPINST sfmt_bra8_ops[] = {
252b5132
RH		 150 { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
151 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
152 { END }
153};
154
eb1b03df 155static const CGEN_OPINST sfmt_bra24_ops[] = {
252b5132
RH		 156 { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
157 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
158 { END }
159};
160
eb1b03df 161static const CGEN_OPINST sfmt_cmp_ops[] = {
252b5132
RH		 162 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
163 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
164 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
165 { END }
166};
167
eb1b03df 168static const CGEN_OPINST sfmt_cmpi_ops[] = {
252b5132
RH		 169 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
170 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
171 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
172 { END }
173};
174
eb1b03df 175static const CGEN_OPINST sfmt_div_ops[] = {
252b5132
RH		 176 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
177 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
178 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
179 { END }
180};
181
eb1b03df 182static const CGEN_OPINST sfmt_jl_ops[] = {
252b5132
RH		 183 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
184 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
185 { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
186 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
187 { END }
188};
189
eb1b03df 190static const CGEN_OPINST sfmt_jmp_ops[] = {
252b5132
RH		 191 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
192 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
193 { END }
194};
195
eb1b03df 196static const CGEN_OPINST sfmt_ld_ops[] = {
252b5132
RH		 197 { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
198 { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
199 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
200 { END }
201};
202
eb1b03df
DE		 203static const CGEN_OPINST sfmt_ld_d_ops[] = {
204 { INPUT, "h_memory_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
252b5132
RH		 205 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
206 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
207 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
208 { END }
209};
210
eb1b03df 211static const CGEN_OPINST sfmt_ld_plus_ops[] = {
252b5132
RH		 212 { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
213 { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
214 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
215 { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
216 { END }
217};
218
eb1b03df 219static const CGEN_OPINST sfmt_ld24_ops[] = {
252b5132
RH		 220 { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
221 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
222 { END }
223};
224
eb1b03df 225static const CGEN_OPINST sfmt_ldi8_ops[] = {
252b5132
RH		 226 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
227 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
228 { END }
229};
230
eb1b03df 231static const CGEN_OPINST sfmt_ldi16_ops[] = {
252b5132
RH		 232 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
233 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
234 { END }
235};
236
eb1b03df 237static const CGEN_OPINST sfmt_lock_ops[] = {
252b5132
RH		 238 { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
239 { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
240 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
241 { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
242 { END }
243};
244
eb1b03df 245static const CGEN_OPINST sfmt_machi_ops[] = {
252b5132
RH		 246 { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
247 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
248 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
249 { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
250 { END }
251};
252
eb1b03df 253static const CGEN_OPINST sfmt_mulhi_ops[] = {
252b5132
RH		 254 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
255 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
256 { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
257 { END }
258};
259
eb1b03df 260static const CGEN_OPINST sfmt_mv_ops[] = {
252b5132
RH		 261 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
262 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
263 { END }
264};
265
eb1b03df 266static const CGEN_OPINST sfmt_mvfachi_ops[] = {
252b5132
RH		 267 { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
268 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
269 { END }
270};
271
eb1b03df 272static const CGEN_OPINST sfmt_mvfc_ops[] = {
252b5132
RH		 273 { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
274 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
275 { END }
276};
277
eb1b03df 278static const CGEN_OPINST sfmt_mvtachi_ops[] = {
252b5132
RH		 279 { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
280 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
281 { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
282 { END }
283};
284
eb1b03df 285static const CGEN_OPINST sfmt_mvtc_ops[] = {
252b5132
RH		 286 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
287 { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
288 { END }
289};
290
eb1b03df 291static const CGEN_OPINST sfmt_nop_ops[] = {
252b5132
RH		 292 { END }
293};
294
eb1b03df 295static const CGEN_OPINST sfmt_rac_ops[] = {
252b5132
RH		 296 { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
297 { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
298 { END }
299};
300
eb1b03df 301static const CGEN_OPINST sfmt_rte_ops[] = {
252b5132
RH		 302 { INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
303 { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
304 { INPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
305 { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
306 { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
307 { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
308 { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
309 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
310 { END }
311};
312
eb1b03df 313static const CGEN_OPINST sfmt_seth_ops[] = {
252b5132
RH		 314 { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
315 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
316 { END }
317};
318
eb1b03df 319static const CGEN_OPINST sfmt_sll3_ops[] = {
252b5132
RH		 320 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
321 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
322 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
323 { END }
324};
325
eb1b03df 326static const CGEN_OPINST sfmt_slli_ops[] = {
252b5132
RH		 327 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
328 { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
329 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
330 { END }
331};
332
eb1b03df 333static const CGEN_OPINST sfmt_st_ops[] = {
252b5132
RH		 334 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
335 { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
336 { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
337 { END }
338};
339
eb1b03df 340static const CGEN_OPINST sfmt_st_d_ops[] = {
252b5132
RH		 341 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
342 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
343 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
eb1b03df 344 { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
252b5132
RH		 345 { END }
346};
347
eb1b03df 348static const CGEN_OPINST sfmt_stb_ops[] = {
252b5132
RH		 349 { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
350 { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
351 { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
352 { END }
353};
354
eb1b03df 355static const CGEN_OPINST sfmt_stb_d_ops[] = {
252b5132
RH		 356 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
357 { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
358 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
eb1b03df 359 { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
252b5132
RH		 360 { END }
361};
362
eb1b03df 363static const CGEN_OPINST sfmt_sth_ops[] = {
252b5132
RH		 364 { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
365 { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
366 { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
367 { END }
368};
369
eb1b03df 370static const CGEN_OPINST sfmt_sth_d_ops[] = {
252b5132
RH		 371 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
372 { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
373 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
eb1b03df 374 { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
252b5132
RH		 375 { END }
376};
377
eb1b03df 378static const CGEN_OPINST sfmt_st_plus_ops[] = {
252b5132
RH		 379 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
380 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
381 { OUTPUT, "h_memory_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
382 { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
383 { END }
384};
385
eb1b03df 386static const CGEN_OPINST sfmt_trap_ops[] = {
252b5132
RH		 387 { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
388 { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
389 { INPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
390 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
391 { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
392 { OUTPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
393 { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
394 { OUTPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
395 { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
396 { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
397 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
398 { END }
399};
400
eb1b03df 401static const CGEN_OPINST sfmt_unlock_ops[] = {
252b5132
RH		 402 { INPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
403 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
404 { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
405 { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
406 { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
407 { END }
408};
409
410#undef INPUT
411#undef OUTPUT
412#undef END
413#undef COND_REF
414#undef OP_ENT
415
416/* Operand instance lookup table. */
417
418static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
419 0,
eb1b03df
DE		 420 & sfmt_add_ops[0],
421 & sfmt_add3_ops[0],
422 & sfmt_add_ops[0],
423 & sfmt_and3_ops[0],
424 & sfmt_add_ops[0],
425 & sfmt_or3_ops[0],
426 & sfmt_add_ops[0],
427 & sfmt_and3_ops[0],
428 & sfmt_addi_ops[0],
429 & sfmt_addv_ops[0],
430 & sfmt_addv3_ops[0],
431 & sfmt_addx_ops[0],
432 & sfmt_bc8_ops[0],
433 & sfmt_bc24_ops[0],
434 & sfmt_beq_ops[0],
435 & sfmt_beqz_ops[0],
436 & sfmt_beqz_ops[0],
437 & sfmt_beqz_ops[0],
438 & sfmt_beqz_ops[0],
439 & sfmt_beqz_ops[0],
440 & sfmt_beqz_ops[0],
441 & sfmt_bl8_ops[0],
442 & sfmt_bl24_ops[0],
443 & sfmt_bc8_ops[0],
444 & sfmt_bc24_ops[0],
445 & sfmt_beq_ops[0],
446 & sfmt_bra8_ops[0],
447 & sfmt_bra24_ops[0],
448 & sfmt_cmp_ops[0],
449 & sfmt_cmpi_ops[0],
450 & sfmt_cmp_ops[0],
451 & sfmt_cmpi_ops[0],
452 & sfmt_div_ops[0],
453 & sfmt_div_ops[0],
454 & sfmt_div_ops[0],
455 & sfmt_div_ops[0],
456 & sfmt_jl_ops[0],
457 & sfmt_jmp_ops[0],
458 & sfmt_ld_ops[0],
459 & sfmt_ld_d_ops[0],
460 & sfmt_ld_ops[0],
461 & sfmt_ld_d_ops[0],
462 & sfmt_ld_ops[0],
463 & sfmt_ld_d_ops[0],
464 & sfmt_ld_ops[0],
465 & sfmt_ld_d_ops[0],
466 & sfmt_ld_ops[0],
467 & sfmt_ld_d_ops[0],
468 & sfmt_ld_plus_ops[0],
469 & sfmt_ld24_ops[0],
470 & sfmt_ldi8_ops[0],
471 & sfmt_ldi16_ops[0],
472 & sfmt_lock_ops[0],
473 & sfmt_machi_ops[0],
474 & sfmt_machi_ops[0],
475 & sfmt_machi_ops[0],
476 & sfmt_machi_ops[0],
477 & sfmt_add_ops[0],
478 & sfmt_mulhi_ops[0],
479 & sfmt_mulhi_ops[0],
480 & sfmt_mulhi_ops[0],
481 & sfmt_mulhi_ops[0],
482 & sfmt_mv_ops[0],
483 & sfmt_mvfachi_ops[0],
484 & sfmt_mvfachi_ops[0],
485 & sfmt_mvfachi_ops[0],
486 & sfmt_mvfc_ops[0],
487 & sfmt_mvtachi_ops[0],
488 & sfmt_mvtachi_ops[0],
489 & sfmt_mvtc_ops[0],
490 & sfmt_mv_ops[0],
491 & sfmt_nop_ops[0],
492 & sfmt_mv_ops[0],
493 & sfmt_rac_ops[0],
494 & sfmt_rac_ops[0],
495 & sfmt_rte_ops[0],
496 & sfmt_seth_ops[0],
497 & sfmt_add_ops[0],
498 & sfmt_sll3_ops[0],
499 & sfmt_slli_ops[0],
500 & sfmt_add_ops[0],
501 & sfmt_sll3_ops[0],
502 & sfmt_slli_ops[0],
503 & sfmt_add_ops[0],
504 & sfmt_sll3_ops[0],
505 & sfmt_slli_ops[0],
506 & sfmt_st_ops[0],
507 & sfmt_st_d_ops[0],
508 & sfmt_stb_ops[0],
509 & sfmt_stb_d_ops[0],
510 & sfmt_sth_ops[0],
511 & sfmt_sth_d_ops[0],
512 & sfmt_st_plus_ops[0],
513 & sfmt_st_plus_ops[0],
514 & sfmt_add_ops[0],
515 & sfmt_addv_ops[0],
516 & sfmt_addx_ops[0],
517 & sfmt_trap_ops[0],
518 & sfmt_unlock_ops[0],
252b5132
RH		 519};
520
521/* Function to call before using the operand instance table. */
522
523void
524m32r_cgen_init_opinst_table (cd)
525 CGEN_CPU_DESC cd;
526{
527 int i;
528 const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
529 CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
530 for (i = 0; i < MAX_INSNS; ++i)
531 insns[i].opinst = oi[i];
532}
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