[thirdparty/binutils-gdb.git] / opcodes / mcore-dis.c

/* Disassemble Motorola M*Core instructions.
   Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "sysdep.h"
#include <stdio.h>
#define STATIC_TABLE
#define DEFINE_TABLE

#include "mcore-opc.h"
#include "dis-asm.h"

/* Mask for each mcore_opclass: */
static const unsigned short imsk[] =
{
    /* O0  */ 0xFFFF,
    /* OT  */ 0xFFFC,
    /* O1  */ 0xFFF0,
    /* OC  */ 0xFFE0,
    /* O2  */ 0xFF00,
    /* X1  */ 0xFFF0,
    /* OI  */ 0xFE00,
    /* OB  */ 0xFE00,
	      
    /* OMa */ 0xFFF0,
    /* SI  */ 0xFE00,
    /* I7  */ 0xF800,
    /* LS  */ 0xF000,
    /* BR  */ 0xF800,
    /* BL  */ 0xFF00,
    /* LR  */ 0xF000,
    /* LJ  */ 0xFF00,
	      
    /* RM  */ 0xFFF0,
    /* RQ  */ 0xFFF0,
    /* JSR */ 0xFFF0,
    /* JMP */ 0xFFF0,
    /* OBRa*/ 0xFFF0,
    /* OBRb*/ 0xFF80,
    /* OBRc*/ 0xFF00,
    /* OBR2*/ 0xFE00,
	      
    /* O1R1*/ 0xFFF0,
    /* OMb */ 0xFF80,
    /* OMc */ 0xFF00,
    /* SIa */ 0xFE00,

  /* MULSH */ 0xFF00,    
  /* OPSR  */ 0xFFF8,   /* psrset/psrclr */
		 
    /* JC  */ 0,		/* JC,JU,JL don't appear in object */
    /* JU  */ 0,
    /* JL  */ 0,
    /* RSI */ 0,
    /* DO21*/ 0,
    /* OB2 */ 0 		/* OB2 won't appear in object. */
};

static const char * grname[] =
{
 "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
 "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15"
};

static const char X[] = "??";

static const char * crname[] =
{
  "psr",  "vbr", "epsr", "fpsr", "epc",  "fpc",  "ss0",  "ss1",
  "ss2",  "ss3", "ss4",  "gcr",  "gsr",     X,      X,      X,
     X,      X,      X,      X,      X,     X,      X,      X,
     X,      X,      X,      X,      X,     X,      X,      X
};

static const unsigned isiz[] = { 2, 0, 1, 0 };

int 
print_insn_mcore (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info * info;
{
  unsigned char       ibytes[4];
  fprintf_ftype       fprintf = info->fprintf_func;
  void *              stream = info->stream;
  unsigned short      inst;
  mcore_opcode_info * op;
  int                 status;

  info->bytes_per_chunk = 2;

  status = info->read_memory_func (memaddr, ibytes, 2, info);

  if (status != 0) 
    {
      info->memory_error_func (status, memaddr, info);
      return -1;
    }

  if (info->endian == BFD_ENDIAN_BIG)
    inst = (ibytes[0] << 8) | ibytes[1];
  else if (info->endian == BFD_ENDIAN_LITTLE)
    inst = (ibytes[1] << 8) | ibytes[0];
  else
    abort ();

  /* Just a linear search of the table.  */
  for (op = mcore_table; op->name != 0; op ++)
    if (op->inst == (inst & imsk[op->opclass]))
      break;

  if (op->name == 0)
    fprintf (stream, ".short 0x%04x", inst);
  else
    {
      const char * name = grname[inst & 0x0F];
      
      fprintf (stream, "%s", op->name);
      
      switch (op->opclass)
	{
	case O0: break;
	case OT: fprintf (stream, "\t%d", inst & 0x3); break;
	case O1:
	case JMP:
	case JSR: fprintf (stream, "\t%s", name); break;
	case OC:  fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
	case O1R1: fprintf (stream, "\t%s, r1", name); break;
	case MULSH:
	case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
	case X1: fprintf (stream, "\tr1, %s", name); break;
	case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
	case RM: fprintf (stream, "\t%s-r15, (r0)", name); break;
	case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break;
	case OB:
	case OBRa:
	case OBRb:
	case OBRc:
	case SI:
	case SIa:
	case OMa:
	case OMb:
	case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break;
	case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break;
	case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
			  name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
	  break;
	  
	case BR:
	  {
	    long val = inst & 0x3FF;
	    
	    if (inst & 0x400)
	      val |= 0xFFFFFC00;
	    
	    fprintf (stream, "\t0x%x", memaddr + 2 + (val<<1));
	    
	    if (strcmp (op->name, "bsr") == 0)
	      {
		/* for bsr, we'll try to get a symbol for the target */
		val = memaddr + 2 + (val << 1);
		
		if (info->print_address_func && val != 0)
		  {
		    fprintf (stream, "\t// ");
		    info->print_address_func (val, info);
		  }
	      }
	  }
	  break;
	  
	case BL:
	  {
	    long val;
	    val = (inst & 0x000F);
	    fprintf (stream, "\t%s, 0x%x",
		    grname[(inst >> 4) & 0xF], memaddr - (val << 1));
	  }
	  break;
	  
	case LR:
	  {
	    unsigned long val;
	    
	    val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
	    
	    status = info->read_memory_func (val, ibytes, 4, info);
	    if (status != 0) 
	      {
		info->memory_error_func (status, memaddr, info);
		break;
	      }
	    
	    if (info->endian == BFD_ENDIAN_LITTLE)
	      val = (ibytes[3] << 24) | (ibytes[2] << 16)
		| (ibytes[1] << 8) | (ibytes[0]);
	    else
	      val = (ibytes[0] << 24) | (ibytes[1] << 16)
		| (ibytes[2] << 8) | (ibytes[3]);
	    
	    /* Removed [] around literal value to match ABI syntax 12/95.  */
	    fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val);

	    if (val == 0)
	      fprintf (stream, "\t// from address pool at 0x%x",
		       (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	  }
	  break;
	  
	case LJ:
	  {
	    unsigned long val;
	    
	    val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
	    
	    status = info->read_memory_func (val, ibytes, 4, info);
	    if (status != 0) 
	      {
		info->memory_error_func (status, memaddr, info);
		break;
	      }

	    if (info->endian == BFD_ENDIAN_LITTLE)
	      val = (ibytes[3] << 24) | (ibytes[2] << 16)
		| (ibytes[1] << 8) | (ibytes[0]);
	    else
	      val = (ibytes[0] << 24) | (ibytes[1] << 16)
		| (ibytes[2] << 8) | (ibytes[3]);
	    
	    /* Removed [] around literal value to match ABI syntax 12/95.  */
	    fprintf (stream, "\t0x%X", val);
	    /* For jmpi/jsri, we'll try to get a symbol for the target.  */
	    if (info->print_address_func && val != 0)
	      {
		fprintf (stream, "\t// ");
		info->print_address_func (val, info);
	      }
	    else
	      {
		fprintf (stream, "\t// from address pool at 0x%x",
			 (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	      }
	  }
	  break;
	  
	case OPSR:
	  {
	    static char * fields[] = 
	    {
	      "af", "ie",    "fe",    "fe,ie", 
	      "ee", "ee,ie", "ee,fe", "ee,fe,ie"
	    };
	    
	    fprintf (stream, "\t%s", fields[inst & 0x7]);
	  }
	  break;
	  
	default:
	  /* if the disassembler lags the instruction set */
	  fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
	  break;
	}
    }
  
  /* Say how many bytes we consumed? */
  return 2;
}
Commit	Line	Data
3442f309	1	/* Disassemble Motorola M*Core instructions.
97ee9b94	2	Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
3f230321 NC	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
d7f1f2b0	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
3f230321	17
0d8dfecf	18	#include "sysdep.h"
3f230321 NC	19	#include <stdio.h>
	20	#define STATIC_TABLE
	21	#define DEFINE_TABLE
	22
	23	#include "mcore-opc.h"
	24	#include "dis-asm.h"
	25
9cac79d3 NC	26	/* Mask for each mcore_opclass: */
	27	static const unsigned short imsk[] =
	28	{
	29	/* O0 */ 0xFFFF,
	30	/* OT */ 0xFFFC,
	31	/* O1 */ 0xFFF0,
	32	/* OC */ 0xFFE0,
	33	/* O2 */ 0xFF00,
	34	/* X1 */ 0xFFF0,
	35	/* OI */ 0xFE00,
	36	/* OB */ 0xFE00,
	37
	38	/* OMa */ 0xFFF0,
	39	/* SI */ 0xFE00,
	40	/* I7 */ 0xF800,
	41	/* LS */ 0xF000,
	42	/* BR */ 0xF800,
	43	/* BL */ 0xFF00,
	44	/* LR */ 0xF000,
	45	/* LJ */ 0xFF00,
	46
	47	/* RM */ 0xFFF0,
	48	/* RQ */ 0xFFF0,
	49	/* JSR */ 0xFFF0,
	50	/* JMP */ 0xFFF0,
	51	/* OBRa*/ 0xFFF0,
	52	/* OBRb*/ 0xFF80,
	53	/* OBRc*/ 0xFF00,
	54	/* OBR2*/ 0xFE00,
	55
	56	/* O1R1*/ 0xFFF0,
	57	/* OMb */ 0xFF80,
	58	/* OMc */ 0xFF00,
	59	/* SIa */ 0xFE00,
	60
97ee9b94 NC	61	/* MULSH */ 0xFF00,
	62	/* OPSR / 0xFFF8, / psrset/psrclr */
	63
3f230321 NC	64	/* JC / 0, / JC,JU,JL don't appear in object */
	65	/* JU */ 0,
	66	/* JL */ 0,
	67	/* RSI */ 0,
	68	/* DO21*/ 0,
	69	/* OB2 / 0 / OB2 won't appear in object. */
	70	};
	71
	72	static const char * grname[] =
	73	{
	74	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
	75	"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
	76	};
	77
	78	static const char X[] = "??";
	79
	80	static const char * crname[] =
	81	{
	82	"psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1",
	83	"ss2", "ss3", "ss4", "gcr", "gsr", X, X, X,
	84	X, X, X, X, X, X, X, X,
	85	X, X, X, X, X, X, X, X
	86	};
	87
	88	static const unsigned isiz[] = { 2, 0, 1, 0 };
	89
	90	int
	91	print_insn_mcore (memaddr, info)
	92	bfd_vma memaddr;
	93	struct disassemble_info * info;
	94	{
	95	unsigned char ibytes[4];
	96	fprintf_ftype fprintf = info->fprintf_func;
	97	void * stream = info->stream;
	98	unsigned short inst;
	99	mcore_opcode_info * op;
	100	int status;
	101
	102	info->bytes_per_chunk = 2;
	103
	104	status = info->read_memory_func (memaddr, ibytes, 2, info);
	105
	106	if (status != 0)
	107	{
	108	info->memory_error_func (status, memaddr, info);
	109	return -1;
	110	}
	111
97ee9b94	112	if (info->endian == BFD_ENDIAN_BIG)
3f230321	113	inst = (ibytes[0] << 8) \| ibytes[1];
97ee9b94 NC	114	else if (info->endian == BFD_ENDIAN_LITTLE)
	115	inst = (ibytes[1] << 8) \| ibytes[0];
	116	else
	117	abort ();
3f230321 NC	118
	119	/* Just a linear search of the table. */
	120	for (op = mcore_table; op->name != 0; op ++)
	121	if (op->inst == (inst & imsk[op->opclass]))
	122	break;
	123
	124	if (op->name == 0)
88685153	125	fprintf (stream, ".short 0x%04x", inst);
3f230321 NC	126	else
	127	{
	128	const char * name = grname[inst & 0x0F];
	129
	130	fprintf (stream, "%s", op->name);
	131
	132	switch (op->opclass)
	133	{
	134	case O0: break;
	135	case OT: fprintf (stream, "\t%d", inst & 0x3); break;
	136	case O1:
	137	case JMP:
	138	case JSR: fprintf (stream, "\t%s", name); break;
	139	case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
	140	case O1R1: fprintf (stream, "\t%s, r1", name); break;
97ee9b94	141	case MULSH:
3f230321 NC	142	case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
	143	case X1: fprintf (stream, "\tr1, %s", name); break;
	144	case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
	145	case RM: fprintf (stream, "\t%s-r15, (r0)", name); break;
	146	case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break;
	147	case OB:
	148	case OBRa:
	149	case OBRb:
	150	case OBRc:
	151	case SI:
	152	case SIa:
	153	case OMa:
	154	case OMb:
	155	case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break;
	156	case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break;
	157	case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
	158	name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
	159	break;
	160
	161	case BR:
	162	{
	163	long val = inst & 0x3FF;
	164
	165	if (inst & 0x400)
	166	val \|= 0xFFFFFC00;
	167
	168	fprintf (stream, "\t0x%x", memaddr + 2 + (val<<1));
	169
	170	if (strcmp (op->name, "bsr") == 0)
	171	{
	172	/* for bsr, we'll try to get a symbol for the target */
	173	val = memaddr + 2 + (val << 1);
	174
	175	if (info->print_address_func && val != 0)
	176	{
	177	fprintf (stream, "\t// ");
	178	info->print_address_func (val, info);
	179	}
	180	}
	181	}
	182	break;
	183
	184	case BL:
	185	{
	186	long val;
	187	val = (inst & 0x000F);
	188	fprintf (stream, "\t%s, 0x%x",
	189	grname[(inst >> 4) & 0xF], memaddr - (val << 1));
	190	}
	191	break;
	192
	193	case LR:
	194	{
	195	unsigned long val;
	196
	197	val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
	198
	199	status = info->read_memory_func (val, ibytes, 4, info);
	200	if (status != 0)
	201	{
	202	info->memory_error_func (status, memaddr, info);
	203	break;
	204	}
	205
97ee9b94 NC	206	if (info->endian == BFD_ENDIAN_LITTLE)
	207	val = (ibytes[3] << 24) \| (ibytes[2] << 16)
	208	\| (ibytes[1] << 8) \| (ibytes[0]);
	209	else
3f230321 NC	210	val = (ibytes[0] << 24) \| (ibytes[1] << 16)
	211	\| (ibytes[2] << 8) \| (ibytes[3]);
	212
	213	/* Removed [] around literal value to match ABI syntax 12/95. */
	214	fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val);
	215
	216	if (val == 0)
	217	fprintf (stream, "\t// from address pool at 0x%x",
	218	(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	219	}
	220	break;
	221
	222	case LJ:
	223	{
	224	unsigned long val;
	225
	226	val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
	227
	228	status = info->read_memory_func (val, ibytes, 4, info);
	229	if (status != 0)
	230	{
	231	info->memory_error_func (status, memaddr, info);
	232	break;
	233	}
	234
97ee9b94 NC	235	if (info->endian == BFD_ENDIAN_LITTLE)
	236	val = (ibytes[3] << 24) \| (ibytes[2] << 16)
	237	\| (ibytes[1] << 8) \| (ibytes[0]);
	238	else
3f230321 NC	239	val = (ibytes[0] << 24) \| (ibytes[1] << 16)
	240	\| (ibytes[2] << 8) \| (ibytes[3]);
	241
	242	/* Removed [] around literal value to match ABI syntax 12/95. */
	243	fprintf (stream, "\t0x%X", val);
	244	/* For jmpi/jsri, we'll try to get a symbol for the target. */
	245	if (info->print_address_func && val != 0)
	246	{
	247	fprintf (stream, "\t// ");
	248	info->print_address_func (val, info);
	249	}
	250	else
	251	{
	252	fprintf (stream, "\t// from address pool at 0x%x",
	253	(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	254	}
	255	}
	256	break;
	257
97ee9b94 NC	258	case OPSR:
	259	{
	260	static char * fields[] =
	261	{
	262	"af", "ie", "fe", "fe,ie",
	263	"ee", "ee,ie", "ee,fe", "ee,fe,ie"
	264	};
	265
	266	fprintf (stream, "\t%s", fields[inst & 0x7]);
	267	}
	268	break;
	269
3f230321 NC	270	default:
	271	/* if the disassembler lags the instruction set */
	272	fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
	273	break;
	274	}
	275	}
	276
	277	/* Say how many bytes we consumed? */
	278	return 2;
	279	}