[thirdparty/binutils-gdb.git] / opcodes / mcore-dis.c

/* Disassemble Motorolla M*Core instructions.
   Copyright (C) 1993, 1999 Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <stdio.h>
#define STATIC_TABLE
#define DEFINE_TABLE

#include "mcore-opc.h"
#include "dis-asm.h"

/* Mask for each mcore_opclass: */
static const unsigned short imsk[] =
{
    /* O0  */ 0xFFFF,
    /* OT  */ 0xFFFC,
    /* O1  */ 0xFFF0,
    /* OC  */ 0xFFE0,
    /* O2  */ 0xFF00,
    /* X1  */ 0xFFF0,
    /* OI  */ 0xFE00,
    /* OB  */ 0xFE00,
	      
    /* OMa */ 0xFFF0,
    /* SI  */ 0xFE00,
    /* I7  */ 0xF800,
    /* LS  */ 0xF000,
    /* BR  */ 0xF800,
    /* BL  */ 0xFF00,
    /* LR  */ 0xF000,
    /* LJ  */ 0xFF00,
	      
    /* RM  */ 0xFFF0,
    /* RQ  */ 0xFFF0,
    /* JSR */ 0xFFF0,
    /* JMP */ 0xFFF0,
    /* OBRa*/ 0xFFF0,
    /* OBRb*/ 0xFF80,
    /* OBRc*/ 0xFF00,
    /* OBR2*/ 0xFE00,
	      
    /* O1R1*/ 0xFFF0,
    /* OMb */ 0xFF80,
    /* OMc */ 0xFF00,
    /* SIa */ 0xFE00,

    /* JC  */ 0,		/* JC,JU,JL don't appear in object */
    /* JU  */ 0,
    /* JL  */ 0,
    /* RSI */ 0,
    /* DO21*/ 0,
    /* OB2 */ 0 		/* OB2 won't appear in object. */
};

static const char * grname[] =
{
 "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
 "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15"
};

static const char X[] = "??";

static const char * crname[] =
{
  "psr",  "vbr", "epsr", "fpsr", "epc",  "fpc",  "ss0",  "ss1",
  "ss2",  "ss3", "ss4",  "gcr",  "gsr",     X,      X,      X,
     X,      X,      X,      X,      X,     X,      X,      X,
     X,      X,      X,      X,      X,     X,      X,      X
};

static const unsigned isiz[] = { 2, 0, 1, 0 };

int 
print_insn_mcore (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info * info;
{
  unsigned char       ibytes[4];
  fprintf_ftype       fprintf = info->fprintf_func;
  void *              stream = info->stream;
  unsigned short      inst;
  mcore_opcode_info * op;
  int                 status;

  info->bytes_per_chunk = 2;

  status = info->read_memory_func (memaddr, ibytes, 2, info);

  if (status != 0) 
    {
      info->memory_error_func (status, memaddr, info);
      return -1;
    }

    inst = (ibytes[0] << 8) | ibytes[1];

  /* Just a linear search of the table.  */
  for (op = mcore_table; op->name != 0; op ++)
    if (op->inst == (inst & imsk[op->opclass]))
      break;

  if (op->name == 0)
    fprintf (stream, ".short 0x%04x", inst);
  else
    {
      const char * name = grname[inst & 0x0F];
      
      fprintf (stream, "%s", op->name);
      
      switch (op->opclass)
	{
	case O0: break;
	case OT: fprintf (stream, "\t%d", inst & 0x3); break;
	case O1:
	case JMP:
	case JSR: fprintf (stream, "\t%s", name); break;
	case OC:  fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
	case O1R1: fprintf (stream, "\t%s, r1", name); break;
	case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
	case X1: fprintf (stream, "\tr1, %s", name); break;
	case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
	case RM: fprintf (stream, "\t%s-r15, (r0)", name); break;
	case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break;
	case OB:
	case OBRa:
	case OBRb:
	case OBRc:
	case SI:
	case SIa:
	case OMa:
	case OMb:
	case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break;
	case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break;
	case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
			  name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
	  break;
	  
	case BR:
	  {
	    long val = inst & 0x3FF;
	    
	    if (inst & 0x400)
	      val |= 0xFFFFFC00;
	    
	    fprintf (stream, "\t0x%x", memaddr + 2 + (val<<1));
	    
	    if (strcmp (op->name, "bsr") == 0)
	      {
		/* for bsr, we'll try to get a symbol for the target */
		val = memaddr + 2 + (val << 1);
		
		if (info->print_address_func && val != 0)
		  {
		    fprintf (stream, "\t// ");
		    info->print_address_func (val, info);
		  }
	      }
	  }
	  break;
	  
	case BL:
	  {
	    long val;
	    val = (inst & 0x000F);
	    fprintf (stream, "\t%s, 0x%x",
		    grname[(inst >> 4) & 0xF], memaddr - (val << 1));
	  }
	  break;
	  
	case LR:
	  {
	    unsigned long val;
	    
	    val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
	    
	    status = info->read_memory_func (val, ibytes, 4, info);
	    if (status != 0) 
	      {
		info->memory_error_func (status, memaddr, info);
		break;
	      }
	    
	      val = (ibytes[0] << 24) | (ibytes[1] << 16)
		| (ibytes[2] << 8) | (ibytes[3]);
	    
	    /* Removed [] around literal value to match ABI syntax 12/95.  */
	    fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val);

	    if (val == 0)
	      fprintf (stream, "\t// from address pool at 0x%x",
		       (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	  }
	  break;
	  
	case LJ:
	  {
	    unsigned long val;
	    
	    val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
	    
	    status = info->read_memory_func (val, ibytes, 4, info);
	    if (status != 0) 
	      {
		info->memory_error_func (status, memaddr, info);
		break;
	      }

	      val = (ibytes[0] << 24) | (ibytes[1] << 16)
		| (ibytes[2] << 8) | (ibytes[3]);
	    
	    /* Removed [] around literal value to match ABI syntax 12/95.  */
	    fprintf (stream, "\t0x%X", val);
	    /* For jmpi/jsri, we'll try to get a symbol for the target.  */
	    if (info->print_address_func && val != 0)
	      {
		fprintf (stream, "\t// ");
		info->print_address_func (val, info);
	      }
	    else
	      {
		fprintf (stream, "\t// from address pool at 0x%x",
			 (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	      }
	  }
	  break;
	  
	default:
	  /* if the disassembler lags the instruction set */
	  fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
	  break;
	}
    }
  
  /* Say how many bytes we consumed? */
  return 2;
}
Commit	Line	Data
3f230321 NC	1	/* Disassemble Motorolla M*Core instructions.
	2	Copyright (C) 1993, 1999 Free Software Foundation, Inc.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
d7f1f2b0	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
3f230321 NC	17
	18	#include <stdio.h>
	19	#define STATIC_TABLE
	20	#define DEFINE_TABLE
	21
	22	#include "mcore-opc.h"
	23	#include "dis-asm.h"
	24
9cac79d3 NC	25	/* Mask for each mcore_opclass: */
	26	static const unsigned short imsk[] =
	27	{
	28	/* O0 */ 0xFFFF,
	29	/* OT */ 0xFFFC,
	30	/* O1 */ 0xFFF0,
	31	/* OC */ 0xFFE0,
	32	/* O2 */ 0xFF00,
	33	/* X1 */ 0xFFF0,
	34	/* OI */ 0xFE00,
	35	/* OB */ 0xFE00,
	36
	37	/* OMa */ 0xFFF0,
	38	/* SI */ 0xFE00,
	39	/* I7 */ 0xF800,
	40	/* LS */ 0xF000,
	41	/* BR */ 0xF800,
	42	/* BL */ 0xFF00,
	43	/* LR */ 0xF000,
	44	/* LJ */ 0xFF00,
	45
	46	/* RM */ 0xFFF0,
	47	/* RQ */ 0xFFF0,
	48	/* JSR */ 0xFFF0,
	49	/* JMP */ 0xFFF0,
	50	/* OBRa*/ 0xFFF0,
	51	/* OBRb*/ 0xFF80,
	52	/* OBRc*/ 0xFF00,
	53	/* OBR2*/ 0xFE00,
	54
	55	/* O1R1*/ 0xFFF0,
	56	/* OMb */ 0xFF80,
	57	/* OMc */ 0xFF00,
	58	/* SIa */ 0xFE00,
	59
3f230321 NC	60	/* JC / 0, / JC,JU,JL don't appear in object */
	61	/* JU */ 0,
	62	/* JL */ 0,
	63	/* RSI */ 0,
	64	/* DO21*/ 0,
	65	/* OB2 / 0 / OB2 won't appear in object. */
	66	};
	67
	68	static const char * grname[] =
	69	{
	70	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
	71	"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
	72	};
	73
	74	static const char X[] = "??";
	75
	76	static const char * crname[] =
	77	{
	78	"psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1",
	79	"ss2", "ss3", "ss4", "gcr", "gsr", X, X, X,
	80	X, X, X, X, X, X, X, X,
	81	X, X, X, X, X, X, X, X
	82	};
	83
	84	static const unsigned isiz[] = { 2, 0, 1, 0 };
	85
	86	int
	87	print_insn_mcore (memaddr, info)
	88	bfd_vma memaddr;
	89	struct disassemble_info * info;
	90	{
	91	unsigned char ibytes[4];
	92	fprintf_ftype fprintf = info->fprintf_func;
	93	void * stream = info->stream;
	94	unsigned short inst;
	95	mcore_opcode_info * op;
	96	int status;
	97
	98	info->bytes_per_chunk = 2;
	99
	100	status = info->read_memory_func (memaddr, ibytes, 2, info);
	101
	102	if (status != 0)
	103	{
	104	info->memory_error_func (status, memaddr, info);
	105	return -1;
	106	}
	107
3f230321	108	inst = (ibytes[0] << 8) \| ibytes[1];
3f230321 NC	109
	110	/* Just a linear search of the table. */
	111	for (op = mcore_table; op->name != 0; op ++)
	112	if (op->inst == (inst & imsk[op->opclass]))
	113	break;
	114
	115	if (op->name == 0)
88685153	116	fprintf (stream, ".short 0x%04x", inst);
3f230321 NC	117	else
	118	{
	119	const char * name = grname[inst & 0x0F];
	120
	121	fprintf (stream, "%s", op->name);
	122
	123	switch (op->opclass)
	124	{
	125	case O0: break;
	126	case OT: fprintf (stream, "\t%d", inst & 0x3); break;
	127	case O1:
	128	case JMP:
	129	case JSR: fprintf (stream, "\t%s", name); break;
	130	case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
	131	case O1R1: fprintf (stream, "\t%s, r1", name); break;
3f230321 NC	132	case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
	133	case X1: fprintf (stream, "\tr1, %s", name); break;
	134	case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
	135	case RM: fprintf (stream, "\t%s-r15, (r0)", name); break;
	136	case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break;
	137	case OB:
	138	case OBRa:
	139	case OBRb:
	140	case OBRc:
	141	case SI:
	142	case SIa:
	143	case OMa:
	144	case OMb:
	145	case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break;
	146	case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break;
	147	case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
	148	name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
	149	break;
	150
	151	case BR:
	152	{
	153	long val = inst & 0x3FF;
	154
	155	if (inst & 0x400)
	156	val \|= 0xFFFFFC00;
	157
	158	fprintf (stream, "\t0x%x", memaddr + 2 + (val<<1));
	159
	160	if (strcmp (op->name, "bsr") == 0)
	161	{
	162	/* for bsr, we'll try to get a symbol for the target */
	163	val = memaddr + 2 + (val << 1);
	164
	165	if (info->print_address_func && val != 0)
	166	{
	167	fprintf (stream, "\t// ");
	168	info->print_address_func (val, info);
	169	}
	170	}
	171	}
	172	break;
	173
	174	case BL:
	175	{
	176	long val;
	177	val = (inst & 0x000F);
	178	fprintf (stream, "\t%s, 0x%x",
	179	grname[(inst >> 4) & 0xF], memaddr - (val << 1));
	180	}
	181	break;
	182
	183	case LR:
	184	{
	185	unsigned long val;
	186
	187	val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
	188
	189	status = info->read_memory_func (val, ibytes, 4, info);
	190	if (status != 0)
	191	{
	192	info->memory_error_func (status, memaddr, info);
	193	break;
	194	}
	195
3f230321 NC	196	val = (ibytes[0] << 24) \| (ibytes[1] << 16)
	197	\| (ibytes[2] << 8) \| (ibytes[3]);
	198
	199	/* Removed [] around literal value to match ABI syntax 12/95. */
	200	fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val);
	201
	202	if (val == 0)
	203	fprintf (stream, "\t// from address pool at 0x%x",
	204	(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	205	}
	206	break;
	207
	208	case LJ:
	209	{
	210	unsigned long val;
	211
	212	val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
	213
	214	status = info->read_memory_func (val, ibytes, 4, info);
	215	if (status != 0)
	216	{
	217	info->memory_error_func (status, memaddr, info);
	218	break;
	219	}
	220
3f230321 NC	221	val = (ibytes[0] << 24) \| (ibytes[1] << 16)
	222	\| (ibytes[2] << 8) \| (ibytes[3]);
	223
	224	/* Removed [] around literal value to match ABI syntax 12/95. */
	225	fprintf (stream, "\t0x%X", val);
	226	/* For jmpi/jsri, we'll try to get a symbol for the target. */
	227	if (info->print_address_func && val != 0)
	228	{
	229	fprintf (stream, "\t// ");
	230	info->print_address_func (val, info);
	231	}
	232	else
	233	{
	234	fprintf (stream, "\t// from address pool at 0x%x",
	235	(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	236	}
	237	}
	238	break;
	239
	240	default:
	241	/* if the disassembler lags the instruction set */
	242	fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
	243	break;
	244	}
	245	}
	246
	247	/* Say how many bytes we consumed? */
	248	return 2;
	249	}