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252b5132 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
47b0e7ad 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
47b0e7ad
NC		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
252b5132
RH		 22#include "sysdep.h"
23#include "dis-asm.h"
640c0ccd 24#include "libiberty.h"
252b5132
RH		 25#include "opcode/mips.h"
26#include "opintl.h"
27
28/* FIXME: These are needed to figure out if the code is mips16 or
29 not. The low bit of the address is often a good indicator. No
30 symbol table is available when this code runs out in an embedded
7f6621cd 31 system as when it is used for disassembler support in a monitor. */
252b5132
RH		 32
33#if !defined(EMBEDDED_ENV)
34#define SYMTAB_AVAILABLE 1
35#include "elf-bfd.h"
36#include "elf/mips.h"
37#endif
38
aa5f19f2
NC		 39/* Mips instructions are at maximum this many bytes long. */
40#define INSNLEN 4
41
252b5132 42\f
aa5f19f2 43/* FIXME: These should be shared with gdb somehow. */
252b5132 44
47b0e7ad
NC		 45struct mips_cp0sel_name
46{
47 unsigned int cp0reg;
48 unsigned int sel;
49 const char * const name;
bbcc0807
CD		 50};
51
47b0e7ad
NC		 52static const char * const mips_gpr_names_numeric[32] =
53{
640c0ccd
CD		 54 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
55 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
56 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
57 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
aa5f19f2
NC		 58};
59
47b0e7ad
NC		 60static const char * const mips_gpr_names_oldabi[32] =
61{
640c0ccd
CD		 62 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
63 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
64 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
65 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
aa5f19f2
NC		 66};
67
47b0e7ad
NC		 68static const char * const mips_gpr_names_newabi[32] =
69{
640c0ccd 70 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
0b14f26e 71 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
640c0ccd
CD		 72 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
73 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
74};
75
47b0e7ad
NC		 76static const char * const mips_fpr_names_numeric[32] =
77{
640c0ccd
CD		 78 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
79 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
80 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
81 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
82};
83
47b0e7ad
NC		 84static const char * const mips_fpr_names_32[32] =
85{
640c0ccd
CD		 86 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
87 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
88 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
89 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
90};
91
47b0e7ad
NC		 92static const char * const mips_fpr_names_n32[32] =
93{
640c0ccd
CD		 94 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
95 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
96 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
97 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
98};
99
47b0e7ad
NC		 100static const char * const mips_fpr_names_64[32] =
101{
640c0ccd
CD		 102 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
103 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
104 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
105 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
106};
107
47b0e7ad
NC		 108static const char * const mips_cp0_names_numeric[32] =
109{
640c0ccd
CD		 110 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
111 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
112 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
113 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
114};
115
dc76d757
AB		 116static const char * const mips_cp1_names_numeric[32] =
117{
118 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
119 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
120 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
121 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
122};
123
f409fd1e
MR		 124static const char * const mips_cp0_names_r3000[32] =
125{
126 "c0_index", "c0_random", "c0_entrylo", "$3",
127 "c0_context", "$5", "$6", "$7",
128 "c0_badvaddr", "$9", "c0_entryhi", "$11",
129 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
130 "$16", "$17", "$18", "$19",
131 "$20", "$21", "$22", "$23",
132 "$24", "$25", "$26", "$27",
133 "$28", "$29", "$30", "$31",
134};
135
136static const char * const mips_cp0_names_r4000[32] =
137{
138 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
139 "c0_context", "c0_pagemask", "c0_wired", "$7",
140 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
141 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
142 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
143 "c0_xcontext", "$21", "$22", "$23",
144 "$24", "$25", "c0_ecc", "c0_cacheerr",
145 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
146};
147
e407c74b
NC		 148static const char * const mips_cp0_names_r5900[32] =
149{
150 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
151 "c0_context", "c0_pagemask", "c0_wired", "$7",
152 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
153 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
154 "c0_config", "$17", "$18", "$19",
155 "$20", "$21", "$22", "c0_badpaddr",
156 "c0_depc", "c0_perfcnt", "$26", "$27",
157 "c0_taglo", "c0_taghi", "c0_errorepc", "$31"
158};
159
47b0e7ad
NC		 160static const char * const mips_cp0_names_mips3264[32] =
161{
640c0ccd
CD		 162 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
163 "c0_context", "c0_pagemask", "c0_wired", "$7",
164 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
165 "c0_status", "c0_cause", "c0_epc", "c0_prid",
166 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
167 "c0_xcontext", "$21", "$22", "c0_debug",
168 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
169 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
170};
171
dc76d757
AB		 172static const char * const mips_cp1_names_mips3264[32] =
173{
174 "c1_fir", "c1_ufr", "$2", "$3",
175 "c1_unfr", "$5", "$6", "$7",
176 "$8", "$9", "$10", "$11",
177 "$12", "$13", "$14", "$15",
178 "$16", "$17", "$18", "$19",
179 "$20", "$21", "$22", "$23",
180 "$24", "c1_fccr", "c1_fexr", "$27",
181 "c1_fenr", "$29", "$30", "c1_fcsr"
182};
183
47b0e7ad
NC		 184static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
185{
bbcc0807
CD		 186 { 16, 1, "c0_config1" },
187 { 16, 2, "c0_config2" },
188 { 16, 3, "c0_config3" },
189 { 18, 1, "c0_watchlo,1" },
190 { 18, 2, "c0_watchlo,2" },
191 { 18, 3, "c0_watchlo,3" },
192 { 18, 4, "c0_watchlo,4" },
193 { 18, 5, "c0_watchlo,5" },
194 { 18, 6, "c0_watchlo,6" },
195 { 18, 7, "c0_watchlo,7" },
196 { 19, 1, "c0_watchhi,1" },
197 { 19, 2, "c0_watchhi,2" },
198 { 19, 3, "c0_watchhi,3" },
199 { 19, 4, "c0_watchhi,4" },
200 { 19, 5, "c0_watchhi,5" },
201 { 19, 6, "c0_watchhi,6" },
202 { 19, 7, "c0_watchhi,7" },
203 { 25, 1, "c0_perfcnt,1" },
204 { 25, 2, "c0_perfcnt,2" },
205 { 25, 3, "c0_perfcnt,3" },
206 { 25, 4, "c0_perfcnt,4" },
207 { 25, 5, "c0_perfcnt,5" },
208 { 25, 6, "c0_perfcnt,6" },
209 { 25, 7, "c0_perfcnt,7" },
210 { 27, 1, "c0_cacheerr,1" },
211 { 27, 2, "c0_cacheerr,2" },
212 { 27, 3, "c0_cacheerr,3" },
213 { 28, 1, "c0_datalo" },
214 { 29, 1, "c0_datahi" }
215};
216
47b0e7ad
NC		 217static const char * const mips_cp0_names_mips3264r2[32] =
218{
af7ee8bf
CD		 219 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
220 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
221 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
222 "c0_status", "c0_cause", "c0_epc", "c0_prid",
223 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
224 "c0_xcontext", "$21", "$22", "c0_debug",
225 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
226 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
227};
228
47b0e7ad
NC		 229static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
230{
bbcc0807 231 { 4, 1, "c0_contextconfig" },
59c455b3
TS		 232 { 0, 1, "c0_mvpcontrol" },
233 { 0, 2, "c0_mvpconf0" },
234 { 0, 3, "c0_mvpconf1" },
235 { 1, 1, "c0_vpecontrol" },
236 { 1, 2, "c0_vpeconf0" },
237 { 1, 3, "c0_vpeconf1" },
238 { 1, 4, "c0_yqmask" },
239 { 1, 5, "c0_vpeschedule" },
240 { 1, 6, "c0_vpeschefback" },
241 { 2, 1, "c0_tcstatus" },
242 { 2, 2, "c0_tcbind" },
243 { 2, 3, "c0_tcrestart" },
244 { 2, 4, "c0_tchalt" },
245 { 2, 5, "c0_tccontext" },
246 { 2, 6, "c0_tcschedule" },
247 { 2, 7, "c0_tcschefback" },
bbcc0807 248 { 5, 1, "c0_pagegrain" },
59c455b3
TS		 249 { 6, 1, "c0_srsconf0" },
250 { 6, 2, "c0_srsconf1" },
251 { 6, 3, "c0_srsconf2" },
252 { 6, 4, "c0_srsconf3" },
253 { 6, 5, "c0_srsconf4" },
bbcc0807
CD		 254 { 12, 1, "c0_intctl" },
255 { 12, 2, "c0_srsctl" },
256 { 12, 3, "c0_srsmap" },
257 { 15, 1, "c0_ebase" },
258 { 16, 1, "c0_config1" },
259 { 16, 2, "c0_config2" },
260 { 16, 3, "c0_config3" },
261 { 18, 1, "c0_watchlo,1" },
262 { 18, 2, "c0_watchlo,2" },
263 { 18, 3, "c0_watchlo,3" },
264 { 18, 4, "c0_watchlo,4" },
265 { 18, 5, "c0_watchlo,5" },
266 { 18, 6, "c0_watchlo,6" },
267 { 18, 7, "c0_watchlo,7" },
268 { 19, 1, "c0_watchhi,1" },
269 { 19, 2, "c0_watchhi,2" },
270 { 19, 3, "c0_watchhi,3" },
271 { 19, 4, "c0_watchhi,4" },
272 { 19, 5, "c0_watchhi,5" },
273 { 19, 6, "c0_watchhi,6" },
274 { 19, 7, "c0_watchhi,7" },
275 { 23, 1, "c0_tracecontrol" },
276 { 23, 2, "c0_tracecontrol2" },
277 { 23, 3, "c0_usertracedata" },
278 { 23, 4, "c0_tracebpc" },
279 { 25, 1, "c0_perfcnt,1" },
280 { 25, 2, "c0_perfcnt,2" },
281 { 25, 3, "c0_perfcnt,3" },
282 { 25, 4, "c0_perfcnt,4" },
283 { 25, 5, "c0_perfcnt,5" },
284 { 25, 6, "c0_perfcnt,6" },
285 { 25, 7, "c0_perfcnt,7" },
286 { 27, 1, "c0_cacheerr,1" },
287 { 27, 2, "c0_cacheerr,2" },
288 { 27, 3, "c0_cacheerr,3" },
289 { 28, 1, "c0_datalo" },
290 { 28, 2, "c0_taglo1" },
291 { 28, 3, "c0_datalo1" },
292 { 28, 4, "c0_taglo2" },
293 { 28, 5, "c0_datalo2" },
294 { 28, 6, "c0_taglo3" },
295 { 28, 7, "c0_datalo3" },
296 { 29, 1, "c0_datahi" },
297 { 29, 2, "c0_taghi1" },
298 { 29, 3, "c0_datahi1" },
299 { 29, 4, "c0_taghi2" },
300 { 29, 5, "c0_datahi2" },
301 { 29, 6, "c0_taghi3" },
302 { 29, 7, "c0_datahi3" },
303};
304
640c0ccd 305/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
47b0e7ad
NC		 306static const char * const mips_cp0_names_sb1[32] =
307{
640c0ccd
CD		 308 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
309 "c0_context", "c0_pagemask", "c0_wired", "$7",
310 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
311 "c0_status", "c0_cause", "c0_epc", "c0_prid",
312 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
313 "c0_xcontext", "$21", "$22", "c0_debug",
314 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
315 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
316};
317
47b0e7ad
NC		 318static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
319{
bbcc0807
CD		 320 { 16, 1, "c0_config1" },
321 { 18, 1, "c0_watchlo,1" },
322 { 19, 1, "c0_watchhi,1" },
323 { 22, 0, "c0_perftrace" },
324 { 23, 3, "c0_edebug" },
325 { 25, 1, "c0_perfcnt,1" },
326 { 25, 2, "c0_perfcnt,2" },
327 { 25, 3, "c0_perfcnt,3" },
328 { 25, 4, "c0_perfcnt,4" },
329 { 25, 5, "c0_perfcnt,5" },
330 { 25, 6, "c0_perfcnt,6" },
331 { 25, 7, "c0_perfcnt,7" },
332 { 26, 1, "c0_buserr_pa" },
333 { 27, 1, "c0_cacheerr_d" },
334 { 27, 3, "c0_cacheerr_d_pa" },
335 { 28, 1, "c0_datalo_i" },
336 { 28, 2, "c0_taglo_d" },
337 { 28, 3, "c0_datalo_d" },
338 { 29, 1, "c0_datahi_i" },
339 { 29, 2, "c0_taghi_d" },
340 { 29, 3, "c0_datahi_d" },
341};
342
52b6b6b9
JM		 343/* Xlr cop0 register names. */
344static const char * const mips_cp0_names_xlr[32] = {
345 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
346 "c0_context", "c0_pagemask", "c0_wired", "$7",
347 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
348 "c0_status", "c0_cause", "c0_epc", "c0_prid",
349 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
350 "c0_xcontext", "$21", "$22", "c0_debug",
351 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
352 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
353};
354
355/* XLR's CP0 Select Registers. */
356
357static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
358 { 9, 6, "c0_extintreq" },
359 { 9, 7, "c0_extintmask" },
360 { 15, 1, "c0_ebase" },
361 { 16, 1, "c0_config1" },
362 { 16, 2, "c0_config2" },
363 { 16, 3, "c0_config3" },
364 { 16, 7, "c0_procid2" },
365 { 18, 1, "c0_watchlo,1" },
366 { 18, 2, "c0_watchlo,2" },
367 { 18, 3, "c0_watchlo,3" },
368 { 18, 4, "c0_watchlo,4" },
369 { 18, 5, "c0_watchlo,5" },
370 { 18, 6, "c0_watchlo,6" },
371 { 18, 7, "c0_watchlo,7" },
372 { 19, 1, "c0_watchhi,1" },
373 { 19, 2, "c0_watchhi,2" },
374 { 19, 3, "c0_watchhi,3" },
375 { 19, 4, "c0_watchhi,4" },
376 { 19, 5, "c0_watchhi,5" },
377 { 19, 6, "c0_watchhi,6" },
378 { 19, 7, "c0_watchhi,7" },
379 { 25, 1, "c0_perfcnt,1" },
380 { 25, 2, "c0_perfcnt,2" },
381 { 25, 3, "c0_perfcnt,3" },
382 { 25, 4, "c0_perfcnt,4" },
383 { 25, 5, "c0_perfcnt,5" },
384 { 25, 6, "c0_perfcnt,6" },
385 { 25, 7, "c0_perfcnt,7" },
386 { 27, 1, "c0_cacheerr,1" },
387 { 27, 2, "c0_cacheerr,2" },
388 { 27, 3, "c0_cacheerr,3" },
389 { 28, 1, "c0_datalo" },
390 { 29, 1, "c0_datahi" }
391};
392
47b0e7ad
NC		 393static const char * const mips_hwr_names_numeric[32] =
394{
af7ee8bf
CD		 395 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
396 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
397 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
398 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
399};
400
47b0e7ad
NC		 401static const char * const mips_hwr_names_mips3264r2[32] =
402{
af7ee8bf
CD		 403 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
404 "$4", "$5", "$6", "$7",
405 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
406 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
407 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
408};
409
4edbb8e3
CF		 410static const char * const msa_control_names[32] =
411{
412 "msa_ir", "msa_csr", "msa_access", "msa_save",
413 "msa_modify", "msa_request", "msa_map", "msa_unmap",
414 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
415 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
416 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
417};
418
47b0e7ad
NC		 419struct mips_abi_choice
420{
421 const char * name;
640c0ccd
CD		 422 const char * const *gpr_names;
423 const char * const *fpr_names;
424};
425
47b0e7ad
NC		 426struct mips_abi_choice mips_abi_choices[] =
427{
640c0ccd
CD		 428 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
429 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
430 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
431 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
432};
433
47b0e7ad
NC		 434struct mips_arch_choice
435{
640c0ccd
CD		 436 const char *name;
437 int bfd_mach_valid;
438 unsigned long bfd_mach;
439 int processor;
440 int isa;
d301a56b 441 int ase;
640c0ccd 442 const char * const *cp0_names;
bbcc0807
CD		 443 const struct mips_cp0sel_name *cp0sel_names;
444 unsigned int cp0sel_names_len;
dc76d757 445 const char * const *cp1_names;
af7ee8bf 446 const char * const *hwr_names;
640c0ccd
CD		 447};
448
47b0e7ad
NC		 449const struct mips_arch_choice mips_arch_choices[] =
450{
d301a56b 451 { "numeric", 0, 0, 0, 0, 0,
dc76d757
AB		 452 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
453 mips_hwr_names_numeric },
bbcc0807 454
d301a56b 455 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
dc76d757
AB		 456 mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric,
457 mips_hwr_names_numeric },
d301a56b 458 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
dc76d757
AB		 459 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
460 mips_hwr_names_numeric },
d301a56b 461 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
dc76d757
AB		 462 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
463 mips_hwr_names_numeric },
d301a56b 464 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
dc76d757
AB		 465 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
466 mips_hwr_names_numeric },
d301a56b 467 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
dc76d757
AB		 468 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
469 mips_hwr_names_numeric },
d301a56b 470 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
dc76d757
AB		 471 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
472 mips_hwr_names_numeric },
d301a56b 473 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
dc76d757
AB		 474 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
475 mips_hwr_names_numeric },
d301a56b 476 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
dc76d757
AB		 477 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
478 mips_hwr_names_numeric },
d301a56b 479 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
dc76d757
AB		 480 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
481 mips_hwr_names_numeric },
d301a56b 482 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
dc76d757
AB		 483 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
484 mips_hwr_names_numeric },
d301a56b 485 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
dc76d757
AB		 486 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
487 mips_hwr_names_numeric },
d301a56b 488 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
dc76d757
AB		 489 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
490 mips_hwr_names_numeric },
d301a56b 491 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
dc76d757
AB		 492 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
493 mips_hwr_names_numeric },
d301a56b 494 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
dc76d757
AB		 495 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
496 mips_hwr_names_numeric },
d301a56b 497 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
dc76d757
AB		 498 mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric,
499 mips_hwr_names_numeric },
d301a56b 500 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
dc76d757
AB		 501 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
502 mips_hwr_names_numeric },
d301a56b 503 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
dc76d757
AB		 504 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
505 mips_hwr_names_numeric },
d301a56b 506 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
dc76d757
AB		 507 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
508 mips_hwr_names_numeric },
d301a56b 509 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
dc76d757
AB		 510 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
511 mips_hwr_names_numeric },
d301a56b 512 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
dc76d757
AB		 513 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
514 mips_hwr_names_numeric },
d301a56b 515 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
dc76d757
AB		 516 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
517 mips_hwr_names_numeric },
d301a56b 518 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
dc76d757
AB		 519 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
520 mips_hwr_names_numeric },
d301a56b 521 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
dc76d757
AB		 522 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
523 mips_hwr_names_numeric },
d301a56b 524 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
dc76d757
AB		 525 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
526 mips_hwr_names_numeric },
bbcc0807 527
640c0ccd
CD		 528 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
529 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
530 _MIPS32 Architecture For Programmers Volume I: Introduction to the
531 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
532 page 1. */
533 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
d301a56b 534 ISA_MIPS32, ASE_SMARTMIPS,
bbcc0807
CD		 535 mips_cp0_names_mips3264,
536 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
dc76d757 537 mips_cp1_names_mips3264, mips_hwr_names_numeric },
bbcc0807 538
af7ee8bf 539 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
d301a56b 540 ISA_MIPS32R2,
7f3c4072 541 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
7d64c587 542 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
bbcc0807
CD		 543 mips_cp0_names_mips3264r2,
544 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
dc76d757 545 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
bbcc0807 546
ae52f483
AB		 547 { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3,
548 ISA_MIPS32R3,
549 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
550 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
551 mips_cp0_names_mips3264r2,
552 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
553 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
554
555 { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5,
556 ISA_MIPS32R5,
557 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
558 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
559 mips_cp0_names_mips3264r2,
560 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
561 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
562
7361da2c
AB		 563 { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
564 ISA_MIPS32R6,
565 (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
8f4f9071 566 | ASE_DSPR2 | ASE_DSPR3),
7361da2c
AB		 567 mips_cp0_names_mips3264r2,
568 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
569 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
570
640c0ccd
CD		 571 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
572 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
d301a56b 573 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
bbcc0807
CD		 574 mips_cp0_names_mips3264,
575 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
dc76d757 576 mips_cp1_names_mips3264, mips_hwr_names_numeric },
bbcc0807 577
5f74bc13 578 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
d301a56b 579 ISA_MIPS64R2,
7f3c4072 580 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
7d64c587 581 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
5f74bc13
CD		 582 mips_cp0_names_mips3264r2,
583 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
dc76d757 584 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
5f74bc13 585
ae52f483
AB		 586 { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3,
587 ISA_MIPS64R3,
588 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
589 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
590 mips_cp0_names_mips3264r2,
591 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
592 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
593
594 { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5,
595 ISA_MIPS64R5,
596 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
597 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
598 mips_cp0_names_mips3264r2,
599 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
600 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
601
7361da2c
AB		 602 { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
603 ISA_MIPS64R6,
604 (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
8f4f9071 605 | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3),
7361da2c
AB		 606 mips_cp0_names_mips3264r2,
607 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
608 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
609
640c0ccd 610 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
d301a56b 611 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
bbcc0807
CD		 612 mips_cp0_names_sb1,
613 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
dc76d757 614 mips_cp1_names_mips3264, mips_hwr_names_numeric },
640c0ccd 615
350cc38d 616 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
d301a56b 617 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
dc76d757 618 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
350cc38d
MS		 619
620 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
d301a56b 621 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
dc76d757 622 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
350cc38d 623
fd503541 624 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
4ba154f5 625 ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
dc76d757 626 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
fd503541 627
57b592a3 628 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
d301a56b 629 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
dc76d757 630 mips_cp1_names_mips3264, mips_hwr_names_numeric },
57b592a3 631
dd6a37e7 632 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
d301a56b 633 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
dc76d757 634 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
432233b3
AP		 635
636 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
d301a56b 637 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
dc76d757 638 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
dd6a37e7 639
2c629856
N		 640 { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3,
641 ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64,
642 mips_cp0_names_numeric,
643 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
644
52b6b6b9 645 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
d301a56b 646 ISA_MIPS64 | INSN_XLR, 0,
52b6b6b9
JM		 647 mips_cp0_names_xlr,
648 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
dc76d757 649 mips_cp1_names_mips3264, mips_hwr_names_numeric },
52b6b6b9 650
55a36193
MK		 651 /* XLP is mostly like XLR, with the prominent exception it is being
652 MIPS64R2. */
653 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
d301a56b 654 ISA_MIPS64R2 | INSN_XLR, 0,
55a36193
MK		 655 mips_cp0_names_xlr,
656 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
dc76d757 657 mips_cp1_names_mips3264, mips_hwr_names_numeric },
55a36193 658
640c0ccd
CD		 659 /* This entry, mips16, is here only for ISA/processor selection; do
660 not print its name. */
25499ac7
MR		 661 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS64,
662 ASE_MIPS16E2 | ASE_MIPS16E2_MT,
dc76d757
AB		 663 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
664 mips_hwr_names_numeric },
640c0ccd
CD		 665};
666
667/* ISA and processor type to disassemble for, and register names to use.
668 set_default_mips_dis_options and parse_mips_dis_options fill in these
669 values. */
670static int mips_processor;
671static int mips_isa;
d301a56b 672static int mips_ase;
df58fc94 673static int micromips_ase;
640c0ccd
CD		 674static const char * const *mips_gpr_names;
675static const char * const *mips_fpr_names;
676static const char * const *mips_cp0_names;
bbcc0807
CD		 677static const struct mips_cp0sel_name *mips_cp0sel_names;
678static int mips_cp0sel_names_len;
dc76d757 679static const char * const *mips_cp1_names;
af7ee8bf 680static const char * const *mips_hwr_names;
640c0ccd 681
986e18a5 682/* Other options */
47b0e7ad 683static int no_aliases; /* If set disassemble as most general inst. */
640c0ccd
CD		 684\f
685static const struct mips_abi_choice *
47b0e7ad 686choose_abi_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 687{
688 const struct mips_abi_choice *c;
689 unsigned int i;
690
691 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
47b0e7ad
NC		 692 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
693 && strlen (mips_abi_choices[i].name) == namelen)
694 c = &mips_abi_choices[i];
695
640c0ccd
CD		 696 return c;
697}
698
699static const struct mips_arch_choice *
47b0e7ad 700choose_arch_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 701{
702 const struct mips_arch_choice *c = NULL;
703 unsigned int i;
704
705 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
47b0e7ad
NC		 706 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
707 && strlen (mips_arch_choices[i].name) == namelen)
708 c = &mips_arch_choices[i];
709
640c0ccd
CD		 710 return c;
711}
712
713static const struct mips_arch_choice *
47b0e7ad 714choose_arch_by_number (unsigned long mach)
640c0ccd
CD		 715{
716 static unsigned long hint_bfd_mach;
717 static const struct mips_arch_choice *hint_arch_choice;
718 const struct mips_arch_choice *c;
719 unsigned int i;
720
721 /* We optimize this because even if the user specifies no
722 flags, this will be done for every instruction! */
723 if (hint_bfd_mach == mach
724 && hint_arch_choice != NULL
725 && hint_arch_choice->bfd_mach == hint_bfd_mach)
726 return hint_arch_choice;
727
728 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
729 {
730 if (mips_arch_choices[i].bfd_mach_valid
731 && mips_arch_choices[i].bfd_mach == mach)
732 {
733 c = &mips_arch_choices[i];
734 hint_bfd_mach = mach;
735 hint_arch_choice = c;
736 }
737 }
738 return c;
739}
740
47b0e7ad
NC		 741/* Check if the object uses NewABI conventions. */
742
743static int
744is_newabi (Elf_Internal_Ehdr *header)
745{
746 /* There are no old-style ABIs which use 64-bit ELF. */
747 if (header->e_ident[EI_CLASS] == ELFCLASS64)
748 return 1;
749
750 /* If a 32-bit ELF file, n32 is a new-style ABI. */
751 if ((header->e_flags & EF_MIPS_ABI2) != 0)
752 return 1;
753
754 return 0;
755}
756
df58fc94
RS		 757/* Check if the object has microMIPS ASE code. */
758
759static int
760is_micromips (Elf_Internal_Ehdr *header)
761{
762 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
763 return 1;
764
765 return 0;
766}
767
5e7fc731
MR		 768/* Convert ASE flags from .MIPS.abiflags to internal values. */
769
770static unsigned long
771mips_convert_abiflags_ases (unsigned long afl_ases)
772{
773 unsigned long opcode_ases = 0;
774
775 if (afl_ases & AFL_ASE_DSP)
776 opcode_ases |= ASE_DSP;
777 if (afl_ases & AFL_ASE_DSPR2)
778 opcode_ases |= ASE_DSPR2;
779 if (afl_ases & AFL_ASE_EVA)
780 opcode_ases |= ASE_EVA;
781 if (afl_ases & AFL_ASE_MCU)
782 opcode_ases |= ASE_MCU;
783 if (afl_ases & AFL_ASE_MDMX)
784 opcode_ases |= ASE_MDMX;
785 if (afl_ases & AFL_ASE_MIPS3D)
786 opcode_ases |= ASE_MIPS3D;
787 if (afl_ases & AFL_ASE_MT)
788 opcode_ases |= ASE_MT;
789 if (afl_ases & AFL_ASE_SMARTMIPS)
790 opcode_ases |= ASE_SMARTMIPS;
791 if (afl_ases & AFL_ASE_VIRT)
792 opcode_ases |= ASE_VIRT;
793 if (afl_ases & AFL_ASE_MSA)
794 opcode_ases |= ASE_MSA;
795 if (afl_ases & AFL_ASE_XPA)
796 opcode_ases |= ASE_XPA;
797 if (afl_ases & AFL_ASE_DSPR3)
798 opcode_ases |= ASE_DSPR3;
25499ac7
MR		 799 if (afl_ases & AFL_ASE_MIPS16E2)
800 opcode_ases |= ASE_MIPS16E2;
801 if ((afl_ases & (AFL_ASE_MIPS16E2 | AFL_ASE_MT))
802 == (AFL_ASE_MIPS16E2 | AFL_ASE_MT))
803 opcode_ases |= ASE_MIPS16E2_MT;
5e7fc731
MR		 804 return opcode_ases;
805}
806
47b0e7ad
NC		 807static void
808set_default_mips_dis_options (struct disassemble_info *info)
640c0ccd
CD		 809{
810 const struct mips_arch_choice *chosen_arch;
811
df58fc94
RS		 812 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
813 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
814 CP0 register, and HWR names. */
640c0ccd 815 mips_isa = ISA_MIPS3;
df58fc94
RS		 816 mips_processor = CPU_R3000;
817 micromips_ase = 0;
d301a56b 818 mips_ase = 0;
640c0ccd
CD		 819 mips_gpr_names = mips_gpr_names_oldabi;
820 mips_fpr_names = mips_fpr_names_numeric;
821 mips_cp0_names = mips_cp0_names_numeric;
bbcc0807
CD		 822 mips_cp0sel_names = NULL;
823 mips_cp0sel_names_len = 0;
dc76d757 824 mips_cp1_names = mips_cp1_names_numeric;
af7ee8bf 825 mips_hwr_names = mips_hwr_names_numeric;
986e18a5 826 no_aliases = 0;
640c0ccd 827
640c0ccd
CD		 828 /* Set ISA, architecture, and cp0 register names as best we can. */
829#if ! SYMTAB_AVAILABLE
830 /* This is running out on a target machine, not in a host tool.
831 FIXME: Where does mips_target_info come from? */
832 target_processor = mips_target_info.processor;
833 mips_isa = mips_target_info.isa;
d301a56b 834 mips_ase = mips_target_info.ase;
640c0ccd
CD		 835#else
836 chosen_arch = choose_arch_by_number (info->mach);
837 if (chosen_arch != NULL)
838 {
839 mips_processor = chosen_arch->processor;
840 mips_isa = chosen_arch->isa;
d301a56b 841 mips_ase = chosen_arch->ase;
bbcc0807
CD		 842 mips_cp0_names = chosen_arch->cp0_names;
843 mips_cp0sel_names = chosen_arch->cp0sel_names;
844 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
dc76d757 845 mips_cp1_names = chosen_arch->cp1_names;
bbcc0807 846 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd 847 }
8184783a
MR		 848
849 /* Update settings according to the ELF file header flags. */
850 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
851 {
5e7fc731
MR		 852 struct bfd *abfd = info->section->owner;
853 Elf_Internal_Ehdr *header = elf_elfheader (abfd);
4df995c7
MR		 854 Elf_Internal_ABIFlags_v0 *abiflags = NULL;
855
9e76c212
MR		 856 /* We won't ever get here if !HAVE_BFD_MIPS_ELF_GET_ABIFLAGS,
857 because we won't then have a MIPS/ELF BFD, however we need
858 to guard against a link error in a `--enable-targets=...'
859 configuration with a 32-bit host where the MIPS target is
860 a secondary, or with MIPS/ECOFF configurations. */
861#ifdef HAVE_BFD_MIPS_ELF_GET_ABIFLAGS
4df995c7
MR		 862 abiflags = bfd_mips_elf_get_abiflags (abfd);
863#endif
8184783a
MR		 864 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
865 if (is_newabi (header))
866 mips_gpr_names = mips_gpr_names_newabi;
867 /* If a microMIPS binary, then don't use MIPS16 bindings. */
868 micromips_ase = is_micromips (header);
5e7fc731
MR		 869 /* OR in any extra ASE flags set in ELF file structures. */
870 if (abiflags)
871 mips_ase |= mips_convert_abiflags_ases (abiflags->ases);
872 else if (header->e_flags & EF_MIPS_ARCH_ASE_MDMX)
873 mips_ase |= ASE_MDMX;
8184783a 874 }
91068ec6 875#endif
640c0ccd
CD		 876}
877
47b0e7ad
NC		 878static void
879parse_mips_dis_option (const char *option, unsigned int len)
640c0ccd
CD		 880{
881 unsigned int i, optionlen, vallen;
882 const char *val;
883 const struct mips_abi_choice *chosen_abi;
884 const struct mips_arch_choice *chosen_arch;
885
986e18a5 886 /* Try to match options that are simple flags */
0112cd26 887 if (CONST_STRNEQ (option, "no-aliases"))
986e18a5
FF		 888 {
889 no_aliases = 1;
890 return;
891 }
b015e599 892
4edbb8e3
CF		 893 if (CONST_STRNEQ (option, "msa"))
894 {
895 mips_ase |= ASE_MSA;
ae52f483
AB		 896 if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2
897 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3
7361da2c
AB		 898 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5
899 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)
4edbb8e3
CF		 900 mips_ase |= ASE_MSA64;
901 return;
902 }
903
b015e599
AP		 904 if (CONST_STRNEQ (option, "virt"))
905 {
d301a56b 906 mips_ase |= ASE_VIRT;
ae52f483
AB		 907 if (mips_isa & ISA_MIPS64R2
908 || mips_isa & ISA_MIPS64R3
7361da2c
AB		 909 || mips_isa & ISA_MIPS64R5
910 || mips_isa & ISA_MIPS64R6)
d301a56b 911 mips_ase |= ASE_VIRT64;
b015e599
AP		 912 return;
913 }
7d64c587
AB		 914
915 if (CONST_STRNEQ (option, "xpa"))
916 {
917 mips_ase |= ASE_XPA;
918 return;
919 }
43e65147
L		 920
921
640c0ccd
CD		 922 /* Look for the = that delimits the end of the option name. */
923 for (i = 0; i < len; i++)
47b0e7ad
NC		 924 if (option[i] == '=')
925 break;
926
640c0ccd
CD		 927 if (i == 0) /* Invalid option: no name before '='. */
928 return;
929 if (i == len) /* Invalid option: no '='. */
930 return;
931 if (i == (len - 1)) /* Invalid option: no value after '='. */
932 return;
933
934 optionlen = i;
935 val = option + (optionlen + 1);
936 vallen = len - (optionlen + 1);
937
47b0e7ad
NC		 938 if (strncmp ("gpr-names", option, optionlen) == 0
939 && strlen ("gpr-names") == optionlen)
640c0ccd
CD		 940 {
941 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 942 if (chosen_abi != NULL)
640c0ccd
CD		 943 mips_gpr_names = chosen_abi->gpr_names;
944 return;
945 }
946
47b0e7ad
NC		 947 if (strncmp ("fpr-names", option, optionlen) == 0
948 && strlen ("fpr-names") == optionlen)
640c0ccd
CD		 949 {
950 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 951 if (chosen_abi != NULL)
640c0ccd
CD		 952 mips_fpr_names = chosen_abi->fpr_names;
953 return;
954 }
955
47b0e7ad
NC		 956 if (strncmp ("cp0-names", option, optionlen) == 0
957 && strlen ("cp0-names") == optionlen)
640c0ccd
CD		 958 {
959 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807
CD		 960 if (chosen_arch != NULL)
961 {
962 mips_cp0_names = chosen_arch->cp0_names;
963 mips_cp0sel_names = chosen_arch->cp0sel_names;
964 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
965 }
640c0ccd
CD		 966 return;
967 }
968
dc76d757
AB		 969 if (strncmp ("cp1-names", option, optionlen) == 0
970 && strlen ("cp1-names") == optionlen)
971 {
972 chosen_arch = choose_arch_by_name (val, vallen);
973 if (chosen_arch != NULL)
974 mips_cp1_names = chosen_arch->cp1_names;
975 return;
976 }
977
47b0e7ad
NC		 978 if (strncmp ("hwr-names", option, optionlen) == 0
979 && strlen ("hwr-names") == optionlen)
af7ee8bf
CD		 980 {
981 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807 982 if (chosen_arch != NULL)
af7ee8bf
CD		 983 mips_hwr_names = chosen_arch->hwr_names;
984 return;
985 }
986
47b0e7ad
NC		 987 if (strncmp ("reg-names", option, optionlen) == 0
988 && strlen ("reg-names") == optionlen)
640c0ccd
CD		 989 {
990 /* We check both ABI and ARCH here unconditionally, so
991 that "numeric" will do the desirable thing: select
992 numeric register names for all registers. Other than
993 that, a given name probably won't match both. */
994 chosen_abi = choose_abi_by_name (val, vallen);
995 if (chosen_abi != NULL)
996 {
bbcc0807
CD		 997 mips_gpr_names = chosen_abi->gpr_names;
998 mips_fpr_names = chosen_abi->fpr_names;
640c0ccd
CD		 999 }
1000 chosen_arch = choose_arch_by_name (val, vallen);
1001 if (chosen_arch != NULL)
1002 {
bbcc0807
CD		 1003 mips_cp0_names = chosen_arch->cp0_names;
1004 mips_cp0sel_names = chosen_arch->cp0sel_names;
1005 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
dc76d757 1006 mips_cp1_names = chosen_arch->cp1_names;
bbcc0807 1007 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 1008 }
1009 return;
1010 }
1011
1012 /* Invalid option. */
1013}
1014
47b0e7ad
NC		 1015static void
1016parse_mips_dis_options (const char *options)
640c0ccd
CD		 1017{
1018 const char *option_end;
1019
1020 if (options == NULL)
1021 return;
1022
1023 while (*options != '\0')
1024 {
1025 /* Skip empty options. */
1026 if (*options == ',')
1027 {
1028 options++;
1029 continue;
1030 }
1031
1032 /* We know that *options is neither NUL or a comma. */
1033 option_end = options + 1;
1034 while (*option_end != ',' && *option_end != '\0')
1035 option_end++;
1036
1037 parse_mips_dis_option (options, option_end - options);
1038
1039 /* Go on to the next one. If option_end points to a comma, it
1040 will be skipped above. */
1041 options = option_end;
1042 }
1043}
1044
bbcc0807 1045static const struct mips_cp0sel_name *
47b0e7ad
NC		 1046lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
1047 unsigned int len,
1048 unsigned int cp0reg,
1049 unsigned int sel)
bbcc0807
CD		 1050{
1051 unsigned int i;
1052
1053 for (i = 0; i < len; i++)
1054 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
1055 return &names[i];
1056 return NULL;
1057}
ab902481
RS		 1058
1059/* Print register REGNO, of type TYPE, for instruction OPCODE. */
aa5f19f2 1060
794ac9d0 1061static void
ab902481
RS		 1062print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
1063 enum mips_reg_operand_type type, int regno)
252b5132 1064{
ab902481
RS		 1065 switch (type)
1066 {
1067 case OP_REG_GP:
1068 info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]);
1069 break;
440cc0bc 1070
ab902481
RS		 1071 case OP_REG_FP:
1072 info->fprintf_func (info->stream, "%s", mips_fpr_names[regno]);
1073 break;
252b5132 1074
ab902481
RS		 1075 case OP_REG_CCC:
1076 if (opcode->pinfo & (FP_D | FP_S))
1077 info->fprintf_func (info->stream, "$fcc%d", regno);
1078 else
1079 info->fprintf_func (info->stream, "$cc%d", regno);
1080 break;
794ac9d0 1081
ab902481
RS		 1082 case OP_REG_VEC:
1083 if (opcode->membership & INSN_5400)
1084 info->fprintf_func (info->stream, "$f%d", regno);
1085 else
1086 info->fprintf_func (info->stream, "$v%d", regno);
1087 break;
794ac9d0 1088
ab902481
RS		 1089 case OP_REG_ACC:
1090 info->fprintf_func (info->stream, "$ac%d", regno);
1091 break;
794ac9d0 1092
ab902481
RS		 1093 case OP_REG_COPRO:
1094 if (opcode->name[strlen (opcode->name) - 1] == '0')
1095 info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]);
dc76d757
AB		 1096 else if (opcode->name[strlen (opcode->name) - 1] == '1')
1097 info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]);
ab902481
RS		 1098 else
1099 info->fprintf_func (info->stream, "$%d", regno);
1100 break;
8b082fb1 1101
ab902481
RS		 1102 case OP_REG_HW:
1103 info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]);
1104 break;
14daeee3
RS		 1105
1106 case OP_REG_VF:
1107 info->fprintf_func (info->stream, "$vf%d", regno);
1108 break;
1109
1110 case OP_REG_VI:
1111 info->fprintf_func (info->stream, "$vi%d", regno);
1112 break;
1113
1114 case OP_REG_R5900_I:
1115 info->fprintf_func (info->stream, "$I");
1116 break;
1117
1118 case OP_REG_R5900_Q:
1119 info->fprintf_func (info->stream, "$Q");
1120 break;
1121
1122 case OP_REG_R5900_R:
1123 info->fprintf_func (info->stream, "$R");
1124 break;
1125
1126 case OP_REG_R5900_ACC:
1127 info->fprintf_func (info->stream, "$ACC");
1128 break;
4edbb8e3
CF		 1129
1130 case OP_REG_MSA:
1131 info->fprintf_func (info->stream, "$w%d", regno);
1132 break;
1133
1134 case OP_REG_MSA_CTRL:
1135 info->fprintf_func (info->stream, "%s", msa_control_names[regno]);
1136 break;
1137
ab902481
RS		 1138 }
1139}
1140\f
1141/* Used to track the state carried over from previous operands in
1142 an instruction. */
1143struct mips_print_arg_state {
1144 /* The value of the last OP_INT seen. We only use this for OP_MSB,
1145 where the value is known to be unsigned and small. */
1146 unsigned int last_int;
1147
1148 /* The type and number of the last OP_REG seen. We only use this for
1149 OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */
1150 enum mips_reg_operand_type last_reg_type;
1151 unsigned int last_regno;
7361da2c
AB		 1152 unsigned int dest_regno;
1153 unsigned int seen_dest;
ab902481 1154};
fd25c5a9 1155
ab902481 1156/* Initialize STATE for the start of an instruction. */
fd25c5a9 1157
ab902481
RS		 1158static inline void
1159init_print_arg_state (struct mips_print_arg_state *state)
1160{
1161 memset (state, 0, sizeof (*state));
1162}
fd25c5a9 1163
14daeee3
RS		 1164/* Print OP_VU0_SUFFIX or OP_VU0_MATCH_SUFFIX operand OPERAND,
1165 whose value is given by UVAL. */
1166
1167static void
1168print_vu0_channel (struct disassemble_info *info,
1169 const struct mips_operand *operand, unsigned int uval)
1170{
1171 if (operand->size == 4)
1172 info->fprintf_func (info->stream, "%s%s%s%s",
1173 uval & 8 ? "x" : "",
1174 uval & 4 ? "y" : "",
1175 uval & 2 ? "z" : "",
1176 uval & 1 ? "w" : "");
1177 else if (operand->size == 2)
1178 info->fprintf_func (info->stream, "%c", "xyzw"[uval]);
1179 else
1180 abort ();
1181}
1182
7361da2c
AB		 1183/* Record information about a register operand. */
1184
1185static void
1186mips_seen_register (struct mips_print_arg_state *state,
1187 unsigned int regno,
1188 enum mips_reg_operand_type reg_type)
1189{
1190 state->last_reg_type = reg_type;
1191 state->last_regno = regno;
1192
1193 if (!state->seen_dest)
1194 {
1195 state->seen_dest = 1;
1196 state->dest_regno = regno;
1197 }
1198}
1199
ab902481
RS		 1200/* Print operand OPERAND of OPCODE, using STATE to track inter-operand state.
1201 UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is
1202 the base address for OP_PCREL operands. */
fd25c5a9 1203
ab902481
RS		 1204static void
1205print_insn_arg (struct disassemble_info *info,
1206 struct mips_print_arg_state *state,
1207 const struct mips_opcode *opcode,
1208 const struct mips_operand *operand,
1209 bfd_vma base_pc,
1210 unsigned int uval)
1211{
1212 const fprintf_ftype infprintf = info->fprintf_func;
1213 void *is = info->stream;
fd25c5a9 1214
ab902481
RS		 1215 switch (operand->type)
1216 {
1217 case OP_INT:
1218 {
1219 const struct mips_int_operand *int_op;
fd25c5a9 1220
ab902481
RS		 1221 int_op = (const struct mips_int_operand *) operand;
1222 uval = mips_decode_int_operand (int_op, uval);
1223 state->last_int = uval;
1224 if (int_op->print_hex)
1225 infprintf (is, "0x%x", uval);
1226 else
1227 infprintf (is, "%d", uval);
1228 }
1229 break;
fd25c5a9 1230
ab902481
RS		 1231 case OP_MAPPED_INT:
1232 {
1233 const struct mips_mapped_int_operand *mint_op;
fd25c5a9 1234
ab902481
RS		 1235 mint_op = (const struct mips_mapped_int_operand *) operand;
1236 uval = mint_op->int_map[uval];
1237 state->last_int = uval;
1238 if (mint_op->print_hex)
1239 infprintf (is, "0x%x", uval);
1240 else
1241 infprintf (is, "%d", uval);
1242 }
1243 break;
fd25c5a9 1244
ab902481
RS		 1245 case OP_MSB:
1246 {
1247 const struct mips_msb_operand *msb_op;
dec0624d 1248
ab902481
RS		 1249 msb_op = (const struct mips_msb_operand *) operand;
1250 uval += msb_op->bias;
1251 if (msb_op->add_lsb)
1252 uval -= state->last_int;
1253 infprintf (is, "0x%x", uval);
1254 }
1255 break;
dec0624d 1256
ab902481 1257 case OP_REG:
0f35dbc4 1258 case OP_OPTIONAL_REG:
ab902481
RS		 1259 {
1260 const struct mips_reg_operand *reg_op;
fd25c5a9 1261
ab902481 1262 reg_op = (const struct mips_reg_operand *) operand;
fc76e730 1263 uval = mips_decode_reg_operand (reg_op, uval);
ab902481 1264 print_reg (info, opcode, reg_op->reg_type, uval);
fd25c5a9 1265
7361da2c 1266 mips_seen_register (state, uval, reg_op->reg_type);
ab902481
RS		 1267 }
1268 break;
61cc0267 1269
ab902481
RS		 1270 case OP_REG_PAIR:
1271 {
1272 const struct mips_reg_pair_operand *pair_op;
1273
1274 pair_op = (const struct mips_reg_pair_operand *) operand;
1275 print_reg (info, opcode, pair_op->reg_type,
1276 pair_op->reg1_map[uval]);
1277 infprintf (is, ",");
1278 print_reg (info, opcode, pair_op->reg_type,
1279 pair_op->reg2_map[uval]);
1280 }
1281 break;
61cc0267 1282
ab902481
RS		 1283 case OP_PCREL:
1284 {
1285 const struct mips_pcrel_operand *pcrel_op;
61cc0267 1286
ab902481
RS		 1287 pcrel_op = (const struct mips_pcrel_operand *) operand;
1288 info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval);
61cc0267 1289
a4ddc54e
MR		 1290 /* For jumps and branches clear the ISA bit except for
1291 the GDB disassembler. */
1292 if (pcrel_op->include_isa_bit
1293 && info->flavour != bfd_target_unknown_flavour)
ab902481 1294 info->target &= -2;
61cc0267 1295
ab902481
RS		 1296 (*info->print_address_func) (info->target, info);
1297 }
1298 break;
794ac9d0 1299
ab902481
RS		 1300 case OP_PERF_REG:
1301 infprintf (is, "%d", uval);
1302 break;
794ac9d0 1303
ab902481
RS		 1304 case OP_ADDIUSP_INT:
1305 {
1306 int sval;
794ac9d0 1307
ab902481
RS		 1308 sval = mips_signed_operand (operand, uval) * 4;
1309 if (sval >= -8 && sval < 8)
1310 sval ^= 0x400;
1311 infprintf (is, "%d", sval);
1312 break;
1313 }
794ac9d0 1314
ab902481
RS		 1315 case OP_CLO_CLZ_DEST:
1316 {
1317 unsigned int reg1, reg2;
1318
1319 reg1 = uval & 31;
1320 reg2 = uval >> 5;
1321 /* If one is zero use the other. */
1322 if (reg1 == reg2 || reg2 == 0)
1323 infprintf (is, "%s", mips_gpr_names[reg1]);
1324 else if (reg1 == 0)
1325 infprintf (is, "%s", mips_gpr_names[reg2]);
1326 else
1327 /* Bogus, result depends on processor. */
1328 infprintf (is, "%s or %s", mips_gpr_names[reg1],
1329 mips_gpr_names[reg2]);
1330 }
1331 break;
794ac9d0 1332
7361da2c
AB		 1333 case OP_SAME_RS_RT:
1334 case OP_CHECK_PREV:
1335 case OP_NON_ZERO_REG:
1336 {
1337 print_reg (info, opcode, OP_REG_GP, uval & 31);
1338 mips_seen_register (state, uval, OP_REG_GP);
1339 }
1340 break;
1341
ab902481
RS		 1342 case OP_LWM_SWM_LIST:
1343 if (operand->size == 2)
1344 {
1345 if (uval == 0)
1346 infprintf (is, "%s,%s",
1347 mips_gpr_names[16],
1348 mips_gpr_names[31]);
1349 else
1350 infprintf (is, "%s-%s,%s",
1351 mips_gpr_names[16],
1352 mips_gpr_names[16 + uval],
1353 mips_gpr_names[31]);
1354 }
1355 else
1356 {
1357 int s_reg_encode;
794ac9d0 1358
ab902481
RS		 1359 s_reg_encode = uval & 0xf;
1360 if (s_reg_encode != 0)
1361 {
1362 if (s_reg_encode == 1)
1363 infprintf (is, "%s", mips_gpr_names[16]);
1364 else if (s_reg_encode < 9)
1365 infprintf (is, "%s-%s",
1366 mips_gpr_names[16],
1367 mips_gpr_names[15 + s_reg_encode]);
1368 else if (s_reg_encode == 9)
1369 infprintf (is, "%s-%s,%s",
1370 mips_gpr_names[16],
1371 mips_gpr_names[23],
1372 mips_gpr_names[30]);
1373 else
1374 infprintf (is, "UNKNOWN");
1375 }
794ac9d0 1376
ab902481
RS		 1377 if (uval & 0x10) /* For ra. */
1378 {
1379 if (s_reg_encode == 0)
1380 infprintf (is, "%s", mips_gpr_names[31]);
1381 else
1382 infprintf (is, ",%s", mips_gpr_names[31]);
1383 }
1384 }
1385 break;
794ac9d0 1386
c3c07478
RS		 1387 case OP_ENTRY_EXIT_LIST:
1388 {
1389 const char *sep;
1390 unsigned int amask, smask;
1391
1392 sep = "";
1393 amask = (uval >> 3) & 7;
1394 if (amask > 0 && amask < 5)
1395 {
1396 infprintf (is, "%s", mips_gpr_names[4]);
1397 if (amask > 1)
1398 infprintf (is, "-%s", mips_gpr_names[amask + 3]);
1399 sep = ",";
1400 }
1401
1402 smask = (uval >> 1) & 3;
1403 if (smask == 3)
1404 {
1405 infprintf (is, "%s??", sep);
1406 sep = ",";
1407 }
1408 else if (smask > 0)
1409 {
1410 infprintf (is, "%s%s", sep, mips_gpr_names[16]);
1411 if (smask > 1)
1412 infprintf (is, "-%s", mips_gpr_names[smask + 15]);
1413 sep = ",";
1414 }
1415
1416 if (uval & 1)
1417 {
1418 infprintf (is, "%s%s", sep, mips_gpr_names[31]);
1419 sep = ",";
1420 }
1421
1422 if (amask == 5 || amask == 6)
1423 {
1424 infprintf (is, "%s%s", sep, mips_fpr_names[0]);
1425 if (amask == 6)
1426 infprintf (is, "-%s", mips_fpr_names[1]);
1427 }
1428 }
1429 break;
1430
1431 case OP_SAVE_RESTORE_LIST:
1432 /* Should be handled by the caller due to extend behavior. */
1433 abort ();
1434
ab902481
RS		 1435 case OP_MDMX_IMM_REG:
1436 {
1437 unsigned int vsel;
794ac9d0 1438
ab902481
RS		 1439 vsel = uval >> 5;
1440 uval &= 31;
1441 if ((vsel & 0x10) == 0)
794ac9d0 1442 {
ab902481
RS		 1443 int fmt;
1444
1445 vsel &= 0x0f;
1446 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1447 if ((vsel & 1) == 0)
1448 break;
1449 print_reg (info, opcode, OP_REG_VEC, uval);
1450 infprintf (is, "[%d]", vsel >> 1);
794ac9d0 1451 }
ab902481
RS		 1452 else if ((vsel & 0x08) == 0)
1453 print_reg (info, opcode, OP_REG_VEC, uval);
1454 else
1455 infprintf (is, "0x%x", uval);
1456 }
1457 break;
794ac9d0 1458
ab902481
RS		 1459 case OP_REPEAT_PREV_REG:
1460 print_reg (info, opcode, state->last_reg_type, state->last_regno);
1461 break;
794ac9d0 1462
ab902481 1463 case OP_REPEAT_DEST_REG:
7361da2c
AB		 1464 print_reg (info, opcode, state->last_reg_type, state->dest_regno);
1465 break;
794ac9d0 1466
ab902481
RS		 1467 case OP_PC:
1468 infprintf (is, "$pc");
1469 break;
14daeee3 1470
25499ac7
MR		 1471 case OP_REG28:
1472 print_reg (info, opcode, OP_REG_GP, 28);
1473 break;
1474
14daeee3
RS		 1475 case OP_VU0_SUFFIX:
1476 case OP_VU0_MATCH_SUFFIX:
1477 print_vu0_channel (info, operand, uval);
1478 break;
4edbb8e3
CF		 1479
1480 case OP_IMM_INDEX:
1481 infprintf (is, "[%d]", uval);
1482 break;
1483
1484 case OP_REG_INDEX:
1485 infprintf (is, "[");
1486 print_reg (info, opcode, OP_REG_GP, uval);
1487 infprintf (is, "]");
1488 break;
ab902481
RS		 1489 }
1490}
794ac9d0 1491
7361da2c
AB		 1492/* Validate the arguments for INSN, which is described by OPCODE.
1493 Use DECODE_OPERAND to get the encoding of each operand. */
1494
1495static bfd_boolean
1496validate_insn_args (const struct mips_opcode *opcode,
1497 const struct mips_operand *(*decode_operand) (const char *),
1498 unsigned int insn)
1499{
1500 struct mips_print_arg_state state;
1501 const struct mips_operand *operand;
1502 const char *s;
1503 unsigned int uval;
1504
1505 init_print_arg_state (&state);
1506 for (s = opcode->args; *s; ++s)
1507 {
1508 switch (*s)
1509 {
1510 case ',':
1511 case '(':
1512 case ')':
1513 break;
1514
1515 case '#':
1516 ++s;
1517 break;
1518
1519 default:
1520 operand = decode_operand (s);
1521
1522 if (operand)
1523 {
1524 uval = mips_extract_operand (operand, insn);
1525 switch (operand->type)
1526 {
1527 case OP_REG:
1528 case OP_OPTIONAL_REG:
1529 {
1530 const struct mips_reg_operand *reg_op;
1531
1532 reg_op = (const struct mips_reg_operand *) operand;
1533 uval = mips_decode_reg_operand (reg_op, uval);
1534 mips_seen_register (&state, uval, reg_op->reg_type);
1535 }
1536 break;
1537
1538 case OP_SAME_RS_RT:
1539 {
1540 unsigned int reg1, reg2;
1541
1542 reg1 = uval & 31;
1543 reg2 = uval >> 5;
1544
1545 if (reg1 != reg2 || reg1 == 0)
1546 return FALSE;
1547 }
1548 break;
1549
1550 case OP_CHECK_PREV:
1551 {
1552 const struct mips_check_prev_operand *prev_op;
1553
1554 prev_op = (const struct mips_check_prev_operand *) operand;
1555
1556 if (!prev_op->zero_ok && uval == 0)
1557 return FALSE;
1558
1559 if (((prev_op->less_than_ok && uval < state.last_regno)
1560 || (prev_op->greater_than_ok && uval > state.last_regno)
1561 || (prev_op->equal_ok && uval == state.last_regno)))
1562 break;
1563
1564 return FALSE;
1565 }
1566
1567 case OP_NON_ZERO_REG:
1568 {
1569 if (uval == 0)
1570 return FALSE;
1571 }
1572 break;
1573
1574 case OP_INT:
1575 case OP_MAPPED_INT:
1576 case OP_MSB:
1577 case OP_REG_PAIR:
1578 case OP_PCREL:
1579 case OP_PERF_REG:
1580 case OP_ADDIUSP_INT:
1581 case OP_CLO_CLZ_DEST:
1582 case OP_LWM_SWM_LIST:
1583 case OP_ENTRY_EXIT_LIST:
1584 case OP_MDMX_IMM_REG:
1585 case OP_REPEAT_PREV_REG:
1586 case OP_REPEAT_DEST_REG:
1587 case OP_PC:
25499ac7 1588 case OP_REG28:
7361da2c
AB		 1589 case OP_VU0_SUFFIX:
1590 case OP_VU0_MATCH_SUFFIX:
1591 case OP_IMM_INDEX:
1592 case OP_REG_INDEX:
1593 break;
1594
1595 case OP_SAVE_RESTORE_LIST:
1596 /* Should be handled by the caller due to extend behavior. */
1597 abort ();
1598 }
1599 }
1600 if (*s == 'm' || *s == '+' || *s == '-')
1601 ++s;
1602 }
1603 }
1604 return TRUE;
1605}
1606
ab902481
RS		 1607/* Print the arguments for INSN, which is described by OPCODE.
1608 Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC
7361da2c
AB		 1609 as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL
1610 operand is for a branch or jump. */
af7ee8bf 1611
ab902481
RS		 1612static void
1613print_insn_args (struct disassemble_info *info,
1614 const struct mips_opcode *opcode,
1615 const struct mips_operand *(*decode_operand) (const char *),
7361da2c 1616 unsigned int insn, bfd_vma insn_pc, unsigned int length)
ab902481
RS		 1617{
1618 const fprintf_ftype infprintf = info->fprintf_func;
1619 void *is = info->stream;
1620 struct mips_print_arg_state state;
1621 const struct mips_operand *operand;
1622 const char *s;
794ac9d0 1623
ab902481
RS		 1624 init_print_arg_state (&state);
1625 for (s = opcode->args; *s; ++s)
1626 {
1627 switch (*s)
1628 {
1629 case ',':
1630 case '(':
1631 case ')':
1632 infprintf (is, "%c", *s);
794ac9d0
CD		 1633 break;
1634
14daeee3
RS		 1635 case '#':
1636 ++s;
1637 infprintf (is, "%c%c", *s, *s);
1638 break;
1639
ab902481
RS		 1640 default:
1641 operand = decode_operand (s);
1642 if (!operand)
fa7616a4 1643 {
ab902481
RS		 1644 /* xgettext:c-format */
1645 infprintf (is,
1646 _("# internal error, undefined operand in `%s %s'"),
1647 opcode->name, opcode->args);
1648 return;
1649 }
1650 if (operand->type == OP_REG
1651 && s[1] == ','
1652 && s[2] == 'H'
1653 && opcode->name[strlen (opcode->name) - 1] == '0')
1654 {
fdfb4752 1655 /* Coprocessor register 0 with sel field. */
ab902481
RS		 1656 const struct mips_cp0sel_name *n;
1657 unsigned int reg, sel;
1658
1659 reg = mips_extract_operand (operand, insn);
1660 s += 2;
1661 operand = decode_operand (s);
1662 sel = mips_extract_operand (operand, insn);
1663
1664 /* CP0 register including 'sel' code for mftc0, to be
1665 printed textually if known. If not known, print both
1666 CP0 register name and sel numerically since CP0 register
1667 with sel 0 may have a name unrelated to register being
1668 printed. */
1669 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
1670 mips_cp0sel_names_len,
1671 reg, sel);
1672 if (n != NULL)
1673 infprintf (is, "%s", n->name);
fa7616a4 1674 else
ab902481 1675 infprintf (is, "$%d,%d", reg, sel);
fa7616a4 1676 }
794ac9d0 1677 else
7361da2c
AB		 1678 {
1679 bfd_vma base_pc = insn_pc;
1680
1681 /* Adjust the PC relative base so that branch/jump insns use
1682 the following PC as the base but genuinely PC relative
1683 operands use the current PC. */
1684 if (operand->type == OP_PCREL)
1685 {
1686 const struct mips_pcrel_operand *pcrel_op;
1687
1688 pcrel_op = (const struct mips_pcrel_operand *) operand;
1689 /* The include_isa_bit flag is sufficient to distinguish
1690 branch/jump from other PC relative operands. */
1691 if (pcrel_op->include_isa_bit)
1692 base_pc += length;
1693 }
1694
1695 print_insn_arg (info, &state, opcode, operand, base_pc,
1696 mips_extract_operand (operand, insn));
1697 }
1698 if (*s == 'm' || *s == '+' || *s == '-')
ab902481 1699 ++s;
794ac9d0 1700 break;
af7ee8bf 1701 }
252b5132
RH		 1702 }
1703}
1704\f
252b5132
RH		 1705/* Print the mips instruction at address MEMADDR in debugged memory,
1706 on using INFO. Returns length of the instruction, in bytes, which is
aa5f19f2 1707 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
252b5132
RH		 1708 this is little-endian code. */
1709
1710static int
47b0e7ad 1711print_insn_mips (bfd_vma memaddr,
fc8c4fd1 1712 int word,
47b0e7ad 1713 struct disassemble_info *info)
252b5132 1714{
ab902481
RS		 1715#define GET_OP(insn, field) \
1716 (((insn) >> OP_SH_##field) & OP_MASK_##field)
fc8c4fd1
MR		 1717 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1718 const fprintf_ftype infprintf = info->fprintf_func;
47b0e7ad 1719 const struct mips_opcode *op;
b34976b6 1720 static bfd_boolean init = 0;
fc8c4fd1 1721 void *is = info->stream;
252b5132
RH		 1722
1723 /* Build a hash table to shorten the search time. */
1724 if (! init)
1725 {
1726 unsigned int i;
1727
1728 for (i = 0; i <= OP_MASK_OP; i++)
1729 {
1730 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1731 {
986e18a5 1732 if (op->pinfo == INSN_MACRO
9e836e3d 1733 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
252b5132 1734 continue;
fc8c4fd1 1735 if (i == GET_OP (op->match, OP))
252b5132
RH		 1736 {
1737 mips_hash[i] = op;
1738 break;
1739 }
1740 }
7f6621cd 1741 }
252b5132
RH		 1742
1743 init = 1;
1744 }
1745
aa5f19f2 1746 info->bytes_per_chunk = INSNLEN;
252b5132 1747 info->display_endian = info->endian;
9bb28706
CD		 1748 info->insn_info_valid = 1;
1749 info->branch_delay_insns = 0;
def7143b 1750 info->data_size = 0;
9bb28706
CD		 1751 info->insn_type = dis_nonbranch;
1752 info->target = 0;
1753 info->target2 = 0;
252b5132 1754
fc8c4fd1 1755 op = mips_hash[GET_OP (word, OP)];
252b5132
RH		 1756 if (op != NULL)
1757 {
1758 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1759 {
43e65147 1760 if (op->pinfo != INSN_MACRO
9e836e3d 1761 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
986e18a5 1762 && (word & op->mask) == op->match)
252b5132 1763 {
7361da2c 1764 /* We always disassemble the jalx instruction, except for MIPS r6. */
d301a56b 1765 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
7361da2c
AB		 1766 && (strcmp (op->name, "jalx")
1767 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6
1768 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6))
252b5132
RH		 1769 continue;
1770
9bb28706
CD		 1771 /* Figure out instruction type and branch delay information. */
1772 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1773 {
fc76e730 1774 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0)
9bb28706
CD		 1775 info->insn_type = dis_jsr;
1776 else
1777 info->insn_type = dis_branch;
1778 info->branch_delay_insns = 1;
1779 }
1780 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1781 | INSN_COND_BRANCH_LIKELY)) != 0)
1782 {
c680e7f6 1783 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
9bb28706
CD		 1784 info->insn_type = dis_condjsr;
1785 else
1786 info->insn_type = dis_condbranch;
1787 info->branch_delay_insns = 1;
1788 }
1789 else if ((op->pinfo & (INSN_STORE_MEMORY
67dc82bc 1790 | INSN_LOAD_MEMORY)) != 0)
9bb28706
CD		 1791 info->insn_type = dis_dref;
1792
7361da2c
AB		 1793 if (!validate_insn_args (op, decode_mips_operand, word))
1794 continue;
1795
fc8c4fd1 1796 infprintf (is, "%s", op->name);
14daeee3
RS		 1797 if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
1798 {
1799 unsigned int uval;
1800
1801 infprintf (is, ".");
1802 uval = mips_extract_operand (&mips_vu0_channel_mask, word);
1803 print_vu0_channel (info, &mips_vu0_channel_mask, uval);
1804 }
252b5132 1805
ab902481 1806 if (op->args[0])
252b5132 1807 {
fc8c4fd1 1808 infprintf (is, "\t");
ab902481 1809 print_insn_args (info, op, decode_mips_operand, word,
7361da2c 1810 memaddr, 4);
252b5132
RH		 1811 }
1812
aa5f19f2 1813 return INSNLEN;
252b5132
RH		 1814 }
1815 }
1816 }
fc8c4fd1 1817#undef GET_OP
252b5132
RH		 1818
1819 /* Handle undefined instructions. */
9bb28706 1820 info->insn_type = dis_noninsn;
fc8c4fd1 1821 infprintf (is, "0x%x", word);
aa5f19f2 1822 return INSNLEN;
252b5132 1823}
aa5f19f2 1824\f
252b5132
RH		 1825/* Disassemble an operand for a mips16 instruction. */
1826
1827static void
c3c07478
RS		 1828print_mips16_insn_arg (struct disassemble_info *info,
1829 struct mips_print_arg_state *state,
1830 const struct mips_opcode *opcode,
1831 char type, bfd_vma memaddr,
1832 unsigned insn, bfd_boolean use_extend,
1833 unsigned extend, bfd_boolean is_offset)
252b5132 1834{
fc8c4fd1
MR		 1835 const fprintf_ftype infprintf = info->fprintf_func;
1836 void *is = info->stream;
c3c07478 1837 const struct mips_operand *operand, *ext_operand;
bdd15286 1838 unsigned short ext_size;
c3c07478
RS		 1839 unsigned int uval;
1840 bfd_vma baseaddr;
1841
1842 if (!use_extend)
1843 extend = 0;
fc8c4fd1 1844
252b5132
RH		 1845 switch (type)
1846 {
1847 case ',':
1848 case '(':
1849 case ')':
fc8c4fd1 1850 infprintf (is, "%c", type);
252b5132
RH		 1851 break;
1852
c3c07478
RS		 1853 default:
1854 operand = decode_mips16_operand (type, FALSE);
1855 if (!operand)
1856 {
1857 /* xgettext:c-format */
1858 infprintf (is, _("# internal error, undefined operand in `%s %s'"),
1859 opcode->name, opcode->args);
1860 return;
1861 }
252b5132 1862
c3c07478
RS		 1863 if (operand->type == OP_SAVE_RESTORE_LIST)
1864 {
5f5c6e03 1865 /* Handle this case here because of the complex interaction
c3c07478
RS		 1866 with the EXTEND opcode. */
1867 unsigned int amask, nargs, nstatics, nsreg, smask, frame_size, i, j;
1868 const char *sep;
252b5132 1869
c3c07478
RS		 1870 amask = extend & 0xf;
1871 if (amask == MIPS16_ALL_ARGS)
1872 {
1873 nargs = 4;
1874 nstatics = 0;
1875 }
1876 else if (amask == MIPS16_ALL_STATICS)
1877 {
1878 nargs = 0;
1879 nstatics = 4;
1880 }
1881 else
1882 {
1883 nargs = amask >> 2;
1884 nstatics = amask & 3;
1885 }
252b5132 1886
c3c07478
RS		 1887 sep = "";
1888 if (nargs > 0)
1889 {
1890 infprintf (is, "%s", mips_gpr_names[4]);
1891 if (nargs > 1)
1892 infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]);
1893 sep = ",";
1894 }
252b5132 1895
c3c07478
RS		 1896 frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8;
1897 if (frame_size == 0 && !use_extend)
1898 frame_size = 128;
1899 infprintf (is, "%s%d", sep, frame_size);
1900
1901 if (insn & 0x40) /* $ra */
1902 infprintf (is, ",%s", mips_gpr_names[31]);
1903
1904 nsreg = (extend >> 8) & 0x7;
1905 smask = 0;
1906 if (insn & 0x20) /* $s0 */
1907 smask |= 1 << 0;
1908 if (insn & 0x10) /* $s1 */
1909 smask |= 1 << 1;
1910 if (nsreg > 0) /* $s2-$s8 */
1911 smask |= ((1 << nsreg) - 1) << 2;
1912
1913 for (i = 0; i < 9; i++)
1914 if (smask & (1 << i))
252b5132 1915 {
c3c07478
RS		 1916 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1917 /* Skip over string of set bits. */
1918 for (j = i; smask & (2 << j); j++)
1919 continue;
1920 if (j > i)
1921 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1922 i = j + 1;
252b5132 1923 }
c3c07478
RS		 1924 /* Statics $ax - $a3. */
1925 if (nstatics == 1)
1926 infprintf (is, ",%s", mips_gpr_names[7]);
1927 else if (nstatics > 0)
1928 infprintf (is, ",%s-%s",
1929 mips_gpr_names[7 - nstatics + 1],
1930 mips_gpr_names[7]);
1931 break;
1932 }
252b5132 1933
c3c07478
RS		 1934 if (is_offset && operand->type == OP_INT)
1935 {
1936 const struct mips_int_operand *int_op;
252b5132 1937
c3c07478
RS		 1938 int_op = (const struct mips_int_operand *) operand;
1939 info->insn_type = dis_dref;
1940 info->data_size = 1 << int_op->shift;
1941 }
252b5132 1942
bdd15286
MR		 1943 ext_size = 0;
1944 if (use_extend)
c3c07478 1945 {
bdd15286 1946 ext_operand = decode_mips16_operand (type, TRUE);
25499ac7
MR		 1947 if (ext_operand != operand
1948 || (operand->type == OP_INT && operand->lsb == 0
1949 && mips_opcode_32bit_p (opcode)))
c3c07478 1950 {
bdd15286
MR		 1951 ext_size = ext_operand->size;
1952 operand = ext_operand;
c3c07478
RS		 1953 }
1954 }
bdd15286
MR		 1955 if (operand->size == 26)
1956 uval = ((extend & 0x1f) << 21) | ((extend & 0x3e0) << 11) | insn;
25499ac7 1957 else if (ext_size == 16 || ext_size == 9)
bdd15286
MR		 1958 uval = ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f);
1959 else if (ext_size == 15)
1960 uval = ((extend & 0xf) << 11) | (extend & 0x7f0) | (insn & 0xf);
1961 else if (ext_size == 6)
1962 uval = ((extend >> 6) & 0x1f) | (extend & 0x20);
1963 else
1964 uval = mips_extract_operand (operand, (extend << 16) | insn);
25499ac7
MR		 1965 if (ext_size == 9)
1966 uval &= (1U << ext_size) - 1;
c3c07478
RS		 1967
1968 baseaddr = memaddr + 2;
1969 if (operand->type == OP_PCREL)
1970 {
1971 const struct mips_pcrel_operand *pcrel_op;
1972
1973 pcrel_op = (const struct mips_pcrel_operand *) operand;
1974 if (!pcrel_op->include_isa_bit && use_extend)
1975 baseaddr = memaddr - 2;
1976 else if (!pcrel_op->include_isa_bit)
39f66f3a
MR		 1977 {
1978 bfd_byte buffer[2];
1979
1980 /* If this instruction is in the delay slot of a JAL/JALX
1981 instruction, the base address is the address of the
1982 JAL/JALX instruction. If it is in the delay slot of
1983 a JR/JALR instruction, the base address is the address
1984 of the JR/JALR instruction. This test is unreliable:
1985 we have no way of knowing whether the previous word is
1986 instruction or data. */
1987 if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0
1988 && (((info->endian == BFD_ENDIAN_BIG
1989 ? bfd_getb16 (buffer)
1990 : bfd_getl16 (buffer))
1991 & 0xf800) == 0x1800))
1992 baseaddr = memaddr - 4;
1993 else if (info->read_memory_func (memaddr - 2, buffer, 2,
1994 info) == 0
1995 && (((info->endian == BFD_ENDIAN_BIG
1996 ? bfd_getb16 (buffer)
1997 : bfd_getl16 (buffer))
1998 & 0xf89f) == 0xe800)
1999 && (((info->endian == BFD_ENDIAN_BIG
2000 ? bfd_getb16 (buffer)
2001 : bfd_getl16 (buffer))
2002 & 0x0060) != 0x0060))
2003 baseaddr = memaddr - 2;
2004 else
2005 baseaddr = memaddr;
2006 }
c3c07478 2007 }
0499d65b 2008
6d075bce 2009 print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval);
0499d65b 2010 break;
252b5132
RH		 2011 }
2012}
640c0ccd 2013
1bbce132
MR		 2014
2015/* Check if the given address is the last word of a MIPS16 PLT entry.
2016 This word is data and depending on the value it may interfere with
2017 disassembly of further PLT entries. We make use of the fact PLT
2018 symbols are marked BSF_SYNTHETIC. */
2019static bfd_boolean
2020is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr)
2021{
2022 if (info->symbols
2023 && info->symbols[0]
2024 && (info->symbols[0]->flags & BSF_SYNTHETIC)
2025 && addr == bfd_asymbol_value (info->symbols[0]) + 12)
2026 return TRUE;
2027
2028 return FALSE;
2029}
2030
7fd53920
MR		 2031/* Whether none, a 32-bit or a 16-bit instruction match has been done. */
2032
2033enum match_kind
2034{
2035 MATCH_NONE,
2036 MATCH_FULL,
2037 MATCH_SHORT
2038};
2039
47b0e7ad
NC		 2040/* Disassemble mips16 instructions. */
2041
2042static int
2043print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
2044{
fc8c4fd1 2045 const fprintf_ftype infprintf = info->fprintf_func;
47b0e7ad 2046 int status;
1bbce132 2047 bfd_byte buffer[4];
47b0e7ad 2048 const struct mips_opcode *op, *opend;
c3c07478 2049 struct mips_print_arg_state state;
fc8c4fd1 2050 void *is = info->stream;
7fd53920 2051 bfd_boolean have_second;
25499ac7 2052 bfd_boolean extend_only;
7fd53920
MR		 2053 unsigned int second;
2054 unsigned int first;
2055 unsigned int full;
47b0e7ad
NC		 2056
2057 info->bytes_per_chunk = 2;
2058 info->display_endian = info->endian;
2059 info->insn_info_valid = 1;
2060 info->branch_delay_insns = 0;
2061 info->data_size = 0;
47b0e7ad
NC		 2062 info->target = 0;
2063 info->target2 = 0;
2064
c3c07478
RS		 2065#define GET_OP(insn, field) \
2066 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
1bbce132
MR		 2067 /* Decode PLT entry's GOT slot address word. */
2068 if (is_mips16_plt_tail (info, memaddr))
2069 {
2070 info->insn_type = dis_noninsn;
2071 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
2072 if (status == 0)
2073 {
2074 unsigned int gotslot;
2075
2076 if (info->endian == BFD_ENDIAN_BIG)
2077 gotslot = bfd_getb32 (buffer);
2078 else
2079 gotslot = bfd_getl32 (buffer);
2080 infprintf (is, ".word\t0x%x", gotslot);
2081
2082 return 4;
2083 }
2084 }
2085 else
2086 {
2087 info->insn_type = dis_nonbranch;
2088 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2089 }
47b0e7ad
NC		 2090 if (status != 0)
2091 {
2092 (*info->memory_error_func) (status, memaddr, info);
2093 return -1;
2094 }
2095
25499ac7
MR		 2096 extend_only = FALSE;
2097
47b0e7ad 2098 if (info->endian == BFD_ENDIAN_BIG)
7fd53920 2099 first = bfd_getb16 (buffer);
47b0e7ad 2100 else
7fd53920 2101 first = bfd_getl16 (buffer);
47b0e7ad 2102
7fd53920
MR		 2103 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2104 if (status == 0)
47b0e7ad 2105 {
7fd53920 2106 have_second = TRUE;
47b0e7ad 2107 if (info->endian == BFD_ENDIAN_BIG)
7fd53920 2108 second = bfd_getb16 (buffer);
47b0e7ad 2109 else
7fd53920
MR		 2110 second = bfd_getl16 (buffer);
2111 full = (first << 16) | second;
2112 }
2113 else
2114 {
2115 have_second = FALSE;
2116 second = 0;
2117 full = first;
47b0e7ad
NC		 2118 }
2119
2120 /* FIXME: Should probably use a hash table on the major opcode here. */
2121
2122 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2123 for (op = mips16_opcodes; op < opend; op++)
2124 {
7fd53920 2125 enum match_kind match;
47b0e7ad 2126
11dd08e9
MR		 2127 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor))
2128 continue;
2129
7fd53920
MR		 2130 if (op->pinfo == INSN_MACRO
2131 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
2132 match = MATCH_NONE;
2133 else if (mips_opcode_32bit_p (op))
2134 {
2135 if (have_second
2136 && (full & op->mask) == op->match)
2137 match = MATCH_FULL;
2138 else
2139 match = MATCH_NONE;
2140 }
2141 else if ((first & op->mask) == op->match)
2142 {
2143 match = MATCH_SHORT;
2144 second = 0;
2145 full = first;
2146 }
2147 else if ((first & 0xf800) == 0xf000
2148 && have_second
25499ac7 2149 && !extend_only
7fd53920 2150 && (second & op->mask) == op->match)
25499ac7
MR		 2151 {
2152 if (op->pinfo2 & INSN2_SHORT_ONLY)
2153 {
2154 match = MATCH_NONE;
2155 extend_only = TRUE;
2156 }
2157 else
2158 match = MATCH_FULL;
2159 }
7fd53920
MR		 2160 else
2161 match = MATCH_NONE;
47b0e7ad 2162
7fd53920
MR		 2163 if (match != MATCH_NONE)
2164 {
2165 const char *s;
47b0e7ad 2166
fc8c4fd1 2167 infprintf (is, "%s", op->name);
47b0e7ad 2168 if (op->args[0] != '\0')
fc8c4fd1 2169 infprintf (is, "\t");
47b0e7ad 2170
c3c07478 2171 init_print_arg_state (&state);
47b0e7ad
NC		 2172 for (s = op->args; *s != '\0'; s++)
2173 {
2174 if (*s == ','
2175 && s[1] == 'w'
7fd53920 2176 && GET_OP (full, RX) == GET_OP (full, RY))
47b0e7ad
NC		 2177 {
2178 /* Skip the register and the comma. */
2179 ++s;
2180 continue;
2181 }
2182 if (*s == ','
2183 && s[1] == 'v'
7fd53920 2184 && GET_OP (full, RZ) == GET_OP (full, RX))
47b0e7ad
NC		 2185 {
2186 /* Skip the register and the comma. */
2187 ++s;
2188 continue;
2189 }
25499ac7
MR		 2190 if (s[0] == 'N'
2191 && s[1] == ','
2192 && s[2] == 'O'
2193 && op->name[strlen (op->name) - 1] == '0')
7fd53920 2194 {
25499ac7
MR		 2195 /* Coprocessor register 0 with sel field. */
2196 const struct mips_cp0sel_name *n;
2197 const struct mips_operand *operand;
2198 unsigned int reg, sel;
2199
2200 operand = decode_mips16_operand (*s, TRUE);
2201 reg = mips_extract_operand (operand, (first << 16) | second);
2202 s += 2;
2203 operand = decode_mips16_operand (*s, TRUE);
2204 sel = mips_extract_operand (operand, (first << 16) | second);
2205
2206 /* CP0 register including 'sel' code for mftc0, to be
2207 printed textually if known. If not known, print both
2208 CP0 register name and sel numerically since CP0 register
2209 with sel 0 may have a name unrelated to register being
2210 printed. */
2211 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
2212 mips_cp0sel_names_len,
2213 reg, sel);
2214 if (n != NULL)
2215 infprintf (is, "%s", n->name);
2216 else
2217 infprintf (is, "$%d,%d", reg, sel);
7fd53920 2218 }
25499ac7
MR		 2219 else
2220 switch (match)
2221 {
2222 case MATCH_FULL:
2223 print_mips16_insn_arg (info, &state, op, *s, memaddr + 2,
2224 second, TRUE, first, s[1] == '(');
2225 break;
2226 case MATCH_SHORT:
2227 print_mips16_insn_arg (info, &state, op, *s, memaddr,
2228 first, FALSE, 0, s[1] == '(');
2229 break;
2230 case MATCH_NONE: /* Stop the compiler complaining. */
2231 break;
2232 }
47b0e7ad
NC		 2233 }
2234
9a2c7088 2235 /* Figure out branch instruction type and delay slot information. */
47b0e7ad 2236 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
9a2c7088 2237 info->branch_delay_insns = 1;
26545944
RS		 2238 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2239 || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0)
47b0e7ad 2240 {
9a2c7088
MR		 2241 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2242 info->insn_type = dis_jsr;
2243 else
47b0e7ad
NC		 2244 info->insn_type = dis_branch;
2245 }
26545944 2246 else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0)
9a2c7088 2247 info->insn_type = dis_condbranch;
47b0e7ad 2248
7fd53920 2249 return match == MATCH_FULL ? 4 : 2;
47b0e7ad
NC		 2250 }
2251 }
fc8c4fd1 2252#undef GET_OP
47b0e7ad 2253
7fd53920 2254 infprintf (is, "0x%x", first);
47b0e7ad
NC		 2255 info->insn_type = dis_noninsn;
2256
7fd53920 2257 return 2;
47b0e7ad
NC		 2258}
2259
df58fc94
RS		 2260/* Disassemble microMIPS instructions. */
2261
2262static int
2263print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
2264{
0c7533d3 2265 const fprintf_ftype infprintf = info->fprintf_func;
df58fc94 2266 const struct mips_opcode *op, *opend;
df58fc94 2267 void *is = info->stream;
df58fc94 2268 bfd_byte buffer[2];
ab902481
RS		 2269 unsigned int higher;
2270 unsigned int length;
df58fc94 2271 int status;
ab902481 2272 unsigned int insn;
df58fc94
RS		 2273
2274 info->bytes_per_chunk = 2;
2275 info->display_endian = info->endian;
2276 info->insn_info_valid = 1;
2277 info->branch_delay_insns = 0;
2278 info->data_size = 0;
2279 info->insn_type = dis_nonbranch;
2280 info->target = 0;
2281 info->target2 = 0;
2282
2283 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2284 if (status != 0)
2285 {
2286 (*info->memory_error_func) (status, memaddr, info);
2287 return -1;
2288 }
2289
2290 length = 2;
2291
2292 if (info->endian == BFD_ENDIAN_BIG)
2293 insn = bfd_getb16 (buffer);
2294 else
2295 insn = bfd_getl16 (buffer);
2296
100b4f2e 2297 if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
df58fc94
RS		 2298 {
2299 /* This is a 32-bit microMIPS instruction. */
2300 higher = insn;
2301
2302 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2303 if (status != 0)
2304 {
0c7533d3 2305 infprintf (is, "micromips 0x%x", higher);
df58fc94
RS		 2306 (*info->memory_error_func) (status, memaddr + 2, info);
2307 return -1;
2308 }
2309
2310 if (info->endian == BFD_ENDIAN_BIG)
2311 insn = bfd_getb16 (buffer);
2312 else
2313 insn = bfd_getl16 (buffer);
2314
2315 insn = insn | (higher << 16);
2316
2317 length += 2;
2318 }
2319
2320 /* FIXME: Should probably use a hash table on the major opcode here. */
2321
df58fc94
RS		 2322 opend = micromips_opcodes + bfd_micromips_num_opcodes;
2323 for (op = micromips_opcodes; op < opend; op++)
2324 {
2325 if (op->pinfo != INSN_MACRO
2326 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2327 && (insn & op->mask) == op->match
2328 && ((length == 2 && (op->mask & 0xffff0000) == 0)
2329 || (length == 4 && (op->mask & 0xffff0000) != 0)))
2330 {
7361da2c
AB		 2331 if (!validate_insn_args (op, decode_micromips_operand, insn))
2332 continue;
2333
0c7533d3 2334 infprintf (is, "%s", op->name);
df58fc94 2335
ab902481 2336 if (op->args[0])
df58fc94 2337 {
ab902481
RS		 2338 infprintf (is, "\t");
2339 print_insn_args (info, op, decode_micromips_operand, insn,
7361da2c 2340 memaddr + 1, length);
df58fc94
RS		 2341 }
2342
2343 /* Figure out instruction type and branch delay information. */
2344 if ((op->pinfo
2345 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
2346 info->branch_delay_insns = 1;
2347 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
2348 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
2349 {
fc76e730 2350 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0)
df58fc94
RS		 2351 info->insn_type = dis_jsr;
2352 else
2353 info->insn_type = dis_branch;
2354 }
2355 else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
2356 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
2357 {
2358 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2359 info->insn_type = dis_condjsr;
2360 else
2361 info->insn_type = dis_condbranch;
2362 }
2363 else if ((op->pinfo
67dc82bc 2364 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0)
df58fc94
RS		 2365 info->insn_type = dis_dref;
2366
2367 return length;
2368 }
2369 }
df58fc94 2370
0c7533d3 2371 infprintf (is, "0x%x", insn);
df58fc94
RS		 2372 info->insn_type = dis_noninsn;
2373
2374 return length;
2375}
2376
2377/* Return 1 if a symbol associated with the location being disassembled
1401d2fe
MR		 2378 indicates a compressed mode, either MIPS16 or microMIPS, according to
2379 MICROMIPS_P. We iterate over all the symbols at the address being
2380 considered assuming if at least one of them indicates code compression,
2381 then such code has been genuinely produced here (other symbols could
2382 have been derived from function symbols defined elsewhere or could
2383 define data). Otherwise, return 0. */
df58fc94
RS		 2384
2385static bfd_boolean
1401d2fe 2386is_compressed_mode_p (struct disassemble_info *info, bfd_boolean micromips_p)
df58fc94 2387{
df58fc94 2388 int i;
1bbce132
MR		 2389 int l;
2390
2391 for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++)
2392 if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0
1401d2fe 2393 && ((!micromips_p
1bbce132 2394 && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i))
1401d2fe 2395 || (micromips_p
1bbce132
MR		 2396 && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i))))
2397 return 1;
2398 else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour
2399 && info->symtab[i]->section == info->section)
2400 {
2401 elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i];
1401d2fe 2402 if ((!micromips_p
1bbce132 2403 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
1401d2fe 2404 || (micromips_p
1bbce132
MR		 2405 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
2406 return 1;
2407 }
df58fc94
RS		 2408
2409 return 0;
2410}
2411
47b0e7ad
NC		 2412/* In an environment where we do not know the symbol type of the
2413 instruction we are forced to assume that the low order bit of the
2414 instructions' address may mark it as a mips16 instruction. If we
2415 are single stepping, or the pc is within the disassembled function,
2416 this works. Otherwise, we need a clue. Sometimes. */
2417
2418static int
2419_print_insn_mips (bfd_vma memaddr,
2420 struct disassemble_info *info,
2421 enum bfd_endian endianness)
2422{
2423 bfd_byte buffer[INSNLEN];
2424 int status;
2425
2426 set_default_mips_dis_options (info);
2427 parse_mips_dis_options (info->disassembler_options);
2428
df58fc94
RS		 2429 if (info->mach == bfd_mach_mips16)
2430 return print_insn_mips16 (memaddr, info);
2431 if (info->mach == bfd_mach_mips_micromips)
2432 return print_insn_micromips (memaddr, info);
2433
47b0e7ad 2434#if 1
df58fc94 2435 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */
47b0e7ad
NC		 2436 /* Only a few tools will work this way. */
2437 if (memaddr & 0x01)
1401d2fe
MR		 2438 {
2439 if (micromips_ase)
2440 return print_insn_micromips (memaddr, info);
2441 else
2442 return print_insn_mips16 (memaddr, info);
2443 }
47b0e7ad
NC		 2444#endif
2445
2446#if SYMTAB_AVAILABLE
1401d2fe
MR		 2447 if (is_compressed_mode_p (info, TRUE))
2448 return print_insn_micromips (memaddr, info);
2449 if (is_compressed_mode_p (info, FALSE))
2450 return print_insn_mips16 (memaddr, info);
47b0e7ad
NC		 2451#endif
2452
2453 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2454 if (status == 0)
2455 {
fc8c4fd1 2456 int insn;
47b0e7ad
NC		 2457
2458 if (endianness == BFD_ENDIAN_BIG)
fc8c4fd1 2459 insn = bfd_getb32 (buffer);
47b0e7ad 2460 else
fc8c4fd1 2461 insn = bfd_getl32 (buffer);
47b0e7ad
NC		 2462
2463 return print_insn_mips (memaddr, insn, info);
2464 }
2465 else
2466 {
2467 (*info->memory_error_func) (status, memaddr, info);
2468 return -1;
2469 }
2470}
2471
2472int
2473print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2474{
2475 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2476}
2477
2478int
2479print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2480{
2481 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2482}
2483\f
640c0ccd 2484void
47b0e7ad 2485print_mips_disassembler_options (FILE *stream)
640c0ccd 2486{
4a9a3c54 2487 unsigned int i;
640c0ccd
CD		 2488
2489 fprintf (stream, _("\n\
2490The following MIPS specific disassembler options are supported for use\n\
2491with the -M switch (multiple options should be separated by commas):\n"));
2492
0348fd79
MR		 2493 fprintf (stream, _("\n\
2494 no-aliases Use canonical instruction forms.\n"));
2495
4edbb8e3 2496 fprintf (stream, _("\n\
6725647c 2497 msa Recognize MSA instructions.\n"));
4edbb8e3 2498
b015e599 2499 fprintf (stream, _("\n\
6725647c 2500 virt Recognize the virtualization ASE instructions.\n"));
b015e599 2501
7d64c587 2502 fprintf (stream, _("\n\
6725647c
MR		 2503 xpa Recognize the eXtended Physical Address (XPA)\n\
2504 ASE instructions.\n"));
7d64c587 2505
640c0ccd 2506 fprintf (stream, _("\n\
6725647c 2507 gpr-names=ABI Print GPR names according to specified ABI.\n\
640c0ccd
CD		 2508 Default: based on binary being disassembled.\n"));
2509
2510 fprintf (stream, _("\n\
2511 fpr-names=ABI Print FPR names according to specified ABI.\n\
2512 Default: numeric.\n"));
2513
2514 fprintf (stream, _("\n\
2515 cp0-names=ARCH Print CP0 register names according to\n\
2516 specified architecture.\n\
2517 Default: based on binary being disassembled.\n"));
2518
af7ee8bf
CD		 2519 fprintf (stream, _("\n\
2520 hwr-names=ARCH Print HWR names according to specified \n\
6725647c 2521 architecture.\n\
af7ee8bf
CD		 2522 Default: based on binary being disassembled.\n"));
2523
640c0ccd
CD		 2524 fprintf (stream, _("\n\
2525 reg-names=ABI Print GPR and FPR names according to\n\
2526 specified ABI.\n"));
2527
2528 fprintf (stream, _("\n\
af7ee8bf 2529 reg-names=ARCH Print CP0 register and HWR names according to\n\
640c0ccd
CD		 2530 specified architecture.\n"));
2531
2532 fprintf (stream, _("\n\
2533 For the options above, the following values are supported for \"ABI\":\n\
2534 "));
4a9a3c54 2535 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
640c0ccd
CD		 2536 fprintf (stream, " %s", mips_abi_choices[i].name);
2537 fprintf (stream, _("\n"));
2538
2539 fprintf (stream, _("\n\
2540 For the options above, The following values are supported for \"ARCH\":\n\
2541 "));
4a9a3c54 2542 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
640c0ccd
CD		 2543 if (*mips_arch_choices[i].name != '\0')
2544 fprintf (stream, " %s", mips_arch_choices[i].name);
2545 fprintf (stream, _("\n"));
2546
2547 fprintf (stream, _("\n"));
2548}
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