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4162bb66 1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
73589c9d 2/* Instruction building/extraction support for or1k. -*- C -*-
87e6d782 3
47b0e7ad
NC
4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
5 - the resultant file is machine generated, cgen-ibld.in isn't
87e6d782 6
219d1afa 7 Copyright (C) 1996-2018 Free Software Foundation, Inc.
87e6d782 8
9b201bb5 9 This file is part of libopcodes.
87e6d782 10
9b201bb5 11 This library is free software; you can redistribute it and/or modify
47b0e7ad 12 it under the terms of the GNU General Public License as published by
9b201bb5 13 the Free Software Foundation; either version 3, or (at your option)
47b0e7ad 14 any later version.
87e6d782 15
9b201bb5
NC
16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
87e6d782 20
47b0e7ad
NC
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
87e6d782
NC
24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
87e6d782
NC
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
73589c9d
CS
34#include "or1k-desc.h"
35#include "or1k-opc.h"
fe8afbc4 36#include "cgen/basic-modes.h"
87e6d782 37#include "opintl.h"
37111cc7 38#include "safe-ctype.h"
87e6d782 39
47b0e7ad 40#undef min
87e6d782 41#define min(a,b) ((a) < (b) ? (a) : (b))
47b0e7ad 42#undef max
87e6d782
NC
43#define max(a,b) ((a) > (b) ? (a) : (b))
44
45/* Used by the ifield rtx function. */
46#define FLD(f) (fields->f)
47
48static const char * insert_normal
ffead7ae
MM
49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
87e6d782 51static const char * insert_insn_normal
ffead7ae
MM
52 (CGEN_CPU_DESC, const CGEN_INSN *,
53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
87e6d782 54static int extract_normal
ffead7ae
MM
55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
56 unsigned int, unsigned int, unsigned int, unsigned int,
57 unsigned int, unsigned int, bfd_vma, long *);
87e6d782 58static int extract_insn_normal
ffead7ae
MM
59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 61#if CGEN_INT_INSN_P
87e6d782 62static void put_insn_int_value
ffead7ae 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
0e2ee3ca
NC
64#endif
65#if ! CGEN_INT_INSN_P
66static CGEN_INLINE void insert_1
ffead7ae 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
0e2ee3ca 68static CGEN_INLINE int fill_cache
ffead7ae 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
0e2ee3ca 70static CGEN_INLINE long extract_1
ffead7ae 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
0e2ee3ca 72#endif
87e6d782
NC
73\f
74/* Operand insertion. */
75
76#if ! CGEN_INT_INSN_P
77
78/* Subroutine of insert_normal. */
79
80static CGEN_INLINE void
ffead7ae
MM
81insert_1 (CGEN_CPU_DESC cd,
82 unsigned long value,
83 int start,
84 int length,
85 int word_length,
86 unsigned char *bufp)
87e6d782
NC
87{
88 unsigned long x,mask;
89 int shift;
87e6d782 90
0e2ee3ca 91 x = cgen_get_insn_value (cd, bufp, word_length);
87e6d782
NC
92
93 /* Written this way to avoid undefined behaviour. */
94 mask = (((1L << (length - 1)) - 1) << 1) | 1;
95 if (CGEN_INSN_LSB0_P)
96 shift = (start + 1) - length;
97 else
98 shift = (word_length - (start + length));
99 x = (x & ~(mask << shift)) | ((value & mask) << shift);
100
0e2ee3ca 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
87e6d782
NC
102}
103
104#endif /* ! CGEN_INT_INSN_P */
105
106/* Default insertion routine.
107
108 ATTRS is a mask of the boolean attributes.
109 WORD_OFFSET is the offset in bits from the start of the insn of the value.
110 WORD_LENGTH is the length of the word in bits in which the value resides.
111 START is the starting bit number in the word, architecture origin.
112 LENGTH is the length of VALUE in bits.
113 TOTAL_LENGTH is the total length of the insn in bits.
114
115 The result is an error message or NULL if success. */
116
117/* ??? This duplicates functionality with bfd's howto table and
118 bfd_install_relocation. */
119/* ??? This doesn't handle bfd_vma's. Create another function when
120 necessary. */
121
122static const char *
ffead7ae
MM
123insert_normal (CGEN_CPU_DESC cd,
124 long value,
125 unsigned int attrs,
126 unsigned int word_offset,
127 unsigned int start,
128 unsigned int length,
129 unsigned int word_length,
130 unsigned int total_length,
131 CGEN_INSN_BYTES_PTR buffer)
87e6d782
NC
132{
133 static char errbuf[100];
134 /* Written this way to avoid undefined behaviour. */
135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
136
137 /* If LENGTH is zero, this operand doesn't contribute to the value. */
138 if (length == 0)
139 return NULL;
140
b7cd1872 141 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
142 abort ();
143
144 /* For architectures with insns smaller than the base-insn-bitsize,
145 word_length may be too big. */
146 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
147 {
148 if (word_offset == 0
149 && word_length > total_length)
150 word_length = total_length;
151 }
152
153 /* Ensure VALUE will fit. */
fc7bc883
RH
154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
155 {
156 long minval = - (1L << (length - 1));
157 unsigned long maxval = mask;
43e65147 158
fc7bc883
RH
159 if ((value > 0 && (unsigned long) value > maxval)
160 || value < minval)
161 {
162 /* xgettext:c-format */
163 sprintf (errbuf,
164 _("operand out of range (%ld not between %ld and %lu)"),
165 value, minval, maxval);
166 return errbuf;
167 }
168 }
169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
87e6d782
NC
170 {
171 unsigned long maxval = mask;
ed963e2d
NC
172 unsigned long val = (unsigned long) value;
173
174 /* For hosts with a word size > 32 check to see if value has been sign
175 extended beyond 32 bits. If so then ignore these higher sign bits
176 as the user is attempting to store a 32-bit signed value into an
177 unsigned 32-bit field which is allowed. */
178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
179 val &= 0xFFFFFFFF;
180
181 if (val > maxval)
87e6d782
NC
182 {
183 /* xgettext:c-format */
184 sprintf (errbuf,
ed963e2d
NC
185 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
186 val, maxval);
87e6d782
NC
187 return errbuf;
188 }
189 }
190 else
191 {
192 if (! cgen_signed_overflow_ok_p (cd))
193 {
194 long minval = - (1L << (length - 1));
195 long maxval = (1L << (length - 1)) - 1;
43e65147 196
87e6d782
NC
197 if (value < minval || value > maxval)
198 {
199 sprintf
200 /* xgettext:c-format */
201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
202 value, minval, maxval);
203 return errbuf;
204 }
205 }
206 }
207
208#if CGEN_INT_INSN_P
209
210 {
a143b004 211 int shift_within_word, shift_to_word, shift;
87e6d782 212
a143b004
AB
213 /* How to shift the value to BIT0 of the word. */
214 shift_to_word = total_length - (word_offset + word_length);
215
216 /* How to shift the value to the field within the word. */
87e6d782 217 if (CGEN_INSN_LSB0_P)
a143b004 218 shift_within_word = start + 1 - length;
87e6d782 219 else
a143b004
AB
220 shift_within_word = word_length - start - length;
221
222 /* The total SHIFT, then mask in the value. */
223 shift = shift_to_word + shift_within_word;
87e6d782
NC
224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
225 }
226
227#else /* ! CGEN_INT_INSN_P */
228
229 {
230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
231
232 insert_1 (cd, value, start, length, word_length, bufp);
233 }
234
235#endif /* ! CGEN_INT_INSN_P */
236
237 return NULL;
238}
239
240/* Default insn builder (insert handler).
241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
243 recorded in host byte order, otherwise BUFFER is an array of bytes
244 and the value is recorded in target byte order).
245 The result is an error message or NULL if success. */
246
247static const char *
ffead7ae
MM
248insert_insn_normal (CGEN_CPU_DESC cd,
249 const CGEN_INSN * insn,
250 CGEN_FIELDS * fields,
251 CGEN_INSN_BYTES_PTR buffer,
252 bfd_vma pc)
87e6d782
NC
253{
254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
255 unsigned long value;
256 const CGEN_SYNTAX_CHAR_TYPE * syn;
257
258 CGEN_INIT_INSERT (cd);
259 value = CGEN_INSN_BASE_VALUE (insn);
260
261 /* If we're recording insns as numbers (rather than a string of bytes),
262 target byte order handling is deferred until later. */
263
264#if CGEN_INT_INSN_P
265
266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
267 CGEN_FIELDS_BITSIZE (fields), value);
268
269#else
270
0e2ee3ca
NC
271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
272 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
87e6d782
NC
273 value);
274
275#endif /* ! CGEN_INT_INSN_P */
276
277 /* ??? It would be better to scan the format's fields.
278 Still need to be able to insert a value based on the operand though;
279 e.g. storing a branch displacement that got resolved later.
280 Needs more thought first. */
281
282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
283 {
284 const char *errmsg;
285
286 if (CGEN_SYNTAX_CHAR_P (* syn))
287 continue;
288
289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
290 fields, buffer, pc);
291 if (errmsg)
292 return errmsg;
293 }
294
295 return NULL;
296}
297
0e2ee3ca 298#if CGEN_INT_INSN_P
87e6d782 299/* Cover function to store an insn value into an integral insn. Must go here
47b0e7ad 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
87e6d782
NC
301
302static void
ffead7ae
MM
303put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
304 CGEN_INSN_BYTES_PTR buf,
305 int length,
306 int insn_length,
307 CGEN_INSN_INT value)
87e6d782
NC
308{
309 /* For architectures with insns smaller than the base-insn-bitsize,
310 length may be too big. */
311 if (length > insn_length)
312 *buf = value;
313 else
314 {
315 int shift = insn_length - length;
316 /* Written this way to avoid undefined behaviour. */
317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
47b0e7ad 318
87e6d782
NC
319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
320 }
321}
0e2ee3ca 322#endif
87e6d782
NC
323\f
324/* Operand extraction. */
325
326#if ! CGEN_INT_INSN_P
327
328/* Subroutine of extract_normal.
329 Ensure sufficient bytes are cached in EX_INFO.
330 OFFSET is the offset in bytes from the start of the insn of the value.
331 BYTES is the length of the needed value.
332 Returns 1 for success, 0 for failure. */
333
334static CGEN_INLINE int
ffead7ae
MM
335fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
336 CGEN_EXTRACT_INFO *ex_info,
337 int offset,
338 int bytes,
339 bfd_vma pc)
87e6d782
NC
340{
341 /* It's doubtful that the middle part has already been fetched so
342 we don't optimize that case. kiss. */
0e2ee3ca 343 unsigned int mask;
87e6d782
NC
344 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
345
346 /* First do a quick check. */
347 mask = (1 << bytes) - 1;
348 if (((ex_info->valid >> offset) & mask) == mask)
349 return 1;
350
351 /* Search for the first byte we need to read. */
352 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
353 if (! (mask & ex_info->valid))
354 break;
355
356 if (bytes)
357 {
358 int status;
359
360 pc += offset;
361 status = (*info->read_memory_func)
362 (pc, ex_info->insn_bytes + offset, bytes, info);
363
364 if (status != 0)
365 {
366 (*info->memory_error_func) (status, pc, info);
367 return 0;
368 }
369
370 ex_info->valid |= ((1 << bytes) - 1) << offset;
371 }
372
373 return 1;
374}
375
376/* Subroutine of extract_normal. */
377
378static CGEN_INLINE long
ffead7ae
MM
379extract_1 (CGEN_CPU_DESC cd,
380 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
381 int start,
382 int length,
383 int word_length,
384 unsigned char *bufp,
385 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
386{
387 unsigned long x;
388 int shift;
47b0e7ad 389
e333d2c4
NC
390 x = cgen_get_insn_value (cd, bufp, word_length);
391
87e6d782
NC
392 if (CGEN_INSN_LSB0_P)
393 shift = (start + 1) - length;
394 else
395 shift = (word_length - (start + length));
396 return x >> shift;
397}
398
399#endif /* ! CGEN_INT_INSN_P */
400
401/* Default extraction routine.
402
403 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
404 or sometimes less for cases like the m32r where the base insn size is 32
405 but some insns are 16 bits.
406 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
407 but for generality we take a bitmask of all of them.
408 WORD_OFFSET is the offset in bits from the start of the insn of the value.
409 WORD_LENGTH is the length of the word in bits in which the value resides.
410 START is the starting bit number in the word, architecture origin.
411 LENGTH is the length of VALUE in bits.
412 TOTAL_LENGTH is the total length of the insn in bits.
413
414 Returns 1 for success, 0 for failure. */
415
416/* ??? The return code isn't properly used. wip. */
417
418/* ??? This doesn't handle bfd_vma's. Create another function when
419 necessary. */
420
421static int
ffead7ae 422extract_normal (CGEN_CPU_DESC cd,
87e6d782 423#if ! CGEN_INT_INSN_P
ffead7ae 424 CGEN_EXTRACT_INFO *ex_info,
87e6d782 425#else
ffead7ae 426 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
87e6d782 427#endif
ffead7ae
MM
428 CGEN_INSN_INT insn_value,
429 unsigned int attrs,
430 unsigned int word_offset,
431 unsigned int start,
432 unsigned int length,
433 unsigned int word_length,
434 unsigned int total_length,
87e6d782 435#if ! CGEN_INT_INSN_P
ffead7ae 436 bfd_vma pc,
87e6d782 437#else
ffead7ae 438 bfd_vma pc ATTRIBUTE_UNUSED,
87e6d782 439#endif
ffead7ae 440 long *valuep)
87e6d782 441{
fc7bc883 442 long value, mask;
87e6d782
NC
443
444 /* If LENGTH is zero, this operand doesn't contribute to the value
445 so give it a standard value of zero. */
446 if (length == 0)
447 {
448 *valuep = 0;
449 return 1;
450 }
451
b7cd1872 452 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
453 abort ();
454
455 /* For architectures with insns smaller than the insn-base-bitsize,
456 word_length may be too big. */
457 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
458 {
ed963e2d
NC
459 if (word_offset + word_length > total_length)
460 word_length = total_length - word_offset;
87e6d782
NC
461 }
462
fc7bc883 463 /* Does the value reside in INSN_VALUE, and at the right alignment? */
87e6d782 464
fc7bc883 465 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
87e6d782
NC
466 {
467 if (CGEN_INSN_LSB0_P)
468 value = insn_value >> ((word_offset + start + 1) - length);
469 else
470 value = insn_value >> (total_length - ( word_offset + start + length));
471 }
472
473#if ! CGEN_INT_INSN_P
474
475 else
476 {
477 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
478
b7cd1872 479 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
480 abort ();
481
482 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
483 return 0;
484
485 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
486 }
487
488#endif /* ! CGEN_INT_INSN_P */
489
490 /* Written this way to avoid undefined behaviour. */
491 mask = (((1L << (length - 1)) - 1) << 1) | 1;
492
493 value &= mask;
494 /* sign extend? */
495 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
496 && (value & (1L << (length - 1))))
497 value |= ~mask;
498
499 *valuep = value;
500
501 return 1;
502}
503
504/* Default insn extractor.
505
506 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
507 The extracted fields are stored in FIELDS.
508 EX_INFO is used to handle reading variable length insns.
509 Return the length of the insn in bits, or 0 if no match,
510 or -1 if an error occurs fetching data (memory_error_func will have
511 been called). */
512
513static int
ffead7ae
MM
514extract_insn_normal (CGEN_CPU_DESC cd,
515 const CGEN_INSN *insn,
516 CGEN_EXTRACT_INFO *ex_info,
517 CGEN_INSN_INT insn_value,
518 CGEN_FIELDS *fields,
519 bfd_vma pc)
87e6d782
NC
520{
521 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
522 const CGEN_SYNTAX_CHAR_TYPE *syn;
523
524 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
525
526 CGEN_INIT_EXTRACT (cd);
527
528 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
529 {
530 int length;
531
532 if (CGEN_SYNTAX_CHAR_P (*syn))
533 continue;
534
535 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
536 ex_info, insn_value, fields, pc);
537 if (length <= 0)
538 return length;
539 }
540
541 /* We recognized and successfully extracted this insn. */
542 return CGEN_INSN_BITSIZE (insn);
543}
544\f
47b0e7ad 545/* Machine generated code added here. */
87e6d782 546
73589c9d 547const char * or1k_cgen_insert_operand
47b0e7ad 548 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
0e2ee3ca 549
87e6d782
NC
550/* Main entry point for operand insertion.
551
552 This function is basically just a big switch statement. Earlier versions
553 used tables to look up the function to use, but
554 - if the table contains both assembler and disassembler functions then
555 the disassembler contains much of the assembler and vice-versa,
556 - there's a lot of inlining possibilities as things grow,
557 - using a switch statement avoids the function call overhead.
558
559 This function could be moved into `parse_insn_normal', but keeping it
560 separate makes clear the interface between `parse_insn_normal' and each of
561 the handlers. It's also needed by GAS to insert operands that couldn't be
9a2e995d 562 resolved during parsing. */
87e6d782
NC
563
564const char *
73589c9d 565or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
566 int opindex,
567 CGEN_FIELDS * fields,
568 CGEN_INSN_BYTES_PTR buffer,
569 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
570{
571 const char * errmsg = NULL;
572 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
573
574 switch (opindex)
575 {
73589c9d 576 case OR1K_OPERAND_DISP26 :
87e6d782
NC
577 {
578 long value = fields->f_disp26;
fe8afbc4 579 value = ((SI) (((value) - (pc))) >> (2));
87e6d782
NC
580 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer);
581 }
582 break;
73589c9d
CS
583 case OR1K_OPERAND_RA :
584 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 585 break;
73589c9d
CS
586 case OR1K_OPERAND_RADF :
587 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 588 break;
73589c9d
CS
589 case OR1K_OPERAND_RASF :
590 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 591 break;
73589c9d
CS
592 case OR1K_OPERAND_RB :
593 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
87e6d782 594 break;
73589c9d
CS
595 case OR1K_OPERAND_RBDF :
596 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 597 break;
73589c9d 598 case OR1K_OPERAND_RBSF :
87e6d782
NC
599 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
600 break;
73589c9d 601 case OR1K_OPERAND_RD :
87e6d782
NC
602 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
603 break;
73589c9d
CS
604 case OR1K_OPERAND_RDDF :
605 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 606 break;
73589c9d
CS
607 case OR1K_OPERAND_RDSF :
608 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
609 break;
610 case OR1K_OPERAND_SIMM16 :
611 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer);
612 break;
613 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782
NC
614 {
615{
73589c9d
CS
616 FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31));
617 FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047));
87e6d782 618}
73589c9d 619 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782
NC
620 if (errmsg)
621 break;
73589c9d 622 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
87e6d782
NC
623 if (errmsg)
624 break;
625 }
626 break;
73589c9d 627 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
628 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer);
629 break;
73589c9d
CS
630 case OR1K_OPERAND_UIMM16_SPLIT :
631 {
632{
633 FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31));
634 FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047));
635}
636 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
637 if (errmsg)
638 break;
639 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
640 if (errmsg)
641 break;
642 }
643 break;
644 case OR1K_OPERAND_UIMM6 :
645 errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer);
87e6d782
NC
646 break;
647
648 default :
649 /* xgettext:c-format */
a6743a54
AM
650 opcodes_error_handler
651 (_("internal error: unrecognized field %d while building insn"),
652 opindex);
87e6d782
NC
653 abort ();
654 }
655
656 return errmsg;
657}
658
73589c9d 659int or1k_cgen_extract_operand
47b0e7ad 660 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 661
87e6d782
NC
662/* Main entry point for operand extraction.
663 The result is <= 0 for error, >0 for success.
664 ??? Actual values aren't well defined right now.
665
666 This function is basically just a big switch statement. Earlier versions
667 used tables to look up the function to use, but
668 - if the table contains both assembler and disassembler functions then
669 the disassembler contains much of the assembler and vice-versa,
670 - there's a lot of inlining possibilities as things grow,
671 - using a switch statement avoids the function call overhead.
672
673 This function could be moved into `print_insn_normal', but keeping it
674 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 675 the handlers. */
87e6d782
NC
676
677int
73589c9d 678or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
679 int opindex,
680 CGEN_EXTRACT_INFO *ex_info,
681 CGEN_INSN_INT insn_value,
682 CGEN_FIELDS * fields,
683 bfd_vma pc)
87e6d782
NC
684{
685 /* Assume success (for those operands that are nops). */
686 int length = 1;
687 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
688
689 switch (opindex)
690 {
73589c9d 691 case OR1K_OPERAND_DISP26 :
87e6d782
NC
692 {
693 long value;
694 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value);
695 value = ((((value) << (2))) + (pc));
696 fields->f_disp26 = value;
697 }
698 break;
73589c9d
CS
699 case OR1K_OPERAND_RA :
700 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 701 break;
73589c9d
CS
702 case OR1K_OPERAND_RADF :
703 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
87e6d782 704 break;
73589c9d
CS
705 case OR1K_OPERAND_RASF :
706 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 707 break;
73589c9d
CS
708 case OR1K_OPERAND_RB :
709 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
87e6d782 710 break;
73589c9d
CS
711 case OR1K_OPERAND_RBDF :
712 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
87e6d782 713 break;
73589c9d 714 case OR1K_OPERAND_RBSF :
87e6d782
NC
715 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
716 break;
73589c9d
CS
717 case OR1K_OPERAND_RD :
718 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
719 break;
720 case OR1K_OPERAND_RDDF :
721 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
722 break;
723 case OR1K_OPERAND_RDSF :
87e6d782
NC
724 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
725 break;
73589c9d
CS
726 case OR1K_OPERAND_SIMM16 :
727 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16);
87e6d782 728 break;
73589c9d 729 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782 730 {
73589c9d 731 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
87e6d782 732 if (length <= 0) break;
73589c9d 733 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
87e6d782 734 if (length <= 0) break;
73589c9d 735 FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
87e6d782
NC
736 }
737 break;
73589c9d 738 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
739 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16);
740 break;
73589c9d
CS
741 case OR1K_OPERAND_UIMM16_SPLIT :
742 {
743 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
744 if (length <= 0) break;
745 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
746 if (length <= 0) break;
747 FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
748 }
749 break;
750 case OR1K_OPERAND_UIMM6 :
751 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6);
87e6d782
NC
752 break;
753
754 default :
755 /* xgettext:c-format */
a6743a54
AM
756 opcodes_error_handler
757 (_("internal error: unrecognized field %d while decoding insn"),
758 opindex);
87e6d782
NC
759 abort ();
760 }
761
762 return length;
763}
764
43e65147 765cgen_insert_fn * const or1k_cgen_insert_handlers[] =
87e6d782
NC
766{
767 insert_insn_normal,
768};
769
43e65147 770cgen_extract_fn * const or1k_cgen_extract_handlers[] =
87e6d782
NC
771{
772 extract_insn_normal,
773};
774
73589c9d
CS
775int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
776bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
0e2ee3ca 777
87e6d782
NC
778/* Getting values from cgen_fields is handled by a collection of functions.
779 They are distinguished by the type of the VALUE argument they return.
780 TODO: floating point, inlining support, remove cases where result type
781 not appropriate. */
782
783int
73589c9d 784or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
785 int opindex,
786 const CGEN_FIELDS * fields)
87e6d782
NC
787{
788 int value;
789
790 switch (opindex)
791 {
73589c9d 792 case OR1K_OPERAND_DISP26 :
87e6d782
NC
793 value = fields->f_disp26;
794 break;
73589c9d
CS
795 case OR1K_OPERAND_RA :
796 value = fields->f_r2;
87e6d782 797 break;
73589c9d
CS
798 case OR1K_OPERAND_RADF :
799 value = fields->f_r1;
87e6d782 800 break;
73589c9d
CS
801 case OR1K_OPERAND_RASF :
802 value = fields->f_r2;
87e6d782 803 break;
73589c9d
CS
804 case OR1K_OPERAND_RB :
805 value = fields->f_r3;
87e6d782 806 break;
73589c9d
CS
807 case OR1K_OPERAND_RBDF :
808 value = fields->f_r1;
87e6d782 809 break;
73589c9d 810 case OR1K_OPERAND_RBSF :
87e6d782
NC
811 value = fields->f_r3;
812 break;
73589c9d
CS
813 case OR1K_OPERAND_RD :
814 value = fields->f_r1;
815 break;
816 case OR1K_OPERAND_RDDF :
87e6d782
NC
817 value = fields->f_r1;
818 break;
73589c9d
CS
819 case OR1K_OPERAND_RDSF :
820 value = fields->f_r1;
821 break;
822 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
823 value = fields->f_simm16;
824 break;
73589c9d
CS
825 case OR1K_OPERAND_SIMM16_SPLIT :
826 value = fields->f_simm16_split;
87e6d782 827 break;
73589c9d 828 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
829 value = fields->f_uimm16;
830 break;
73589c9d
CS
831 case OR1K_OPERAND_UIMM16_SPLIT :
832 value = fields->f_uimm16_split;
833 break;
834 case OR1K_OPERAND_UIMM6 :
835 value = fields->f_uimm6;
87e6d782
NC
836 break;
837
838 default :
839 /* xgettext:c-format */
a6743a54
AM
840 opcodes_error_handler
841 (_("internal error: unrecognized field %d while getting int operand"),
842 opindex);
87e6d782
NC
843 abort ();
844 }
845
846 return value;
847}
848
849bfd_vma
73589c9d 850or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
851 int opindex,
852 const CGEN_FIELDS * fields)
87e6d782
NC
853{
854 bfd_vma value;
855
856 switch (opindex)
857 {
73589c9d 858 case OR1K_OPERAND_DISP26 :
87e6d782
NC
859 value = fields->f_disp26;
860 break;
73589c9d
CS
861 case OR1K_OPERAND_RA :
862 value = fields->f_r2;
87e6d782 863 break;
73589c9d
CS
864 case OR1K_OPERAND_RADF :
865 value = fields->f_r1;
87e6d782 866 break;
73589c9d
CS
867 case OR1K_OPERAND_RASF :
868 value = fields->f_r2;
87e6d782 869 break;
73589c9d
CS
870 case OR1K_OPERAND_RB :
871 value = fields->f_r3;
87e6d782 872 break;
73589c9d
CS
873 case OR1K_OPERAND_RBDF :
874 value = fields->f_r1;
87e6d782 875 break;
73589c9d 876 case OR1K_OPERAND_RBSF :
87e6d782
NC
877 value = fields->f_r3;
878 break;
73589c9d
CS
879 case OR1K_OPERAND_RD :
880 value = fields->f_r1;
881 break;
882 case OR1K_OPERAND_RDDF :
883 value = fields->f_r1;
884 break;
885 case OR1K_OPERAND_RDSF :
87e6d782
NC
886 value = fields->f_r1;
887 break;
73589c9d 888 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
889 value = fields->f_simm16;
890 break;
73589c9d
CS
891 case OR1K_OPERAND_SIMM16_SPLIT :
892 value = fields->f_simm16_split;
87e6d782 893 break;
73589c9d 894 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
895 value = fields->f_uimm16;
896 break;
73589c9d
CS
897 case OR1K_OPERAND_UIMM16_SPLIT :
898 value = fields->f_uimm16_split;
899 break;
900 case OR1K_OPERAND_UIMM6 :
901 value = fields->f_uimm6;
87e6d782
NC
902 break;
903
904 default :
905 /* xgettext:c-format */
a6743a54
AM
906 opcodes_error_handler
907 (_("internal error: unrecognized field %d while getting vma operand"),
908 opindex);
87e6d782
NC
909 abort ();
910 }
911
912 return value;
913}
914
73589c9d
CS
915void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
916void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 917
87e6d782
NC
918/* Stuffing values in cgen_fields is handled by a collection of functions.
919 They are distinguished by the type of the VALUE argument they accept.
920 TODO: floating point, inlining support, remove cases where argument type
921 not appropriate. */
922
923void
73589c9d 924or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
925 int opindex,
926 CGEN_FIELDS * fields,
927 int value)
87e6d782
NC
928{
929 switch (opindex)
930 {
73589c9d 931 case OR1K_OPERAND_DISP26 :
87e6d782
NC
932 fields->f_disp26 = value;
933 break;
73589c9d
CS
934 case OR1K_OPERAND_RA :
935 fields->f_r2 = value;
87e6d782 936 break;
73589c9d
CS
937 case OR1K_OPERAND_RADF :
938 fields->f_r1 = value;
87e6d782 939 break;
73589c9d
CS
940 case OR1K_OPERAND_RASF :
941 fields->f_r2 = value;
87e6d782 942 break;
73589c9d
CS
943 case OR1K_OPERAND_RB :
944 fields->f_r3 = value;
87e6d782 945 break;
73589c9d
CS
946 case OR1K_OPERAND_RBDF :
947 fields->f_r1 = value;
87e6d782 948 break;
73589c9d 949 case OR1K_OPERAND_RBSF :
87e6d782
NC
950 fields->f_r3 = value;
951 break;
73589c9d 952 case OR1K_OPERAND_RD :
87e6d782
NC
953 fields->f_r1 = value;
954 break;
73589c9d
CS
955 case OR1K_OPERAND_RDDF :
956 fields->f_r1 = value;
957 break;
958 case OR1K_OPERAND_RDSF :
959 fields->f_r1 = value;
960 break;
961 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
962 fields->f_simm16 = value;
963 break;
73589c9d
CS
964 case OR1K_OPERAND_SIMM16_SPLIT :
965 fields->f_simm16_split = value;
87e6d782 966 break;
73589c9d 967 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
968 fields->f_uimm16 = value;
969 break;
73589c9d
CS
970 case OR1K_OPERAND_UIMM16_SPLIT :
971 fields->f_uimm16_split = value;
972 break;
973 case OR1K_OPERAND_UIMM6 :
974 fields->f_uimm6 = value;
87e6d782
NC
975 break;
976
977 default :
978 /* xgettext:c-format */
a6743a54
AM
979 opcodes_error_handler
980 (_("internal error: unrecognized field %d while setting int operand"),
981 opindex);
87e6d782
NC
982 abort ();
983 }
984}
985
986void
73589c9d 987or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
988 int opindex,
989 CGEN_FIELDS * fields,
990 bfd_vma value)
87e6d782
NC
991{
992 switch (opindex)
993 {
73589c9d 994 case OR1K_OPERAND_DISP26 :
87e6d782
NC
995 fields->f_disp26 = value;
996 break;
73589c9d
CS
997 case OR1K_OPERAND_RA :
998 fields->f_r2 = value;
87e6d782 999 break;
73589c9d
CS
1000 case OR1K_OPERAND_RADF :
1001 fields->f_r1 = value;
87e6d782 1002 break;
73589c9d
CS
1003 case OR1K_OPERAND_RASF :
1004 fields->f_r2 = value;
87e6d782 1005 break;
73589c9d
CS
1006 case OR1K_OPERAND_RB :
1007 fields->f_r3 = value;
87e6d782 1008 break;
73589c9d
CS
1009 case OR1K_OPERAND_RBDF :
1010 fields->f_r1 = value;
87e6d782 1011 break;
73589c9d 1012 case OR1K_OPERAND_RBSF :
87e6d782
NC
1013 fields->f_r3 = value;
1014 break;
73589c9d
CS
1015 case OR1K_OPERAND_RD :
1016 fields->f_r1 = value;
1017 break;
1018 case OR1K_OPERAND_RDDF :
87e6d782
NC
1019 fields->f_r1 = value;
1020 break;
73589c9d
CS
1021 case OR1K_OPERAND_RDSF :
1022 fields->f_r1 = value;
1023 break;
1024 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
1025 fields->f_simm16 = value;
1026 break;
73589c9d
CS
1027 case OR1K_OPERAND_SIMM16_SPLIT :
1028 fields->f_simm16_split = value;
87e6d782 1029 break;
73589c9d 1030 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
1031 fields->f_uimm16 = value;
1032 break;
73589c9d
CS
1033 case OR1K_OPERAND_UIMM16_SPLIT :
1034 fields->f_uimm16_split = value;
1035 break;
1036 case OR1K_OPERAND_UIMM6 :
1037 fields->f_uimm6 = value;
87e6d782
NC
1038 break;
1039
1040 default :
1041 /* xgettext:c-format */
a6743a54
AM
1042 opcodes_error_handler
1043 (_("internal error: unrecognized field %d while setting vma operand"),
1044 opindex);
87e6d782
NC
1045 abort ();
1046 }
1047}
1048
1049/* Function to call before using the instruction builder tables. */
1050
1051void
73589c9d 1052or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd)
87e6d782 1053{
73589c9d
CS
1054 cd->insert_handlers = & or1k_cgen_insert_handlers[0];
1055 cd->extract_handlers = & or1k_cgen_extract_handlers[0];
87e6d782 1056
73589c9d
CS
1057 cd->insert_operand = or1k_cgen_insert_operand;
1058 cd->extract_operand = or1k_cgen_extract_operand;
87e6d782 1059
73589c9d
CS
1060 cd->get_int_operand = or1k_cgen_get_int_operand;
1061 cd->set_int_operand = or1k_cgen_set_int_operand;
1062 cd->get_vma_operand = or1k_cgen_get_vma_operand;
1063 cd->set_vma_operand = or1k_cgen_set_vma_operand;
87e6d782 1064}