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e23eba97 1/* RISC-V disassembler
250d07de 2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "sysdep.h"
88c1242d 24#include "disassemble.h"
e23eba97
NC		 25#include "libiberty.h"
26#include "opcode/riscv.h"
27#include "opintl.h"
28#include "elf-bfd.h"
29#include "elf/riscv.h"
3d73d29e 30#include "cpu-riscv.h"
e23eba97 31
2d5d5a8f 32#include "bfd_stdint.h"
e23eba97
NC		 33#include <ctype.h>
34
3d73d29e 35static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
8f595e9b 36
e23eba97
NC		 37struct riscv_private_data
38{
39 bfd_vma gp;
40 bfd_vma print_addr;
41 bfd_vma hi_addr[OP_MASK_RD + 1];
42};
43
44static const char * const *riscv_gpr_names;
45static const char * const *riscv_fpr_names;
46
dcd709e0
NC		 47/* If set, disassemble as most general instruction. */
48static int no_aliases;
e23eba97
NC		 49
50static void
51set_default_riscv_dis_options (void)
52{
53 riscv_gpr_names = riscv_gpr_names_abi;
54 riscv_fpr_names = riscv_fpr_names_abi;
55 no_aliases = 0;
56}
57
8f595e9b
NC		 58static bfd_boolean
59parse_riscv_dis_option_without_args (const char *option)
e23eba97
NC		 60{
61 if (strcmp (option, "no-aliases") == 0)
62 no_aliases = 1;
63 else if (strcmp (option, "numeric") == 0)
64 {
65 riscv_gpr_names = riscv_gpr_names_numeric;
66 riscv_fpr_names = riscv_fpr_names_numeric;
67 }
8f595e9b
NC		 68 else
69 return FALSE;
70 return TRUE;
71}
72
73static void
74parse_riscv_dis_option (const char *option)
75{
76 char *equal, *value;
77
78 if (parse_riscv_dis_option_without_args (option))
79 return;
80
81 equal = strchr (option, '=');
82 if (equal == NULL)
83 {
84 /* The option without '=' should be defined above. */
85 opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
86 return;
87 }
88 if (equal == option
89 || *(equal + 1) == '\0')
90 {
91 /* Invalid options with '=', no option name before '=',
92 and no value after '='. */
93 opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
94 option);
95 return;
96 }
97
98 *equal = '\0';
99 value = equal + 1;
100 if (strcmp (option, "priv-spec") == 0)
101 {
3d73d29e
NC		 102 enum riscv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE;
103 const char *name = NULL;
104
105 RISCV_GET_PRIV_SPEC_CLASS (value, priv_spec);
106 if (priv_spec == PRIV_SPEC_CLASS_NONE)
b800637e 107 opcodes_error_handler (_("unknown privileged spec set by %s=%s"),
8152e040
NC		 108 option, value);
109 else if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
110 default_priv_spec = priv_spec;
111 else if (default_priv_spec != priv_spec)
3d73d29e
NC		 112 {
113 RISCV_GET_PRIV_SPEC_NAME (name, default_priv_spec);
114 opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, "
115 "the elf privilege attribute is %s"),
116 option, value, name);
117 }
8f595e9b 118 }
e23eba97
NC		 119 else
120 {
a6743a54
AM		 121 /* xgettext:c-format */
122 opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
e23eba97
NC		 123 }
124}
125
126static void
127parse_riscv_dis_options (const char *opts_in)
128{
129 char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
130
131 set_default_riscv_dis_options ();
132
133 for ( ; opt_end != NULL; opt = opt_end + 1)
134 {
135 if ((opt_end = strchr (opt, ',')) != NULL)
136 *opt_end = 0;
137 parse_riscv_dis_option (opt);
138 }
139
140 free (opts);
141}
142
143/* Print one argument from an array. */
144
145static void
146arg_print (struct disassemble_info *info, unsigned long val,
147 const char* const* array, size_t size)
148{
149 const char *s = val >= size || array[val] == NULL ? "unknown" : array[val];
150 (*info->fprintf_func) (info->stream, "%s", s);
151}
152
153static void
154maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
155{
156 if (pd->hi_addr[base_reg] != (bfd_vma)-1)
157 {
35fd2b2b 158 pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
e23eba97
NC		 159 pd->hi_addr[base_reg] = -1;
160 }
161 else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
162 pd->print_addr = pd->gp + offset;
163 else if (base_reg == X_TP || base_reg == 0)
164 pd->print_addr = offset;
165}
166
167/* Print insn arguments for 32/64-bit code. */
168
169static void
170print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
171{
172 struct riscv_private_data *pd = info->private_data;
173 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
174 int rd = (l >> OP_SH_RD) & OP_MASK_RD;
175 fprintf_ftype print = info->fprintf_func;
176
177 if (*d != '\0')
178 print (info->stream, "\t");
179
180 for (; *d != '\0'; d++)
181 {
182 switch (*d)
183 {
184 case 'C': /* RVC */
185 switch (*++d)
186 {
dcd709e0
NC		 187 case 's': /* RS1 x8-x15. */
188 case 'w': /* RS1 x8-x15. */
e23eba97
NC		 189 print (info->stream, "%s",
190 riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
191 break;
dcd709e0
NC		 192 case 't': /* RS2 x8-x15. */
193 case 'x': /* RS2 x8-x15. */
e23eba97
NC		 194 print (info->stream, "%s",
195 riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
196 break;
dcd709e0 197 case 'U': /* RS1, constrained to equal RD. */
e23eba97
NC		 198 print (info->stream, "%s", riscv_gpr_names[rd]);
199 break;
dcd709e0 200 case 'c': /* RS1, constrained to equal sp. */
e23eba97
NC		 201 print (info->stream, "%s", riscv_gpr_names[X_SP]);
202 break;
203 case 'V': /* RS2 */
204 print (info->stream, "%s",
205 riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
206 break;
207 case 'i':
208 print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
209 break;
f91d48de 210 case 'o':
e23eba97
NC		 211 case 'j':
212 print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
213 break;
214 case 'k':
215 print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
216 break;
217 case 'l':
218 print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
219 break;
220 case 'm':
221 print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
222 break;
223 case 'n':
224 print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
225 break;
226 case 'K':
227 print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
228 break;
229 case 'L':
230 print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
231 break;
232 case 'M':
233 print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
234 break;
235 case 'N':
236 print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
237 break;
238 case 'p':
239 info->target = EXTRACT_RVC_B_IMM (l) + pc;
240 (*info->print_address_func) (info->target, info);
241 break;
242 case 'a':
243 info->target = EXTRACT_RVC_J_IMM (l) + pc;
244 (*info->print_address_func) (info->target, info);
245 break;
246 case 'u':
247 print (info->stream, "0x%x",
248 (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
249 break;
250 case '>':
251 print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
252 break;
253 case '<':
254 print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
255 break;
dcd709e0 256 case 'T': /* Floating-point RS2. */
e23eba97
NC		 257 print (info->stream, "%s",
258 riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
259 break;
dcd709e0 260 case 'D': /* Floating-point RS2 x8-x15. */
e23eba97
NC		 261 print (info->stream, "%s",
262 riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
263 break;
264 }
265 break;
266
267 case ',':
268 case '(':
269 case ')':
270 case '[':
271 case ']':
272 print (info->stream, "%c", *d);
273 break;
274
275 case '0':
dcd709e0 276 /* Only print constant 0 if it is the last argument. */
e23eba97
NC		 277 if (!d[1])
278 print (info->stream, "0");
279 break;
280
281 case 'b':
282 case 's':
35eeb78f
JW		 283 if ((l & MASK_JALR) == MATCH_JALR)
284 maybe_print_address (pd, rs1, 0);
e23eba97
NC		 285 print (info->stream, "%s", riscv_gpr_names[rs1]);
286 break;
287
288 case 't':
289 print (info->stream, "%s",
290 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
291 break;
292
293 case 'u':
294 print (info->stream, "0x%x",
295 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
296 break;
297
298 case 'm':
299 arg_print (info, EXTRACT_OPERAND (RM, l),
300 riscv_rm, ARRAY_SIZE (riscv_rm));
301 break;
302
303 case 'P':
304 arg_print (info, EXTRACT_OPERAND (PRED, l),
305 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
306 break;
307
308 case 'Q':
309 arg_print (info, EXTRACT_OPERAND (SUCC, l),
310 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
311 break;
312
313 case 'o':
314 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
b52d3cfc 315 /* Fall through. */
e23eba97
NC		 316 case 'j':
317 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
318 || (l & MASK_JALR) == MATCH_JALR)
319 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
320 print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
321 break;
322
323 case 'q':
324 maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
325 print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
326 break;
327
328 case 'a':
329 info->target = EXTRACT_UJTYPE_IMM (l) + pc;
330 (*info->print_address_func) (info->target, info);
331 break;
332
333 case 'p':
334 info->target = EXTRACT_SBTYPE_IMM (l) + pc;
335 (*info->print_address_func) (info->target, info);
336 break;
337
338 case 'd':
339 if ((l & MASK_AUIPC) == MATCH_AUIPC)
340 pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
341 else if ((l & MASK_LUI) == MATCH_LUI)
342 pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
343 else if ((l & MASK_C_LUI) == MATCH_C_LUI)
344 pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
345 print (info->stream, "%s", riscv_gpr_names[rd]);
346 break;
347
348 case 'z':
349 print (info->stream, "%s", riscv_gpr_names[0]);
350 break;
351
352 case '>':
353 print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
354 break;
355
356 case '<':
357 print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
358 break;
359
360 case 'S':
361 case 'U':
362 print (info->stream, "%s", riscv_fpr_names[rs1]);
363 break;
364
365 case 'T':
366 print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
367 break;
368
369 case 'D':
370 print (info->stream, "%s", riscv_fpr_names[rd]);
371 break;
372
373 case 'R':
374 print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
375 break;
376
377 case 'E':
378 {
dcd709e0 379 static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs. */
8f595e9b 380 static bfd_boolean init_csr = FALSE;
e23eba97 381 unsigned int csr = EXTRACT_OPERAND (CSR, l);
8f595e9b
NC		 382
383 if (!init_csr)
e23eba97 384 {
8f595e9b
NC		 385 unsigned int i;
386 for (i = 0; i < 4096; i++)
387 riscv_csr_hash[i] = NULL;
388
dcd709e0 389 /* Set to the newest privileged version. */
8f595e9b
NC		 390 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
391 default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
392
08ccfccf
NC		 393#define DECLARE_CSR(name, num, class, define_version, abort_version) \
394 if (riscv_csr_hash[num] == NULL \
395 && ((define_version == PRIV_SPEC_CLASS_NONE \
396 && abort_version == PRIV_SPEC_CLASS_NONE) \
397 || (default_priv_spec >= define_version \
398 && default_priv_spec < abort_version))) \
8f595e9b
NC		 399 riscv_csr_hash[num] = #name;
400#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
401 DECLARE_CSR (name, num, class, define_version, abort_version)
e23eba97
NC		 402#include "opcode/riscv-opc.h"
403#undef DECLARE_CSR
404 }
8f595e9b
NC		 405
406 if (riscv_csr_hash[csr] != NULL)
407 print (info->stream, "%s", riscv_csr_hash[csr]);
e23eba97
NC		 408 else
409 print (info->stream, "0x%x", csr);
410 break;
411 }
412
413 case 'Z':
414 print (info->stream, "%d", rs1);
415 break;
416
417 default:
418 /* xgettext:c-format */
419 print (info->stream, _("# internal error, undefined modifier (%c)"),
420 *d);
421 return;
422 }
423 }
424}
425
426/* Print the RISC-V instruction at address MEMADDR in debugged memory,
427 on using INFO. Returns length of the instruction, in bytes.
428 BIGENDIAN must be 1 if this is big-endian code, 0 if
429 this is little-endian code. */
430
431static int
432riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
433{
434 const struct riscv_opcode *op;
435 static bfd_boolean init = 0;
436 static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
437 struct riscv_private_data *pd;
438 int insnlen;
439
440#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
441
442 /* Build a hash table to shorten the search time. */
443 if (! init)
444 {
445 for (op = riscv_opcodes; op->name; op++)
446 if (!riscv_hash[OP_HASH_IDX (op->match)])
447 riscv_hash[OP_HASH_IDX (op->match)] = op;
448
449 init = 1;
450 }
451
452 if (info->private_data == NULL)
453 {
454 int i;
455
456 pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
457 pd->gp = -1;
458 pd->print_addr = -1;
459 for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
460 pd->hi_addr[i] = -1;
461
462 for (i = 0; i < info->symtab_size; i++)
b5292032 463 if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
e23eba97
NC		 464 pd->gp = bfd_asymbol_value (info->symtab[i]);
465 }
466 else
467 pd = info->private_data;
468
469 insnlen = riscv_insn_length (word);
470
d7560e2d
JW		 471 /* RISC-V instructions are always little-endian. */
472 info->endian_code = BFD_ENDIAN_LITTLE;
473
e23eba97
NC		 474 info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
475 info->bytes_per_line = 8;
d7560e2d
JW		 476 /* We don't support constant pools, so this must be code. */
477 info->display_endian = info->endian_code;
e23eba97
NC		 478 info->insn_info_valid = 1;
479 info->branch_delay_insns = 0;
480 info->data_size = 0;
481 info->insn_type = dis_nonbranch;
482 info->target = 0;
483 info->target2 = 0;
484
485 op = riscv_hash[OP_HASH_IDX (word)];
486 if (op != NULL)
487 {
1080bf78 488 unsigned xlen = 0;
e23eba97 489
2922d21d
AW		 490 /* If XLEN is not known, get its value from the ELF class. */
491 if (info->mach == bfd_mach_riscv64)
492 xlen = 64;
493 else if (info->mach == bfd_mach_riscv32)
494 xlen = 32;
495 else if (info->section != NULL)
e23eba97
NC		 496 {
497 Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
498 xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
499 }
500
501 for (; op->name; op++)
502 {
503 /* Does the opcode match? */
504 if (! (op->match_func) (op, word))
505 continue;
506 /* Is this a pseudo-instruction and may we print it as such? */
507 if (no_aliases && (op->pinfo & INSN_ALIAS))
508 continue;
509 /* Is this instruction restricted to a certain value of XLEN? */
43135d3b 510 if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
e23eba97
NC		 511 continue;
512
513 /* It's a match. */
514 (*info->fprintf_func) (info->stream, "%s", op->name);
515 print_insn_args (op->args, word, memaddr, info);
516
517 /* Try to disassemble multi-instruction addressing sequences. */
518 if (pd->print_addr != (bfd_vma)-1)
519 {
520 info->target = pd->print_addr;
521 (*info->fprintf_func) (info->stream, " # ");
522 (*info->print_address_func) (info->target, info);
523 pd->print_addr = -1;
524 }
525
eb41b248
JW		 526 /* Finish filling out insn_info fields. */
527 switch (op->pinfo & INSN_TYPE)
528 {
529 case INSN_BRANCH:
530 info->insn_type = dis_branch;
531 break;
532 case INSN_CONDBRANCH:
533 info->insn_type = dis_condbranch;
534 break;
535 case INSN_JSR:
536 info->insn_type = dis_jsr;
537 break;
538 case INSN_DREF:
539 info->insn_type = dis_dref;
540 break;
541 default:
542 break;
543 }
544
545 if (op->pinfo & INSN_DATA_SIZE)
546 {
547 int size = ((op->pinfo & INSN_DATA_SIZE)
548 >> INSN_DATA_SIZE_SHIFT);
549 info->data_size = 1 << (size - 1);
550 }
551
e23eba97
NC		 552 return insnlen;
553 }
554 }
555
556 /* We did not find a match, so just print the instruction bits. */
557 info->insn_type = dis_noninsn;
558 (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
559 return insnlen;
560}
561
562int
563print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
564{
565 bfd_byte packet[2];
566 insn_t insn = 0;
567 bfd_vma n;
568 int status;
569
570 if (info->disassembler_options != NULL)
571 {
572 parse_riscv_dis_options (info->disassembler_options);
573 /* Avoid repeatedly parsing the options. */
574 info->disassembler_options = NULL;
575 }
576 else if (riscv_gpr_names == NULL)
577 set_default_riscv_dis_options ();
578
579 /* Instructions are a sequence of 2-byte packets in little-endian order. */
580 for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
581 {
582 status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
583 if (status != 0)
584 {
585 /* Don't fail just because we fell off the end. */
586 if (n > 0)
587 break;
588 (*info->memory_error_func) (status, memaddr, info);
589 return status;
590 }
591
592 insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n);
593 }
594
595 return riscv_disassemble_insn (memaddr, insn, info);
596}
597
8152e040
NC		 598disassembler_ftype
599riscv_get_disassembler (bfd *abfd)
600{
8152e040
NC		 601 if (abfd)
602 {
603 const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
604 if (bfd_get_section_by_name (abfd, sec_name) != NULL)
605 {
606 obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
607 unsigned int Tag_a = Tag_RISCV_priv_spec;
608 unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
609 unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
610 riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
611 attr[Tag_b].i,
612 attr[Tag_c].i,
613 &default_priv_spec);
614 }
615 }
616 return print_insn_riscv;
617}
618
884b49e3
AB		 619/* Prevent use of the fake labels that are generated as part of the DWARF
620 and for relaxable relocations in the assembler. */
621
622bfd_boolean
623riscv_symbol_is_valid (asymbol * sym,
624 struct disassemble_info * info ATTRIBUTE_UNUSED)
625{
626 const char * name;
627
628 if (sym == NULL)
629 return FALSE;
630
631 name = bfd_asymbol_name (sym);
632
633 return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
634}
635
e23eba97
NC		 636void
637print_riscv_disassembler_options (FILE *stream)
638{
639 fprintf (stream, _("\n\
640The following RISC-V-specific disassembler options are supported for use\n\
641with the -M switch (multiple options should be separated by commas):\n"));
642
643 fprintf (stream, _("\n\
8f595e9b
NC		 644 numeric Print numeric register names, rather than ABI names.\n"));
645
646 fprintf (stream, _("\n\
647 no-aliases Disassemble only into canonical instructions, rather\n\
648 than into pseudoinstructions.\n"));
e23eba97
NC		 649
650 fprintf (stream, _("\n\
8f595e9b
NC		 651 priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
652 (1.9, 1.9.1, 1.10, 1.11).\n"));
e23eba97
NC		 653
654 fprintf (stream, _("\n"));
655}
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