projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 1c0d3aa6 | 1 | /* Instruction printing code for Score |
| c3b7224a | 2 | Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. |
| 1c0d3aa6 | 3 | Contributed by: |
| c3b7224a | 4 | Brain.lin (brain.lin@sunplusct.com) |
| 1c0d3aa6 NC |
5 | Mei Ligang (ligang@sunnorth.com.cn) |
| 6 | Pei-Lin Tsai (pltsai@sunplus.com) | |
| 7 | ||
| 9b201bb5 | 8 | This file is part of the GNU opcodes library. |
| 1c0d3aa6 | 9 | |
| 9b201bb5 NC |
10 | This library is free software; you can redistribute it and/or modify |
| 11 | it under the terms of the GNU General Public License as published by | |
| 12 | the Free Software Foundation; either version 3, or (at your option) | |
| 1c0d3aa6 NC |
13 | any later version. |
| 14 | ||
| 9b201bb5 NC |
15 | It is distributed in the hope that it will be useful, but WITHOUT |
| 16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 18 | License for more details. | |
| 1c0d3aa6 NC |
19 | |
| 20 | You should have received a copy of the GNU General Public License | |
| 9b201bb5 NC |
21 | along with this file; see the file COPYING. If not, write to the |
| 22 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 23 | MA 02110-1301, USA. */ | |
| 1c0d3aa6 NC |
24 | |
| 25 | #include "sysdep.h" | |
| 26 | #include "dis-asm.h" | |
| 27 | #define DEFINE_TABLE | |
| 1c0d3aa6 NC |
28 | #include "opintl.h" |
| 29 | #include "bfd.h" | |
| 30 | ||
| 31 | /* FIXME: This shouldn't be done here. */ | |
| 32 | #include "elf-bfd.h" | |
| 33 | #include "elf/internal.h" | |
| 34 | #include "elf/score.h" | |
| 35 | ||
| 02b1cb40 | 36 | #ifdef BFD64 |
| c3b7224a NC |
37 | /* s3_s7: opcodes and export prototypes. */ |
| 38 | extern int | |
| 39 | s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little); | |
| 40 | ||
| 41 | struct score_opcode | |
| 42 | { | |
| 43 | bfd_vma value; | |
| 44 | bfd_vma mask; /* Recognise instruction if (op & mask) == value. */ | |
| 45 | char *assembler; /* Disassembly string. */ | |
| 46 | }; | |
| 47 | ||
| 48 | /* Note: There is a partial ordering in this table - it must be searched from | |
| 49 | the top to obtain a correct match. */ | |
| 50 | ||
| 51 | static struct score_opcode score_opcodes[] = | |
| 52 | { | |
| 53 | /* Score Instructions. */ | |
| 54 | {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"}, | |
| 55 | {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"}, | |
| 56 | {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"}, | |
| 57 | {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 58 | {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"}, | |
| 59 | {0x00000012, 0x3e0003ff, "addc\t\t%20-24r, %15-19r, %10-14r"}, | |
| 60 | {0x00000013, 0x3e0003ff, "addc.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 61 | {0x02000000, 0x3e0e0001, "addi\t\t%20-24r, %1-16i"}, | |
| 62 | {0x02000001, 0x3e0e0001, "addi.c\t\t%20-24r, %1-16i"}, | |
| 63 | {0x0a000000, 0x3e0e0001, "addis\t\t%20-24r, %1-16d(0x%1-16x)"}, | |
| 64 | {0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"}, | |
| 65 | {0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"}, | |
| 66 | {0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"}, | |
| 67 | {0x00004800, 0x00007f00, "add!\t\t%4-7r, %0-3r"}, | |
| 68 | {0x00005c00, 0x00007c00, "addi!\t\t%6-9r, %0-5i"}, | |
| 69 | {0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"}, | |
| 70 | {0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 71 | {0x040000000000LL, 0x1c0000000003LL, "andri48\t\t%38-41r,%34-37r, 0x%2-33x"}, | |
| 72 | {0x040000000001LL, 0x1c0000000003LL, "andri48.c\t\t%38-41r,%34-37r, 0x%2-33x"}, | |
| 73 | {0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"}, | |
| 74 | {0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"}, | |
| 75 | {0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"}, | |
| 76 | {0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"}, | |
| 77 | {0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"}, | |
| 78 | {0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"}, | |
| 79 | {0x00004b00, 0x00007f00, "and!\t\t%4-7r, %0-3r"}, | |
| 80 | {0x08000000, 0x3e007c01, "bcs\t\t%b"}, | |
| 81 | {0x08000400, 0x3e007c01, "bcc\t\t%b"}, | |
| 82 | {0x08003800, 0x3e007c01, "bcnz\t\t%b"}, | |
| 83 | {0x08000001, 0x3e007c01, "bcsl\t\t%b"}, | |
| 84 | {0x08000401, 0x3e007c01, "bccl\t\t%b"}, | |
| 85 | {0x08003801, 0x3e007c01, "bcnzl\t\t%b"}, | |
| 86 | {0x0000004c, 0x3e00007e, "bcmpeqz\t\t%15-19r, %z"}, | |
| 87 | {0x0000004c, 0x3e00007e, "bcmpeq\t\t%15-19r, %z"}, | |
| 88 | {0x0000004e, 0x3e00007e, "bcmpnez\t\t%15-19r, %z"}, | |
| 89 | {0x0000004e, 0x3e00007e, "bcmpne\t\t%15-19r, %z"}, | |
| 90 | {0x00003200, 0x00007e00, "bcnz!\t\t%b"}, | |
| 91 | {0x08001000, 0x3e007c01, "beq\t\t%b"}, | |
| 92 | {0x08001001, 0x3e007c01, "beql\t\t%b"}, | |
| 93 | {0x00003800, 0x00007e00, "beq!\t\t%b"}, | |
| 94 | {0x08000800, 0x3e007c01, "bgtu\t\t%b"}, | |
| 95 | {0x08001800, 0x3e007c01, "bgt\t\t%b"}, | |
| 96 | {0x08002000, 0x3e007c01, "bge\t\t%b"}, | |
| 97 | {0x08000801, 0x3e007c01, "bgtul\t\t%b"}, | |
| 98 | {0x08001801, 0x3e007c01, "bgtl\t\t%b"}, | |
| 99 | {0x08002001, 0x3e007c01, "bgel\t\t%b"}, | |
| 100 | {0x00003400, 0x00007e00, "bgtu!\t\t%b"}, | |
| 101 | {0x00003c00, 0x00007e00, "bgt!\t\t%b"}, | |
| 102 | {0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"}, | |
| 103 | {0x00000028, 0x3e0003ff, "bitclr\t%20-24r, %15-19r, 0x%10-14x"}, | |
| 104 | {0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"}, | |
| 105 | {0x0000002a, 0x3e0003ff, "bitset\t%20-24r, %15-19r, 0x%10-14x"}, | |
| 106 | {0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"}, | |
| 107 | {0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"}, | |
| 108 | {0x0000002e, 0x3e0003ff, "bittgl\t%20-24r, %15-19r, 0x%10-14x"}, | |
| 109 | {0x00005000, 0x00007e00, "bitclr!\t\t%5-8r, 0x%0-4x"}, | |
| 110 | {0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"}, | |
| 111 | {0x00005200, 0x00007e00, "bitset!\t\t%5-8r, 0x%0-4x"}, | |
| 112 | {0x00005400, 0x00007e00, "bittst!\t\t%5-8r, 0x%0-4x"}, | |
| 113 | {0x00005600, 0x00007e00, "bittgl!\t\t%5-8r, 0x%0-4x"}, | |
| 114 | {0x08000c00, 0x3e007c01, "bleu\t\t%b"}, | |
| 115 | {0x08001c00, 0x3e007c01, "ble\t\t%b"}, | |
| 116 | {0x08002400, 0x3e007c01, "blt\t\t%b"}, | |
| 117 | {0x08000c01, 0x3e007c01, "bleul\t\t%b"}, | |
| 118 | {0x08001c01, 0x3e007c01, "blel\t\t%b"}, | |
| 119 | {0x08002401, 0x3e007c01, "bltl\t\t%b"}, | |
| 120 | {0x08003c01, 0x3e007c01, "bl\t\t%b"}, | |
| 121 | {0x00003600, 0x00007e00, "bleu!\t\t%b"}, | |
| 122 | {0x00003e00, 0x00007e00, "ble!\t\t%b"}, | |
| 123 | {0x08002800, 0x3e007c01, "bmi\t\t%b"}, | |
| 124 | {0x08002801, 0x3e007c01, "bmil\t\t%b"}, | |
| 125 | {0x08001400, 0x3e007c01, "bne\t\t%b"}, | |
| 126 | {0x08001401, 0x3e007c01, "bnel\t\t%b"}, | |
| 127 | {0x00003a00, 0x00007e00, "bne!\t\t%b"}, | |
| 128 | {0x08002c00, 0x3e007c01, "bpl\t\t%b"}, | |
| 129 | {0x08002c01, 0x3e007c01, "bpll\t\t%b"}, | |
| 130 | {0x00000008, 0x3e007fff, "brcs\t\t%15-19r"}, | |
| 131 | {0x00000408, 0x3e007fff, "brcc\t\t%15-19r"}, | |
| 132 | {0x00000808, 0x3e007fff, "brgtu\t\t%15-19r"}, | |
| 133 | {0x00000c08, 0x3e007fff, "brleu\t\t%15-19r"}, | |
| 134 | {0x00001008, 0x3e007fff, "breq\t\t%15-19r"}, | |
| 135 | {0x00001408, 0x3e007fff, "brne\t\t%15-19r"}, | |
| 136 | {0x00001808, 0x3e007fff, "brgt\t\t%15-19r"}, | |
| 137 | {0x00001c08, 0x3e007fff, "brle\t\t%15-19r"}, | |
| 138 | {0x00002008, 0x3e007fff, "brge\t\t%15-19r"}, | |
| 139 | {0x00002408, 0x3e007fff, "brlt\t\t%15-19r"}, | |
| 140 | {0x00002808, 0x3e007fff, "brmi\t\t%15-19r"}, | |
| 141 | {0x00002c08, 0x3e007fff, "brpl\t\t%15-19r"}, | |
| 142 | {0x00003008, 0x3e007fff, "brvs\t\t%15-19r"}, | |
| 143 | {0x00003408, 0x3e007fff, "brvc\t\t%15-19r"}, | |
| 144 | {0x00003808, 0x3e007fff, "brcnz\t\t%15-19r"}, | |
| 145 | {0x00003c08, 0x3e007fff, "br\t\t%15-19r"}, | |
| 146 | {0x00000009, 0x3e007fff, "brcsl\t\t%15-19r"}, | |
| 147 | {0x00000409, 0x3e007fff, "brccl\t\t%15-19r"}, | |
| 148 | {0x00000809, 0x3e007fff, "brgtul\t\t%15-19r"}, | |
| 149 | {0x00000c09, 0x3e007fff, "brleul\t\t%15-19r"}, | |
| 150 | {0x00001009, 0x3e007fff, "breql\t\t%15-19r"}, | |
| 151 | {0x00001409, 0x3e007fff, "brnel\t\t%15-19r"}, | |
| 152 | {0x00001809, 0x3e007fff, "brgtl\t\t%15-19r"}, | |
| 153 | {0x00001c09, 0x3e007fff, "brlel\t\t%15-19r"}, | |
| 154 | {0x00002009, 0x3e007fff, "brgel\t\t%15-19r"}, | |
| 155 | {0x00002409, 0x3e007fff, "brltl\t\t%15-19r"}, | |
| 156 | {0x00002809, 0x3e007fff, "brmil\t\t%15-19r"}, | |
| 157 | {0x00002c09, 0x3e007fff, "brpll\t\t%15-19r"}, | |
| 158 | {0x00003009, 0x3e007fff, "brvsl\t\t%15-19r"}, | |
| 159 | {0x00003409, 0x3e007fff, "brvcl\t\t%15-19r"}, | |
| 160 | {0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r"}, | |
| 161 | {0x00003c09, 0x3e007fff, "brl\t\t%15-19r"}, | |
| 162 | {0x00000080, 0x00007fe0, "br!\t\t%0-4r"}, | |
| 163 | {0x000000a0, 0x00007fe0, "brl!\t\t%0-4r"}, | |
| 164 | {0x000000c0, 0x00007fe0, "brr!\t\t%0-4r"}, | |
| 165 | {0x08003000, 0x3e007c01, "bvs\t\t%b"}, | |
| 166 | {0x08003400, 0x3e007c01, "bvc\t\t%b"}, | |
| 167 | {0x08003001, 0x3e007c01, "bvsl\t\t%b"}, | |
| 168 | {0x08003401, 0x3e007c01, "bvcl\t\t%b"}, | |
| 169 | {0x00003000, 0x00007e00, "b!\t\t%b"}, | |
| 170 | {0x08003c00, 0x3e007c01, "b\t\t%b"}, | |
| 171 | {0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 172 | {0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 173 | {0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 174 | {0x30300000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 175 | {0x30400000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 176 | {0x30800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 177 | {0x30900000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 178 | {0x30a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 179 | {0x30b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 180 | {0x30c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 181 | {0x30d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 182 | {0x30e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 183 | {0x31000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 184 | {0x31100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 185 | {0x31800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 186 | {0x31a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 187 | {0x31b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 188 | {0x31c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 189 | {0x31d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 190 | {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 191 | {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, | |
| 192 | {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"}, | |
| 193 | {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"}, | |
| 194 | {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"}, | |
| 195 | {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"}, | |
| 196 | {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"}, | |
| 197 | {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"}, | |
| 198 | {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"}, | |
| 199 | {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"}, | |
| 200 | {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"}, | |
| 201 | {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"}, | |
| 202 | {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"}, | |
| 203 | {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"}, | |
| 204 | {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"}, | |
| 205 | {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"}, | |
| 206 | {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"}, | |
| 207 | ||
| 208 | {0x00000064, 0x3e00007e, "mbitclr\t\t[%15-19r, %m], %10-14d"}, | |
| 209 | {0x0000006c, 0x3e00007e, "mbitset\t\t[%15-19r, %m], %10-14d"}, | |
| 210 | ||
| 211 | {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"}, | |
| 212 | {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"}, | |
| 213 | {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"}, | |
| 214 | {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"}, | |
| 215 | {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"}, | |
| 216 | {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"}, | |
| 217 | {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"}, | |
| 218 | {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"}, | |
| 219 | {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"}, | |
| 220 | {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"}, | |
| 221 | {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"}, | |
| 222 | {0x0000001c, 0x3e007fff, "clz\t\t%20-24r, %15-19r"}, | |
| 223 | {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"}, | |
| 224 | {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"}, | |
| 225 | {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"}, | |
| 226 | {0x00300019, 0x3ff003ff, "cmp.c\t\t%15-19r, %10-14r"}, | |
| 227 | {0x0000001b, 0x3ff07fff, "cmpzteq.c\t%15-19r"}, | |
| 228 | {0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"}, | |
| 229 | {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"}, | |
| 230 | {0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"}, | |
| 231 | {0x00004400, 0x00007c00, "cmp!\t\t%5-9r, %0-4r"}, | |
| 232 | {0x00006000, 0x00007c00, "cmpi!\t\t%5-9r, %0-4i"}, | |
| 233 | {0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, | |
| 234 | {0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, | |
| 235 | {0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, | |
| 236 | {0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"}, | |
| 237 | {0x00000144, 0x3e0003ff, "divr.q\t\t%20-24r,%15-19r, %10-14r"}, | |
| 238 | {0x00000244, 0x3e0003ff, "divr.r\t\t%20-24r,%15-19r, %10-14r"}, | |
| 239 | {0x00000344, 0x3e0003ff, "divr\t\t%20-24r,%15-19r, %10-14r"}, | |
| 240 | {0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"}, | |
| 241 | {0x00000146, 0x3e0003ff, "divur.q\t\t%20-24r,%15-19r, %10-14r"}, | |
| 242 | {0x00000246, 0x3e0003ff, "divur.r\t\t%20-24r,%15-19r, %10-14r"}, | |
| 243 | {0x00000346, 0x3e0003ff, "divur\t\t%20-24r,%15-19r, %10-14r"}, | |
| 244 | {0x0c0000a4, 0x3e0003ff, "drte"}, | |
| 245 | {0x00e0, 0xffe1, "disint!"}, | |
| 246 | {0x00e1, 0xffe1, "enint!"}, | |
| 247 | {0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"}, | |
| 248 | {0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"}, | |
| 249 | {0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"}, | |
| 250 | {0x0000005b, 0x3e0003ff, "extsh.c\t\t%20-24r, %15-19r"}, | |
| 251 | {0x0000005c, 0x3e0003ff, "extzb\t\t%20-24r, %15-19r"}, | |
| 252 | {0x0000005d, 0x3e0003ff, "extzb.c\t\t%20-24r, %15-19r"}, | |
| 253 | {0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"}, | |
| 254 | {0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"}, | |
| 255 | {0x04000001, 0x3e000001, "jl\t\t%j"}, | |
| 256 | {0x04000000, 0x3e000001, "j\t\t%j"}, | |
| 257 | {0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"}, | |
| 258 | {0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"}, | |
| 259 | {0x06000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r, %3-14i]+"}, | |
| 260 | {0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"}, | |
| 261 | {0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"}, | |
| 262 | {0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"}, | |
| 263 | {0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"}, | |
| 264 | {0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"}, | |
| 265 | {0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"}, | |
| 266 | {0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"}, | |
| 267 | {0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"}, | |
| 268 | {0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"}, | |
| 269 | {0x000000000001LL, 0x1c000000001fLL, "ldi48\t\t%37-41r, %5-36i"}, | |
| 270 | {0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"}, | |
| 271 | {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"}, | |
| 272 | {0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"}, | |
| 273 | {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"}, | |
| 274 | {0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"}, | |
| 275 | {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"}, | |
| 276 | {0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"}, | |
| 277 | {0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"}, | |
| 278 | {0x00006400, 0x00007c00, "ldiu!\t\t%5-9r, %0-4d"}, | |
| 279 | {0x00000032, 0x3e0003ff, "ltbw\t\t%20-24r, [%15-19r, %10-14r]"}, | |
| 280 | {0x00000132, 0x3e0003ff, "ltbh\t\t%20-24r, [%15-19r, %10-14r]"}, | |
| 281 | {0x00000332, 0x3e0003ff, "ltbb\t\t%20-24r, [%15-19r, %10-14r]"}, | |
| 282 | {0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"}, | |
| 283 | {0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"}, | |
| 284 | {0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"}, | |
| 285 | {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"}, | |
| 286 | {0x00001000, 0x00007000, "lw!\t\t%8-11r, [%5-7r,%0-4d2]"}, | |
| 287 | {0x000000000002LL, 0x1c000000001fLL, "lw48\t\t%37-41r,[0x%7-36w]"}, | |
| 288 | {0x00007a00, 0x00007f00, "madl.fs!\t\t%4-7r, %0-3r"}, | |
| 289 | {0x00007500, 0x00007f00, "madu!\t\t%4-7r, %0-3r"}, | |
| 290 | {0x00007400, 0x00007f00, "mad.f!\t\t%4-7r, %0-3r"}, | |
| 291 | {0x00007900, 0x00007f00, "mazh.f!\t\t%4-7r, %0-3r"}, | |
| 292 | {0x00007800, 0x00007f00, "mazl.f!\t\t%4-7r, %0-3r"}, | |
| 293 | {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"}, | |
| 294 | {0x00007100, 0x00007ff0, "mfcel!\t\t%0-3r"}, | |
| 295 | {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"}, | |
| 296 | {0x00007110, 0x00007ff0, "mfceh!\t\t%0-3r"}, | |
| 297 | {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"}, | |
| 298 | {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"}, | |
| 299 | {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"}, | |
| 300 | {0x0c000001, 0x3e00001f, "mfcr\t\t%20-24r, c%15-19r"}, | |
| 301 | {0x0c000009, 0x3e00001f, "mfc1\t\t%20-24r, c%15-19r"}, | |
| 302 | {0x0c000011, 0x3e00001f, "mfc2\t\t%20-24r, c%15-19r"}, | |
| 303 | {0x0c000019, 0x3e00001f, "mfc3\t\t%20-24r, c%15-19r"}, | |
| 304 | {0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"}, | |
| 305 | {0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"}, | |
| 306 | {0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"}, | |
| 307 | /* confilct: push! mhfl!. */ | |
| 308 | {0x00000040, 0x00007fe0, "pop!\t\t%0-4r"}, | |
| 309 | {0x00000060, 0x00007fe0, "push!\t\t%0-4r"}, | |
| 310 | {0x00006800, 0x00007c00, "rpop!\t\t%5-9r, %0-4d"}, | |
| 311 | {0x00006c00, 0x00007c00, "rpush!\t\t%5-9r, %0-4d"}, | |
| 312 | {0x00007600, 0x00007f00, "msb.f!\t\t%4-7r, %0-3r"}, | |
| 313 | {0x00007f00, 0x00007f00, "msbh.fs!\t\t%4-7r, %0-3r"}, | |
| 314 | {0x00007e00, 0x00007f00, "msbl.fs!\t\t%4-7r, %0-3r"}, | |
| 315 | {0x00007700, 0x00007f00, "msbu!\t\t%4-7r, %0-3r"}, | |
| 316 | {0x00007d00, 0x00007f00, "mszh.f!\t\t%4-7r, %0-3r"}, | |
| 317 | {0x00007c00, 0x00007f00, "mszl.f!\t\t%4-7r, %0-3r"}, | |
| 318 | {0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"}, | |
| 319 | {0x00007000, 0x00007ff0, "mtcel!\t\t%0-3r"}, | |
| 320 | {0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"}, | |
| 321 | {0x00007010, 0x00007ff0, "mtceh!\t\t%0-3r"}, | |
| 322 | {0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"}, | |
| 323 | {0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"}, | |
| 324 | {0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"}, | |
| 325 | {0x0c000000, 0x3e00001f, "mtcr\t\t%20-24r, c%15-19r"}, | |
| 326 | {0x0c000008, 0x3e00001f, "mtc1\t\t%20-24r, c%15-19r"}, | |
| 327 | {0x0c000010, 0x3e00001f, "mtc2\t\t%20-24r, c%15-19r"}, | |
| 328 | {0x0c000018, 0x3e00001f, "mtc3\t\t%20-24r, c%15-19r"}, | |
| 329 | {0x0c00000e, 0x3e00001f, "mtcc1\t\t%20-24r, c%15-19r"}, | |
| 330 | {0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"}, | |
| 331 | {0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"}, | |
| 332 | {0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"}, | |
| 333 | {0x00000140, 0x3e0003ff, "mulr.l\t\t%20-24r,%15-19r, %10-14r"}, | |
| 334 | {0x00000240, 0x3e0003ff, "mulr.h\t\t%20-24r,%15-19r, %10-14r"}, | |
| 335 | {0x00000340, 0x3e0003ff, "mulr\t\t%20-24r,%15-19r, %10-14r"}, | |
| 336 | {0x00000141, 0x3e0003ff, "mulr.lf\t\t%20-24r,%15-19r, %10-14r"}, | |
| 337 | {0x00000241, 0x3e0003ff, "mulr.hf\t\t%20-24r,%15-19r, %10-14r"}, | |
| 338 | {0x00000341, 0x3e0003ff, "mulr.f\t\t%20-24r,%15-19r, %10-14r"}, | |
| 339 | {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"}, | |
| 340 | {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"}, | |
| 341 | {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"}, | |
| 342 | {0x00007200, 0x00007f00, "mul.f!\t\t%4-7r, %0-3r"}, | |
| 343 | {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"}, | |
| 344 | {0x00000142, 0x3e0003ff, "mulur.l\t\t%20-24r,%15-19r, %10-14r"}, | |
| 345 | {0x00000242, 0x3e0003ff, "mulur.h\t\t%20-24r,%15-19r, %10-14r"}, | |
| 346 | {0x00000342, 0x3e0003ff, "mulur\t\t%20-24r,%15-19r, %10-14r"}, | |
| 347 | {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"}, | |
| 348 | {0x00007300, 0x00007f00, "mulu!\t\t%4-7r, %0-3r"}, | |
| 349 | {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"}, | |
| 350 | {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"}, | |
| 351 | {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"}, | |
| 352 | {0x00000c56, 0x3e007fff, "mvleu\t\t%20-24r, %15-19r"}, | |
| 353 | {0x00001056, 0x3e007fff, "mveq\t\t%20-24r, %15-19r"}, | |
| 354 | {0x00001456, 0x3e007fff, "mvne\t\t%20-24r, %15-19r"}, | |
| 355 | {0x00001856, 0x3e007fff, "mvgt\t\t%20-24r, %15-19r"}, | |
| 356 | {0x00001c56, 0x3e007fff, "mvle\t\t%20-24r, %15-19r"}, | |
| 357 | {0x00002056, 0x3e007fff, "mvge\t\t%20-24r, %15-19r"}, | |
| 358 | {0x00002456, 0x3e007fff, "mvlt\t\t%20-24r, %15-19r"}, | |
| 359 | {0x00002856, 0x3e007fff, "mvmi\t\t%20-24r, %15-19r"}, | |
| 360 | {0x00002c56, 0x3e007fff, "mvpl\t\t%20-24r, %15-19r"}, | |
| 361 | {0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"}, | |
| 362 | {0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"}, | |
| 363 | {0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"}, | |
| 364 | {0x00004000, 0x00007c00, "mv!\t\t%5-9r, %0-4r"}, | |
| 365 | {0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r"}, | |
| 366 | {0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r"}, | |
| 367 | {0x00000000, 0x3e0003ff, "nop"}, | |
| 368 | {0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r"}, | |
| 369 | {0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r"}, | |
| 370 | {0x00000000, 0x00007fff, "nop!"}, | |
| 371 | {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"}, | |
| 372 | {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 373 | {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"}, | |
| 374 | {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"}, | |
| 375 | {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"}, | |
| 376 | {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"}, | |
| 377 | {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"}, | |
| 378 | {0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"}, | |
| 379 | {0x00004a00, 0x00007f00, "or!\t\t%4-7r, %0-3r"}, | |
| 380 | {0x040000000002LL, 0x1c0000000003LL, "orri48\t\t%38-41r,%34-37r, 0x%2-33x"}, | |
| 381 | {0x040000000003LL, 0x1c0000000003LL, "orri48.c\t\t%38-41r,%34-37r, 0x%2-33x"}, | |
| 382 | {0x0000000a, 0x3e0003ff, "pflush"}, | |
| 383 | {0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"}, | |
| 384 | {0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 385 | {0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 386 | {0x0000003c, 0x3e0003ff, "rol\t\t%20-24r, %15-19r, %10-14r"}, | |
| 387 | {0x0000003d, 0x3e0003ff, "rol.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 388 | {0x0000003f, 0x3e0003ff, "rolc.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 389 | {0x00000078, 0x3e0003ff, "rori\t\t%20-24r, %15-19r, %10-14d"}, | |
| 390 | {0x00000079, 0x3e0003ff, "rori.c\t\t%20-24r, %15-19r, %10-14d"}, | |
| 391 | {0x0000007b, 0x3e0003ff, "roric.c\t\t%20-24r, %15-19r, %10-14d"}, | |
| 392 | {0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"}, | |
| 393 | {0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"}, | |
| 394 | {0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"}, | |
| 395 | {0x0c000084, 0x3e0003ff, "rte"}, | |
| 396 | {0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"}, | |
| 397 | {0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"}, | |
| 398 | {0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"}, | |
| 399 | {0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"}, | |
| 400 | {0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"}, | |
| 401 | {0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"}, | |
| 402 | {0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"}, | |
| 403 | {0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"}, | |
| 404 | {0x00000020, 0x00007fe0, "sdbbp!\t\t%0-4d"}, | |
| 405 | {0x000000000000LL, 0x1c000000001fLL, "sdbbp48\t\t%5-9d"}, | |
| 406 | {0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"}, | |
| 407 | {0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"}, | |
| 408 | {0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"}, | |
| 409 | {0x0c0000c4, 0x3e0003ff, "sleep"}, | |
| 410 | {0x0c0000e4, 0x3e0003ff, "rti"}, | |
| 411 | {0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"}, | |
| 412 | {0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 413 | {0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"}, | |
| 414 | {0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"}, | |
| 415 | {0x00005800, 0x00007e00, "slli!\t\t%5-8r, %0-4d"}, | |
| 416 | {0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"}, | |
| 417 | {0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 418 | {0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"}, | |
| 419 | {0x00000037, 0x3e0003ff, "sra.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 420 | {0x00000074, 0x3e0003ff, "srli\t\t%20-24r, %15-19r, %10-14d"}, | |
| 421 | {0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"}, | |
| 422 | {0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"}, | |
| 423 | {0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"}, | |
| 424 | {0x00005a00, 0x00007e00, "srli!\t\t%5-8r, %0-4d"}, | |
| 425 | {0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"}, | |
| 426 | {0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"}, | |
| 427 | {0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"}, | |
| 428 | {0x00000014, 0x3e0003ff, "sub\t\t%20-24r, %15-19r, %10-14r"}, | |
| 429 | {0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 430 | {0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"}, | |
| 431 | {0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 432 | {0x00004900, 0x00007f00, "sub!\t\t%4-7r, %0-3r"}, | |
| 433 | {0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"}, | |
| 434 | {0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"}, | |
| 435 | {0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"}, | |
| 436 | {0x00002000, 0x00007000, "sw!\t\t%8-11r, [%5-7r,%0-4d2]"}, | |
| 437 | {0x000000000003LL, 0x1c000000001fLL, "sw48\t\t%37-41r, [0x%7-36w]"}, | |
| 438 | {0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"}, | |
| 439 | {0x00000054, 0x3e007fff, "tcs"}, | |
| 440 | {0x00000454, 0x3e007fff, "tcc"}, | |
| 441 | {0x00003854, 0x3e007fff, "tcnz"}, | |
| 442 | {0x00001054, 0x3e007fff, "teq"}, | |
| 443 | {0x00000854, 0x3e007fff, "tgtu"}, | |
| 444 | {0x00001854, 0x3e007fff, "tgt"}, | |
| 445 | {0x00002054, 0x3e007fff, "tge"}, | |
| 446 | {0x00000c54, 0x3e007fff, "tleu"}, | |
| 447 | {0x00001c54, 0x3e007fff, "tle"}, | |
| 448 | {0x00002454, 0x3e007fff, "tlt"}, | |
| 449 | {0x0c000004, 0x3e0003ff, "stlb"}, | |
| 450 | {0x0c000024, 0x3e0003ff, "mftlb"}, | |
| 451 | {0x0c000044, 0x3e0003ff, "mtptlb"}, | |
| 452 | {0x0c000064, 0x3e0003ff, "mtrtlb"}, | |
| 453 | {0x00002854, 0x3e007fff, "tmi"}, | |
| 454 | {0x00001454, 0x3e007fff, "tne"}, | |
| 455 | {0x00002c54, 0x3e007fff, "tpl"}, | |
| 456 | {0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"}, | |
| 457 | {0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"}, | |
| 458 | {0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"}, | |
| 459 | {0x00000c04, 0x3e007fff, "trapleu\t\t%15-19d"}, | |
| 460 | {0x00001004, 0x3e007fff, "trapeq\t\t%15-19d"}, | |
| 461 | {0x00001404, 0x3e007fff, "trapne\t\t%15-19d"}, | |
| 462 | {0x00001804, 0x3e007fff, "trapgt\t\t%15-19d"}, | |
| 463 | {0x00001c04, 0x3e007fff, "traple\t\t%15-19d"}, | |
| 464 | {0x00002004, 0x3e007fff, "trapge\t\t%15-19d"}, | |
| 465 | {0x00002404, 0x3e007fff, "traplt\t\t%15-19d"}, | |
| 466 | {0x00002804, 0x3e007fff, "trapmi\t\t%15-19d"}, | |
| 467 | {0x00002c04, 0x3e007fff, "trappl\t\t%15-19d"}, | |
| 468 | {0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"}, | |
| 469 | {0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"}, | |
| 470 | {0x00003c04, 0x3e007fff, "trap\t\t%15-19d"}, | |
| 471 | {0x00003c54, 0x3e007fff, "tset"}, | |
| 472 | {0x00003054, 0x3e007fff, "tvs"}, | |
| 473 | {0x00003454, 0x3e007fff, "tvc"}, | |
| 474 | {0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"}, | |
| 475 | {0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"}, | |
| 476 | }; | |
| 02b1cb40 | 477 | \f |
| c3b7224a | 478 | |
| 1c0d3aa6 | 479 | #ifndef streq |
| c3b7224a | 480 | #define streq(a,b) (strcmp ((a), (b)) == 0) |
| 1c0d3aa6 NC |
481 | #endif |
| 482 | ||
| 483 | #ifndef strneq | |
| c3b7224a | 484 | #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) |
| 1c0d3aa6 NC |
485 | #endif |
| 486 | ||
| 487 | #ifndef NUM_ELEM | |
| 488 | #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) | |
| 489 | #endif | |
| 490 | ||
| 491 | typedef struct | |
| 492 | { | |
| 493 | const char *name; | |
| 494 | const char *description; | |
| 495 | const char *reg_names[32]; | |
| 496 | } score_regname; | |
| 497 | ||
| 498 | static score_regname regnames[] = | |
| 499 | { | |
| 500 | {"gcc", "Select register names used by GCC", | |
| 501 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", | |
| 502 | "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", | |
| 503 | "r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}}, | |
| 504 | }; | |
| 505 | ||
| 506 | static unsigned int regname_selected = 0; | |
| 507 | ||
| 508 | #define NUM_SCORE_REGNAMES NUM_ELEM (regnames) | |
| 509 | #define score_regnames regnames[regname_selected].reg_names | |
| 510 | ||
| c3b7224a NC |
511 | /* Print one instruction from PC on INFO->STREAM. |
| 512 | Return the size of the instruction. */ | |
| 513 | static int | |
| 514 | print_insn_score48 (struct disassemble_info *info, bfd_vma given) | |
| 515 | { | |
| 516 | struct score_opcode *insn; | |
| 517 | void *stream = info->stream; | |
| 518 | fprintf_ftype func = info->fprintf_func; | |
| 519 | ||
| 520 | for (insn = score_opcodes; insn->assembler; insn++) | |
| 521 | { | |
| 02b1cb40 | 522 | /* Using insn->mask &0xff00000000 to distinguish 48/32 bit. */ |
| c3b7224a NC |
523 | if (((insn->mask & 0xff0000000000LL)!=0) && (given & insn->mask) == insn->value) |
| 524 | { | |
| 525 | info->bytes_per_chunk = 2; | |
| 526 | info->bytes_per_line =6; | |
| 527 | ||
| 528 | char *c; | |
| 529 | ||
| 530 | for (c = insn->assembler; *c; c++) | |
| 531 | { | |
| 532 | if (*c == '%') | |
| 533 | { | |
| 534 | switch (*++c) | |
| 535 | { | |
| 536 | case '0': | |
| 537 | case '1': | |
| 538 | case '2': | |
| 539 | case '3': | |
| 540 | case '4': | |
| 541 | case '5': | |
| 542 | case '6': | |
| 543 | case '7': | |
| 544 | case '8': | |
| 545 | case '9': | |
| 546 | { | |
| 547 | int bitstart = *c++ - '0'; | |
| 548 | int bitend = 0; | |
| 549 | ||
| 550 | while (*c >= '0' && *c <= '9') | |
| 551 | bitstart = (bitstart * 10) + *c++ - '0'; | |
| 552 | ||
| 553 | switch (*c) | |
| 554 | { | |
| 555 | case '-': | |
| 556 | c++; | |
| 557 | while (*c >= '0' && *c <= '9') | |
| 558 | bitend = (bitend * 10) + *c++ - '0'; | |
| 559 | ||
| 560 | if (!bitend) | |
| 561 | abort (); | |
| 562 | ||
| 563 | switch (*c) | |
| 564 | { | |
| 565 | case 'r': | |
| 566 | { | |
| 567 | long reg; | |
| 568 | ||
| 569 | reg = given >> bitstart; | |
| 570 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 571 | ||
| 572 | func (stream, "%s", score_regnames[reg]); | |
| 573 | } | |
| 574 | break; | |
| 575 | case 'd': | |
| 576 | { | |
| 577 | long reg; | |
| 578 | ||
| 579 | reg = given >> bitstart; | |
| 580 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 581 | ||
| 582 | func (stream, "%ld", reg); | |
| 583 | } | |
| 584 | break; | |
| 585 | case 'i': | |
| 586 | { | |
| 587 | long reg; | |
| 588 | reg = given >> bitstart; | |
| 589 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 590 | reg = ((reg ^ (1 << (bitend - bitstart))) - | |
| 591 | (1 << (bitend - bitstart))); | |
| 592 | /* Fix bug: s3_testsuite 64-bit. | |
| 593 | Remove high 32 bits. */ | |
| 594 | reg = (int) reg; | |
| 595 | ||
| 596 | if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ | |
| 597 | || ((given & insn->mask) == 0x0c000012) /* ldc2 */ | |
| 598 | || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ | |
| 599 | || ((given & insn->mask) == 0x0c00000b) /* stc1 */ | |
| 600 | || ((given & insn->mask) == 0x0c000013) /* stc2 */ | |
| 601 | || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ | |
| 602 | reg <<= 2; | |
| 603 | ||
| 604 | func (stream, "%ld", reg); | |
| 605 | } | |
| 606 | break; | |
| 607 | case 'x': | |
| 608 | { | |
| 609 | long reg; | |
| 610 | ||
| 611 | reg = given >> bitstart; | |
| 612 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 613 | /* Fix bug: s3_testsuite 64-bit. | |
| 614 | Remove high 32 bits. */ | |
| 615 | reg = (int) reg; | |
| 616 | ||
| 617 | func (stream, "%lx", reg); | |
| 618 | } | |
| 619 | break; | |
| 620 | case 'w': | |
| 621 | { | |
| 622 | long reg; | |
| 623 | reg = given >> bitstart; | |
| 624 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 625 | reg <<=2; | |
| 626 | func (stream, "%lx", reg); | |
| 627 | } | |
| 628 | break; | |
| 629 | ||
| 630 | default: | |
| 631 | abort (); | |
| 632 | } | |
| 633 | break; | |
| 634 | ||
| 635 | case '`': | |
| 636 | c++; | |
| 637 | if ((given & (1 << bitstart)) == 0) | |
| 638 | func (stream, "%c", *c); | |
| 639 | break; | |
| 640 | case '\'': | |
| 641 | c++; | |
| 642 | if ((given & (1 << bitstart)) != 0) | |
| 643 | func (stream, "%c", *c); | |
| 644 | break; | |
| 645 | default: | |
| 646 | abort (); | |
| 647 | } | |
| 648 | break; | |
| 649 | ||
| 650 | default: | |
| 651 | abort (); | |
| 652 | } | |
| 653 | } | |
| 654 | } | |
| 655 | else | |
| 656 | func (stream, "%c", *c); | |
| 657 | } | |
| 658 | return 6; | |
| 659 | } | |
| 660 | } | |
| 661 | ||
| 662 | #if (SCORE_SIMULATOR_ACTIVE) | |
| 663 | func (stream, _("<illegal instruction>")); | |
| 664 | return 6; | |
| 665 | #endif | |
| 02b1cb40 | 666 | |
| c3b7224a NC |
667 | abort (); |
| 668 | } | |
| 669 | ||
| 1c0d3aa6 NC |
670 | /* Print one instruction from PC on INFO->STREAM. |
| 671 | Return the size of the instruction. */ | |
| 672 | static int | |
| 673 | print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given) | |
| 674 | { | |
| 675 | struct score_opcode *insn; | |
| 676 | void *stream = info->stream; | |
| 02b1cb40 | 677 | int rb_equal_zero=1; |
| 1c0d3aa6 NC |
678 | fprintf_ftype func = info->fprintf_func; |
| 679 | ||
| 680 | for (insn = score_opcodes; insn->assembler; insn++) | |
| 681 | { | |
| c3b7224a | 682 | if (((insn->mask & 0xff0000000000LL)==0)&&(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) |
| 1c0d3aa6 | 683 | { |
| c3b7224a NC |
684 | /* check for bcmpeq / bcmpeqz / bcmpne / bcmpnez */ |
| 685 | /* given &0x7c00 is for to test if rb is zero , | |
| 686 | rb_equal_zero =1 : index to bcmpeqz | |
| 687 | rb_equal_zero =0 , index to bcmpeq | |
| 688 | this checking rule only for branch compare ( insn->mask ==0x3e00007e*/ | |
| 689 | if (((given & 0x7c00) !=0)&&(rb_equal_zero ==1)&&(insn->mask == 0x3e00007e) | |
| 690 | && (insn->value == 0x0000004c || insn->value == 0x0000004e)) | |
| 691 | { | |
| 692 | rb_equal_zero =0; | |
| 693 | continue; | |
| 694 | } | |
| 695 | ||
| 1c0d3aa6 NC |
696 | char *c; |
| 697 | ||
| 698 | for (c = insn->assembler; *c; c++) | |
| 699 | { | |
| 700 | if (*c == '%') | |
| 701 | { | |
| 702 | switch (*++c) | |
| 703 | { | |
| 704 | case 'j': | |
| 705 | { | |
| 706 | int target; | |
| 707 | ||
| 708 | if (info->flags & INSN_HAS_RELOC) | |
| 709 | pc = 0; | |
| 710 | target = (pc & 0xfe000000) | (given & 0x01fffffe); | |
| 711 | (*info->print_address_func) (target, info); | |
| 712 | } | |
| 713 | break; | |
| 714 | case 'b': | |
| 715 | { | |
| 716 | /* Sign-extend a 20-bit number. */ | |
| 717 | #define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000) | |
| 718 | int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe); | |
| 719 | int target = (pc + SEXT20 (disp)); | |
| 720 | ||
| 721 | (*info->print_address_func) (target, info); | |
| 722 | } | |
| 723 | break; | |
| c3b7224a NC |
724 | case 'z': |
| 725 | { | |
| 726 | #define SEXT10(x) ((((x) & 0x3ff) ^ (~ 0x1ff)) + 0x200) | |
| 727 | if ((given & 0x7c00 ) == 0) | |
| 728 | { | |
| 729 | /* Sign-extend a 20-bit number. */ | |
| 730 | /* disp : [24 -20] , [9-7 ] , [0] */ | |
| 731 | int disp = (given&1)<<1 |((given>>7)&7)<<2 |((given>>20)&0x1f)<<5; | |
| 732 | int target = (pc + SEXT10 (disp)); | |
| 733 | (*info->print_address_func) (target, info); | |
| 734 | } | |
| 735 | else | |
| 736 | { | |
| 737 | long reg; | |
| 738 | int bitstart = 10; | |
| 739 | int bitend = 14; | |
| 740 | reg = given >> bitstart; | |
| 741 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 742 | /* Sign-extend a 20-bit number. */ | |
| 743 | int disp = (given&1)<<1 |((given>>7)&7)<<2 |((given>>20)&0x1f)<<5; | |
| 744 | int target = (pc + SEXT10 (disp)); | |
| 745 | func (stream, "%s ,", score_regnames[reg] ); | |
| 746 | (*info->print_address_func) (target, info); | |
| 747 | ||
| 748 | } | |
| 749 | ||
| 750 | } | |
| 751 | break; | |
| 752 | case 'm': | |
| 753 | { | |
| 754 | /* disp : [24 -20] , [9-7 ] , [0] */ | |
| 755 | int disp = (given&1)<<2 |((given>>7)&7)<<3 |((given>>20)&0x1f)<<6; | |
| 756 | (*info->print_address_func) (disp, info); | |
| 757 | } | |
| 758 | break; | |
| 1c0d3aa6 NC |
759 | case '0': |
| 760 | case '1': | |
| 761 | case '2': | |
| 762 | case '3': | |
| 763 | case '4': | |
| 764 | case '5': | |
| 765 | case '6': | |
| 766 | case '7': | |
| 767 | case '8': | |
| 768 | case '9': | |
| 769 | { | |
| 770 | int bitstart = *c++ - '0'; | |
| 771 | int bitend = 0; | |
| 772 | ||
| 773 | while (*c >= '0' && *c <= '9') | |
| 774 | bitstart = (bitstart * 10) + *c++ - '0'; | |
| 775 | ||
| 776 | switch (*c) | |
| 777 | { | |
| 778 | case '-': | |
| 779 | c++; | |
| 780 | while (*c >= '0' && *c <= '9') | |
| 781 | bitend = (bitend * 10) + *c++ - '0'; | |
| 782 | ||
| 783 | if (!bitend) | |
| 784 | abort (); | |
| 785 | ||
| 786 | switch (*c) | |
| 787 | { | |
| 788 | case 'r': | |
| 789 | { | |
| 790 | long reg; | |
| 791 | ||
| 792 | reg = given >> bitstart; | |
| 793 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 794 | ||
| 795 | func (stream, "%s", score_regnames[reg]); | |
| 796 | } | |
| 797 | break; | |
| 798 | case 'd': | |
| 799 | { | |
| 800 | long reg; | |
| 801 | ||
| 802 | reg = given >> bitstart; | |
| 803 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 804 | ||
| 805 | func (stream, "%ld", reg); | |
| 806 | } | |
| 807 | break; | |
| 808 | case 'i': | |
| 809 | { | |
| 810 | long reg; | |
| 811 | ||
| 812 | reg = given >> bitstart; | |
| 813 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 814 | reg = ((reg ^ (1 << (bitend - bitstart))) - | |
| 815 | (1 << (bitend - bitstart))); | |
| 816 | ||
| 817 | if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ | |
| 818 | || ((given & insn->mask) == 0x0c000012) /* ldc2 */ | |
| 819 | || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ | |
| 820 | || ((given & insn->mask) == 0x0c00000b) /* stc1 */ | |
| 821 | || ((given & insn->mask) == 0x0c000013) /* stc2 */ | |
| 822 | || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ | |
| 823 | reg <<= 2; | |
| 824 | ||
| 825 | func (stream, "%ld", reg); | |
| 826 | } | |
| 827 | break; | |
| 828 | case 'x': | |
| 829 | { | |
| 830 | long reg; | |
| 831 | ||
| 832 | reg = given >> bitstart; | |
| 833 | reg &= (2 << (bitend - bitstart)) - 1; | |
| 834 | ||
| 835 | func (stream, "%lx", reg); | |
| 836 | } | |
| 837 | break; | |
| 838 | default: | |
| 839 | abort (); | |
| 840 | } | |
| 841 | break; | |
| c3b7224a | 842 | |
| 1c0d3aa6 NC |
843 | case '`': |
| 844 | c++; | |
| 845 | if ((given & (1 << bitstart)) == 0) | |
| 846 | func (stream, "%c", *c); | |
| 847 | break; | |
| 848 | case '\'': | |
| 849 | c++; | |
| 850 | if ((given & (1 << bitstart)) != 0) | |
| 851 | func (stream, "%c", *c); | |
| 852 | break; | |
| 853 | default: | |
| 854 | abort (); | |
| 855 | } | |
| 856 | break; | |
| 857 | ||
| 858 | default: | |
| 859 | abort (); | |
| 860 | } | |
| 861 | } | |
| 862 | } | |
| 863 | else | |
| 864 | func (stream, "%c", *c); | |
| 865 | } | |
| 866 | return 4; | |
| 867 | } | |
| 868 | } | |
| 869 | ||
| 870 | #if (SCORE_SIMULATOR_ACTIVE) | |
| 871 | func (stream, _("<illegal instruction>")); | |
| 872 | return 4; | |
| 873 | #endif | |
| 874 | ||
| 875 | abort (); | |
| 876 | } | |
| 877 | ||
| 1c0d3aa6 NC |
878 | /* Print one instruction from PC on INFO->STREAM. |
| 879 | Return the size of the instruction. */ | |
| 880 | static int | |
| 881 | print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given) | |
| 882 | { | |
| 883 | struct score_opcode *insn; | |
| 884 | void *stream = info->stream; | |
| 885 | fprintf_ftype func = info->fprintf_func; | |
| 886 | ||
| 887 | given &= 0xffff; | |
| 888 | for (insn = score_opcodes; insn->assembler; insn++) | |
| 889 | { | |
| c3b7224a | 890 | if (((insn->mask & 0xff0000000000LL)==0) &&!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) |
| 1c0d3aa6 NC |
891 | { |
| 892 | char *c = insn->assembler; | |
| 893 | ||
| 894 | info->bytes_per_chunk = 2; | |
| 895 | info->bytes_per_line = 4; | |
| 896 | given &= 0xffff; | |
| 897 | ||
| 898 | for (; *c; c++) | |
| 899 | { | |
| 900 | if (*c == '%') | |
| 901 | { | |
| 902 | switch (*++c) | |
| 903 | { | |
| 904 | ||
| 905 | case 'j': | |
| 906 | { | |
| 907 | int target; | |
| 908 | ||
| 909 | if (info->flags & INSN_HAS_RELOC) | |
| 910 | pc = 0; | |
| 911 | ||
| 912 | target = (pc & 0xfffff000) | (given & 0x00000ffe); | |
| 913 | (*info->print_address_func) (target, info); | |
| 914 | } | |
| 915 | break; | |
| 916 | case 'b': | |
| 917 | { | |
| 918 | /* Sign-extend a 9-bit number. */ | |
| c3b7224a NC |
919 | #define SEXT10(x) ((((x) & 0x3ff) ^ (~ 0x1ff)) + 0x200) |
| 920 | int disp = (given & 0x1ff) << 1; | |
| 921 | int target = (pc + SEXT10 (disp)); | |
| 1c0d3aa6 NC |
922 | |
| 923 | (*info->print_address_func) (target, info); | |
| 924 | } | |
| 925 | break; | |
| 926 | ||
| 927 | case '0': | |
| 928 | case '1': | |
| 929 | case '2': | |
| 930 | case '3': | |
| 931 | case '4': | |
| 932 | case '5': | |
| 933 | case '6': | |
| 934 | case '7': | |
| 935 | case '8': | |
| 936 | case '9': | |
| 937 | { | |
| 938 | int bitstart = *c++ - '0'; | |
| 939 | int bitend = 0; | |
| 940 | ||
| 941 | while (*c >= '0' && *c <= '9') | |
| 942 | bitstart = (bitstart * 10) + *c++ - '0'; | |
| 943 | ||
| 944 | switch (*c) | |
| 945 | { | |
| 946 | case '-': | |
| 947 | { | |
| 948 | long reg; | |
| 949 | ||
| 950 | c++; | |
| 951 | while (*c >= '0' && *c <= '9') | |
| 952 | bitend = (bitend * 10) + *c++ - '0'; | |
| 953 | if (!bitend) | |
| 954 | abort (); | |
| 955 | reg = given >> bitstart; | |
| 956 | reg &= (2 << (bitend - bitstart)) - 1; | |
| c3b7224a NC |
957 | |
| 958 | /* Check rpush rd, 0 and rpop! rd, 0. | |
| 959 | If reg = 0, then set to 32. */ | |
| 960 | if (((given & 0x00007c00) == 0x00006c00 | |
| 961 | || (given & 0x00007c00) == 0x00006800) | |
| 962 | && reg == 0) | |
| 963 | { | |
| 964 | reg = 32; | |
| 965 | } | |
| 966 | ||
| 1c0d3aa6 NC |
967 | switch (*c) |
| 968 | { | |
| 969 | case 'R': | |
| 970 | func (stream, "%s", score_regnames[reg + 16]); | |
| 971 | break; | |
| 972 | case 'r': | |
| 973 | func (stream, "%s", score_regnames[reg]); | |
| 974 | break; | |
| 975 | case 'd': | |
| 976 | if (*(c + 1) == '\0') | |
| 977 | func (stream, "%ld", reg); | |
| 978 | else | |
| 979 | { | |
| 980 | c++; | |
| 981 | if (*c == '1') | |
| 982 | func (stream, "%ld", reg << 1); | |
| 983 | else if (*c == '2') | |
| 984 | func (stream, "%ld", reg << 2); | |
| 985 | } | |
| 986 | break; | |
| 987 | ||
| 988 | case 'x': | |
| 989 | if (*(c + 1) == '\0') | |
| 990 | func (stream, "%lx", reg); | |
| 991 | else | |
| 992 | { | |
| 993 | c++; | |
| 994 | if (*c == '1') | |
| 995 | func (stream, "%lx", reg << 1); | |
| 996 | else if (*c == '2') | |
| 997 | func (stream, "%lx", reg << 2); | |
| 998 | } | |
| 999 | break; | |
| 1000 | case 'i': | |
| c3b7224a NC |
1001 | reg = ((reg ^ (1 << bitend)) - (1 << bitend)); |
| 1002 | func (stream, "%ld", reg); | |
| 1c0d3aa6 NC |
1003 | break; |
| 1004 | default: | |
| 1005 | abort (); | |
| 1006 | } | |
| 1007 | } | |
| 1008 | break; | |
| 1009 | ||
| 1010 | case '\'': | |
| 1011 | c++; | |
| 1012 | if ((given & (1 << bitstart)) != 0) | |
| 1013 | func (stream, "%c", *c); | |
| 1014 | break; | |
| 1015 | default: | |
| 1016 | abort (); | |
| 1017 | } | |
| 1018 | } | |
| 1019 | break; | |
| 1020 | default: | |
| 1021 | abort (); | |
| 1022 | } | |
| 1023 | } | |
| 1024 | else | |
| 1025 | func (stream, "%c", *c); | |
| 1026 | } | |
| 1027 | ||
| 1028 | return 2; | |
| 1029 | } | |
| 1030 | } | |
| 1031 | #if (SCORE_SIMULATOR_ACTIVE) | |
| 1032 | func (stream, _("<illegal instruction>")); | |
| 1033 | return 2; | |
| 1034 | #endif | |
| 02b1cb40 | 1035 | |
| 1c0d3aa6 NC |
1036 | /* No match. */ |
| 1037 | abort (); | |
| 1038 | } | |
| 1039 | ||
| 1040 | /* NOTE: There are no checks in these routines that | |
| 1041 | the relevant number of data bytes exist. */ | |
| 1042 | static int | |
| c3b7224a | 1043 | s3_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) |
| 1c0d3aa6 | 1044 | { |
| c3b7224a NC |
1045 | unsigned char b[6]; |
| 1046 | bfd_vma given,given_h , given_l, given_16, given_32, given_48; | |
| c3b7224a NC |
1047 | bfd_vma ridparity; |
| 1048 | int status; | |
| 1049 | void *stream = info->stream; | |
| 1050 | fprintf_ftype func = info->fprintf_func; | |
| 02b1cb40 | 1051 | |
| 1c0d3aa6 | 1052 | info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; |
| c3b7224a NC |
1053 | info->bytes_per_chunk = 2; |
| 1054 | status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info); | |
| 1055 | if (status != 0) | |
| 1c0d3aa6 NC |
1056 | { |
| 1057 | info->bytes_per_chunk = 2; | |
| 1058 | status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); | |
| 1059 | b[3] = b[2] = 0; | |
| c3b7224a NC |
1060 | if (status != 0) |
| 1061 | { | |
| 1062 | info->memory_error_func (status, pc, info); | |
| 1063 | return -1; | |
| 1064 | } | |
| 1065 | } | |
| 1066 | if (little) | |
| 1067 | { | |
| 1068 | given = b[0] | (b[1] << 8); | |
| 1c0d3aa6 NC |
1069 | } |
| 1070 | else | |
| 1071 | { | |
| c3b7224a | 1072 | given = (b[0] << 8) | b[1]; |
| 1c0d3aa6 NC |
1073 | } |
| 1074 | ||
| c3b7224a NC |
1075 | /* Set given_16. */ |
| 1076 | given_16 = given; | |
| 1077 | ||
| 02b1cb40 | 1078 | /* Judge if now is insn_16_p. */ |
| c3b7224a NC |
1079 | if ((given & 0x8000)==0) |
| 1080 | return print_insn_score16 (pc, info, given); | |
| 1081 | ||
| 1082 | else | |
| 1083 | { | |
| 1084 | if (little) | |
| 1085 | { | |
| 1086 | given = ((bfd_vma)b[2]) | ((bfd_vma)b[3] << 8) | ((bfd_vma)b[0] << 16) | ((bfd_vma)b[1] << 24); | |
| 1087 | } | |
| 1088 | else | |
| 1089 | { | |
| 1090 | given = ((bfd_vma)b[0] << 24) | ((bfd_vma)b[1] << 16) | ((bfd_vma)b[2] << 8) | ((bfd_vma)b[3]); | |
| 1091 | } | |
| 1092 | ||
| 1093 | /* Set given_32. */ | |
| 1094 | given_32 = given; | |
| 1095 | ||
| 02b1cb40 | 1096 | /* Judge if now is insn_32. */ |
| c3b7224a NC |
1097 | if ((given &0x80008000)==0x80000000) |
| 1098 | { | |
| 1099 | /* Get rid of parity. */ | |
| 1100 | ridparity = (given & 0x7FFF); | |
| 1101 | ridparity |= (given & 0x7FFF0000) >> 1; | |
| 1102 | given = ridparity; | |
| 1103 | return print_insn_score32 (pc, info, given); | |
| 1104 | } | |
| 1105 | } | |
| 1106 | ||
| 02b1cb40 | 1107 | /* The insn is 48 bit. */ |
| c3b7224a | 1108 | status = info->read_memory_func (pc, (bfd_byte *) & b[0], 6, info); |
| 1c0d3aa6 NC |
1109 | if (status != 0) |
| 1110 | { | |
| 1111 | info->memory_error_func (status, pc, info); | |
| 1112 | return -1; | |
| 1113 | } | |
| 1114 | ||
| 1115 | if (little) | |
| 1116 | { | |
| c3b7224a NC |
1117 | given = ((bfd_vma)b[4]) | ((bfd_vma)b[5] << 8) | ((bfd_vma)b[2] << 16) | ((bfd_vma)b[3] << 24) |
| 1118 | | ((bfd_vma)b[0] << 32) | ((bfd_vma)b[1] << 40); | |
| 1c0d3aa6 NC |
1119 | } |
| 1120 | else | |
| 1121 | { | |
| c3b7224a NC |
1122 | given_l = ((bfd_vma)b[5]) | ((bfd_vma)b[4] << 8) | ((bfd_vma)b[3] << 16) | ((bfd_vma)b[2] << 24) ; |
| 1123 | given_h = ((bfd_vma)b[1] )|((bfd_vma)b[0] <<8); | |
| 1124 | given = ((bfd_vma)given_h<<32) | (bfd_vma)given_l ; | |
| 1125 | ||
| 1c0d3aa6 NC |
1126 | } |
| 1127 | ||
| c3b7224a NC |
1128 | /* Set given_48. */ |
| 1129 | given_48 = given; | |
| 1c0d3aa6 | 1130 | |
| c3b7224a NC |
1131 | if ((given & 0x800080008000LL) == 0x800080000000LL) |
| 1132 | { | |
| 1133 | /* Get rid of parity. */ | |
| 1134 | ridparity = (given & 0x7FFF); | |
| 1135 | ridparity |= (given & 0x7FFF0000) >> 1; | |
| 1136 | ridparity |= (given & 0x7FFF00000000LL) >> 2; | |
| 1137 | given = ridparity; | |
| 1138 | status = print_insn_score48 (info, given); | |
| 1139 | return status; | |
| 1140 | } | |
| 1c0d3aa6 | 1141 | |
| c3b7224a | 1142 | /* Check 0x800080008000, 0x80008000, 0x8000. */ |
| c3b7224a NC |
1143 | if ((given_48 & 0x800080008000LL) != 0x800080000000LL) |
| 1144 | { | |
| 1145 | #if (SCORE_SIMULATOR_ACTIVE) | |
| 1146 | func (stream, _("<illegal instruction>")); | |
| 1147 | return 6; | |
| 1148 | #endif | |
| 1149 | } | |
| 1150 | if (((given_32 & 0xffff00000000LL) == 0) && ((given_32 & 0x80008000) != 0x80000000)) | |
| 1151 | { | |
| 1152 | #if (SCORE_SIMULATOR_ACTIVE) | |
| 1153 | func (stream, _("<illegal instruction>")); | |
| 1154 | return 4; | |
| 1155 | #endif | |
| 1156 | } | |
| 1157 | if (((given_16 & 0xffffffff0000LL) == 0) && ((given_16 & 0x8000) != 0)) | |
| 1158 | { | |
| 1159 | #if (SCORE_SIMULATOR_ACTIVE) | |
| 1160 | func (stream, _("<illegal instruction>")); | |
| 1161 | return 2; | |
| 1162 | #endif | |
| 1163 | } | |
| 1164 | else | |
| 1165 | { | |
| 1166 | return 0; | |
| 1167 | } | |
| 1168 | } | |
| 1c0d3aa6 | 1169 | |
| c3b7224a NC |
1170 | static unsigned long |
| 1171 | score_get_arch (disassemble_info *info) | |
| 1172 | { | |
| 1173 | if (info->arch == bfd_arch_score) | |
| 1174 | return info->mach; | |
| 1c0d3aa6 | 1175 | else |
| c3b7224a | 1176 | return 0; |
| 1c0d3aa6 NC |
1177 | } |
| 1178 | ||
| 1179 | int | |
| 1180 | print_insn_big_score (bfd_vma pc, struct disassemble_info *info) | |
| 1181 | { | |
| c3b7224a NC |
1182 | if (score_get_arch (info) == bfd_mach_score3) |
| 1183 | return s3_print_insn (pc, info, FALSE); | |
| 1184 | else | |
| 1185 | return s7_print_insn (pc, info, FALSE); | |
| 1c0d3aa6 NC |
1186 | } |
| 1187 | ||
| 1188 | int | |
| 1189 | print_insn_little_score (bfd_vma pc, struct disassemble_info *info) | |
| 1190 | { | |
| c3b7224a NC |
1191 | if (score_get_arch (info) == bfd_mach_score3) |
| 1192 | return s3_print_insn (pc, info, TRUE); | |
| 1193 | else | |
| 1194 | return s7_print_insn (pc, info, TRUE); | |
| 1c0d3aa6 | 1195 | } |
| 02b1cb40 NC |
1196 | #else /* not BFD64 */ |
| 1197 | int | |
| 1198 | print_insn_big_score (bfd_vma pc ATTRIBUTE_UNUSED, | |
| 1199 | struct disassemble_info * info ATTRIBUTE_UNUSED) | |
| 1200 | { | |
| 1201 | abort (); | |
| 1202 | } | |
| 1203 | ||
| 1204 | int | |
| 1205 | print_insn_little_score (bfd_vma pc ATTRIBUTE_UNUSED, | |
| 1206 | struct disassemble_info * info ATTRIBUTE_UNUSED) | |
| 1207 | { | |
| 1208 | abort (); | |
| 1209 | } | |
| 1210 | #endif |