[thirdparty/binutils-gdb.git] / opcodes / sh-dis.c

/* Disassemble SH instructions.
   Copyright (C) 1993, 94, 95, 96, 97, 1998, 2000
   Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <stdio.h>
#include "sysdep.h"
#define STATIC_TABLE
#define DEFINE_TABLE

#include "sh-opc.h"
#include "dis-asm.h"

#define LITTLE_BIT 2

static void
print_movxy (op, rn, rm, fprintf_fn, stream)
     sh_opcode_info *op;
     int rn, rm;
     fprintf_ftype fprintf_fn;
     void *stream;
{
  int n;

  fprintf_fn (stream, "%s\t", op->name);
  for (n = 0; n < 2; n++)
    {
      switch (op->arg[n])
	{
	case A_IND_N:
	  fprintf_fn (stream, "@r%d", rn);
	  break;
	case A_INC_N:
	  fprintf_fn (stream, "@r%d+", rn);
	  break;
	case A_PMOD_N:
	  fprintf_fn (stream, "@r%d+r8", rn);
	  break;
	case A_PMODY_N:
	  fprintf_fn (stream, "@r%d+r9", rn);
	  break;
	case DSP_REG_M:
	  fprintf_fn (stream, "a%c", '0' + rm);
	  break;
	case DSP_REG_X:
	  fprintf_fn (stream, "x%c", '0' + rm);
	  break;
	case DSP_REG_Y:
	  fprintf_fn (stream, "y%c", '0' + rm);
	  break;
	default:
	  abort ();
	}
      if (n == 0)
	fprintf_fn (stream, ",");
    }
}

/* Print a double data transfer insn.  INSN is just the lower three
   nibbles of the insn, i.e. field a and the bit that indicates if
   a parallel processing insn follows.
   Return nonzero if a field b of a parallel processing insns follows.  */

static void
print_insn_ddt (insn, info)
     int insn;
     struct disassemble_info *info;
{
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;

  /* If this is just a nop, make sure to emit something.  */
  if (insn == 0x000)
    fprintf_fn (stream, "nopx\tnopy");

  /* If a parallel processing insn was printed before,
     and we got a non-nop, emit a tab.  */
  if ((insn & 0x800) && (insn & 0x3ff))
    fprintf_fn (stream, "\t");

  /* Check if either the x or y part is invalid.  */
  if (((insn & 0xc) == 0 && (insn & 0x2a0))
      || ((insn & 3) == 0 && (insn & 0x150)))
    fprintf_fn (stream, ".word 0x%x", insn);
  else
    {
      static sh_opcode_info *first_movx, *first_movy;
      sh_opcode_info *opx, *opy;
      int insn_x, insn_y;

      if (! first_movx)
	{
	  for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
	    first_movx++;
	  for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
	    first_movy++;
	}
      insn_x = (insn >> 2) & 0xb;
      if (insn_x)
	{
	  for (opx = first_movx; opx->nibbles[2] != insn_x;)
	    opx++;
	  print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
		       fprintf_fn, stream);
	}
      insn_y = (insn & 3) | ((insn >> 1) & 8);
      if (insn_y)
	{
	  if (insn_x)
	    fprintf_fn (stream, "\t");
	  for (opy = first_movy; opy->nibbles[2] != insn_y;)
	    opy++;
	  print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
		       fprintf_fn, stream);
	}
    }
}

static void
print_dsp_reg (rm, fprintf_fn, stream)
     int rm;
     fprintf_ftype fprintf_fn;
     void *stream;
{
  switch (rm)
    {
    case A_A1_NUM:
      fprintf_fn (stream, "a1");
      break;
    case A_A0_NUM:
      fprintf_fn (stream, "a0");
      break;
    case A_X0_NUM:
      fprintf_fn (stream, "x0");
      break;
    case A_X1_NUM:
      fprintf_fn (stream, "x1");
      break;
    case A_Y0_NUM:
      fprintf_fn (stream, "y0");
      break;
    case A_Y1_NUM:
      fprintf_fn (stream, "y1");
      break;
    case A_M0_NUM:
      fprintf_fn (stream, "m0");
      break;
    case A_A1G_NUM:
      fprintf_fn (stream, "a1g");
      break;
    case A_M1_NUM:
      fprintf_fn (stream, "m1");
      break;
    case A_A0G_NUM:
      fprintf_fn (stream, "a0g");
      break;
    default:
      fprintf_fn (stream, "0x%x", rm);
      break;
    }
}

static void
print_insn_ppi (field_b, info)
     int field_b;
     struct disassemble_info *info;
{
  static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
  static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;
  int nib1, nib2, nib3;
  char *dc;
  sh_opcode_info *op;

  if ((field_b & 0xe800) == 0)
    {
      fprintf_fn (stream, "psh%c\t#%d,",
		  field_b & 0x1000 ? 'a' : 'l',
		  (field_b >> 4) & 127);
      print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
      return;
    }
  if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
    {
      static char *du_tab[] = { "x0", "y0", "a0", "a1" };
      static char *se_tab[] = { "x0", "x1", "y0", "a1" };
      static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
      static char *sg_tab[] = { "m0", "m1", "a0", "a1" };

      if (field_b & 0x2000)
	{
	  fprintf_fn (stream, "p%s %s,%s,%s\t",
		      (field_b & 0x1000) ? "add" : "sub",
		      sx_tab[(field_b >> 6) & 3],
		      sy_tab[(field_b >> 4) & 3],
		      du_tab[(field_b >> 0) & 3]);
	}
      fprintf_fn (stream, "pmuls%c%s,%s,%s",
		  field_b & 0x2000 ? ' ' : '\t',
		  se_tab[(field_b >> 10) & 3],
		  sf_tab[(field_b >>  8) & 3],
		  sg_tab[(field_b >>  2) & 3]);
      return;
    }

  nib1 = PPIC;
  nib2 = field_b >> 12 & 0xf;
  nib3 = field_b >> 8 & 0xf;
  switch (nib3 & 0x3)
    {
    case 0:
      dc = "";
      nib1 = PPI3;
      break;
    case 1:
      dc = "";
      break;
    case 2:
      dc = "dct ";
      nib3 -= 1;
      break;
    case 3:
      dc = "dcf ";
      nib3 -= 2;
      break;
    }
  for (op = sh_table; op->name; op++)
    {
      if (op->nibbles[1] == nib1
	  && op->nibbles[2] == nib2
	  && op->nibbles[3] == nib3)
	{
	  int n;

	  fprintf_fn (stream, "%s%s\t", dc, op->name);
	  for (n = 0; n < 3 && op->arg[n] != A_END; n++)
	    {
	      if (n && op->arg[1] != A_END)
		fprintf_fn (stream, ",");
	      switch (op->arg[n])
		{
		case DSP_REG_N:
		  print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
		  break;
		case DSP_REG_X:
		  fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
		  break;
		case DSP_REG_Y:
		  fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
		  break;
		case A_MACH:
		  fprintf_fn (stream, "mach");
		  break;
		case A_MACL:
		  fprintf_fn (stream, "macl");
		  break;
		default:
		  abort ();
		}
	    }
	  return;
	}
    }
  /* Not found.  */
  fprintf_fn (stream, ".word 0x%x", field_b);
}

static int
print_insn_shx (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;
  unsigned char insn[2];
  unsigned char nibs[4];
  int status;
  bfd_vma relmask = ~(bfd_vma) 0;
  sh_opcode_info *op;
  int target_arch;

  switch (info->mach)
    {
    case bfd_mach_sh:
      target_arch = arch_sh1;
      break;
    case bfd_mach_sh2:
      target_arch = arch_sh2;
      break;
    case bfd_mach_sh_dsp:
      target_arch = arch_sh_dsp;
      break;
    case bfd_mach_sh3:
      target_arch = arch_sh3;
      break;
    case bfd_mach_sh3_dsp:
      target_arch = arch_sh3_dsp;
      break;
    case bfd_mach_sh3e:
      target_arch = arch_sh3e;
      break;
    case bfd_mach_sh4:
      target_arch = arch_sh4;
      break;
    default:
      abort ();
    }

  status = info->read_memory_func (memaddr, insn, 2, info);

  if (status != 0)
    {
      info->memory_error_func (status, memaddr, info);
      return -1;
    }

  if (info->flags & LITTLE_BIT)
    {
      nibs[0] = (insn[1] >> 4) & 0xf;
      nibs[1] = insn[1] & 0xf;

      nibs[2] = (insn[0] >> 4) & 0xf;
      nibs[3] = insn[0] & 0xf;
    }
  else
    {
      nibs[0] = (insn[0] >> 4) & 0xf;
      nibs[1] = insn[0] & 0xf;

      nibs[2] = (insn[1] >> 4) & 0xf;
      nibs[3] = insn[1] & 0xf;
    }

  if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up)
    {
      if (nibs[1] & 8)
	{
	  int field_b;

	  status = info->read_memory_func (memaddr + 2, insn, 2, info);

	  if (status != 0)
	    {
	      info->memory_error_func (status, memaddr + 2, info);
	      return -1;
	    }

	  if (info->flags & LITTLE_BIT)
	    field_b = insn[1] << 8 | insn[0];
	  else
	    field_b = insn[0] << 8 | insn[1];

	  print_insn_ppi (field_b, info);
	  print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
	  return 4;
	}
      print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
      return 2;
    }
  for (op = sh_table; op->name; op++)
    {
      int n;
      int imm = 0;
      int rn = 0;
      int rm = 0;
      int rb = 0;
      int disp_pc;
      bfd_vma disp_pc_addr = 0;

      if ((op->arch & target_arch) == 0)
	goto fail;
      for (n = 0; n < 4; n++)
	{
	  int i = op->nibbles[n];

	  if (i < 16)
	    {
	      if (nibs[n] == i)
		continue;
	      goto fail;
	    }
	  switch (i)
	    {
	    case BRANCH_8:
	      imm = (nibs[2] << 4) | (nibs[3]);
	      if (imm & 0x80)
		imm |= ~0xff;
	      imm = ((char) imm) * 2 + 4;
	      goto ok;
	    case BRANCH_12:
	      imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
	      if (imm & 0x800)
		imm |= ~0xfff;
	      imm = imm * 2 + 4;
	      goto ok;
	    case IMM0_4:
	    case IMM1_4:
	      imm = nibs[3];
	      goto ok;
	    case IMM0_4BY2:
	    case IMM1_4BY2:
	      imm = nibs[3] << 1;
	      goto ok;
	    case IMM0_4BY4:
	    case IMM1_4BY4:
	      imm = nibs[3] << 2;
	      goto ok;
	    case IMM0_8:
	    case IMM1_8:
	      imm = (nibs[2] << 4) | nibs[3];
	      goto ok;
	    case PCRELIMM_8BY2:
	      imm = ((nibs[2] << 4) | nibs[3]) << 1;
	      relmask = ~(bfd_vma) 1;
	      goto ok;
	    case PCRELIMM_8BY4:
	      imm = ((nibs[2] << 4) | nibs[3]) << 2;
	      relmask = ~(bfd_vma) 3;
	      goto ok;
	    case IMM0_8BY2:
	    case IMM1_8BY2:
	      imm = ((nibs[2] << 4) | nibs[3]) << 1;
	      goto ok;
	    case IMM0_8BY4:
	    case IMM1_8BY4:
	      imm = ((nibs[2] << 4) | nibs[3]) << 2;
	      goto ok;
	    case REG_N:
	      rn = nibs[n];
	      break;
	    case REG_M:
	      rm = nibs[n];
	      break;
	    case REG_NM:
	      rn = (nibs[n] & 0xc) >> 2;
	      rm = (nibs[n] & 0x3);
	      break;
	    case REG_B:
	      rb = nibs[n] & 0x07;
	      break;
	    case SDT_REG_N:
	      /* sh-dsp: single data transfer.  */
	      rn = nibs[n];
	      if ((rn & 0xc) != 4)
		goto fail;
	      rn = rn & 0x3;
	      rn |= (rn & 2) << 1;
	      break;
	    case PPI:
	    case REPEAT:
	      goto fail;
	    default:
	      abort ();
	    }
	}

    ok:
      fprintf_fn (stream, "%s\t", op->name);
      disp_pc = 0;
      for (n = 0; n < 3 && op->arg[n] != A_END; n++)
	{
	  if (n && op->arg[1] != A_END)
	    fprintf_fn (stream, ",");
	  switch (op->arg[n])
	    {
	    case A_IMM:
	      fprintf_fn (stream, "#%d", (char) (imm));
	      break;
	    case A_R0:
	      fprintf_fn (stream, "r0");
	      break;
	    case A_REG_N:
	      fprintf_fn (stream, "r%d", rn);
	      break;
	    case A_INC_N:
	      fprintf_fn (stream, "@r%d+", rn);
	      break;
	    case A_DEC_N:
	      fprintf_fn (stream, "@-r%d", rn);
	      break;
	    case A_IND_N:
	      fprintf_fn (stream, "@r%d", rn);
	      break;
	    case A_DISP_REG_N:
	      fprintf_fn (stream, "@(%d,r%d)", imm, rn);
	      break;
	    case A_PMOD_N:
	      fprintf_fn (stream, "@r%d+r8", rn);
	      break;
	    case A_REG_M:
	      fprintf_fn (stream, "r%d", rm);
	      break;
	    case A_INC_M:
	      fprintf_fn (stream, "@r%d+", rm);
	      break;
	    case A_DEC_M:
	      fprintf_fn (stream, "@-r%d", rm);
	      break;
	    case A_IND_M:
	      fprintf_fn (stream, "@r%d", rm);
	      break;
	    case A_DISP_REG_M:
	      fprintf_fn (stream, "@(%d,r%d)", imm, rm);
	      break;
	    case A_REG_B:
	      fprintf_fn (stream, "r%d_bank", rb);
	      break;
	    case A_DISP_PC:
	      disp_pc = 1;
	      disp_pc_addr = imm + 4 + (memaddr & relmask);
	      (*info->print_address_func) (disp_pc_addr, info);
	      break;
	    case A_IND_R0_REG_N:
	      fprintf_fn (stream, "@(r0,r%d)", rn);
	      break;
	    case A_IND_R0_REG_M:
	      fprintf_fn (stream, "@(r0,r%d)", rm);
	      break;
	    case A_DISP_GBR:
	      fprintf_fn (stream, "@(%d,gbr)", imm);
	      break;
	    case A_R0_GBR:
	      fprintf_fn (stream, "@(r0,gbr)");
	      break;
	    case A_BDISP12:
	    case A_BDISP8:
	      (*info->print_address_func) (imm + memaddr, info);
	      break;
	    case A_SR:
	      fprintf_fn (stream, "sr");
	      break;
	    case A_GBR:
	      fprintf_fn (stream, "gbr");
	      break;
	    case A_VBR:
	      fprintf_fn (stream, "vbr");
	      break;
	    case A_DSR:
	      fprintf_fn (stream, "dsr");
	      break;
	    case A_MOD:
	      fprintf_fn (stream, "mod");
	      break;
	    case A_RE:
	      fprintf_fn (stream, "re");
	      break;
	    case A_RS:
	      fprintf_fn (stream, "rs");
	      break;
	    case A_A0:
	      fprintf_fn (stream, "a0");
	      break;
	    case A_X0:
	      fprintf_fn (stream, "x0");
	      break;
	    case A_X1:
	      fprintf_fn (stream, "x1");
	      break;
	    case A_Y0:
	      fprintf_fn (stream, "y0");
	      break;
	    case A_Y1:
	      fprintf_fn (stream, "y1");
	      break;
	    case DSP_REG_M:
	      print_dsp_reg (rm, fprintf_fn, stream);
	      break;
	    case A_SSR:
	      fprintf_fn (stream, "ssr");
	      break;
	    case A_SPC:
	      fprintf_fn (stream, "spc");
	      break;
	    case A_MACH:
	      fprintf_fn (stream, "mach");
	      break;
	    case A_MACL:
	      fprintf_fn (stream, "macl");
	      break;
	    case A_PR:
	      fprintf_fn (stream, "pr");
	      break;
	    case A_SGR:
	      fprintf_fn (stream, "sgr");
	      break;
	    case A_DBR:
	      fprintf_fn (stream, "dbr");
	      break;
	    case F_REG_N:
	      fprintf_fn (stream, "fr%d", rn);
	      break;
	    case F_REG_M:
	      fprintf_fn (stream, "fr%d", rm);
	      break;
	    case DX_REG_N:
	      if (rn & 1)
		{
		  fprintf_fn (stream, "xd%d", rn & ~1);
		  break;
		}
	    d_reg_n:
	    case D_REG_N:
	      fprintf_fn (stream, "dr%d", rn);
	      break;
	    case DX_REG_M:
	      if (rm & 1)
		{
		  fprintf_fn (stream, "xd%d", rm & ~1);
		  break;
		}
	    case D_REG_M:
	      fprintf_fn (stream, "dr%d", rm);
	      break;
	    case FPSCR_M:
	    case FPSCR_N:
	      fprintf_fn (stream, "fpscr");
	      break;
	    case FPUL_M:
	    case FPUL_N:
	      fprintf_fn (stream, "fpul");
	      break;
	    case F_FR0:
	      fprintf_fn (stream, "fr0");
	      break;
	    case V_REG_N:
	      fprintf_fn (stream, "fv%d", rn * 4);
	      break;
	    case V_REG_M:
	      fprintf_fn (stream, "fv%d", rm * 4);
	      break;
	    case XMTRX_M4:
	      fprintf_fn (stream, "xmtrx");
	      break;
	    default:
	      abort ();
	    }
	}

#if 0
      /* This code prints instructions in delay slots on the same line
         as the instruction which needs the delay slots.  This can be
         confusing, since other disassembler don't work this way, and
         it means that the instructions are not all in a line.  So I
         disabled it.  Ian.  */
      if (!(info->flags & 1)
	  && (op->name[0] == 'j'
	      || (op->name[0] == 'b'
		  && (op->name[1] == 'r'
		      || op->name[1] == 's'))
	      || (op->name[0] == 'r' && op->name[1] == 't')
	      || (op->name[0] == 'b' && op->name[2] == '.')))
	{
	  info->flags |= 1;
	  fprintf_fn (stream, "\t(slot ");
	  print_insn_shx (memaddr + 2, info);
	  info->flags &= ~1;
	  fprintf_fn (stream, ")");
	  return 4;
	}
#endif

      if (disp_pc && strcmp (op->name, "mova") != 0)
	{
	  int size;
	  bfd_byte bytes[4];

	  if (relmask == ~(bfd_vma) 1)
	    size = 2;
	  else
	    size = 4;
	  status = info->read_memory_func (disp_pc_addr, bytes, size, info);
	  if (status == 0)
	    {
	      unsigned int val;

	      if (size == 2)
		{
		  if ((info->flags & LITTLE_BIT) != 0)
		    val = bfd_getl16 (bytes);
		  else
		    val = bfd_getb16 (bytes);
		}
	      else
		{
		  if ((info->flags & LITTLE_BIT) != 0)
		    val = bfd_getl32 (bytes);
		  else
		    val = bfd_getb32 (bytes);
		}
	      fprintf_fn (stream, "\t! 0x%x", val);
	    }
	}

      return 2;
    fail:
      ;

    }
  fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
  return 2;
}

int
print_insn_shl (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  int r;

  info->flags = LITTLE_BIT;
  r = print_insn_shx (memaddr, info);
  return r;
}

int
print_insn_sh (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  int r;

  info->flags = 0;
  r = print_insn_shx (memaddr, info);
  return r;
}
Commit	Line	Data
252b5132	1	/* Disassemble SH instructions.
69eb4bbf KH	2	Copyright (C) 1993, 94, 95, 96, 97, 1998, 2000
69eb4bbf KH	3	Free Software Foundation, Inc.
252b5132 RH	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	18
	19	#include <stdio.h>
0d8dfecf	20	#include "sysdep.h"
252b5132 RH	21	#define STATIC_TABLE
	22	#define DEFINE_TABLE
	23
	24	#include "sh-opc.h"
	25	#include "dis-asm.h"
	26
	27	#define LITTLE_BIT 2
	28
d4845d57 JR	29	static void
	30	print_movxy (op, rn, rm, fprintf_fn, stream)
	31	sh_opcode_info *op;
	32	int rn, rm;
	33	fprintf_ftype fprintf_fn;
	34	void *stream;
	35	{
	36	int n;
	37
69eb4bbf	38	fprintf_fn (stream, "%s\t", op->name);
d4845d57 JR	39	for (n = 0; n < 2; n++)
	40	{
	41	switch (op->arg[n])
	42	{
	43	case A_IND_N:
69eb4bbf	44	fprintf_fn (stream, "@r%d", rn);
d4845d57 JR	45	break;
d4845d57 JR	46	case A_INC_N:
69eb4bbf	47	fprintf_fn (stream, "@r%d+", rn);
d4845d57 JR	48	break;
d4845d57 JR	49	case A_PMOD_N:
69eb4bbf	50	fprintf_fn (stream, "@r%d+r8", rn);
d4845d57 JR	51	break;
d4845d57 JR	52	case A_PMODY_N:
69eb4bbf	53	fprintf_fn (stream, "@r%d+r9", rn);
d4845d57 JR	54	break;
	55	case DSP_REG_M:
	56	fprintf_fn (stream, "a%c", '0' + rm);
	57	break;
	58	case DSP_REG_X:
	59	fprintf_fn (stream, "x%c", '0' + rm);
	60	break;
	61	case DSP_REG_Y:
	62	fprintf_fn (stream, "y%c", '0' + rm);
	63	break;
	64	default:
	65	abort ();
	66	}
	67	if (n == 0)
69eb4bbf	68	fprintf_fn (stream, ",");
d4845d57 JR	69	}
	70	}
	71
	72	/* Print a double data transfer insn. INSN is just the lower three
	73	nibbles of the insn, i.e. field a and the bit that indicates if
	74	a parallel processing insn follows.
	75	Return nonzero if a field b of a parallel processing insns follows. */
69eb4bbf	76
d4845d57 JR	77	static void
	78	print_insn_ddt (insn, info)
	79	int insn;
	80	struct disassemble_info *info;
	81	{
	82	fprintf_ftype fprintf_fn = info->fprintf_func;
	83	void *stream = info->stream;
	84
	85	/* If this is just a nop, make sure to emit something. */
	86	if (insn == 0x000)
	87	fprintf_fn (stream, "nopx\tnopy");
	88
	89	/* If a parallel processing insn was printed before,
	90	and we got a non-nop, emit a tab. */
	91	if ((insn & 0x800) && (insn & 0x3ff))
	92	fprintf_fn (stream, "\t");
	93
	94	/* Check if either the x or y part is invalid. */
	95	if (((insn & 0xc) == 0 && (insn & 0x2a0))
	96	\|\| ((insn & 3) == 0 && (insn & 0x150)))
	97	fprintf_fn (stream, ".word 0x%x", insn);
	98	else
	99	{
	100	static sh_opcode_info first_movx, first_movy;
	101	sh_opcode_info opx, opy;
	102	int insn_x, insn_y;
	103
	104	if (! first_movx)
	105	{
69eb4bbf	106	for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
d4845d57	107	first_movx++;
69eb4bbf	108	for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
d4845d57 JR	109	first_movy++;
	110	}
	111	insn_x = (insn >> 2) & 0xb;
	112	if (insn_x)
	113	{
69eb4bbf KH	114	for (opx = first_movx; opx->nibbles[2] != insn_x;)
69eb4bbf KH	115	opx++;
d4845d57 JR	116	print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
	117	fprintf_fn, stream);
	118	}
	119	insn_y = (insn & 3) \| ((insn >> 1) & 8);
	120	if (insn_y)
	121	{
	122	if (insn_x)
	123	fprintf_fn (stream, "\t");
69eb4bbf KH	124	for (opy = first_movy; opy->nibbles[2] != insn_y;)
69eb4bbf KH	125	opy++;
d4845d57 JR	126	print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
	127	fprintf_fn, stream);
	128	}
	129	}
	130	}
	131
	132	static void
	133	print_dsp_reg (rm, fprintf_fn, stream)
	134	int rm;
	135	fprintf_ftype fprintf_fn;
	136	void *stream;
	137	{
	138	switch (rm)
	139	{
	140	case A_A1_NUM:
	141	fprintf_fn (stream, "a1");
	142	break;
	143	case A_A0_NUM:
	144	fprintf_fn (stream, "a0");
	145	break;
	146	case A_X0_NUM:
	147	fprintf_fn (stream, "x0");
	148	break;
	149	case A_X1_NUM:
	150	fprintf_fn (stream, "x1");
	151	break;
	152	case A_Y0_NUM:
	153	fprintf_fn (stream, "y0");
	154	break;
	155	case A_Y1_NUM:
	156	fprintf_fn (stream, "y1");
	157	break;
	158	case A_M0_NUM:
	159	fprintf_fn (stream, "m0");
	160	break;
	161	case A_A1G_NUM:
	162	fprintf_fn (stream, "a1g");
	163	break;
	164	case A_M1_NUM:
	165	fprintf_fn (stream, "m1");
	166	break;
	167	case A_A0G_NUM:
	168	fprintf_fn (stream, "a0g");
	169	break;
	170	default:
	171	fprintf_fn (stream, "0x%x", rm);
	172	break;
	173	}
	174	}
	175
	176	static void
	177	print_insn_ppi (field_b, info)
	178	int field_b;
	179	struct disassemble_info *info;
	180	{
69eb4bbf KH	181	static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
69eb4bbf KH	182	static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
d4845d57 JR	183	fprintf_ftype fprintf_fn = info->fprintf_func;
	184	void *stream = info->stream;
	185	int nib1, nib2, nib3;
	186	char *dc;
	187	sh_opcode_info *op;
	188
	189	if ((field_b & 0xe800) == 0)
	190	{
	191	fprintf_fn (stream, "psh%c\t#%d,",
	192	field_b & 0x1000 ? 'a' : 'l',
	193	(field_b >> 4) & 127);
	194	print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
	195	return;
	196	}
	197	if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
	198	{
69eb4bbf KH	199	static char *du_tab[] = { "x0", "y0", "a0", "a1" };
	200	static char *se_tab[] = { "x0", "x1", "y0", "a1" };
	201	static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
	202	static char *sg_tab[] = { "m0", "m1", "a0", "a1" };
d4845d57 JR	203
	204	if (field_b & 0x2000)
	205	{
	206	fprintf_fn (stream, "p%s %s,%s,%s\t",
	207	(field_b & 0x1000) ? "add" : "sub",
	208	sx_tab[(field_b >> 6) & 3],
	209	sy_tab[(field_b >> 4) & 3],
	210	du_tab[(field_b >> 0) & 3]);
	211	}
	212	fprintf_fn (stream, "pmuls%c%s,%s,%s",
	213	field_b & 0x2000 ? ' ' : '\t',
	214	se_tab[(field_b >> 10) & 3],
	215	sf_tab[(field_b >> 8) & 3],
	216	sg_tab[(field_b >> 2) & 3]);
	217	return;
	218	}
	219
	220	nib1 = PPIC;
	221	nib2 = field_b >> 12 & 0xf;
	222	nib3 = field_b >> 8 & 0xf;
	223	switch (nib3 & 0x3)
	224	{
	225	case 0:
	226	dc = "";
	227	nib1 = PPI3;
	228	break;
	229	case 1:
	230	dc = "";
	231	break;
	232	case 2:
	233	dc = "dct ";
	234	nib3 -= 1;
	235	break;
	236	case 3:
	237	dc = "dcf ";
	238	nib3 -= 2;
	239	break;
	240	}
	241	for (op = sh_table; op->name; op++)
	242	{
	243	if (op->nibbles[1] == nib1
	244	&& op->nibbles[2] == nib2
	245	&& op->nibbles[3] == nib3)
	246	{
	247	int n;
	248
	249	fprintf_fn (stream, "%s%s\t", dc, op->name);
69eb4bbf	250	for (n = 0; n < 3 && op->arg[n] != A_END; n++)
d4845d57 JR	251	{
	252	if (n && op->arg[1] != A_END)
	253	fprintf_fn (stream, ",");
69eb4bbf	254	switch (op->arg[n])
d4845d57 JR	255	{
	256	case DSP_REG_N:
	257	print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
	258	break;
	259	case DSP_REG_X:
	260	fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
	261	break;
	262	case DSP_REG_Y:
	263	fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
	264	break;
	265	case A_MACH:
	266	fprintf_fn (stream, "mach");
	267	break;
	268	case A_MACL:
69eb4bbf	269	fprintf_fn (stream, "macl");
d4845d57 JR	270	break;
	271	default:
	272	abort ();
	273	}
	274	}
	275	return;
	276	}
	277	}
	278	/* Not found. */
	279	fprintf_fn (stream, ".word 0x%x", field_b);
	280	}
	281
69eb4bbf	282	static int
252b5132 RH	283	print_insn_shx (memaddr, info)
	284	bfd_vma memaddr;
	285	struct disassemble_info *info;
	286	{
	287	fprintf_ftype fprintf_fn = info->fprintf_func;
	288	void *stream = info->stream;
	289	unsigned char insn[2];
	290	unsigned char nibs[4];
	291	int status;
69eb4bbf	292	bfd_vma relmask = ~(bfd_vma) 0;
252b5132	293	sh_opcode_info *op;
d4845d57 JR	294	int target_arch;
	295
	296	switch (info->mach)
	297	{
	298	case bfd_mach_sh:
	299	target_arch = arch_sh1;
	300	break;
	301	case bfd_mach_sh2:
	302	target_arch = arch_sh2;
	303	break;
	304	case bfd_mach_sh_dsp:
	305	target_arch = arch_sh_dsp;
	306	break;
	307	case bfd_mach_sh3:
	308	target_arch = arch_sh3;
	309	break;
	310	case bfd_mach_sh3_dsp:
	311	target_arch = arch_sh3_dsp;
	312	break;
	313	case bfd_mach_sh3e:
	314	target_arch = arch_sh3e;
	315	break;
	316	case bfd_mach_sh4:
	317	target_arch = arch_sh4;
	318	break;
	319	default:
	320	abort ();
	321	}
252b5132 RH	322
	323	status = info->read_memory_func (memaddr, insn, 2, info);
	324
69eb4bbf	325	if (status != 0)
252b5132 RH	326	{
	327	info->memory_error_func (status, memaddr, info);
	328	return -1;
	329	}
	330
69eb4bbf	331	if (info->flags & LITTLE_BIT)
252b5132 RH	332	{
	333	nibs[0] = (insn[1] >> 4) & 0xf;
	334	nibs[1] = insn[1] & 0xf;
	335
	336	nibs[2] = (insn[0] >> 4) & 0xf;
	337	nibs[3] = insn[0] & 0xf;
	338	}
69eb4bbf	339	else
252b5132 RH	340	{
	341	nibs[0] = (insn[0] >> 4) & 0xf;
	342	nibs[1] = insn[0] & 0xf;
	343
	344	nibs[2] = (insn[1] >> 4) & 0xf;
	345	nibs[3] = insn[1] & 0xf;
	346	}
	347
d4845d57 JR	348	if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up)
	349	{
	350	if (nibs[1] & 8)
	351	{
	352	int field_b;
	353
	354	status = info->read_memory_func (memaddr + 2, insn, 2, info);
	355
69eb4bbf	356	if (status != 0)
d4845d57 JR	357	{
	358	info->memory_error_func (status, memaddr + 2, info);
	359	return -1;
	360	}
	361
69eb4bbf	362	if (info->flags & LITTLE_BIT)
d4845d57 JR	363	field_b = insn[1] << 8 \| insn[0];
	364	else
	365	field_b = insn[0] << 8 \| insn[1];
	366
	367	print_insn_ppi (field_b, info);
	368	print_insn_ddt ((nibs[1] << 8) \| (nibs[2] << 4) \| nibs[3], info);
	369	return 4;
	370	}
	371	print_insn_ddt ((nibs[1] << 8) \| (nibs[2] << 4) \| nibs[3], info);
	372	return 2;
	373	}
69eb4bbf	374	for (op = sh_table; op->name; op++)
252b5132 RH	375	{
	376	int n;
	377	int imm = 0;
	378	int rn = 0;
	379	int rm = 0;
	380	int rb = 0;
	381	int disp_pc;
	382	bfd_vma disp_pc_addr = 0;
	383
d4845d57 JR	384	if ((op->arch & target_arch) == 0)
d4845d57 JR	385	goto fail;
252b5132 RH	386	for (n = 0; n < 4; n++)
	387	{
	388	int i = op->nibbles[n];
	389
69eb4bbf	390	if (i < 16)
252b5132 RH	391	{
	392	if (nibs[n] == i)
	393	continue;
	394	goto fail;
	395	}
	396	switch (i)
	397	{
	398	case BRANCH_8:
69eb4bbf	399	imm = (nibs[2] << 4) \| (nibs[3]);
252b5132 RH	400	if (imm & 0x80)
252b5132 RH	401	imm \|= ~0xff;
69eb4bbf	402	imm = ((char) imm) * 2 + 4;
252b5132 RH	403	goto ok;
	404	case BRANCH_12:
	405	imm = ((nibs[1]) << 8) \| (nibs[2] << 4) \| (nibs[3]);
	406	if (imm & 0x800)
	407	imm \|= ~0xfff;
	408	imm = imm * 2 + 4;
	409	goto ok;
015551fc JR	410	case IMM0_4:
015551fc JR	411	case IMM1_4:
252b5132 RH	412	imm = nibs[3];
252b5132 RH	413	goto ok;
015551fc JR	414	case IMM0_4BY2:
015551fc JR	415	case IMM1_4BY2:
69eb4bbf	416	imm = nibs[3] << 1;
252b5132	417	goto ok;
015551fc JR	418	case IMM0_4BY4:
015551fc JR	419	case IMM1_4BY4:
69eb4bbf	420	imm = nibs[3] << 2;
252b5132	421	goto ok;
015551fc JR	422	case IMM0_8:
015551fc JR	423	case IMM1_8:
252b5132 RH	424	imm = (nibs[2] << 4) \| nibs[3];
	425	goto ok;
	426	case PCRELIMM_8BY2:
69eb4bbf KH	427	imm = ((nibs[2] << 4) \| nibs[3]) << 1;
69eb4bbf KH	428	relmask = ~(bfd_vma) 1;
252b5132 RH	429	goto ok;
252b5132 RH	430	case PCRELIMM_8BY4:
69eb4bbf KH	431	imm = ((nibs[2] << 4) \| nibs[3]) << 2;
69eb4bbf KH	432	relmask = ~(bfd_vma) 3;
252b5132	433	goto ok;
015551fc JR	434	case IMM0_8BY2:
015551fc JR	435	case IMM1_8BY2:
69eb4bbf	436	imm = ((nibs[2] << 4) \| nibs[3]) << 1;
252b5132	437	goto ok;
015551fc JR	438	case IMM0_8BY4:
015551fc JR	439	case IMM1_8BY4:
69eb4bbf	440	imm = ((nibs[2] << 4) \| nibs[3]) << 2;
252b5132	441	goto ok;
252b5132 RH	442	case REG_N:
	443	rn = nibs[n];
	444	break;
	445	case REG_M:
	446	rm = nibs[n];
	447	break;
	448	case REG_NM:
	449	rn = (nibs[n] & 0xc) >> 2;
	450	rm = (nibs[n] & 0x3);
	451	break;
	452	case REG_B:
	453	rb = nibs[n] & 0x07;
69eb4bbf	454	break;
d4845d57 JR	455	case SDT_REG_N:
	456	/* sh-dsp: single data transfer. */
	457	rn = nibs[n];
	458	if ((rn & 0xc) != 4)
	459	goto fail;
	460	rn = rn & 0x3;
	461	rn \|= (rn & 2) << 1;
	462	break;
	463	case PPI:
015551fc	464	case REPEAT:
d4845d57	465	goto fail;
252b5132	466	default:
69eb4bbf	467	abort ();
252b5132 RH	468	}
	469	}
	470
	471	ok:
69eb4bbf	472	fprintf_fn (stream, "%s\t", op->name);
252b5132	473	disp_pc = 0;
69eb4bbf	474	for (n = 0; n < 3 && op->arg[n] != A_END; n++)
252b5132 RH	475	{
	476	if (n && op->arg[1] != A_END)
	477	fprintf_fn (stream, ",");
69eb4bbf	478	switch (op->arg[n])
252b5132 RH	479	{
252b5132 RH	480	case A_IMM:
69eb4bbf	481	fprintf_fn (stream, "#%d", (char) (imm));
252b5132 RH	482	break;
	483	case A_R0:
	484	fprintf_fn (stream, "r0");
	485	break;
	486	case A_REG_N:
	487	fprintf_fn (stream, "r%d", rn);
	488	break;
	489	case A_INC_N:
69eb4bbf	490	fprintf_fn (stream, "@r%d+", rn);
252b5132 RH	491	break;
252b5132 RH	492	case A_DEC_N:
69eb4bbf	493	fprintf_fn (stream, "@-r%d", rn);
252b5132 RH	494	break;
252b5132 RH	495	case A_IND_N:
69eb4bbf	496	fprintf_fn (stream, "@r%d", rn);
252b5132 RH	497	break;
252b5132 RH	498	case A_DISP_REG_N:
69eb4bbf	499	fprintf_fn (stream, "@(%d,r%d)", imm, rn);
252b5132	500	break;
d4845d57	501	case A_PMOD_N:
69eb4bbf	502	fprintf_fn (stream, "@r%d+r8", rn);
d4845d57	503	break;
252b5132 RH	504	case A_REG_M:
	505	fprintf_fn (stream, "r%d", rm);
	506	break;
	507	case A_INC_M:
69eb4bbf	508	fprintf_fn (stream, "@r%d+", rm);
252b5132 RH	509	break;
252b5132 RH	510	case A_DEC_M:
69eb4bbf	511	fprintf_fn (stream, "@-r%d", rm);
252b5132 RH	512	break;
252b5132 RH	513	case A_IND_M:
69eb4bbf	514	fprintf_fn (stream, "@r%d", rm);
252b5132 RH	515	break;
252b5132 RH	516	case A_DISP_REG_M:
69eb4bbf	517	fprintf_fn (stream, "@(%d,r%d)", imm, rm);
252b5132 RH	518	break;
	519	case A_REG_B:
	520	fprintf_fn (stream, "r%d_bank", rb);
	521	break;
	522	case A_DISP_PC:
	523	disp_pc = 1;
	524	disp_pc_addr = imm + 4 + (memaddr & relmask);
	525	(*info->print_address_func) (disp_pc_addr, info);
	526	break;
	527	case A_IND_R0_REG_N:
	528	fprintf_fn (stream, "@(r0,r%d)", rn);
69eb4bbf	529	break;
252b5132 RH	530	case A_IND_R0_REG_M:
252b5132 RH	531	fprintf_fn (stream, "@(r0,r%d)", rm);
69eb4bbf	532	break;
252b5132	533	case A_DISP_GBR:
69eb4bbf	534	fprintf_fn (stream, "@(%d,gbr)", imm);
252b5132 RH	535	break;
	536	case A_R0_GBR:
	537	fprintf_fn (stream, "@(r0,gbr)");
	538	break;
	539	case A_BDISP12:
	540	case A_BDISP8:
	541	(*info->print_address_func) (imm + memaddr, info);
	542	break;
	543	case A_SR:
	544	fprintf_fn (stream, "sr");
	545	break;
	546	case A_GBR:
	547	fprintf_fn (stream, "gbr");
	548	break;
	549	case A_VBR:
	550	fprintf_fn (stream, "vbr");
	551	break;
d4845d57 JR	552	case A_DSR:
	553	fprintf_fn (stream, "dsr");
	554	break;
	555	case A_MOD:
	556	fprintf_fn (stream, "mod");
	557	break;
	558	case A_RE:
	559	fprintf_fn (stream, "re");
	560	break;
	561	case A_RS:
	562	fprintf_fn (stream, "rs");
	563	break;
	564	case A_A0:
	565	fprintf_fn (stream, "a0");
	566	break;
	567	case A_X0:
	568	fprintf_fn (stream, "x0");
	569	break;
	570	case A_X1:
	571	fprintf_fn (stream, "x1");
	572	break;
	573	case A_Y0:
	574	fprintf_fn (stream, "y0");
	575	break;
	576	case A_Y1:
	577	fprintf_fn (stream, "y1");
	578	break;
	579	case DSP_REG_M:
	580	print_dsp_reg (rm, fprintf_fn, stream);
	581	break;
252b5132 RH	582	case A_SSR:
	583	fprintf_fn (stream, "ssr");
	584	break;
	585	case A_SPC:
	586	fprintf_fn (stream, "spc");
	587	break;
	588	case A_MACH:
	589	fprintf_fn (stream, "mach");
	590	break;
	591	case A_MACL:
69eb4bbf	592	fprintf_fn (stream, "macl");
252b5132 RH	593	break;
	594	case A_PR:
	595	fprintf_fn (stream, "pr");
	596	break;
	597	case A_SGR:
	598	fprintf_fn (stream, "sgr");
	599	break;
	600	case A_DBR:
	601	fprintf_fn (stream, "dbr");
	602	break;
252b5132 RH	603	case F_REG_N:
	604	fprintf_fn (stream, "fr%d", rn);
	605	break;
	606	case F_REG_M:
	607	fprintf_fn (stream, "fr%d", rm);
	608	break;
	609	case DX_REG_N:
	610	if (rn & 1)
	611	{
	612	fprintf_fn (stream, "xd%d", rn & ~1);
	613	break;
	614	}
	615	d_reg_n:
	616	case D_REG_N:
	617	fprintf_fn (stream, "dr%d", rn);
	618	break;
	619	case DX_REG_M:
	620	if (rm & 1)
	621	{
	622	fprintf_fn (stream, "xd%d", rm & ~1);
	623	break;
	624	}
	625	case D_REG_M:
	626	fprintf_fn (stream, "dr%d", rm);
	627	break;
	628	case FPSCR_M:
	629	case FPSCR_N:
	630	fprintf_fn (stream, "fpscr");
	631	break;
	632	case FPUL_M:
	633	case FPUL_N:
	634	fprintf_fn (stream, "fpul");
	635	break;
	636	case F_FR0:
	637	fprintf_fn (stream, "fr0");
	638	break;
	639	case V_REG_N:
69eb4bbf	640	fprintf_fn (stream, "fv%d", rn * 4);
252b5132 RH	641	break;
252b5132 RH	642	case V_REG_M:
69eb4bbf	643	fprintf_fn (stream, "fv%d", rm * 4);
252b5132 RH	644	break;
	645	case XMTRX_M4:
	646	fprintf_fn (stream, "xmtrx");
	647	break;
	648	default:
69eb4bbf	649	abort ();
252b5132 RH	650	}
	651	}
	652
	653	#if 0
	654	/* This code prints instructions in delay slots on the same line
	655	as the instruction which needs the delay slots. This can be
	656	confusing, since other disassembler don't work this way, and
	657	it means that the instructions are not all in a line. So I
	658	disabled it. Ian. */
	659	if (!(info->flags & 1)
	660	&& (op->name[0] == 'j'
	661	\|\| (op->name[0] == 'b'
69eb4bbf	662	&& (op->name[1] == 'r'
252b5132 RH	663	\|\| op->name[1] == 's'))
	664	\|\| (op->name[0] == 'r' && op->name[1] == 't')
	665	\|\| (op->name[0] == 'b' && op->name[2] == '.')))
	666	{
	667	info->flags \|= 1;
	668	fprintf_fn (stream, "\t(slot ");
	669	print_insn_shx (memaddr + 2, info);
	670	info->flags &= ~1;
	671	fprintf_fn (stream, ")");
	672	return 4;
	673	}
	674	#endif
	675
	676	if (disp_pc && strcmp (op->name, "mova") != 0)
	677	{
	678	int size;
	679	bfd_byte bytes[4];
	680
69eb4bbf	681	if (relmask == ~(bfd_vma) 1)
252b5132 RH	682	size = 2;
	683	else
	684	size = 4;
	685	status = info->read_memory_func (disp_pc_addr, bytes, size, info);
	686	if (status == 0)
	687	{
	688	unsigned int val;
	689
	690	if (size == 2)
	691	{
	692	if ((info->flags & LITTLE_BIT) != 0)
	693	val = bfd_getl16 (bytes);
	694	else
	695	val = bfd_getb16 (bytes);
	696	}
	697	else
	698	{
	699	if ((info->flags & LITTLE_BIT) != 0)
	700	val = bfd_getl32 (bytes);
	701	else
	702	val = bfd_getb32 (bytes);
	703	}
	704	fprintf_fn (stream, "\t! 0x%x", val);
	705	}
	706	}
	707
	708	return 2;
	709	fail:
	710	;
	711
	712	}
	713	fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
	714	return 2;
	715	}
	716
69eb4bbf	717	int
252b5132 RH	718	print_insn_shl (memaddr, info)
	719	bfd_vma memaddr;
	720	struct disassemble_info *info;
	721	{
	722	int r;
	723
	724	info->flags = LITTLE_BIT;
	725	r = print_insn_shx (memaddr, info);
	726	return r;
	727	}
	728
69eb4bbf	729	int
252b5132 RH	730	print_insn_sh (memaddr, info)
	731	bfd_vma memaddr;
	732	struct disassemble_info *info;
	733	{
	734	int r;
	735
	736	info->flags = 0;
	737	r = print_insn_shx (memaddr, info);
	738	return r;
	739	}