[thirdparty/binutils-gdb.git] / opcodes / v850-opc.c

#include "ansidecl.h"
#include "opcode/v850.h"

/* Local insertion and extraction functions.  */
static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
static long extract_d9 PARAMS ((unsigned long, int *));

/* regular opcode */
#define OP(x)		((x & 0x3f) << 5)
#define OP_MASK		OP(0x3f)

/* conditional branch opcode */
#define BOP(x)		((0x0b << 7) | (x & 0x0f))
#define BOP_MASK	((0x0b << 7) | 0x0f)

/* one-word opcodes */
#define one(x)		((unsigned int) (x))

/* two-word opcodes */
#define two(x,y)	((unsigned int) (y) | ((unsigned int) (x) << 16))


\f
const struct v850_operand v850_operands[] = {
#define UNUSED	0
  { 0, 0, 0, 0, 0 }, 

/* The R1 field in a format 1, 6, 7, or 9 insn. */
#define R1	(UNUSED+1)
  { 5, 0, 0, 0, V850_OPERAND_REG }, 

/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
#define R2	(R1+1)
  { 5, 11, 0, 0, V850_OPERAND_REG },

/* The IMM5 field in a format 2 insn. */
#define I5	(R2+1)
  { 5, 0, 0, 0, V850_OPERAND_SIGNED }, 

#define I5U	(I5+1)
  { 5, 0, 0, 0, 0 },

/* The IMM16 field in a format 6 insn. */
#define I16	(I5U+1)
  { 16, 0, 0, 0, 0 }, 

/* The signed DISP7 field in a format 4 insn. */
#define D7S	(I16+1)
  { 7, 0, 0, 0, V850_OPERAND_SIGNED },

/* The DISP9 field in a format 3 insn. */
#define D9	(D7S+1)
  { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },

/* The DISP16 field in a format 6 insn. */
#define D16	(D9+1)
  { 16, 0, 0, 0, V850_OPERAND_SIGNED }, 

/* The DISP22 field in a format 4 insn. */
#define D22	(D16+1)
  { 16, 0, 0, 0, 0 },

#define B3	(D22+1)
/* The 3 bit immediate field in format 8 insn.  */
  { 3, 11, 0, 0, 0 },

#define CCCC	(B3+1)
/* The 4 bit condition code in a setf instruction */
  { 4, 0, 0, 0, V850_OPERAND_CC },

/* The unsigned DISP8 field in a format 4 insn. */
#define D8	(CCCC+1)
  { 8, 0, 0, 0, 0 },

} ; 

\f
/* reg-reg instruction format (Format I) */
#define IF1	{R1, R2}

/* imm-reg instruction format (Format II) */
#define IF2	{I5, R2}

/* conditional branch instruction format (Format III) */
#define IF3	{D9}

/* 16-bit load/store instruction (Format IV) */
#define IF4A	{D7S, R1, R2}
#define IF4B	{R2, D7S, R1}
#define IF4C	{D8, R1, R2}
#define IF4D	{R2, D8, R1}

/* Jump instruction (Format V) */
#define IF5	{D22}

/* 3 operand instruction (Format VI) */
#define IF6	{I16, R1, R2}

/* 32-bit load/store instruction (Format VII) */
#define IF7A	{D16, R1, R2}
#define IF7B	{R2, D16, R1}

/* Bit manipulation function.  */


\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct v850_opcode v850_opcodes[] = {
/* load/store instructions */
{ "sld.b",	OP(0x00),		OP_MASK,	IF4A, 2 },
{ "sld.h",	OP(0x00),		OP_MASK,	IF4C, 2 },
{ "sld.w",	OP(0x00),		OP_MASK,	IF4C, 2 },
{ "sst.b",	OP(0x00),		OP_MASK,	IF4B, 2 },
{ "sst.h",	OP(0x00),		OP_MASK,	IF4D, 2 },
{ "sst.w",	OP(0x00),		OP_MASK,	IF4D, 2 },

{ "ld.b",	OP(0x00),		OP_MASK,	IF7A, 4 },
{ "ld.h",	OP(0x00),		OP_MASK,	IF7A, 4 },
{ "ld.w",	OP(0x00),		OP_MASK,	IF7A, 4 },
{ "st.b",	OP(0x00),		OP_MASK,	IF7B, 4 },
{ "st.h",	OP(0x00),		OP_MASK,	IF7B, 4 },
{ "st.w",	OP(0x00),		OP_MASK,	IF7B, 4 },

/* arithmetic operation instructions */
{ "mov",        OP(0x00),		OP_MASK,	IF1, 2 },
{ "mov",	OP(0x08),		OP_MASK,	IF2, 2 },
{ "movea",	OP(0x31),		OP_MASK,	IF6, 4 },
{ "movhi",	OP(0x31),		OP_MASK,	IF6, 4 },
{ "add",	OP(0x0e),		OP_MASK,	IF1, 2 },
{ "add",	OP(0x12),		OP_MASK,	IF2, 2 },
{ "addi",	OP(0x30),		OP_MASK,	IF6, 4 },
{ "sub",	OP(0x0d),		OP_MASK,	IF1, 2 },
{ "subr", 	OP(0x0c),		OP_MASK,	IF1, 2 },
{ "mulh",	OP(0x07),		OP_MASK,	IF1, 2 },
{ "mulh",	OP(0x17),		OP_MASK,	IF2, 2 },
{ "mulhi",	OP(0x37),		OP_MASK,	IF6, 4 },
{ "divh",	OP(0x02),		OP_MASK,	IF1, 2 },
{ "cmp",	OP(0x0f),		OP_MASK,	IF1, 2 },
{ "cmp",	OP(0x13),		OP_MASK,	IF2, 2 },
{ "setf",	two(0x0000,0x0000),	two(0x0000,0xffff), {CCCC,R2}, 4 },

/* saturated operation instructions */
{ "satadd",	OP(0x06),		OP_MASK,	IF1, 2 },
{ "satadd",	OP(0x11),		OP_MASK,	IF2, 2 },
{ "satsub",	OP(0x05),		OP_MASK,	IF1, 2 },
{ "satsubi",	OP(0x33),		OP_MASK,	IF6, 4 },
{ "satsubr",	OP(0x04),		OP_MASK,	IF1, 2 },

/* logical operation instructions */
{ "tst",	OP(0x0b),		OP_MASK,	IF1, 2 },
{ "or",		OP(0x08),		OP_MASK,	IF1, 2 },
{ "ori",	OP(0x34),		OP_MASK,	IF6, 4 },
{ "and",	OP(0x0a),		OP_MASK,	IF1, 2 },
{ "andi",	OP(0x36),		OP_MASK,	IF6, 4 },
{ "xor",	OP(0x09),		OP_MASK,	IF1, 2 },
{ "xori",	OP(0x35),		OP_MASK,	IF6, 4 },
{ "not",	OP(0x01),		OP_MASK,	IF1, 4 },
{ "sar",	OP(0x15),		OP_MASK,	{I5U, R2}, 2 },
{ "sar",	two(0x07e0,0x00a0),	two(0x07e0,0xffff),	{R1,R2}, 4 },
{ "shl",	OP(0x16),		OP_MASK,		{I5U, R2}, 2 },
{ "shl",	two(0x07e0,0x00c0),	two(0x07e0,0xffff),	{R1,R2}, 4 },
{ "shr",	OP(0x14),		OP_MASK,		{I5U, R2}, 2 },
{ "shr",	two(0x07e0,0x0080),	two(0x07e0,0xffff),	{R1,R2}, 4 },

/* branch instructions */
	/* signed integer */
{ "bgt",	BOP(0xf),		BOP_MASK,	IF3, 2 },
{ "bge",	BOP(0xe),		BOP_MASK,	IF3, 2 },
{ "blt",	BOP(0x6),		BOP_MASK,	IF3, 2 },
{ "ble",	BOP(0x7),		BOP_MASK,	IF3, 2 },
	/* unsigned integer */
{ "bh",		BOP(0xb),		BOP_MASK,	IF3, 2 },
{ "bnh",	BOP(0x3),		BOP_MASK,	IF3, 2 },
{ "bl",		BOP(0x1),		BOP_MASK,	IF3, 2 },
{ "bnl",	BOP(0x9),		BOP_MASK,	IF3, 2 },
	/* common */
{ "be",		BOP(0x2),		BOP_MASK,	IF3, 2 },
{ "bne",	BOP(0xa),		BOP_MASK,	IF3, 2 },
	/* others */
{ "bv",		BOP(0x0),		BOP_MASK,	IF3, 2 },
{ "bnv",	BOP(0x8),		BOP_MASK,	IF3, 2 },
{ "bn",		BOP(0x4),		BOP_MASK,	IF3, 2 },
{ "bp",		BOP(0xc),		BOP_MASK,	IF3, 2 },
{ "bc",		BOP(0x1),		BOP_MASK,	IF3, 2 },
{ "bnc",	BOP(0x9),		BOP_MASK,	IF3, 2 },
{ "bz",		BOP(0x2),		BOP_MASK,	IF3, 2 },
{ "bnz",	BOP(0xa),		BOP_MASK,	IF3, 2 },
{ "br",		BOP(0x5),		BOP_MASK,	IF3, 2 },
{ "bsa",	BOP(0xd),		BOP_MASK,	IF3, 2 },

{ "jmp",	one(0x0060),		one(0xffe0),	{ R1}, 2 },
{ "jarl",	one(0x0780),		one(0xf83f),	{ D22, R2 }, 4 }, 
{ "jr",		one(0x0780),		one(0xffe0),	{ D22 }, 4 },

/* bit manipulation instructions */
{ "set1",	two(0x07c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1}, 4 },
{ "not1",	two(0x47c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1}, 4 },
{ "clr1",	two(0x87c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1}, 4 },
{ "tst1",	two(0xc7c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1}, 4 },

/* special instructions */
{ "di",		two(0x07e0,0x0160),	two(0xffff,0xffff),	{0}, 4 },
{ "ei",		two(0x87e0,0x0160),	two(0xffff,0xffff),	{0}, 4 },
{ "halt",	two(0x07e0,0x0120),	two(0xffff,0xffff),	{0}, 4 },
{ "reti",	two(0x07e0,0x0140),	two(0xffff,0xffff),	{0}, 4 },
{ "trap",	two(0x07e0,0x0100),	two(0xffe0,0xffff),	{I5U}, 4 },
{ "ldsr",	two(0x07e0,0x0020),	two(0x07e0,0xffff),	IF1, 4 },
{ "stsr",	two(0x07e0,0x0040),	two(0x07e0,0xffff),	IF1, 4 },
{ "nop",	one(0x00),		one(0xff),		{0}, 2 },

} ;

const int v850_num_opcodes =
  sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);

\f
/* The functions used to insert and extract complicated operands.  */

static unsigned long
insert_d9 (insn, value, errmsg)
     unsigned long insn;
     long value;
     const char **errmsg;
{
  if (value > 511 || value <= -512)
    *errmsg = "value out of range";

  return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
}

static long
extract_d9 (insn, invalid)
     unsigned long insn;
     int *invalid;
{
  long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);

  if ((insn & 0x8000) != 0)
    ret -= 0x0200;

  return ret;
}
Commit	Line	Data
6d1e1ee8 C	1	#include "ansidecl.h"
	2	#include "opcode/v850.h"
	3
4f235110 C	4	/* Local insertion and extraction functions. */
	5	static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
	6	static long extract_d9 PARAMS ((unsigned long, int *));
	7
6d1e1ee8 C	8	/* regular opcode */
	9	#define OP(x) ((x & 0x3f) << 5)
	10	#define OP_MASK OP(0x3f)
	11
	12	/* conditional branch opcode */
	13	#define BOP(x) ((0x0b << 7) \| (x & 0x0f))
	14	#define BOP_MASK ((0x0b << 7) \| 0x0f)
	15
	16	/* one-word opcodes */
	17	#define one(x) ((unsigned int) (x))
	18
	19	/* two-word opcodes */
	20	#define two(x,y) ((unsigned int) (y) \| ((unsigned int) (x) << 16))
	21
	22
	23	\f
	24	const struct v850_operand v850_operands[] = {
	25	#define UNUSED 0
69463cbb	26	{ 0, 0, 0, 0, 0 },
6d1e1ee8 C	27
	28	/* The R1 field in a format 1, 6, 7, or 9 insn. */
	29	#define R1 (UNUSED+1)
69463cbb	30	{ 5, 0, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	31
	32	/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
	33	#define R2 (R1+1)
69463cbb	34	{ 5, 11, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	35
	36	/* The IMM5 field in a format 2 insn. */
	37	#define I5 (R2+1)
dbc6a8f6 C	38	{ 5, 0, 0, 0, V850_OPERAND_SIGNED },
	39
	40	#define I5U (I5+1)
	41	{ 5, 0, 0, 0, 0 },
6d1e1ee8	42
4f235110	43	/* The IMM16 field in a format 6 insn. */
dbc6a8f6	44	#define I16 (I5U+1)
69463cbb	45	{ 16, 0, 0, 0, 0 },
6d1e1ee8	46
4be84c49 JL	47	/* The signed DISP7 field in a format 4 insn. */
	48	#define D7S (I16+1)
	49	{ 7, 0, 0, 0, V850_OPERAND_SIGNED },
6d1e1ee8	50
4f235110	51	/* The DISP9 field in a format 3 insn. */
4be84c49	52	#define D9 (D7S+1)
dbc6a8f6	53	{ 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
6d1e1ee8 C	54
6d1e1ee8 C	55	/* The DISP16 field in a format 6 insn. */
4f235110	56	#define D16 (D9+1)
dbc6a8f6	57	{ 16, 0, 0, 0, V850_OPERAND_SIGNED },
6d1e1ee8 C	58
	59	/* The DISP22 field in a format 4 insn. */
	60	#define D22 (D16+1)
69463cbb	61	{ 16, 0, 0, 0, 0 },
7c8157dd JL	62
	63	#define B3 (D22+1)
	64	/* The 3 bit immediate field in format 8 insn. */
3c72ab70	65	{ 3, 11, 0, 0, 0 },
69463cbb C	66
	67	#define CCCC (B3+1)
	68	/* The 4 bit condition code in a setf instruction */
4be84c49 JL	69	{ 4, 0, 0, 0, V850_OPERAND_CC },
	70
	71	/* The unsigned DISP8 field in a format 4 insn. */
	72	#define D8 (CCCC+1)
	73	{ 8, 0, 0, 0, 0 },
	74
6d1e1ee8 C	75	} ;
	76
	77	\f
	78	/* reg-reg instruction format (Format I) */
	79	#define IF1 {R1, R2}
	80
	81	/* imm-reg instruction format (Format II) */
	82	#define IF2 {I5, R2}
	83
	84	/* conditional branch instruction format (Format III) */
4f235110	85	#define IF3 {D9}
6d1e1ee8 C	86
6d1e1ee8 C	87	/* 16-bit load/store instruction (Format IV) */
4be84c49 JL	88	#define IF4A {D7S, R1, R2}
	89	#define IF4B {R2, D7S, R1}
	90	#define IF4C {D8, R1, R2}
	91	#define IF4D {R2, D8, R1}
6d1e1ee8 C	92
	93	/* Jump instruction (Format V) */
	94	#define IF5 {D22}
	95
	96	/* 3 operand instruction (Format VI) */
e89a42c1	97	#define IF6 {I16, R1, R2}
6d1e1ee8 C	98
6d1e1ee8 C	99	/* 32-bit load/store instruction (Format VII) */
e89a42c1 C	100	#define IF7A {D16, R1, R2}
e89a42c1 C	101	#define IF7B {R2, D16, R1}
6d1e1ee8	102
b10e29f4	103	/* Bit manipulation function. */
6d1e1ee8 C	104
	105
	106	\f
	107	/* The opcode table.
	108
	109	The format of the opcode table is:
	110
	111	NAME OPCODE MASK { OPERANDS }
	112
	113	NAME is the name of the instruction.
	114	OPCODE is the instruction opcode.
	115	MASK is the opcode mask; this is used to tell the disassembler
	116	which bits in the actual opcode must match OPCODE.
	117	OPERANDS is the list of operands.
	118
	119	The disassembler reads the table in order and prints the first
	120	instruction which matches, so this table is sorted to put more
	121	specific instructions before more general instructions. It is also
	122	sorted by major opcode. */
	123
	124	const struct v850_opcode v850_opcodes[] = {
	125	/* load/store instructions */
280d40df JL	126	{ "sld.b", OP(0x00), OP_MASK, IF4A, 2 },
	127	{ "sld.h", OP(0x00), OP_MASK, IF4C, 2 },
	128	{ "sld.w", OP(0x00), OP_MASK, IF4C, 2 },
	129	{ "sst.b", OP(0x00), OP_MASK, IF4B, 2 },
	130	{ "sst.h", OP(0x00), OP_MASK, IF4D, 2 },
	131	{ "sst.w", OP(0x00), OP_MASK, IF4D, 2 },
	132
	133	{ "ld.b", OP(0x00), OP_MASK, IF7A, 4 },
	134	{ "ld.h", OP(0x00), OP_MASK, IF7A, 4 },
	135	{ "ld.w", OP(0x00), OP_MASK, IF7A, 4 },
	136	{ "st.b", OP(0x00), OP_MASK, IF7B, 4 },
	137	{ "st.h", OP(0x00), OP_MASK, IF7B, 4 },
	138	{ "st.w", OP(0x00), OP_MASK, IF7B, 4 },
6d1e1ee8 C	139
6d1e1ee8 C	140	/* arithmetic operation instructions */
280d40df JL	141	{ "mov", OP(0x00), OP_MASK, IF1, 2 },
	142	{ "mov", OP(0x08), OP_MASK, IF2, 2 },
	143	{ "movea", OP(0x31), OP_MASK, IF6, 4 },
	144	{ "movhi", OP(0x31), OP_MASK, IF6, 4 },
	145	{ "add", OP(0x0e), OP_MASK, IF1, 2 },
	146	{ "add", OP(0x12), OP_MASK, IF2, 2 },
	147	{ "addi", OP(0x30), OP_MASK, IF6, 4 },
	148	{ "sub", OP(0x0d), OP_MASK, IF1, 2 },
	149	{ "subr", OP(0x0c), OP_MASK, IF1, 2 },
	150	{ "mulh", OP(0x07), OP_MASK, IF1, 2 },
	151	{ "mulh", OP(0x17), OP_MASK, IF2, 2 },
	152	{ "mulhi", OP(0x37), OP_MASK, IF6, 4 },
	153	{ "divh", OP(0x02), OP_MASK, IF1, 2 },
	154	{ "cmp", OP(0x0f), OP_MASK, IF1, 2 },
	155	{ "cmp", OP(0x13), OP_MASK, IF2, 2 },
	156	{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2}, 4 },
6d1e1ee8 C	157
6d1e1ee8 C	158	/* saturated operation instructions */
280d40df JL	159	{ "satadd", OP(0x06), OP_MASK, IF1, 2 },
	160	{ "satadd", OP(0x11), OP_MASK, IF2, 2 },
	161	{ "satsub", OP(0x05), OP_MASK, IF1, 2 },
	162	{ "satsubi", OP(0x33), OP_MASK, IF6, 4 },
	163	{ "satsubr", OP(0x04), OP_MASK, IF1, 2 },
6d1e1ee8 C	164
6d1e1ee8 C	165	/* logical operation instructions */
280d40df JL	166	{ "tst", OP(0x0b), OP_MASK, IF1, 2 },
	167	{ "or", OP(0x08), OP_MASK, IF1, 2 },
	168	{ "ori", OP(0x34), OP_MASK, IF6, 4 },
	169	{ "and", OP(0x0a), OP_MASK, IF1, 2 },
	170	{ "andi", OP(0x36), OP_MASK, IF6, 4 },
	171	{ "xor", OP(0x09), OP_MASK, IF1, 2 },
	172	{ "xori", OP(0x35), OP_MASK, IF6, 4 },
	173	{ "not", OP(0x01), OP_MASK, IF1, 4 },
	174	{ "sar", OP(0x15), OP_MASK, {I5U, R2}, 2 },
	175	{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2}, 4 },
	176	{ "shl", OP(0x16), OP_MASK, {I5U, R2}, 2 },
	177	{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2}, 4 },
	178	{ "shr", OP(0x14), OP_MASK, {I5U, R2}, 2 },
	179	{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2}, 4 },
6d1e1ee8 C	180
6d1e1ee8 C	181	/* branch instructions */
6bc33c7f	182	/* signed integer */
280d40df JL	183	{ "bgt", BOP(0xf), BOP_MASK, IF3, 2 },
	184	{ "bge", BOP(0xe), BOP_MASK, IF3, 2 },
	185	{ "blt", BOP(0x6), BOP_MASK, IF3, 2 },
	186	{ "ble", BOP(0x7), BOP_MASK, IF3, 2 },
6bc33c7f	187	/* unsigned integer */
280d40df JL	188	{ "bh", BOP(0xb), BOP_MASK, IF3, 2 },
	189	{ "bnh", BOP(0x3), BOP_MASK, IF3, 2 },
	190	{ "bl", BOP(0x1), BOP_MASK, IF3, 2 },
	191	{ "bnl", BOP(0x9), BOP_MASK, IF3, 2 },
6bc33c7f	192	/* common */
280d40df JL	193	{ "be", BOP(0x2), BOP_MASK, IF3, 2 },
280d40df JL	194	{ "bne", BOP(0xa), BOP_MASK, IF3, 2 },
6bc33c7f	195	/* others */
280d40df JL	196	{ "bv", BOP(0x0), BOP_MASK, IF3, 2 },
	197	{ "bnv", BOP(0x8), BOP_MASK, IF3, 2 },
	198	{ "bn", BOP(0x4), BOP_MASK, IF3, 2 },
	199	{ "bp", BOP(0xc), BOP_MASK, IF3, 2 },
	200	{ "bc", BOP(0x1), BOP_MASK, IF3, 2 },
	201	{ "bnc", BOP(0x9), BOP_MASK, IF3, 2 },
	202	{ "bz", BOP(0x2), BOP_MASK, IF3, 2 },
	203	{ "bnz", BOP(0xa), BOP_MASK, IF3, 2 },
	204	{ "br", BOP(0x5), BOP_MASK, IF3, 2 },
	205	{ "bsa", BOP(0xd), BOP_MASK, IF3, 2 },
	206
85b52013	207	{ "jmp", one(0x0060), one(0xffe0), { R1}, 2 },
280d40df JL	208	{ "jarl", one(0x0780), one(0xf83f), { D22, R2 }, 4 },
280d40df JL	209	{ "jr", one(0x0780), one(0xffe0), { D22 }, 4 },
6d1e1ee8	210
6d1e1ee8	211	/* bit manipulation instructions */
280d40df JL	212	{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
	213	{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
	214	{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
	215	{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
6d1e1ee8 C	216
6d1e1ee8 C	217	/* special instructions */
280d40df JL	218	{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0}, 4 },
	219	{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0}, 4 },
	220	{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0}, 4 },
	221	{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0}, 4 },
c262d7d8	222	{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5U}, 4 },
280d40df JL	223	{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), IF1, 4 },
	224	{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), IF1, 4 },
	225	{ "nop", one(0x00), one(0xff), {0}, 2 },
6d1e1ee8 C	226
	227	} ;
	228
	229	const int v850_num_opcodes =
	230	sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
	231
4f235110 C	232	\f
	233	/* The functions used to insert and extract complicated operands. */
	234
	235	static unsigned long
	236	insert_d9 (insn, value, errmsg)
	237	unsigned long insn;
	238	long value;
	239	const char **errmsg;
	240	{
	241	if (value > 511 \|\| value <= -512)
	242	*errmsg = "value out of range";
	243
	244	return (insn \| ((value & 0x1f0) << 7) \| ((value & 0x0e) << 3));
	245	}
	246
	247	static long
	248	extract_d9 (insn, invalid)
	249	unsigned long insn;
	250	int *invalid;
	251	{
	252	long ret = ((insn & 0xf800) >> 7) \| ((insn & 0x0070) >> 3);
	253
	254	if ((insn & 0x8000) != 0)
	255	ret -= 0x0200;
	256
	257	return ret;
	258	}