[thirdparty/binutils-gdb.git] / opcodes / v850-opc.c

#include "ansidecl.h"
#include "opcode/v850.h"

/* TODO:

   * All sld instructions will need special insert/extrat code. */

/* Local insertion and extraction functions.  */
static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
static long extract_d9 PARAMS ((unsigned long, int *));
static unsigned long insert_d22 PARAMS ((unsigned long, long, const char **));
static long extract_d22 PARAMS ((unsigned long, int *));
static unsigned long insert_d16_15 PARAMS ((unsigned long, long,
					    const char **));
static long extract_d16_15 PARAMS ((unsigned long, int *));

/* regular opcode */
#define OP(x)		((x & 0x3f) << 5)
#define OP_MASK		OP(0x3f)

/* conditional branch opcode */
#define BOP(x)		((0x0b << 7) | (x & 0x0f))
#define BOP_MASK	((0x0b << 7) | 0x0f)

/* one-word opcodes */
#define one(x)		((unsigned int) (x))

/* two-word opcodes */
#define two(x,y)	((unsigned int) (x) | ((unsigned int) (y) << 16))


\f
const struct v850_operand v850_operands[] = {
#define UNUSED	0
  { 0, 0, 0, 0, 0 }, 

/* The R1 field in a format 1, 6, 7, or 9 insn. */
#define R1	(UNUSED+1)
  { 5, 0, 0, 0, V850_OPERAND_REG }, 

/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
#define R2	(R1+1)
  { 5, 11, 0, 0, V850_OPERAND_REG },

/* The IMM5 field in a format 2 insn. */
#define I5	(R2+1)
  { 5, 0, 0, 0, V850_OPERAND_SIGNED }, 

#define I5U	(I5+1)
  { 5, 0, 0, 0, 0 },

/* The IMM16 field in a format 6 insn. */
#define I16	(I5U+1)
  { 16, 16, 0, 0, V850_OPERAND_SIGNED }, 

/* The signed DISP7 field in a format 4 insn. */
#define D7S	(I16+1)
  { 7, 0, 0, 0, V850_OPERAND_SIGNED },

/* The DISP9 field in a format 3 insn. */
#define D9	(D7S+1)
  { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },

/* The DISP16 field in a format 6 insn. */
#define D16_15	(D9+1)
  { 16, 16, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, 

/* The DISP22 field in a format 4 insn. */
#define D22	(D16_15+1)
  { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED },

#define B3	(D22+1)
/* The 3 bit immediate field in format 8 insn.  */
  { 3, 11, 0, 0, 0 },

#define CCCC	(B3+1)
/* The 4 bit condition code in a setf instruction */
  { 4, 0, 0, 0, V850_OPERAND_CC },

/* The unsigned DISP8 field in a format 4 insn. */
#define D8	(CCCC+1)
  { 8, 0, 0, 0, 0 },

/* System register operands.  */
#define SR1	(D8+1)
  { 5, 0, 0, 0, V850_OPERAND_SRG },

/* EP Register.  */
#define EP	(SR1+1)
  { 0, 0, 0, 0, V850_OPERAND_EP },

/* The IMM16 field (unsigned0 in a format 6 insn. */
#define I16U	(EP+1)
  { 16, 16, 0, 0, 0}, 

/* The R2 field as a system register.  */
#define SR2	(I16U+1)
  { 5, 11, 0, 0, V850_OPERAND_SRG },

/* The DISP16 field in a format 8 insn. */
#define D16	(SR2+1)
  { 16, 16, 0, 0, V850_OPERAND_SIGNED }, 

} ; 

\f
/* reg-reg instruction format (Format I) */
#define IF1	{R1, R2}

/* imm-reg instruction format (Format II) */
#define IF2	{I5, R2}

/* conditional branch instruction format (Format III) */
#define IF3	{D9}

/* 16-bit load/store instruction (Format IV) */
#define IF4A	{D7S, EP, R2}
#define IF4B	{R2, D7S, EP}
#define IF4C	{D8, EP, R2}
#define IF4D	{R2, D8, EP}

/* Jump instruction (Format V) */
#define IF5	{D22}

/* 3 operand instruction (Format VI) */
#define IF6	{I16, R1, R2}

/* 3 operand instruction (Format VI) */
#define IF6U	{I16U, R1, R2}

/* 32-bit load/store half/word instruction (Format VII) */
#define IF7A	{D16_15, R1, R2}
#define IF7B	{R2, D16_15, R1}

/* 32-bit load/store byte instruction (Format VII) */
#define IF7C	{D16, R1, R2}
#define IF7D	{R2, D16, R1}

/* Bit manipulation function.  */


\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct v850_opcode v850_opcodes[] = {
/* load/store instructions */
{ "sld.b",	one(0x0300),		one(0x0780),	IF4A, 2 },
{ "sld.h",	one(0x0400),		one(0x0780),	IF4A, 2 },
{ "sld.w",	one(0x0500),		one(0x0781),	IF4A, 2 },
{ "sst.b",	one(0x0380),		one(0x0780),	IF4B, 2 },
{ "sst.h",	one(0x0480),		one(0x0780),	IF4D, 2 },
{ "sst.w",	one(0x0501),		one(0x0781),	IF4D, 2 },

{ "ld.b",	two(0x0700,0x0000),	two (0x07e0,0x0000),	IF7C, 4 },
{ "ld.h",	two(0x0720,0x0000),	two (0x07e0,0x0001),	IF7A, 4 },
{ "ld.w",	two(0x0720,0x0001),	two (0x07e0,0x0001),	IF7A, 4 },
{ "st.b",	two(0x0740,0x0000),	two (0x07e0,0x0000),	IF7D, 4 },
{ "st.h",	two(0x0760,0x0000),	two (0x07e0,0x0001),	IF7B, 4 },
{ "st.w",	two(0x0760,0x0001),	two (0x07e0,0x0001),	IF7B, 4 },

/* arithmetic operation instructions */
{ "mov",        OP(0x00),		OP_MASK,	IF1, 2 },
{ "mov",	OP(0x10),		OP_MASK,	IF2, 2 },
{ "movea",	OP(0x31),		OP_MASK,	IF6, 4 },
{ "movhi",	OP(0x32),		OP_MASK,	IF6, 4 },
{ "add",	OP(0x0e),		OP_MASK,	IF1, 2 },
{ "add",	OP(0x12),		OP_MASK,	IF2, 2 },
{ "addi",	OP(0x30),		OP_MASK,	IF6, 4 },
{ "sub",	OP(0x0d),		OP_MASK,	IF1, 2 },
{ "subr", 	OP(0x0c),		OP_MASK,	IF1, 2 },
{ "mulh",	OP(0x07),		OP_MASK,	IF1, 2 },
{ "mulh",	OP(0x17),		OP_MASK,	IF2, 2 },
{ "mulhi",	OP(0x37),		OP_MASK,	IF6, 4 },
{ "divh",	OP(0x02),		OP_MASK,	IF1, 2 },
{ "cmp",	OP(0x0f),		OP_MASK,	IF1, 2 },
{ "cmp",	OP(0x13),		OP_MASK,	IF2, 2 },
{ "setf",	two(0x07e0,0x0000),	two(0x07f0,0xffff), {CCCC,R2}, 4 },

/* saturated operation instructions */
{ "satadd",	OP(0x06),		OP_MASK,	IF1, 2 },
{ "satadd",	OP(0x11),		OP_MASK,	IF2, 2 },
{ "satsub",	OP(0x05),		OP_MASK,	IF1, 2 },
{ "satsubi",	OP(0x33),		OP_MASK,	IF6, 4 },
{ "satsubr",	OP(0x04),		OP_MASK,	IF1, 2 },

/* logical operation instructions */
{ "tst",	OP(0x0b),		OP_MASK,	IF1, 2 },
{ "or",		OP(0x08),		OP_MASK,	IF1, 2 },
{ "ori",	OP(0x34),		OP_MASK,	IF6U, 4 },
{ "and",	OP(0x0a),		OP_MASK,	IF1, 2 },
{ "andi",	OP(0x36),		OP_MASK,	IF6U, 4 },
{ "xor",	OP(0x09),		OP_MASK,	IF1, 2 },
{ "xori",	OP(0x35),		OP_MASK,	IF6U, 4 },
{ "not",	OP(0x01),		OP_MASK,	IF1, 2 },
{ "sar",	OP(0x15),		OP_MASK,	{I5U, R2}, 2 },
{ "sar",	two(0x07e0,0x00a0),	two(0x07e0,0xffff),	{R1,R2}, 4 },
{ "shl",	OP(0x16),		OP_MASK,		{I5U, R2}, 2 },
{ "shl",	two(0x07e0,0x00c0),	two(0x07e0,0xffff),	{R1,R2}, 4 },
{ "shr",	OP(0x14),		OP_MASK,		{I5U, R2}, 2 },
{ "shr",	two(0x07e0,0x0080),	two(0x07e0,0xffff),	{R1,R2}, 4 },

/* branch instructions */
	/* signed integer */
{ "bgt",	BOP(0xf),		BOP_MASK,	IF3, 2 },
{ "bge",	BOP(0xe),		BOP_MASK,	IF3, 2 },
{ "blt",	BOP(0x6),		BOP_MASK,	IF3, 2 },
{ "ble",	BOP(0x7),		BOP_MASK,	IF3, 2 },
	/* unsigned integer */
{ "bh",		BOP(0xb),		BOP_MASK,	IF3, 2 },
{ "bnh",	BOP(0x3),		BOP_MASK,	IF3, 2 },
{ "bl",		BOP(0x1),		BOP_MASK,	IF3, 2 },
{ "bnl",	BOP(0x9),		BOP_MASK,	IF3, 2 },
	/* common */
{ "be",		BOP(0x2),		BOP_MASK,	IF3, 2 },
{ "bne",	BOP(0xa),		BOP_MASK,	IF3, 2 },
	/* others */
{ "bv",		BOP(0x0),		BOP_MASK,	IF3, 2 },
{ "bnv",	BOP(0x8),		BOP_MASK,	IF3, 2 },
{ "bn",		BOP(0x4),		BOP_MASK,	IF3, 2 },
{ "bp",		BOP(0xc),		BOP_MASK,	IF3, 2 },
{ "bc",		BOP(0x1),		BOP_MASK,	IF3, 2 },
{ "bnc",	BOP(0x9),		BOP_MASK,	IF3, 2 },
{ "bz",		BOP(0x2),		BOP_MASK,	IF3, 2 },
{ "bnz",	BOP(0xa),		BOP_MASK,	IF3, 2 },
{ "br",		BOP(0x5),		BOP_MASK,	IF3, 2 },
{ "bsa",	BOP(0xd),		BOP_MASK,	IF3, 2 },

{ "jmp",	one(0x0060),		one(0xffe0),	{ R1}, 2 },
{ "jarl",	one(0x0780),		one(0xf83f),	{ D22, R2 }, 4 }, 
{ "jr",		one(0x0780),		one(0xffe0),	{ D22 }, 4 },

/* bit manipulation instructions */
{ "set1",	two(0x07c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1}, 4 },
{ "not1",	two(0x47c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1}, 4 },
{ "clr1",	two(0x87c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1}, 4 },
{ "tst1",	two(0xc7c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1}, 4 },

/* special instructions */
{ "di",		two(0x07e0,0x0160),	two(0xffff,0xffff),	{0}, 4 },
{ "ei",		two(0x87e0,0x0160),	two(0xffff,0xffff),	{0}, 4 },
{ "halt",	two(0x07e0,0x0120),	two(0xffff,0xffff),	{0}, 4 },
{ "reti",	two(0x07e0,0x0140),	two(0xffff,0xffff),	{0}, 4 },
{ "trap",	two(0x07e0,0x0100),	two(0xffe0,0xffff),	{I5U}, 4 },
{ "ldsr",	two(0x07e0,0x0020),	two(0x07e0,0xffff),	{R1,SR2}, 4 },
{ "stsr",	two(0x07e0,0x0040),	two(0x07e0,0xffff),	{SR1,R2}, 4 },
{ "nop",	one(0x00),		one(0xffff),		{0}, 2 },
{ 0, 0, 0, {0}, 0 },

} ;

const int v850_num_opcodes =
  sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);

\f
/* The functions used to insert and extract complicated operands.  */

static unsigned long
insert_d9 (insn, value, errmsg)
     unsigned long insn;
     long value;
     const char **errmsg;
{
  if (value > 255 || value <= -256)
    *errmsg = "branch value out of range";

  if ((value % 2) != 0)
    *errmsg = "branch to odd offset";

  return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
}

static long
extract_d9 (insn, invalid)
     unsigned long insn;
     int *invalid;
{
  long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);

  if ((insn & 0x8000) != 0)
    ret -= 0x0200;

  return ret;
}

static unsigned long
insert_d22 (insn, value, errmsg)
     unsigned long insn;
     long value;
     const char **errmsg;
{
  if (value > 0xfffff || value <= -0x100000)
    *errmsg = "branch value out of range";

  if ((value % 2) != 0)
    *errmsg = "branch to odd offset";

  return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
}

static long
extract_d22 (insn, invalid)
     unsigned long insn;
     int *invalid;
{
  int ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);

  return ((ret << 10) >> 10);
}

static unsigned long
insert_d16_15 (insn, value, errmsg)
     unsigned long insn;
     long value;
     const char **errmsg;
{
  if (value > 0x7fff || value <= -0x8000)
    *errmsg = "value out of range";

  if ((value % 2) != 0)
    *errmsg = "load/store at odd offset";

  return (insn | ((value & 0xfffe) << 16));
}

static long
extract_d16_15 (insn, invalid)
     unsigned long insn;
     int *invalid;
{
  int ret = ((insn & 0xfffe0000) >> 16);

  return ((ret << 16) >> 16);
}
Commit	Line	Data
6d1e1ee8 C	1	#include "ansidecl.h"
	2	#include "opcode/v850.h"
	3
69ae4b82 JL	4	/* TODO:
69ae4b82 JL	5
69ae4b82 JL	6	* All sld instructions will need special insert/extrat code. */
69ae4b82 JL	7
4f235110 C	8	/* Local insertion and extraction functions. */
	9	static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
	10	static long extract_d9 PARAMS ((unsigned long, int *));
574b9cb3 JL	11	static unsigned long insert_d22 PARAMS ((unsigned long, long, const char **));
574b9cb3 JL	12	static long extract_d22 PARAMS ((unsigned long, int *));
c6b9c135 JL	13	static unsigned long insert_d16_15 PARAMS ((unsigned long, long,
	14	const char **));
	15	static long extract_d16_15 PARAMS ((unsigned long, int *));
4f235110	16
6d1e1ee8 C	17	/* regular opcode */
	18	#define OP(x) ((x & 0x3f) << 5)
	19	#define OP_MASK OP(0x3f)
	20
	21	/* conditional branch opcode */
	22	#define BOP(x) ((0x0b << 7) \| (x & 0x0f))
	23	#define BOP_MASK ((0x0b << 7) \| 0x0f)
	24
	25	/* one-word opcodes */
	26	#define one(x) ((unsigned int) (x))
	27
	28	/* two-word opcodes */
b1e897a9	29	#define two(x,y) ((unsigned int) (x) \| ((unsigned int) (y) << 16))
6d1e1ee8 C	30
	31
	32	\f
	33	const struct v850_operand v850_operands[] = {
	34	#define UNUSED 0
69463cbb	35	{ 0, 0, 0, 0, 0 },
6d1e1ee8 C	36
	37	/* The R1 field in a format 1, 6, 7, or 9 insn. */
	38	#define R1 (UNUSED+1)
69463cbb	39	{ 5, 0, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	40
	41	/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
	42	#define R2 (R1+1)
69463cbb	43	{ 5, 11, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	44
	45	/* The IMM5 field in a format 2 insn. */
	46	#define I5 (R2+1)
dbc6a8f6 C	47	{ 5, 0, 0, 0, V850_OPERAND_SIGNED },
	48
	49	#define I5U (I5+1)
	50	{ 5, 0, 0, 0, 0 },
6d1e1ee8	51
4f235110	52	/* The IMM16 field in a format 6 insn. */
dbc6a8f6	53	#define I16 (I5U+1)
e7dd7775	54	{ 16, 16, 0, 0, V850_OPERAND_SIGNED },
6d1e1ee8	55
4be84c49 JL	56	/* The signed DISP7 field in a format 4 insn. */
	57	#define D7S (I16+1)
	58	{ 7, 0, 0, 0, V850_OPERAND_SIGNED },
6d1e1ee8	59
4f235110	60	/* The DISP9 field in a format 3 insn. */
4be84c49	61	#define D9 (D7S+1)
d44b697b	62	{ 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
6d1e1ee8 C	63
6d1e1ee8 C	64	/* The DISP16 field in a format 6 insn. */
c6b9c135 JL	65	#define D16_15 (D9+1)
c6b9c135 JL	66	{ 16, 16, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
6d1e1ee8 C	67
6d1e1ee8 C	68	/* The DISP22 field in a format 4 insn. */
c6b9c135	69	#define D22 (D16_15+1)
574b9cb3	70	{ 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED },
7c8157dd JL	71
	72	#define B3 (D22+1)
	73	/* The 3 bit immediate field in format 8 insn. */
3c72ab70	74	{ 3, 11, 0, 0, 0 },
69463cbb C	75
	76	#define CCCC (B3+1)
	77	/* The 4 bit condition code in a setf instruction */
4be84c49 JL	78	{ 4, 0, 0, 0, V850_OPERAND_CC },
	79
	80	/* The unsigned DISP8 field in a format 4 insn. */
	81	#define D8 (CCCC+1)
	82	{ 8, 0, 0, 0, 0 },
	83
e41c99bd JL	84	/* System register operands. */
e41c99bd JL	85	#define SR1 (D8+1)
d3edb57f JL	86	{ 5, 0, 0, 0, V850_OPERAND_SRG },
	87
	88	/* EP Register. */
	89	#define EP (SR1+1)
e7dd7775 JL	90	{ 0, 0, 0, 0, V850_OPERAND_EP },
	91
	92	/* The IMM16 field (unsigned0 in a format 6 insn. */
	93	#define I16U (EP+1)
	94	{ 16, 16, 0, 0, 0},
e9ebb364 JL	95
	96	/* The R2 field as a system register. */
	97	#define SR2 (I16U+1)
	98	{ 5, 11, 0, 0, V850_OPERAND_SRG },
	99
c6b9c135 JL	100	/* The DISP16 field in a format 8 insn. */
	101	#define D16 (SR2+1)
	102	{ 16, 16, 0, 0, V850_OPERAND_SIGNED },
	103
6d1e1ee8 C	104	} ;
	105
	106	\f
	107	/* reg-reg instruction format (Format I) */
	108	#define IF1 {R1, R2}
	109
	110	/* imm-reg instruction format (Format II) */
	111	#define IF2 {I5, R2}
	112
	113	/* conditional branch instruction format (Format III) */
4f235110	114	#define IF3 {D9}
6d1e1ee8 C	115
6d1e1ee8 C	116	/* 16-bit load/store instruction (Format IV) */
d3edb57f JL	117	#define IF4A {D7S, EP, R2}
	118	#define IF4B {R2, D7S, EP}
	119	#define IF4C {D8, EP, R2}
	120	#define IF4D {R2, D8, EP}
6d1e1ee8 C	121
	122	/* Jump instruction (Format V) */
	123	#define IF5 {D22}
	124
	125	/* 3 operand instruction (Format VI) */
e89a42c1	126	#define IF6 {I16, R1, R2}
6d1e1ee8	127
e7dd7775 JL	128	/* 3 operand instruction (Format VI) */
	129	#define IF6U {I16U, R1, R2}
	130
c6b9c135 JL	131	/* 32-bit load/store half/word instruction (Format VII) */
	132	#define IF7A {D16_15, R1, R2}
	133	#define IF7B {R2, D16_15, R1}
	134
	135	/* 32-bit load/store byte instruction (Format VII) */
	136	#define IF7C {D16, R1, R2}
	137	#define IF7D {R2, D16, R1}
6d1e1ee8	138
b10e29f4	139	/* Bit manipulation function. */
6d1e1ee8 C	140
	141
	142	\f
	143	/* The opcode table.
	144
	145	The format of the opcode table is:
	146
	147	NAME OPCODE MASK { OPERANDS }
	148
	149	NAME is the name of the instruction.
	150	OPCODE is the instruction opcode.
	151	MASK is the opcode mask; this is used to tell the disassembler
	152	which bits in the actual opcode must match OPCODE.
	153	OPERANDS is the list of operands.
	154
	155	The disassembler reads the table in order and prints the first
	156	instruction which matches, so this table is sorted to put more
	157	specific instructions before more general instructions. It is also
	158	sorted by major opcode. */
	159
	160	const struct v850_opcode v850_opcodes[] = {
	161	/* load/store instructions */
fb6da868 JL	162	{ "sld.b", one(0x0300), one(0x0780), IF4A, 2 },
fb6da868 JL	163	{ "sld.h", one(0x0400), one(0x0780), IF4A, 2 },
e7f3e5fb JL	164	{ "sld.w", one(0x0500), one(0x0781), IF4A, 2 },
	165	{ "sst.b", one(0x0380), one(0x0780), IF4B, 2 },
	166	{ "sst.h", one(0x0480), one(0x0780), IF4D, 2 },
	167	{ "sst.w", one(0x0501), one(0x0781), IF4D, 2 },
280d40df	168
c6b9c135	169	{ "ld.b", two(0x0700,0x0000), two (0x07e0,0x0000), IF7C, 4 },
fb6da868 JL	170	{ "ld.h", two(0x0720,0x0000), two (0x07e0,0x0001), IF7A, 4 },
fb6da868 JL	171	{ "ld.w", two(0x0720,0x0001), two (0x07e0,0x0001), IF7A, 4 },
c6b9c135	172	{ "st.b", two(0x0740,0x0000), two (0x07e0,0x0000), IF7D, 4 },
fb6da868 JL	173	{ "st.h", two(0x0760,0x0000), two (0x07e0,0x0001), IF7B, 4 },
fb6da868 JL	174	{ "st.w", two(0x0760,0x0001), two (0x07e0,0x0001), IF7B, 4 },
6d1e1ee8 C	175
6d1e1ee8 C	176	/* arithmetic operation instructions */
280d40df	177	{ "mov", OP(0x00), OP_MASK, IF1, 2 },
18c97701	178	{ "mov", OP(0x10), OP_MASK, IF2, 2 },
280d40df	179	{ "movea", OP(0x31), OP_MASK, IF6, 4 },
18c97701	180	{ "movhi", OP(0x32), OP_MASK, IF6, 4 },
280d40df JL	181	{ "add", OP(0x0e), OP_MASK, IF1, 2 },
	182	{ "add", OP(0x12), OP_MASK, IF2, 2 },
	183	{ "addi", OP(0x30), OP_MASK, IF6, 4 },
	184	{ "sub", OP(0x0d), OP_MASK, IF1, 2 },
	185	{ "subr", OP(0x0c), OP_MASK, IF1, 2 },
	186	{ "mulh", OP(0x07), OP_MASK, IF1, 2 },
	187	{ "mulh", OP(0x17), OP_MASK, IF2, 2 },
	188	{ "mulhi", OP(0x37), OP_MASK, IF6, 4 },
	189	{ "divh", OP(0x02), OP_MASK, IF1, 2 },
	190	{ "cmp", OP(0x0f), OP_MASK, IF1, 2 },
	191	{ "cmp", OP(0x13), OP_MASK, IF2, 2 },
6c1fc4d3	192	{ "setf", two(0x07e0,0x0000), two(0x07f0,0xffff), {CCCC,R2}, 4 },
6d1e1ee8 C	193
6d1e1ee8 C	194	/* saturated operation instructions */
280d40df JL	195	{ "satadd", OP(0x06), OP_MASK, IF1, 2 },
	196	{ "satadd", OP(0x11), OP_MASK, IF2, 2 },
	197	{ "satsub", OP(0x05), OP_MASK, IF1, 2 },
	198	{ "satsubi", OP(0x33), OP_MASK, IF6, 4 },
	199	{ "satsubr", OP(0x04), OP_MASK, IF1, 2 },
6d1e1ee8 C	200
6d1e1ee8 C	201	/* logical operation instructions */
280d40df JL	202	{ "tst", OP(0x0b), OP_MASK, IF1, 2 },
280d40df JL	203	{ "or", OP(0x08), OP_MASK, IF1, 2 },
e7dd7775	204	{ "ori", OP(0x34), OP_MASK, IF6U, 4 },
280d40df	205	{ "and", OP(0x0a), OP_MASK, IF1, 2 },
e7dd7775	206	{ "andi", OP(0x36), OP_MASK, IF6U, 4 },
280d40df	207	{ "xor", OP(0x09), OP_MASK, IF1, 2 },
e7dd7775	208	{ "xori", OP(0x35), OP_MASK, IF6U, 4 },
38c7a450	209	{ "not", OP(0x01), OP_MASK, IF1, 2 },
280d40df JL	210	{ "sar", OP(0x15), OP_MASK, {I5U, R2}, 2 },
	211	{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2}, 4 },
	212	{ "shl", OP(0x16), OP_MASK, {I5U, R2}, 2 },
	213	{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2}, 4 },
	214	{ "shr", OP(0x14), OP_MASK, {I5U, R2}, 2 },
	215	{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2}, 4 },
6d1e1ee8 C	216
6d1e1ee8 C	217	/* branch instructions */
6bc33c7f	218	/* signed integer */
280d40df JL	219	{ "bgt", BOP(0xf), BOP_MASK, IF3, 2 },
	220	{ "bge", BOP(0xe), BOP_MASK, IF3, 2 },
	221	{ "blt", BOP(0x6), BOP_MASK, IF3, 2 },
	222	{ "ble", BOP(0x7), BOP_MASK, IF3, 2 },
6bc33c7f	223	/* unsigned integer */
280d40df JL	224	{ "bh", BOP(0xb), BOP_MASK, IF3, 2 },
	225	{ "bnh", BOP(0x3), BOP_MASK, IF3, 2 },
	226	{ "bl", BOP(0x1), BOP_MASK, IF3, 2 },
	227	{ "bnl", BOP(0x9), BOP_MASK, IF3, 2 },
6bc33c7f	228	/* common */
280d40df JL	229	{ "be", BOP(0x2), BOP_MASK, IF3, 2 },
280d40df JL	230	{ "bne", BOP(0xa), BOP_MASK, IF3, 2 },
6bc33c7f	231	/* others */
280d40df JL	232	{ "bv", BOP(0x0), BOP_MASK, IF3, 2 },
	233	{ "bnv", BOP(0x8), BOP_MASK, IF3, 2 },
	234	{ "bn", BOP(0x4), BOP_MASK, IF3, 2 },
	235	{ "bp", BOP(0xc), BOP_MASK, IF3, 2 },
	236	{ "bc", BOP(0x1), BOP_MASK, IF3, 2 },
	237	{ "bnc", BOP(0x9), BOP_MASK, IF3, 2 },
	238	{ "bz", BOP(0x2), BOP_MASK, IF3, 2 },
	239	{ "bnz", BOP(0xa), BOP_MASK, IF3, 2 },
	240	{ "br", BOP(0x5), BOP_MASK, IF3, 2 },
	241	{ "bsa", BOP(0xd), BOP_MASK, IF3, 2 },
	242
85b52013	243	{ "jmp", one(0x0060), one(0xffe0), { R1}, 2 },
280d40df JL	244	{ "jarl", one(0x0780), one(0xf83f), { D22, R2 }, 4 },
280d40df JL	245	{ "jr", one(0x0780), one(0xffe0), { D22 }, 4 },
6d1e1ee8	246
6d1e1ee8	247	/* bit manipulation instructions */
280d40df JL	248	{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
	249	{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
	250	{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
	251	{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
6d1e1ee8 C	252
6d1e1ee8 C	253	/* special instructions */
280d40df JL	254	{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0}, 4 },
	255	{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0}, 4 },
	256	{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0}, 4 },
	257	{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0}, 4 },
c262d7d8	258	{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5U}, 4 },
e9ebb364	259	{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {R1,SR2}, 4 },
e41c99bd	260	{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {SR1,R2}, 4 },
e7f3e5fb	261	{ "nop", one(0x00), one(0xffff), {0}, 2 },
e7dd7775	262	{ 0, 0, 0, {0}, 0 },
6d1e1ee8 C	263
	264	} ;
	265
	266	const int v850_num_opcodes =
	267	sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
	268
4f235110 C	269	\f
	270	/* The functions used to insert and extract complicated operands. */
	271
	272	static unsigned long
	273	insert_d9 (insn, value, errmsg)
	274	unsigned long insn;
	275	long value;
	276	const char **errmsg;
	277	{
574b9cb3	278	if (value > 255 \|\| value <= -256)
fb8c25a3 JL	279	*errmsg = "branch value out of range";
	280
	281	if ((value % 2) != 0)
	282	*errmsg = "branch to odd offset";
4f235110 C	283
	284	return (insn \| ((value & 0x1f0) << 7) \| ((value & 0x0e) << 3));
	285	}
	286
	287	static long
	288	extract_d9 (insn, invalid)
	289	unsigned long insn;
	290	int *invalid;
	291	{
	292	long ret = ((insn & 0xf800) >> 7) \| ((insn & 0x0070) >> 3);
	293
	294	if ((insn & 0x8000) != 0)
	295	ret -= 0x0200;
	296
	297	return ret;
	298	}
574b9cb3 JL	299
	300	static unsigned long
	301	insert_d22 (insn, value, errmsg)
	302	unsigned long insn;
	303	long value;
	304	const char **errmsg;
	305	{
	306	if (value > 0xfffff \|\| value <= -0x100000)
c6b9c135	307	*errmsg = "branch value out of range";
574b9cb3	308
fb8c25a3 JL	309	if ((value % 2) != 0)
	310	*errmsg = "branch to odd offset";
	311
574b9cb3 JL	312	return (insn \| ((value & 0xfffe) << 16) \| ((value & 0x3f0000) >> 16));
	313	}
	314
	315	static long
	316	extract_d22 (insn, invalid)
	317	unsigned long insn;
	318	int *invalid;
	319	{
	320	int ret = ((insn & 0xfffe0000) >> 16) \| ((insn & 0x3f) << 16);
	321
	322	return ((ret << 10) >> 10);
	323	}
c6b9c135 JL	324
	325	static unsigned long
	326	insert_d16_15 (insn, value, errmsg)
	327	unsigned long insn;
	328	long value;
	329	const char **errmsg;
	330	{
	331	if (value > 0x7fff \|\| value <= -0x8000)
	332	*errmsg = "value out of range";
	333
	334	if ((value % 2) != 0)
	335	*errmsg = "load/store at odd offset";
	336
	337	return (insn \| ((value & 0xfffe) << 16));
	338	}
	339
	340	static long
	341	extract_d16_15 (insn, invalid)
	342	unsigned long insn;
	343	int *invalid;
	344	{
	345	int ret = ((insn & 0xfffe0000) >> 16);
	346
	347	return ((ret << 16) >> 16);
	348	}