[people/ms/u-boot.git] / post / cpu / mpc8xx / cache_8xx.S

/*
 *  Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>

#if defined(CONFIG_MPC823) || \
    defined(CONFIG_MPC850) || \
    defined(CONFIG_MPC855) || \
    defined(CONFIG_MPC860) || \
    defined(CONFIG_MPC862)

#include <post.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>

#if CONFIG_POST & CONFIG_SYS_POST_CACHE

	.text

cache_post_dinvalidate:
	lis	r10, IDC_INVALL@h
	mtspr	DC_CST, r10
	blr

cache_post_iinvalidate:
	lis	r10, IDC_INVALL@h
	mtspr	IC_CST, r10
	isync
	blr

cache_post_ddisable:
	lis	r10, IDC_DISABLE@h
	mtspr	DC_CST, r10
	blr

cache_post_dwb:
	lis	r10, IDC_ENABLE@h
	mtspr	DC_CST, r10
	lis	r10, DC_CFWT@h
	mtspr	DC_CST, r10
	blr

cache_post_dwt:
	lis	r10, IDC_ENABLE@h
	mtspr	DC_CST, r10
	lis	r10, DC_SFWT@h
	mtspr	DC_CST, r10
	blr

cache_post_idisable:
	lis	r10, IDC_DISABLE@h
	mtspr	IC_CST, r10
	isync
	blr

cache_post_ienable:
	lis	r10, IDC_ENABLE@h
	mtspr	IC_CST, r10
	isync
	blr

cache_post_iunlock:
	lis	r10, IDC_UNALL@h
	mtspr	IC_CST, r10
	isync
	blr

cache_post_ilock:
	mtspr	IC_ADR, r3
	lis	r10, IDC_LDLCK@h
	mtspr	IC_CST, r10
	isync
	blr

/*
 * turn on the data cache
 * switch the data cache to write-back or write-through mode
 * invalidate the data cache
 * write the negative pattern to a cached area
 * read the area
 *
 * The negative pattern must be read at the last step
 */
	.global cache_post_test1
cache_post_test1:
	mflr	r0
	stw	r0, 4(r1)

	stwu	r3, -4(r1)
	stwu	r4, -4(r1)

	bl	cache_post_dwb
	bl	cache_post_dinvalidate

	/* Write the negative pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0xff
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	/* Read the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	lwz	r4, 4(r1)
	subi	r4, r4, 1
	li	r3, 0
1:
	lbzu	r0, 1(r4)
	cmpli	cr0, r0, 0xff
	beq	2f
	li	r3, -1
	b	3f
2:
	bdnz	1b
3:

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	addi	r1, r1, 8

	lwz	r0, 4(r1)
	mtlr	r0
	blr

/*
 * turn on the data cache
 * switch the data cache to write-back or write-through mode
 * invalidate the data cache
 * write the zero pattern to a cached area
 * turn off the data cache
 * write the negative pattern to the area
 * turn on the data cache
 * read the area
 *
 * The negative pattern must be read at the last step
 */
	.global cache_post_test2
cache_post_test2:
	mflr	r0
	stw	r0, 4(r1)

	stwu	r3, -4(r1)
	stwu	r4, -4(r1)

	bl	cache_post_dwb
	bl	cache_post_dinvalidate

	/* Write the zero pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_ddisable

	/* Write the negative pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0xff
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_dwb

	/* Read the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	lwz	r4, 4(r1)
	subi	r4, r4, 1
	li	r3, 0
1:
	lbzu	r0, 1(r4)
	cmpli	cr0, r0, 0xff
	beq	2f
	li	r3, -1
	b	3f
2:
	bdnz	1b
3:

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	addi	r1, r1, 8

	lwz	r0, 4(r1)
	mtlr	r0
	blr

/*
 * turn on the data cache
 * switch the data cache to write-through mode
 * invalidate the data cache
 * write the zero pattern to a cached area
 * flush the data cache
 * write the negative pattern to the area
 * turn off the data cache
 * read the area
 *
 * The negative pattern must be read at the last step
 */
	.global cache_post_test3
cache_post_test3:
	mflr	r0
	stw	r0, 4(r1)

	stwu	r3, -4(r1)
	stwu	r4, -4(r1)

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	/* Write the zero pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_dwt
	bl	cache_post_dinvalidate

	/* Write the negative pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0xff
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	/* Read the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	lwz	r4, 4(r1)
	subi	r4, r4, 1
	li	r3, 0
1:
	lbzu	r0, 1(r4)
	cmpli	cr0, r0, 0xff
	beq	2f
	li	r3, -1
	b	3f
2:
	bdnz	1b
3:

	addi	r1, r1, 8

	lwz	r0, 4(r1)
	mtlr	r0
	blr

/*
 * turn on the data cache
 * switch the data cache to write-back mode
 * invalidate the data cache
 * write the negative pattern to a cached area
 * flush the data cache
 * write the zero pattern to the area
 * invalidate the data cache
 * read the area
 *
 * The negative pattern must be read at the last step
 */
	.global cache_post_test4
cache_post_test4:
	mflr	r0
	stw	r0, 4(r1)

	stwu	r3, -4(r1)
	stwu	r4, -4(r1)

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	/* Write the negative pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0xff
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_dwb
	bl	cache_post_dinvalidate

	/* Write the zero pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	/* Read the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	lwz	r4, 4(r1)
	subi	r4, r4, 1
	li	r3, 0
1:
	lbzu	r0, 1(r4)
	cmpli	cr0, r0, 0xff
	beq	2f
	li	r3, -1
	b	3f
2:
	bdnz	1b
3:

	addi	r1, r1, 8

	lwz	r0, 4(r1)
	mtlr	r0
	blr

cache_post_test5_1:
	li	r3, 0
cache_post_test5_2:
	li	r3, -1

/*
 * turn on the instruction cache
 * unlock the entire instruction cache
 * invalidate the instruction cache
 * lock a branch instruction in the instruction cache
 * replace the branch instruction with "nop"
 * jump to the branch instruction
 * check that the branch instruction was executed
*/
	.global cache_post_test5
cache_post_test5:
	mflr	r0
	stw	r0, 4(r1)

	bl	cache_post_ienable
	bl	cache_post_iunlock
	bl	cache_post_iinvalidate

	/* Compute r9 = cache_post_test5_reloc */
	bl	cache_post_test5_reloc
cache_post_test5_reloc:
	mflr	r9

	/* Copy the test instruction to cache_post_test5_data */
	lis	r3, (cache_post_test5_1 - cache_post_test5_reloc)@h
	ori	r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l
	add	r3, r3, r9
	lis	r4, (cache_post_test5_data - cache_post_test5_reloc)@h
	ori	r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
	add	r4, r4, r9
	lwz	r0, 0(r3)
	stw	r0, 0(r4)

	bl	cache_post_iinvalidate

	/* Lock the branch instruction */
	lis	r3, (cache_post_test5_data - cache_post_test5_reloc)@h
	ori	r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l
	add	r3, r3, r9
	bl	cache_post_ilock

	/* Replace the test instruction */
	lis	r3, (cache_post_test5_2 - cache_post_test5_reloc)@h
	ori	r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l
	add	r3, r3, r9
	lis	r4, (cache_post_test5_data - cache_post_test5_reloc)@h
	ori	r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
	add	r4, r4, r9
	lwz	r0, 0(r3)
	stw	r0, 0(r4)

	bl	cache_post_iinvalidate

	/* Execute to the test instruction */
cache_post_test5_data:
	nop

	bl	cache_post_iunlock

	lwz	r0, 4(r1)
	mtlr	r0
	blr

cache_post_test6_1:
	li	r3, -1
cache_post_test6_2:
	li	r3, 0

/*
 * turn on the instruction cache
 * unlock the entire instruction cache
 * invalidate the instruction cache
 * lock a branch instruction in the instruction cache
 * replace the branch instruction with "nop"
 * jump to the branch instruction
 * check that the branch instruction was executed
 */
	.global cache_post_test6
cache_post_test6:
	mflr	r0
	stw	r0, 4(r1)

	bl	cache_post_ienable
	bl	cache_post_iunlock
	bl	cache_post_iinvalidate

	/* Compute r9 = cache_post_test6_reloc */
	bl	cache_post_test6_reloc
cache_post_test6_reloc:
	mflr	r9

	/* Copy the test instruction to cache_post_test6_data */
	lis	r3, (cache_post_test6_1 - cache_post_test6_reloc)@h
	ori	r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l
	add	r3, r3, r9
	lis	r4, (cache_post_test6_data - cache_post_test6_reloc)@h
	ori	r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
	add	r4, r4, r9
	lwz	r0, 0(r3)
	stw	r0, 0(r4)

	bl	cache_post_iinvalidate

	/* Replace the test instruction */
	lis	r3, (cache_post_test6_2 - cache_post_test6_reloc)@h
	ori	r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l
	add	r3, r3, r9
	lis	r4, (cache_post_test6_data - cache_post_test6_reloc)@h
	ori	r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
	add	r4, r4, r9
	lwz	r0, 0(r3)
	stw	r0, 0(r4)

	bl	cache_post_iinvalidate

	/* Execute to the test instruction */
cache_post_test6_data:
	nop

	lwz	r0, 4(r1)
	mtlr	r0
	blr

#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */
#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
Commit	Line	Data
ad5bb451 WD	1	/*
	2	* Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <config.h>
	24
ad5bb451 WD	25	#if defined(CONFIG_MPC823) \|\| \
	26	defined(CONFIG_MPC850) \|\| \
	27	defined(CONFIG_MPC855) \|\| \
	28	defined(CONFIG_MPC860) \|\| \
	29	defined(CONFIG_MPC862)
	30
	31	#include <post.h>
	32	#include <ppc_asm.tmpl>
	33	#include <ppc_defs.h>
	34	#include <asm/cache.h>
	35
6d0f6bcf	36	#if CONFIG_POST & CONFIG_SYS_POST_CACHE
ad5bb451 WD	37
	38	.text
	39
	40	cache_post_dinvalidate:
	41	lis r10, IDC_INVALL@h
	42	mtspr DC_CST, r10
	43	blr
	44
	45	cache_post_iinvalidate:
	46	lis r10, IDC_INVALL@h
	47	mtspr IC_CST, r10
	48	isync
	49	blr
	50
	51	cache_post_ddisable:
	52	lis r10, IDC_DISABLE@h
	53	mtspr DC_CST, r10
	54	blr
	55
	56	cache_post_dwb:
	57	lis r10, IDC_ENABLE@h
	58	mtspr DC_CST, r10
	59	lis r10, DC_CFWT@h
	60	mtspr DC_CST, r10
	61	blr
	62
	63	cache_post_dwt:
	64	lis r10, IDC_ENABLE@h
	65	mtspr DC_CST, r10
	66	lis r10, DC_SFWT@h
	67	mtspr DC_CST, r10
	68	blr
	69
	70	cache_post_idisable:
	71	lis r10, IDC_DISABLE@h
	72	mtspr IC_CST, r10
	73	isync
	74	blr
	75
	76	cache_post_ienable:
	77	lis r10, IDC_ENABLE@h
	78	mtspr IC_CST, r10
	79	isync
	80	blr
	81
	82	cache_post_iunlock:
	83	lis r10, IDC_UNALL@h
	84	mtspr IC_CST, r10
	85	isync
	86	blr
	87
	88	cache_post_ilock:
	89	mtspr IC_ADR, r3
	90	lis r10, IDC_LDLCK@h
	91	mtspr IC_CST, r10
	92	isync
	93	blr
	94
	95	/*
	96	* turn on the data cache
	97	* switch the data cache to write-back or write-through mode
	98	* invalidate the data cache
	99	* write the negative pattern to a cached area
	100	* read the area
101	*
102	* The negative pattern must be read at the last step
103	*/
104	.global cache_post_test1
105	cache_post_test1:
106	mflr r0
107	stw r0, 4(r1)
108
109	stwu r3, -4(r1)
110	stwu r4, -4(r1)
111
112	bl cache_post_dwb
113	bl cache_post_dinvalidate
114
115	/* Write the negative pattern to the test area */
116	lwz r0, 0(r1)
117	mtctr r0
118	li r0, 0xff
119	lwz r3, 4(r1)
120	subi r3, r3, 1
121	1:
122	stbu r0, 1(r3)
123	bdnz 1b
124
125	/* Read the test area */
126	lwz r0, 0(r1)
127	mtctr r0
128	lwz r4, 4(r1)
129	subi r4, r4, 1
130	li r3, 0
131	1:
132	lbzu r0, 1(r4)
133	cmpli cr0, r0, 0xff
134	beq 2f
135	li r3, -1
136	b 3f
137	2:
138	bdnz 1b
139	3:
140
141	bl cache_post_ddisable
142	bl cache_post_dinvalidate
143
144	addi r1, r1, 8
145
146	lwz r0, 4(r1)
147	mtlr r0
148	blr
149
150	/*
151	* turn on the data cache
152	* switch the data cache to write-back or write-through mode
153	* invalidate the data cache
154	* write the zero pattern to a cached area
155	* turn off the data cache
156	* write the negative pattern to the area
157	* turn on the data cache
158	* read the area
159	*
160	* The negative pattern must be read at the last step
161	*/
162	.global cache_post_test2
163	cache_post_test2:
164	mflr r0
165	stw r0, 4(r1)
166
167	stwu r3, -4(r1)
168	stwu r4, -4(r1)
169
170	bl cache_post_dwb
171	bl cache_post_dinvalidate
172
173	/* Write the zero pattern to the test area */
174	lwz r0, 0(r1)
175	mtctr r0
176	li r0, 0
177	lwz r3, 4(r1)
178	subi r3, r3, 1
179	1:
180	stbu r0, 1(r3)
181	bdnz 1b
182
183	bl cache_post_ddisable
184
185	/* Write the negative pattern to the test area */
186	lwz r0, 0(r1)
187	mtctr r0
188	li r0, 0xff
189	lwz r3, 4(r1)
190	subi r3, r3, 1
191	1:
192	stbu r0, 1(r3)
193	bdnz 1b
194
195	bl cache_post_dwb
196
197	/* Read the test area */
198	lwz r0, 0(r1)
199	mtctr r0
200	lwz r4, 4(r1)
201	subi r4, r4, 1
202	li r3, 0
203	1:
204	lbzu r0, 1(r4)
205	cmpli cr0, r0, 0xff
206	beq 2f
207	li r3, -1
208	b 3f
209	2:
210	bdnz 1b
211	3:
212
213	bl cache_post_ddisable
214	bl cache_post_dinvalidate
215
216	addi r1, r1, 8
217
218	lwz r0, 4(r1)
219	mtlr r0
220	blr
221
222	/*
223	* turn on the data cache
224	* switch the data cache to write-through mode
225	* invalidate the data cache
226	* write the zero pattern to a cached area
227	* flush the data cache
228	* write the negative pattern to the area
229	* turn off the data cache
230	* read the area
231	*
232	* The negative pattern must be read at the last step
233	*/
234	.global cache_post_test3
235	cache_post_test3:
236	mflr r0
237	stw r0, 4(r1)
238
239	stwu r3, -4(r1)
240	stwu r4, -4(r1)
241
242	bl cache_post_ddisable
243	bl cache_post_dinvalidate
244
245	/* Write the zero pattern to the test area */
246	lwz r0, 0(r1)
247	mtctr r0
248	li r0, 0
249	lwz r3, 4(r1)
250	subi r3, r3, 1
251	1:
252	stbu r0, 1(r3)
253	bdnz 1b
254
255	bl cache_post_dwt
256	bl cache_post_dinvalidate
257
258	/* Write the negative pattern to the test area */
259	lwz r0, 0(r1)
260	mtctr r0
261	li r0, 0xff
262	lwz r3, 4(r1)
263	subi r3, r3, 1
264	1:
265	stbu r0, 1(r3)
266	bdnz 1b
267
268	bl cache_post_ddisable
269	bl cache_post_dinvalidate
270
271	/* Read the test area */
272	lwz r0, 0(r1)
273	mtctr r0
274	lwz r4, 4(r1)
275	subi r4, r4, 1
276	li r3, 0
277	1:
278	lbzu r0, 1(r4)
279	cmpli cr0, r0, 0xff
280	beq 2f
281	li r3, -1
282	b 3f
283	2:
284	bdnz 1b
285	3:
286
287	addi r1, r1, 8
288
289	lwz r0, 4(r1)
290	mtlr r0
291	blr
292
293	/*
294	* turn on the data cache
295	* switch the data cache to write-back mode
296	* invalidate the data cache
297	* write the negative pattern to a cached area
298	* flush the data cache
299	* write the zero pattern to the area
300	* invalidate the data cache
301	* read the area
302	*
303	* The negative pattern must be read at the last step
304	*/
305	.global cache_post_test4
306	cache_post_test4:
307	mflr r0
308	stw r0, 4(r1)
309
310	stwu r3, -4(r1)
311	stwu r4, -4(r1)
312
313	bl cache_post_ddisable
314	bl cache_post_dinvalidate
315
316	/* Write the negative pattern to the test area */
317	lwz r0, 0(r1)
318	mtctr r0
319	li r0, 0xff
320	lwz r3, 4(r1)
321	subi r3, r3, 1
322	1:
323	stbu r0, 1(r3)
324	bdnz 1b
325
326	bl cache_post_dwb
327	bl cache_post_dinvalidate
328
329	/* Write the zero pattern to the test area */
330	lwz r0, 0(r1)
331	mtctr r0
332	li r0, 0
333	lwz r3, 4(r1)
334	subi r3, r3, 1
335	1:
336	stbu r0, 1(r3)
337	bdnz 1b
338
339	bl cache_post_ddisable
340	bl cache_post_dinvalidate
341
342	/* Read the test area */
343	lwz r0, 0(r1)
344	mtctr r0
345	lwz r4, 4(r1)
346	subi r4, r4, 1
347	li r3, 0
348	1:
349	lbzu r0, 1(r4)
350	cmpli cr0, r0, 0xff
351	beq 2f
352	li r3, -1
353	b 3f
354	2:
355	bdnz 1b
356	3:
357
358	addi r1, r1, 8
359
360	lwz r0, 4(r1)
361	mtlr r0
362	blr
363
364	cache_post_test5_1:
365	li r3, 0
366	cache_post_test5_2:
367	li r3, -1
368
369	/*
370	* turn on the instruction cache
371	* unlock the entire instruction cache
372	* invalidate the instruction cache
373	* lock a branch instruction in the instruction cache
374	* replace the branch instruction with "nop"
375	* jump to the branch instruction
376	* check that the branch instruction was executed
377	*/
378	.global cache_post_test5
379	cache_post_test5:
380	mflr r0
381	stw r0, 4(r1)
382
383	bl cache_post_ienable
384	bl cache_post_iunlock
385	bl cache_post_iinvalidate
386
387	/* Compute r9 = cache_post_test5_reloc */
388	bl cache_post_test5_reloc
389	cache_post_test5_reloc:
390	mflr r9
391
392	/* Copy the test instruction to cache_post_test5_data */
393	lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h
394	ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l
395	add r3, r3, r9
396	lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h
397	ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
398	add r4, r4, r9
399	lwz r0, 0(r3)
400	stw r0, 0(r4)
401
402	bl cache_post_iinvalidate
403
404	/* Lock the branch instruction */
405	lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h
406	ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l
407	add r3, r3, r9
408	bl cache_post_ilock
409
410	/* Replace the test instruction */
411	lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h
412	ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l
413	add r3, r3, r9
414	lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h
415	ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
416	add r4, r4, r9
417	lwz r0, 0(r3)
418	stw r0, 0(r4)
419
420	bl cache_post_iinvalidate
421
422	/* Execute to the test instruction */
423	cache_post_test5_data:
424	nop
425
426	bl cache_post_iunlock
427
428	lwz r0, 4(r1)
429	mtlr r0
430	blr
431
432	cache_post_test6_1:
433	li r3, -1
434	cache_post_test6_2:
435	li r3, 0
436
437	/*
438	* turn on the instruction cache
439	* unlock the entire instruction cache
440	* invalidate the instruction cache
441	* lock a branch instruction in the instruction cache
442	* replace the branch instruction with "nop"
443	* jump to the branch instruction
444	* check that the branch instruction was executed
445	*/
446	.global cache_post_test6
447	cache_post_test6:
448	mflr r0
449	stw r0, 4(r1)
450
451	bl cache_post_ienable
452	bl cache_post_iunlock
453	bl cache_post_iinvalidate
454
455	/* Compute r9 = cache_post_test6_reloc */
456	bl cache_post_test6_reloc
457	cache_post_test6_reloc:
458	mflr r9
459
460	/* Copy the test instruction to cache_post_test6_data */
461	lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h
462	ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l
463	add r3, r3, r9
464	lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h
465	ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
466	add r4, r4, r9
467	lwz r0, 0(r3)
468	stw r0, 0(r4)
469
470	bl cache_post_iinvalidate
471
472	/* Replace the test instruction */
473	lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h
474	ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l
475	add r3, r3, r9
476	lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h
477	ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
478	add r4, r4, r9
479	lwz r0, 0(r3)
480	stw r0, 0(r4)
481
482	bl cache_post_iinvalidate
483
484	/* Execute to the test instruction */
485	cache_post_test6_data:
486	nop
487
488	lwz r0, 4(r1)
489	mtlr r0
490	blr
491
492	#endif /* CONFIG_MPC823 \|\| MPC850 \|\| MPC855 \|\| MPC860 */
6d0f6bcf	493	#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */