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[people/ms/u-boot.git] / post / cpu / mpc8xx / ether.c
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ad5bb451
WD		 1/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
ad5bb451
WD		 6 */
7
8#include <common.h>
9
10/*
11 * Ethernet test
12 *
13 * The Serial Communication Controllers (SCC) listed in ctlr_list array below
14 * are tested in the loopback ethernet mode.
15 * The controllers are configured accordingly and several packets
16 * are transmitted. The configurable test parameters are:
17 * MIN_PACKET_LENGTH - minimum size of packet to transmit
18 * MAX_PACKET_LENGTH - maximum size of packet to transmit
19 * TEST_NUM - number of tests
20 */
21
ad5bb451 22#include <post.h>
6d0f6bcf 23#if CONFIG_POST & CONFIG_SYS_POST_ETHER
ad5bb451
WD		 24#if defined(CONFIG_8xx)
25#include <commproc.h>
26#elif defined(CONFIG_MPC8260)
27#include <asm/cpm_8260.h>
28#else
29#error "Apparently a bad configuration, please fix."
30#endif
31
32#include <command.h>
33#include <net.h>
34#include <serial.h>
35
36DECLARE_GLOBAL_DATA_PTR;
37
38#define MIN_PACKET_LENGTH 64
39#define MAX_PACKET_LENGTH 256
40#define TEST_NUM 1
41
42#define CTLR_SCC 0
43
44extern void spi_init_f (void);
45extern void spi_init_r (void);
46
47/* The list of controllers to test */
48#if defined(CONFIG_MPC823)
49static int ctlr_list[][2] = { {CTLR_SCC, 1} };
50#else
51static int ctlr_list[][2] = { };
52#endif
53
ad5bb451
WD		 54static struct {
55 void (*init) (int index);
56 void (*halt) (int index);
57 int (*send) (int index, volatile void *packet, int length);
58 int (*recv) (int index, void *packet, int length);
59} ctlr_proc[1];
60
61static char *ctlr_name[1] = { "SCC" };
62
63/* Ethernet Transmit and Receive Buffers */
64#define DBUF_LENGTH 1520
65
66#define TX_BUF_CNT 2
67
68#define TOUT_LOOP 100
69
70static char txbuf[DBUF_LENGTH];
71
72static uint rxIdx; /* index of the current RX buffer */
73static uint txIdx; /* index of the current TX buffer */
74
75/*
76 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
77 * immr->udata_bd address on Dual-Port RAM
78 * Provide for Double Buffering
79 */
80
81typedef volatile struct CommonBufferDescriptor {
82 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
83 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
84} RTXBD;
85
86static RTXBD *rtx;
87
88 /*
89 * SCC callbacks
90 */
91
92static void scc_init (int scc_index)
93{
6bacfa6a 94 uchar ea[6];
ad5bb451 95
97b05d7d
WD		 96 static int proff[] = {
97 PROFF_SCC1,
98 PROFF_SCC2,
99 PROFF_SCC3,
100 PROFF_SCC4,
101 };
102 static unsigned int cpm_cr[] = {
103 CPM_CR_CH_SCC1,
104 CPM_CR_CH_SCC2,
105 CPM_CR_CH_SCC3,
106 CPM_CR_CH_SCC4,
107 };
ad5bb451
WD		 108
109 int i;
110 scc_enet_t *pram_ptr;
111
6d0f6bcf 112 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ad5bb451
WD		 113
114 immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
115 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
116
117#if defined(CONFIG_FADS)
118#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
119 /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
120 *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
121 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
122 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
123#else
124 *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
125 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
126 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
127#endif
128#endif
129
130 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
131
132 rxIdx = 0;
133 txIdx = 0;
134
6d0f6bcf 135#ifdef CONFIG_SYS_ALLOC_DPRAM
ad5bb451
WD		 136 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
137 dpram_alloc_align (sizeof (RTXBD), 8));
138#else
139 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
140#endif
141
142#if 0
143
144#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
145 /* Configure port A pins for Txd and Rxd.
146 */
147 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
148 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
149 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
150#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
151 /* Configure port B pins for Txd and Rxd.
152 */
153 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
154 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
155 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
156#else
157#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
158#endif
159
160#if defined(PC_ENET_LBK)
161 /* Configure port C pins to disable External Loopback
162 */
163 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
164 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
165 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
166 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
167#endif /* PC_ENET_LBK */
168
169 /* Configure port C pins to enable CLSN and RENA.
170 */
171 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
172 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
173 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
174
175 /* Configure port A for TCLK and RCLK.
176 */
177 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
178 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
179
180 /*
181 * Configure Serial Interface clock routing -- see section 16.7.5.3
182 * First, clear all SCC bits to zero, then set the ones we want.
183 */
184
185 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
186 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
187#else
188 /*
189 * SCC2 receive clock is BRG2
190 * SCC2 transmit clock is BRG3
191 */
192 immr->im_cpm.cp_brgc2 = 0x0001000C;
193 immr->im_cpm.cp_brgc3 = 0x0001000C;
194
195 immr->im_cpm.cp_sicr &= ~0x00003F00;
196 immr->im_cpm.cp_sicr |= 0x00000a00;
197#endif /* 0 */
198
199
200 /*
201 * Initialize SDCR -- see section 16.9.23.7
202 * SDMA configuration register
203 */
204 immr->im_siu_conf.sc_sdcr = 0x01;
205
206
207 /*
208 * Setup SCC Ethernet Parameter RAM
209 */
210
211 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
212 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
213
214 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
215
216 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
217 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
218
219 /*
220 * Setup Receiver Buffer Descriptors (13.14.24.18)
221 * Settings:
222 * Empty, Wrap
223 */
224
225 for (i = 0; i < PKTBUFSRX; i++) {
226 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
227 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
228 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
229 }
230
231 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
232
233 /*
234 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
235 * Settings:
236 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
237 */
238
239 for (i = 0; i < TX_BUF_CNT; i++) {
240 rtx->txbd[i].cbd_sc =
241 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
242 rtx->txbd[i].cbd_datlen = 0; /* Reset */
243 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
244 }
245
246 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
247
248 /*
249 * Enter Command: Initialize Rx Params for SCC
250 */
251
252 do { /* Spin until ready to issue command */
253 __asm__ ("eieio");
254 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
255 /* Issue command */
256 immr->im_cpm.cp_cpcr =
257 ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
258 CPM_CR_FLG);
259 do { /* Spin until command processed */
260 __asm__ ("eieio");
261 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
262
263 /*
264 * Ethernet Specific Parameter RAM
265 * see table 13-16, pg. 660,
266 * pg. 681 (example with suggested settings)
267 */
268
269 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
270 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
271 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
272 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
273 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
274 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
275
276 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
277 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
278 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
279
280 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
281 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
282
283 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
284 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
285 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
286 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
287
6bacfa6a 288 eth_getenv_enetaddr("ethaddr", ea);
ad5bb451
WD		 289 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
290 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
291 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
ad5bb451
WD		 292
293 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
294 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
295 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
296 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
297 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
298 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
299 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
300 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
301
302 /*
303 * Enter Command: Initialize Tx Params for SCC
304 */
305
306 do { /* Spin until ready to issue command */
307 __asm__ ("eieio");
308 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
309 /* Issue command */
310 immr->im_cpm.cp_cpcr =
311 ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
312 CPM_CR_FLG);
313 do { /* Spin until command processed */
314 __asm__ ("eieio");
315 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
316
317 /*
318 * Mask all Events in SCCM - we use polling mode
319 */
320 immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
321
322 /*
323 * Clear Events in SCCE -- Clear bits by writing 1's
324 */
325
326 immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
327
328
329 /*
330 * Initialize GSMR High 32-Bits
331 * Settings: Normal Mode
332 */
333
334 immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
335
336 /*
337 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
338 * Settings:
339 * TCI = Invert
340 * TPL = 48 bits
341 * TPP = Repeating 10's
342 * LOOP = Loopback
343 * MODE = Ethernet
344 */
345
346 immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
347 SCC_GSMRL_TPL_48 |
348 SCC_GSMRL_TPP_10 |
349 SCC_GSMRL_DIAG_LOOP |
350 SCC_GSMRL_MODE_ENET);
351
352 /*
353 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
354 */
355
356 immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
357
358 /*
359 * Initialize the PSMR
360 * Settings:
361 * CRC = 32-Bit CCITT
362 * NIB = Begin searching for SFD 22 bits after RENA
363 * LPB = Loopback Enable (Needed when FDE is set)
364 */
365 immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
366 SCC_PSMR_NIB22 | SCC_PSMR_LPB;
367
ad5bb451
WD		 368 /*
369 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
370 */
371
372 immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
373 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
374
375 /*
376 * Work around transmit problem with first eth packet
377 */
378#if defined (CONFIG_FADS)
379 udelay (10000); /* wait 10 ms */
ad5bb451
WD		 380#endif
381}
382
383static void scc_halt (int scc_index)
384{
6d0f6bcf 385 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ad5bb451
WD		 386
387 immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
388 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
389 immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
390}
391
392static int scc_send (int index, volatile void *packet, int length)
393{
394 int i, j = 0;
395
396 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
397 udelay (1); /* will also trigger Wd if needed */
398 j++;
399 }
400 if (j >= TOUT_LOOP)
401 printf ("TX not ready\n");
402 rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
403 rtx->txbd[txIdx].cbd_datlen = length;
404 rtx->txbd[txIdx].cbd_sc |=
405 (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
406 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
407 udelay (1); /* will also trigger Wd if needed */
408 j++;
409 }
410 if (j >= TOUT_LOOP)
411 printf ("TX timeout\n");
412 i = (rtx->txbd[txIdx].
413 cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
414 return i;
415}
416
417static int scc_recv (int index, void *packet, int max_length)
418{
419 int length = -1;
420
421 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
422 goto Done; /* nothing received */
423 }
424
425 if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
426 length = rtx->rxbd[rxIdx].cbd_datlen - 4;
427 memcpy (packet,
428 (void *) (NetRxPackets[rxIdx]),
429 length < max_length ? length : max_length);
430 }
431
432 /* Give the buffer back to the SCC. */
433 rtx->rxbd[rxIdx].cbd_datlen = 0;
434
435 /* wrap around buffer index when necessary */
436 if ((rxIdx + 1) >= PKTBUFSRX) {
437 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
438 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
439 rxIdx = 0;
440 } else {
441 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
442 rxIdx++;
443 }
444
445Done:
446 return length;
447}
448
449 /*
450 * Test routines
451 */
452
453static void packet_fill (char *packet, int length)
454{
455 char c = (char) length;
456 int i;
457
458 packet[0] = 0xFF;
459 packet[1] = 0xFF;
460 packet[2] = 0xFF;
461 packet[3] = 0xFF;
462 packet[4] = 0xFF;
463 packet[5] = 0xFF;
464
465 for (i = 6; i < length; i++) {
466 packet[i] = c++;
467 }
468}
469
470static int packet_check (char *packet, int length)
471{
472 char c = (char) length;
473 int i;
474
475 for (i = 6; i < length; i++) {
476 if (packet[i] != c++)
477 return -1;
478 }
479
480 return 0;
481}
482
483static int test_ctlr (int ctlr, int index)
484{
485 int res = -1;
486 char packet_send[MAX_PACKET_LENGTH];
487 char packet_recv[MAX_PACKET_LENGTH];
488 int length;
489 int i;
490 int l;
491
492 ctlr_proc[ctlr].init (index);
493
494 for (i = 0; i < TEST_NUM; i++) {
495 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
496 packet_fill (packet_send, l);
497
498 ctlr_proc[ctlr].send (index, packet_send, l);
499
500 length = ctlr_proc[ctlr].recv (index, packet_recv,
501 MAX_PACKET_LENGTH);
502
503 if (length != l || packet_check (packet_recv, length) < 0) {
504 goto Done;
505 }
506 }
507 }
508
509 res = 0;
510
511Done:
512
513 ctlr_proc[ctlr].halt (index);
514
515 /*
516 * SCC2 Ethernet parameter RAM space overlaps
517 * the SPI parameter RAM space. So we need to restore
518 * the SPI configuration after SCC2 ethernet test.
519 */
520#if defined(CONFIG_SPI)
521 if (ctlr == CTLR_SCC && index == 1) {
522 spi_init_f ();
523 spi_init_r ();
524 }
525#endif
526
527 if (res != 0) {
528 post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
529 index + 1);
530 }
531
532 return res;
533}
534
535int ether_post_test (int flags)
536{
537 int res = 0;
538 int i;
539
540 ctlr_proc[CTLR_SCC].init = scc_init;
541 ctlr_proc[CTLR_SCC].halt = scc_halt;
542 ctlr_proc[CTLR_SCC].send = scc_send;
543 ctlr_proc[CTLR_SCC].recv = scc_recv;
544
d2397817 545 for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
ad5bb451
WD		 546 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
547 res = -1;
548 }
549 }
550
551#if !defined(CONFIG_8xx_CONS_NONE)
552 serial_reinit_all ();
553#endif
554 return res;
555}
556
6d0f6bcf 557#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
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