[people/ms/u-boot.git] / post / cpu / mpc8xx / ether.c

/*
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

/*
 * Ethernet test
 *
 * The Serial Communication Controllers (SCC) listed in ctlr_list array below
 * are tested in the loopback ethernet mode.
 * The controllers are configured accordingly and several packets
 * are transmitted. The configurable test parameters are:
 *   MIN_PACKET_LENGTH - minimum size of packet to transmit
 *   MAX_PACKET_LENGTH - maximum size of packet to transmit
 *   TEST_NUM - number of tests
 */

#include <post.h>
#if CONFIG_POST & CONFIG_SYS_POST_ETHER
#if defined(CONFIG_8xx)
#include <commproc.h>
#elif defined(CONFIG_MPC8260)
#include <asm/cpm_8260.h>
#else
#error "Apparently a bad configuration, please fix."
#endif

#include <command.h>
#include <net.h>
#include <serial.h>

DECLARE_GLOBAL_DATA_PTR;

#define MIN_PACKET_LENGTH	64
#define MAX_PACKET_LENGTH	256
#define TEST_NUM		1

#define CTLR_SCC 0

extern void spi_init_f (void);
extern void spi_init_r (void);

/* The list of controllers to test */
#if defined(CONFIG_MPC823)
static int ctlr_list[][2] = { {CTLR_SCC, 1} };
#else
static int ctlr_list[][2] = { };
#endif

static struct {
	void (*init) (int index);
	void (*halt) (int index);
	int (*send) (int index, volatile void *packet, int length);
	int (*recv) (int index, void *packet, int length);
} ctlr_proc[1];

static char *ctlr_name[1] = { "SCC" };

/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH  1520

#define TX_BUF_CNT 2

#define TOUT_LOOP 100

static char txbuf[DBUF_LENGTH];

static uint rxIdx;		/* index of the current RX buffer */
static uint txIdx;		/* index of the current TX buffer */

/*
  * SCC Ethernet Tx and Rx buffer descriptors allocated at the
  *  immr->udata_bd address on Dual-Port RAM
  * Provide for Double Buffering
  */

typedef volatile struct CommonBufferDescriptor {
	cbd_t rxbd[PKTBUFSRX];		/* Rx BD */
	cbd_t txbd[TX_BUF_CNT];		/* Tx BD */
} RTXBD;

static RTXBD *rtx;

  /*
   * SCC callbacks
   */

static void scc_init (int scc_index)
{
	uchar ea[6];

	static int proff[] = {
				PROFF_SCC1,
				PROFF_SCC2,
				PROFF_SCC3,
				PROFF_SCC4,
	};
	static unsigned int cpm_cr[] = {
				CPM_CR_CH_SCC1,
				CPM_CR_CH_SCC2,
				CPM_CR_CH_SCC3,
				CPM_CR_CH_SCC4,
	};

	int i;
	scc_enet_t *pram_ptr;

	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
			~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

#if defined(CONFIG_FADS)
#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
	/* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
	*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
	*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#else
	*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
	*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif
#endif

	pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);

	rxIdx = 0;
	txIdx = 0;

#ifdef CONFIG_SYS_ALLOC_DPRAM
	rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
					 dpram_alloc_align (sizeof (RTXBD), 8));
#else
	rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#endif

#if 0

#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
	/* Configure port A pins for Txd and Rxd.
	 */
	immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
	immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
	immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
	/* Configure port B pins for Txd and Rxd.
	 */
	immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
	immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
	immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
#else
#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
#endif

#if defined(PC_ENET_LBK)
	/* Configure port C pins to disable External Loopback
	 */
	immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
	immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
	immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
	immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK;	/* Disable Loopback */
#endif /* PC_ENET_LBK */

	/* Configure port C pins to enable CLSN and RENA.
	 */
	immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
	immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
	immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);

	/* Configure port A for TCLK and RCLK.
	 */
	immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
	immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);

	/*
	 * Configure Serial Interface clock routing -- see section 16.7.5.3
	 * First, clear all SCC bits to zero, then set the ones we want.
	 */

	immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
	immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
#else
	/*
	 * SCC2 receive clock is BRG2
	 * SCC2 transmit clock is BRG3
	 */
	immr->im_cpm.cp_brgc2 = 0x0001000C;
	immr->im_cpm.cp_brgc3 = 0x0001000C;

	immr->im_cpm.cp_sicr &= ~0x00003F00;
	immr->im_cpm.cp_sicr |=  0x00000a00;
#endif /* 0 */


	/*
	 * Initialize SDCR -- see section 16.9.23.7
	 * SDMA configuration register
	 */
	immr->im_siu_conf.sc_sdcr = 0x01;


	/*
	 * Setup SCC Ethernet Parameter RAM
	 */

	pram_ptr->sen_genscc.scc_rfcr = 0x18;	/* Normal Operation and Mot byte ordering */
	pram_ptr->sen_genscc.scc_tfcr = 0x18;	/* Mot byte ordering, Normal access */

	pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH;	/* max. ET package len 1520 */

	pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]);	/* Set RXBD tbl start at Dual Port */
	pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]);	/* Set TXBD tbl start at Dual Port */

	/*
	 * Setup Receiver Buffer Descriptors (13.14.24.18)
	 * Settings:
	 *     Empty, Wrap
	 */

	for (i = 0; i < PKTBUFSRX; i++) {
		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
	}

	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

	/*
	 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	 * Settings:
	 *    Add PADs to Short FRAMES, Wrap, Last, Tx CRC
	 */

	for (i = 0; i < TX_BUF_CNT; i++) {
		rtx->txbd[i].cbd_sc =
				(BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
		rtx->txbd[i].cbd_datlen = 0;	/* Reset */
		rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
	}

	rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;

	/*
	 * Enter Command:  Initialize Rx Params for SCC
	 */

	do {				/* Spin until ready to issue command    */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	/* Issue command */
	immr->im_cpm.cp_cpcr =
			((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
			 CPM_CR_FLG);
	do {				/* Spin until command processed     */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

	/*
	 * Ethernet Specific Parameter RAM
	 *     see table 13-16, pg. 660,
	 *     pg. 681 (example with suggested settings)
	 */

	pram_ptr->sen_cpres = ~(0x0);	/* Preset CRC */
	pram_ptr->sen_cmask = 0xdebb20e3;	/* Constant Mask for CRC */
	pram_ptr->sen_crcec = 0x0;	/* Error Counter CRC (unused) */
	pram_ptr->sen_alec = 0x0;	/* Alignment Error Counter (unused) */
	pram_ptr->sen_disfc = 0x0;	/* Discard Frame Counter (unused) */
	pram_ptr->sen_pads = 0x8888;	/* Short Frame PAD Characters */

	pram_ptr->sen_retlim = 15;	/* Retry Limit Threshold */
	pram_ptr->sen_maxflr = 1518;	/* MAX Frame Length Register */
	pram_ptr->sen_minflr = 64;	/* MIN Frame Length Register */

	pram_ptr->sen_maxd1 = DBUF_LENGTH;	/* MAX DMA1 Length Register */
	pram_ptr->sen_maxd2 = DBUF_LENGTH;	/* MAX DMA2 Length Register */

	pram_ptr->sen_gaddr1 = 0x0;	/* Group Address Filter 1 (unused) */
	pram_ptr->sen_gaddr2 = 0x0;	/* Group Address Filter 2 (unused) */
	pram_ptr->sen_gaddr3 = 0x0;	/* Group Address Filter 3 (unused) */
	pram_ptr->sen_gaddr4 = 0x0;	/* Group Address Filter 4 (unused) */

	eth_getenv_enetaddr("ethaddr", ea);
	pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
	pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
	pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];

	pram_ptr->sen_pper = 0x0;	/* Persistence (unused) */
	pram_ptr->sen_iaddr1 = 0x0;	/* Individual Address Filter 1 (unused) */
	pram_ptr->sen_iaddr2 = 0x0;	/* Individual Address Filter 2 (unused) */
	pram_ptr->sen_iaddr3 = 0x0;	/* Individual Address Filter 3 (unused) */
	pram_ptr->sen_iaddr4 = 0x0;	/* Individual Address Filter 4 (unused) */
	pram_ptr->sen_taddrh = 0x0;	/* Tmp Address (MSB) (unused) */
	pram_ptr->sen_taddrm = 0x0;	/* Tmp Address (unused) */
	pram_ptr->sen_taddrl = 0x0;	/* Tmp Address (LSB) (unused) */

	/*
	 * Enter Command:  Initialize Tx Params for SCC
	 */

	do {				/* Spin until ready to issue command    */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	/* Issue command */
	immr->im_cpm.cp_cpcr =
			((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
			 CPM_CR_FLG);
	do {				/* Spin until command processed     */
		__asm__ ("eieio");
	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

	/*
	 * Mask all Events in SCCM - we use polling mode
	 */
	immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;

	/*
	 * Clear Events in SCCE -- Clear bits by writing 1's
	 */

	immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);


	/*
	 * Initialize GSMR High 32-Bits
	 * Settings:  Normal Mode
	 */

	immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;

	/*
	 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
	 * Settings:
	 *     TCI = Invert
	 *     TPL =  48 bits
	 *     TPP = Repeating 10's
	 *     LOOP = Loopback
	 *     MODE = Ethernet
	 */

	immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
						    SCC_GSMRL_TPL_48 |
						    SCC_GSMRL_TPP_10 |
						    SCC_GSMRL_DIAG_LOOP |
						    SCC_GSMRL_MODE_ENET);

	/*
	 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
	 */

	immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;

	/*
	 * Initialize the PSMR
	 * Settings:
	 *  CRC = 32-Bit CCITT
	 *  NIB = Begin searching for SFD 22 bits after RENA
	 *  LPB = Loopback Enable (Needed when FDE is set)
	 */
	immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
			SCC_PSMR_NIB22 | SCC_PSMR_LPB;

#ifdef CONFIG_RPXCLASSIC
	*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
	*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
#endif

#ifdef CONFIG_RPXLITE
	*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif

#ifdef CONFIG_MBX
	board_ether_init ();
#endif

	/*
	 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
	 */

	immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
			(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	/*
	 * Work around transmit problem with first eth packet
	 */
#if defined (CONFIG_FADS)
	udelay (10000);				/* wait 10 ms */
#elif defined(CONFIG_RPXCLASSIC)
	udelay (100000);			/* wait 100 ms */
#endif
}

static void scc_halt (int scc_index)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
			~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
	immr->im_ioport.iop_pcso  &=  ~(PC_ENET_CLSN | PC_ENET_RENA);
}

static int scc_send (int index, volatile void *packet, int length)
{
	int i, j = 0;

	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
		udelay (1);		/* will also trigger Wd if needed */
		j++;
	}
	if (j >= TOUT_LOOP)
		printf ("TX not ready\n");
	rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
	rtx->txbd[txIdx].cbd_datlen = length;
	rtx->txbd[txIdx].cbd_sc |=
			(BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
		udelay (1);		/* will also trigger Wd if needed */
		j++;
	}
	if (j >= TOUT_LOOP)
		printf ("TX timeout\n");
	i = (rtx->txbd[txIdx].
		 cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
	return i;
}

static int scc_recv (int index, void *packet, int max_length)
{
	int length = -1;

	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
		goto Done;		/* nothing received */
	}

	if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
		length = rtx->rxbd[rxIdx].cbd_datlen - 4;
		memcpy (packet,
				(void *) (NetRxPackets[rxIdx]),
				length < max_length ? length : max_length);
	}

	/* Give the buffer back to the SCC. */
	rtx->rxbd[rxIdx].cbd_datlen = 0;

	/* wrap around buffer index when necessary */
	if ((rxIdx + 1) >= PKTBUFSRX) {
		rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
				(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
		rxIdx = 0;
	} else {
		rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
		rxIdx++;
	}

Done:
	return length;
}

  /*
   * Test routines
   */

static void packet_fill (char *packet, int length)
{
	char c = (char) length;
	int i;

	packet[0] = 0xFF;
	packet[1] = 0xFF;
	packet[2] = 0xFF;
	packet[3] = 0xFF;
	packet[4] = 0xFF;
	packet[5] = 0xFF;

	for (i = 6; i < length; i++) {
		packet[i] = c++;
	}
}

static int packet_check (char *packet, int length)
{
	char c = (char) length;
	int i;

	for (i = 6; i < length; i++) {
		if (packet[i] != c++)
			return -1;
	}

	return 0;
}

static int test_ctlr (int ctlr, int index)
{
	int res = -1;
	char packet_send[MAX_PACKET_LENGTH];
	char packet_recv[MAX_PACKET_LENGTH];
	int length;
	int i;
	int l;

	ctlr_proc[ctlr].init (index);

	for (i = 0; i < TEST_NUM; i++) {
		for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
			packet_fill (packet_send, l);

			ctlr_proc[ctlr].send (index, packet_send, l);

			length = ctlr_proc[ctlr].recv (index, packet_recv,
							MAX_PACKET_LENGTH);

			if (length != l || packet_check (packet_recv, length) < 0) {
				goto Done;
			}
		}
	}

	res = 0;

Done:

	ctlr_proc[ctlr].halt (index);

	/*
	 * SCC2 Ethernet parameter RAM space overlaps
	 * the SPI parameter RAM space. So we need to restore
	 * the SPI configuration after SCC2 ethernet test.
	 */
#if defined(CONFIG_SPI)
	if (ctlr == CTLR_SCC && index == 1) {
		spi_init_f ();
		spi_init_r ();
	}
#endif

	if (res != 0) {
		post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
				  index + 1);
	}

	return res;
}

int ether_post_test (int flags)
{
	int res = 0;
	int i;

	ctlr_proc[CTLR_SCC].init = scc_init;
	ctlr_proc[CTLR_SCC].halt = scc_halt;
	ctlr_proc[CTLR_SCC].send = scc_send;
	ctlr_proc[CTLR_SCC].recv = scc_recv;

	for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
		if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
			res = -1;
		}
	}

#if !defined(CONFIG_8xx_CONS_NONE)
	serial_reinit_all ();
#endif
	return res;
}

#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
Commit	Line	Data
ad5bb451 WD	1	/*
	2	* (C) Copyright 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25
	26	/*
	27	* Ethernet test
	28	*
	29	* The Serial Communication Controllers (SCC) listed in ctlr_list array below
	30	* are tested in the loopback ethernet mode.
	31	* The controllers are configured accordingly and several packets
	32	* are transmitted. The configurable test parameters are:
	33	* MIN_PACKET_LENGTH - minimum size of packet to transmit
	34	* MAX_PACKET_LENGTH - maximum size of packet to transmit
	35	* TEST_NUM - number of tests
	36	*/
	37
ad5bb451	38	#include <post.h>
6d0f6bcf	39	#if CONFIG_POST & CONFIG_SYS_POST_ETHER
ad5bb451 WD	40	#if defined(CONFIG_8xx)
	41	#include <commproc.h>
	42	#elif defined(CONFIG_MPC8260)
	43	#include <asm/cpm_8260.h>
	44	#else
	45	#error "Apparently a bad configuration, please fix."
	46	#endif
	47
	48	#include <command.h>
	49	#include <net.h>
	50	#include <serial.h>
	51
	52	DECLARE_GLOBAL_DATA_PTR;
	53
	54	#define MIN_PACKET_LENGTH 64
	55	#define MAX_PACKET_LENGTH 256
	56	#define TEST_NUM 1
	57
	58	#define CTLR_SCC 0
	59
	60	extern void spi_init_f (void);
	61	extern void spi_init_r (void);
	62
	63	/* The list of controllers to test */
	64	#if defined(CONFIG_MPC823)
	65	static int ctlr_list[][2] = { {CTLR_SCC, 1} };
	66	#else
	67	static int ctlr_list[][2] = { };
	68	#endif
	69
ad5bb451 WD	70	static struct {
	71	void (*init) (int index);
	72	void (*halt) (int index);
	73	int (send) (int index, volatile void packet, int length);
	74	int (recv) (int index, void packet, int length);
	75	} ctlr_proc[1];
	76
	77	static char *ctlr_name[1] = { "SCC" };
	78
	79	/* Ethernet Transmit and Receive Buffers */
	80	#define DBUF_LENGTH 1520
	81
	82	#define TX_BUF_CNT 2
	83
	84	#define TOUT_LOOP 100
	85
	86	static char txbuf[DBUF_LENGTH];
	87
	88	static uint rxIdx; /* index of the current RX buffer */
	89	static uint txIdx; /* index of the current TX buffer */
	90
	91	/*
	92	* SCC Ethernet Tx and Rx buffer descriptors allocated at the
	93	* immr->udata_bd address on Dual-Port RAM
	94	* Provide for Double Buffering
	95	*/
	96
	97	typedef volatile struct CommonBufferDescriptor {
	98	cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
	99	cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
	100	} RTXBD;
	101
	102	static RTXBD *rtx;
	103
	104	/*
	105	* SCC callbacks
	106	*/
	107
	108	static void scc_init (int scc_index)
	109	{
6bacfa6a	110	uchar ea[6];
ad5bb451	111
97b05d7d WD	112	static int proff[] = {
	113	PROFF_SCC1,
	114	PROFF_SCC2,
	115	PROFF_SCC3,
	116	PROFF_SCC4,
	117	};
	118	static unsigned int cpm_cr[] = {
	119	CPM_CR_CH_SCC1,
	120	CPM_CR_CH_SCC2,
	121	CPM_CR_CH_SCC3,
	122	CPM_CR_CH_SCC4,
	123	};
ad5bb451 WD	124
	125	int i;
	126	scc_enet_t *pram_ptr;
	127
6d0f6bcf	128	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	129
	130	immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
	131	~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	132
	133	#if defined(CONFIG_FADS)
	134	#if defined(CONFIG_MPC860T) \|\| defined(CONFIG_MPC86xADS)
	135	/* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
	136	((uint ) BCSR4) &= ~BCSR4_ETHLOOP;
	137	((uint ) BCSR4) \|= BCSR4_TFPLDL \| BCSR4_TPSQEL;
	138	((uint ) BCSR1) &= ~BCSR1_ETHEN;
	139	#else
	140	((uint ) BCSR4) &= ~(BCSR4_ETHLOOP \| BCSR4_MODEM_EN);
	141	((uint ) BCSR4) \|= BCSR4_TFPLDL \| BCSR4_TPSQEL \| BCSR4_DATA_VOICE;
	142	((uint ) BCSR1) &= ~BCSR1_ETHEN;
	143	#endif
	144	#endif
	145
	146	pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
	147
	148	rxIdx = 0;
	149	txIdx = 0;
	150
6d0f6bcf	151	#ifdef CONFIG_SYS_ALLOC_DPRAM
ad5bb451 WD	152	rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
	153	dpram_alloc_align (sizeof (RTXBD), 8));
	154	#else
	155	rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
	156	#endif
	157
	158	#if 0
	159
	160	#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
	161	/* Configure port A pins for Txd and Rxd.
	162	*/
	163	immr->im_ioport.iop_papar \|= (PA_ENET_RXD \| PA_ENET_TXD);
	164	immr->im_ioport.iop_padir &= ~(PA_ENET_RXD \| PA_ENET_TXD);
	165	immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
	166	#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
	167	/* Configure port B pins for Txd and Rxd.
	168	*/
	169	immr->im_cpm.cp_pbpar \|= (PB_ENET_RXD \| PB_ENET_TXD);
	170	immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD \| PB_ENET_TXD);
	171	immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
	172	#else
	173	#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
	174	#endif
	175
	176	#if defined(PC_ENET_LBK)
	177	/* Configure port C pins to disable External Loopback
	178	*/
	179	immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
	180	immr->im_ioport.iop_pcdir \|= PC_ENET_LBK;
	181	immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
	182	immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
	183	#endif /* PC_ENET_LBK */
	184
	185	/* Configure port C pins to enable CLSN and RENA.
	186	*/
	187	immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN \| PC_ENET_RENA);
	188	immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN \| PC_ENET_RENA);
	189	immr->im_ioport.iop_pcso \|= (PC_ENET_CLSN \| PC_ENET_RENA);
	190
	191	/* Configure port A for TCLK and RCLK.
	192	*/
	193	immr->im_ioport.iop_papar \|= (PA_ENET_TCLK \| PA_ENET_RCLK);
	194	immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK \| PA_ENET_RCLK);
	195
	196	/*
	197	* Configure Serial Interface clock routing -- see section 16.7.5.3
	198	* First, clear all SCC bits to zero, then set the ones we want.
	199	*/
	200
	201	immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
	202	immr->im_cpm.cp_sicr \|= SICR_ENET_CLKRT;
	203	#else
	204	/*
	205	* SCC2 receive clock is BRG2
	206	* SCC2 transmit clock is BRG3
	207	*/
	208	immr->im_cpm.cp_brgc2 = 0x0001000C;
	209	immr->im_cpm.cp_brgc3 = 0x0001000C;
	210
	211	immr->im_cpm.cp_sicr &= ~0x00003F00;
	212	immr->im_cpm.cp_sicr \|= 0x00000a00;
	213	#endif /* 0 */
	214
	215
216	/*
217	* Initialize SDCR -- see section 16.9.23.7
218	* SDMA configuration register
219	*/
220	immr->im_siu_conf.sc_sdcr = 0x01;
221
222
223	/*
224	* Setup SCC Ethernet Parameter RAM
225	*/
226
227	pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
228	pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
229
230	pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
231
232	pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
233	pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
234
235	/*
236	* Setup Receiver Buffer Descriptors (13.14.24.18)
237	* Settings:
238	* Empty, Wrap
239	*/
240
241	for (i = 0; i < PKTBUFSRX; i++) {
242	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
243	rtx->rxbd[i].cbd_datlen = 0; /* Reset */
244	rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
245	}
246
247	rtx->rxbd[PKTBUFSRX - 1].cbd_sc \|= BD_ENET_RX_WRAP;
248
249	/*
250	* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
251	* Settings:
252	* Add PADs to Short FRAMES, Wrap, Last, Tx CRC
253	*/
254
255	for (i = 0; i < TX_BUF_CNT; i++) {
256	rtx->txbd[i].cbd_sc =
257	(BD_ENET_TX_PAD \| BD_ENET_TX_LAST \| BD_ENET_TX_TC);
258	rtx->txbd[i].cbd_datlen = 0; /* Reset */
259	rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
260	}
261
262	rtx->txbd[TX_BUF_CNT - 1].cbd_sc \|= BD_ENET_TX_WRAP;
263
264	/*
265	* Enter Command: Initialize Rx Params for SCC
266	*/
267
268	do { /* Spin until ready to issue command */
269	__asm__ ("eieio");
270	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
271	/* Issue command */
272	immr->im_cpm.cp_cpcr =
273	((CPM_CR_INIT_RX << 8) \| (cpm_cr[scc_index] << 4) \|
274	CPM_CR_FLG);
275	do { /* Spin until command processed */
276	__asm__ ("eieio");
277	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
278
279	/*
280	* Ethernet Specific Parameter RAM
281	* see table 13-16, pg. 660,
282	* pg. 681 (example with suggested settings)
283	*/
284
285	pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
286	pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
287	pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
288	pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
289	pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
290	pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
291
292	pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
293	pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
294	pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
295
296	pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
297	pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
298
299	pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
300	pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
301	pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
302	pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
303
6bacfa6a	304	eth_getenv_enetaddr("ethaddr", ea);
ad5bb451 WD	305	pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
	306	pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
	307	pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
ad5bb451 WD	308
	309	pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
	310	pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
	311	pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
	312	pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
	313	pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
	314	pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
	315	pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
	316	pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
	317
	318	/*
	319	* Enter Command: Initialize Tx Params for SCC
	320	*/
	321
	322	do { /* Spin until ready to issue command */
	323	__asm__ ("eieio");
	324	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	325	/* Issue command */
	326	immr->im_cpm.cp_cpcr =
	327	((CPM_CR_INIT_TX << 8) \| (cpm_cr[scc_index] << 4) \|
	328	CPM_CR_FLG);
	329	do { /* Spin until command processed */
	330	__asm__ ("eieio");
	331	} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	332
	333	/*
	334	* Mask all Events in SCCM - we use polling mode
	335	*/
	336	immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
	337
	338	/*
	339	* Clear Events in SCCE -- Clear bits by writing 1's
	340	*/
	341
	342	immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
	343
	344
	345	/*
	346	* Initialize GSMR High 32-Bits
	347	* Settings: Normal Mode
	348	*/
	349
	350	immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
	351
	352	/*
	353	* Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
	354	* Settings:
	355	* TCI = Invert
	356	* TPL = 48 bits
	357	* TPP = Repeating 10's
	358	* LOOP = Loopback
	359	* MODE = Ethernet
	360	*/
	361
	362	immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI \|
	363	SCC_GSMRL_TPL_48 \|
	364	SCC_GSMRL_TPP_10 \|
	365	SCC_GSMRL_DIAG_LOOP \|
	366	SCC_GSMRL_MODE_ENET);
	367
	368	/*
	369	* Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
	370	*/
	371
372	immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
373
374	/*
375	* Initialize the PSMR
376	* Settings:
377	* CRC = 32-Bit CCITT
378	* NIB = Begin searching for SFD 22 bits after RENA
379	* LPB = Loopback Enable (Needed when FDE is set)
380	*/
381	immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC \|
382	SCC_PSMR_NIB22 \| SCC_PSMR_LPB;
383
ad5bb451 WD	384	#ifdef CONFIG_RPXCLASSIC
	385	((uchar ) BCSR0) &= ~BCSR0_ETHLPBK;
	386	((uchar ) BCSR0) \|= (BCSR0_ETHEN \| BCSR0_COLTEST \| BCSR0_FULLDPLX);
	387	#endif
	388
	389	#ifdef CONFIG_RPXLITE
	390	((uchar ) BCSR0) \|= BCSR0_ETHEN;
	391	#endif
	392
	393	#ifdef CONFIG_MBX
	394	board_ether_init ();
	395	#endif
	396
	397	/*
	398	* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
	399	*/
	400
	401	immr->im_cpm.cp_scc[scc_index].scc_gsmrl \|=
	402	(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	403
	404	/*
	405	* Work around transmit problem with first eth packet
	406	*/
	407	#if defined (CONFIG_FADS)
	408	udelay (10000); /* wait 10 ms */
1b0757ec	409	#elif defined(CONFIG_RPXCLASSIC)
ad5bb451 WD	410	udelay (100000); /* wait 100 ms */
	411	#endif
	412	}
	413
	414	static void scc_halt (int scc_index)
	415	{
6d0f6bcf	416	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	417
	418	immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
	419	~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	420	immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN \| PC_ENET_RENA);
	421	}
	422
	423	static int scc_send (int index, volatile void *packet, int length)
	424	{
	425	int i, j = 0;
	426
	427	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
	428	udelay (1); /* will also trigger Wd if needed */
	429	j++;
	430	}
	431	if (j >= TOUT_LOOP)
	432	printf ("TX not ready\n");
	433	rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
	434	rtx->txbd[txIdx].cbd_datlen = length;
	435	rtx->txbd[txIdx].cbd_sc \|=
	436	(BD_ENET_TX_READY \| BD_ENET_TX_LAST \| BD_ENET_TX_WRAP);
	437	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
	438	udelay (1); /* will also trigger Wd if needed */
	439	j++;
	440	}
	441	if (j >= TOUT_LOOP)
	442	printf ("TX timeout\n");
	443	i = (rtx->txbd[txIdx].
	444	cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
	445	return i;
	446	}
	447
	448	static int scc_recv (int index, void *packet, int max_length)
	449	{
	450	int length = -1;
	451
	452	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
	453	goto Done; /* nothing received */
	454	}
	455
	456	if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
	457	length = rtx->rxbd[rxIdx].cbd_datlen - 4;
	458	memcpy (packet,
	459	(void *) (NetRxPackets[rxIdx]),
	460	length < max_length ? length : max_length);
	461	}
	462
	463	/* Give the buffer back to the SCC. */
	464	rtx->rxbd[rxIdx].cbd_datlen = 0;
	465
	466	/* wrap around buffer index when necessary */
	467	if ((rxIdx + 1) >= PKTBUFSRX) {
	468	rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
	469	(BD_ENET_RX_WRAP \| BD_ENET_RX_EMPTY);
	470	rxIdx = 0;
	471	} else {
	472	rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
	473	rxIdx++;
	474	}
	475
	476	Done:
	477	return length;
	478	}
	479
	480	/*
481	* Test routines
482	*/
483
484	static void packet_fill (char *packet, int length)
485	{
486	char c = (char) length;
487	int i;
488
489	packet[0] = 0xFF;
490	packet[1] = 0xFF;
491	packet[2] = 0xFF;
492	packet[3] = 0xFF;
493	packet[4] = 0xFF;
494	packet[5] = 0xFF;
495
496	for (i = 6; i < length; i++) {
497	packet[i] = c++;
498	}
499	}
500
501	static int packet_check (char *packet, int length)
502	{
503	char c = (char) length;
504	int i;
505
506	for (i = 6; i < length; i++) {
507	if (packet[i] != c++)
508	return -1;
509	}
510
511	return 0;
512	}
513
514	static int test_ctlr (int ctlr, int index)
515	{
516	int res = -1;
517	char packet_send[MAX_PACKET_LENGTH];
518	char packet_recv[MAX_PACKET_LENGTH];
519	int length;
520	int i;
521	int l;
522
523	ctlr_proc[ctlr].init (index);
524
525	for (i = 0; i < TEST_NUM; i++) {
526	for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
527	packet_fill (packet_send, l);
528
529	ctlr_proc[ctlr].send (index, packet_send, l);
530
531	length = ctlr_proc[ctlr].recv (index, packet_recv,
532	MAX_PACKET_LENGTH);
533
534	if (length != l \|\| packet_check (packet_recv, length) < 0) {
535	goto Done;
536	}
537	}
538	}
539
540	res = 0;
541
542	Done:
543
544	ctlr_proc[ctlr].halt (index);
545
546	/*
547	* SCC2 Ethernet parameter RAM space overlaps
548	* the SPI parameter RAM space. So we need to restore
549	* the SPI configuration after SCC2 ethernet test.
550	*/
551	#if defined(CONFIG_SPI)
552	if (ctlr == CTLR_SCC && index == 1) {
553	spi_init_f ();
554	spi_init_r ();
555	}
556	#endif
557
558	if (res != 0) {
559	post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
560	index + 1);
561	}
562
563	return res;
564	}
565
566	int ether_post_test (int flags)
567	{
568	int res = 0;
569	int i;
570
571	ctlr_proc[CTLR_SCC].init = scc_init;
572	ctlr_proc[CTLR_SCC].halt = scc_halt;
573	ctlr_proc[CTLR_SCC].send = scc_send;
574	ctlr_proc[CTLR_SCC].recv = scc_recv;
575
d2397817	576	for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
ad5bb451 WD	577	if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
	578	res = -1;
	579	}
	580	}
	581
	582	#if !defined(CONFIG_8xx_CONS_NONE)
	583	serial_reinit_all ();
	584	#endif
	585	return res;
	586	}
	587
6d0f6bcf	588	#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */