]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ad5bb451 WD |
2 | /* |
3 | * (C) Copyright 2002 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
ad5bb451 WD |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
f7ae49fc | 8 | #include <log.h> |
401d1c4f | 9 | #include <asm/global_data.h> |
ad5bb451 WD |
10 | |
11 | /* Memory test | |
12 | * | |
13 | * General observations: | |
14 | * o The recommended test sequence is to test the data lines: if they are | |
15 | * broken, nothing else will work properly. Then test the address | |
16 | * lines. Finally, test the cells in the memory now that the test | |
17 | * program knows that the address and data lines work properly. | |
18 | * This sequence also helps isolate and identify what is faulty. | |
19 | * | |
20 | * o For the address line test, it is a good idea to use the base | |
21 | * address of the lowest memory location, which causes a '1' bit to | |
22 | * walk through a field of zeros on the address lines and the highest | |
23 | * memory location, which causes a '0' bit to walk through a field of | |
24 | * '1's on the address line. | |
25 | * | |
26 | * o Floating buses can fool memory tests if the test routine writes | |
27 | * a value and then reads it back immediately. The problem is, the | |
28 | * write will charge the residual capacitance on the data bus so the | |
29 | * bus retains its state briefely. When the test program reads the | |
30 | * value back immediately, the capacitance of the bus can allow it | |
31 | * to read back what was written, even though the memory circuitry | |
32 | * is broken. To avoid this, the test program should write a test | |
33 | * pattern to the target location, write a different pattern elsewhere | |
34 | * to charge the residual capacitance in a differnt manner, then read | |
35 | * the target location back. | |
36 | * | |
37 | * o Always read the target location EXACTLY ONCE and save it in a local | |
38 | * variable. The problem with reading the target location more than | |
39 | * once is that the second and subsequent reads may work properly, | |
40 | * resulting in a failed test that tells the poor technician that | |
41 | * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which | |
42 | * doesn't help him one bit and causes puzzled phone calls. Been there, | |
43 | * done that. | |
44 | * | |
45 | * Data line test: | |
46 | * --------------- | |
47 | * This tests data lines for shorts and opens by forcing adjacent data | |
48 | * to opposite states. Because the data lines could be routed in an | |
49 | * arbitrary manner the must ensure test patterns ensure that every case | |
50 | * is tested. By using the following series of binary patterns every | |
51 | * combination of adjacent bits is test regardless of routing. | |
52 | * | |
53 | * ...101010101010101010101010 | |
54 | * ...110011001100110011001100 | |
55 | * ...111100001111000011110000 | |
56 | * ...111111110000000011111111 | |
57 | * | |
58 | * Carrying this out, gives us six hex patterns as follows: | |
59 | * | |
60 | * 0xaaaaaaaaaaaaaaaa | |
61 | * 0xcccccccccccccccc | |
62 | * 0xf0f0f0f0f0f0f0f0 | |
63 | * 0xff00ff00ff00ff00 | |
64 | * 0xffff0000ffff0000 | |
65 | * 0xffffffff00000000 | |
66 | * | |
67 | * To test for short and opens to other signals on our boards, we | |
68 | * simply test with the 1's complemnt of the paterns as well, resulting | |
69 | * in twelve patterns total. | |
70 | * | |
71 | * After writing a test pattern. a special pattern 0x0123456789ABCDEF is | |
72 | * written to a different address in case the data lines are floating. | |
73 | * Thus, if a byte lane fails, you will see part of the special | |
74 | * pattern in that byte lane when the test runs. For example, if the | |
75 | * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa | |
76 | * (for the 'a' test pattern). | |
77 | * | |
78 | * Address line test: | |
79 | * ------------------ | |
80 | * This function performs a test to verify that all the address lines | |
81 | * hooked up to the RAM work properly. If there is an address line | |
82 | * fault, it usually shows up as two different locations in the address | |
83 | * map (related by the faulty address line) mapping to one physical | |
84 | * memory storage location. The artifact that shows up is writing to | |
85 | * the first location "changes" the second location. | |
86 | * | |
87 | * To test all address lines, we start with the given base address and | |
88 | * xor the address with a '1' bit to flip one address line. For each | |
89 | * test, we shift the '1' bit left to test the next address line. | |
90 | * | |
91 | * In the actual code, we start with address sizeof(ulong) since our | |
92 | * test pattern we use is a ulong and thus, if we tried to test lower | |
93 | * order address bits, it wouldn't work because our pattern would | |
94 | * overwrite itself. | |
95 | * | |
96 | * Example for a 4 bit address space with the base at 0000: | |
97 | * 0000 <- base | |
98 | * 0001 <- test 1 | |
99 | * 0010 <- test 2 | |
100 | * 0100 <- test 3 | |
101 | * 1000 <- test 4 | |
102 | * Example for a 4 bit address space with the base at 0010: | |
103 | * 0010 <- base | |
104 | * 0011 <- test 1 | |
105 | * 0000 <- (below the base address, skipped) | |
106 | * 0110 <- test 2 | |
107 | * 1010 <- test 3 | |
108 | * | |
109 | * The test locations are successively tested to make sure that they are | |
110 | * not "mirrored" onto the base address due to a faulty address line. | |
111 | * Note that the base and each test location are related by one address | |
112 | * line flipped. Note that the base address need not be all zeros. | |
113 | * | |
114 | * Memory tests 1-4: | |
115 | * ----------------- | |
116 | * These tests verify RAM using sequential writes and reads | |
117 | * to/from RAM. There are several test cases that use different patterns to | |
118 | * verify RAM. Each test case fills a region of RAM with one pattern and | |
119 | * then reads the region back and compares its contents with the pattern. | |
120 | * The following patterns are used: | |
121 | * | |
122 | * 1a) zero pattern (0x00000000) | |
123 | * 1b) negative pattern (0xffffffff) | |
124 | * 1c) checkerboard pattern (0x55555555) | |
125 | * 1d) checkerboard pattern (0xaaaaaaaa) | |
126 | * 2) bit-flip pattern ((1 << (offset % 32)) | |
127 | * 3) address pattern (offset) | |
128 | * 4) address pattern (~offset) | |
129 | * | |
130 | * Being run in normal mode, the test verifies only small 4Kb | |
131 | * regions of RAM around each 1Mb boundary. For example, for 64Mb | |
132 | * RAM the following areas are verified: 0x00000000-0x00000800, | |
133 | * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- | |
134 | * 0x04000000. If the test is run in slow-test mode, it verifies | |
135 | * the whole RAM. | |
136 | */ | |
137 | ||
ad5bb451 WD |
138 | #include <post.h> |
139 | #include <watchdog.h> | |
140 | ||
9cebc4ad | 141 | #if CFG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS) |
ad5bb451 WD |
142 | |
143 | DECLARE_GLOBAL_DATA_PTR; | |
144 | ||
145 | /* | |
146 | * Define INJECT_*_ERRORS for testing error detection in the presence of | |
147 | * _good_ hardware. | |
148 | */ | |
149 | #undef INJECT_DATA_ERRORS | |
150 | #undef INJECT_ADDRESS_ERRORS | |
151 | ||
152 | #ifdef INJECT_DATA_ERRORS | |
153 | #warning "Injecting data line errors for testing purposes" | |
154 | #endif | |
155 | ||
156 | #ifdef INJECT_ADDRESS_ERRORS | |
157 | #warning "Injecting address line errors for testing purposes" | |
158 | #endif | |
159 | ||
160 | ||
161 | /* | |
162 | * This function performs a double word move from the data at | |
163 | * the source pointer to the location at the destination pointer. | |
164 | * This is helpful for testing memory on processors which have a 64 bit | |
165 | * wide data bus. | |
166 | * | |
167 | * On those PowerPC with FPU, use assembly and a floating point move: | |
168 | * this does a 64 bit move. | |
169 | * | |
170 | * For other processors, let the compiler generate the best code it can. | |
171 | */ | |
44b4dbed | 172 | static void move64(const unsigned long long *src, unsigned long long *dest) |
ad5bb451 | 173 | { |
ad5bb451 | 174 | *dest = *src; |
ad5bb451 WD |
175 | } |
176 | ||
177 | /* | |
178 | * This is 64 bit wide test patterns. Note that they reside in ROM | |
179 | * (which presumably works) and the tests write them to RAM which may | |
180 | * not work. | |
181 | * | |
182 | * The "otherpattern" is written to drive the data bus to values other | |
183 | * than the test pattern. This is for detecting floating bus lines. | |
184 | * | |
185 | */ | |
186 | const static unsigned long long pattern[] = { | |
187 | 0xaaaaaaaaaaaaaaaaULL, | |
188 | 0xccccccccccccccccULL, | |
189 | 0xf0f0f0f0f0f0f0f0ULL, | |
190 | 0xff00ff00ff00ff00ULL, | |
191 | 0xffff0000ffff0000ULL, | |
192 | 0xffffffff00000000ULL, | |
193 | 0x00000000ffffffffULL, | |
194 | 0x0000ffff0000ffffULL, | |
195 | 0x00ff00ff00ff00ffULL, | |
196 | 0x0f0f0f0f0f0f0f0fULL, | |
197 | 0x3333333333333333ULL, | |
198 | 0x5555555555555555ULL | |
199 | }; | |
200 | const unsigned long long otherpattern = 0x0123456789abcdefULL; | |
201 | ||
202 | ||
203 | static int memory_post_dataline(unsigned long long * pmem) | |
204 | { | |
205 | unsigned long long temp64 = 0; | |
d2397817 | 206 | int num_patterns = ARRAY_SIZE(pattern); |
ad5bb451 WD |
207 | int i; |
208 | unsigned int hi, lo, pathi, patlo; | |
209 | int ret = 0; | |
210 | ||
211 | for ( i = 0; i < num_patterns; i++) { | |
44b4dbed | 212 | move64(&(pattern[i]), pmem++); |
ad5bb451 WD |
213 | /* |
214 | * Put a different pattern on the data lines: otherwise they | |
215 | * may float long enough to read back what we wrote. | |
216 | */ | |
44b4dbed | 217 | move64(&otherpattern, pmem--); |
ad5bb451 WD |
218 | move64(pmem, &temp64); |
219 | ||
220 | #ifdef INJECT_DATA_ERRORS | |
221 | temp64 ^= 0x00008000; | |
222 | #endif | |
223 | ||
224 | if (temp64 != pattern[i]){ | |
225 | pathi = (pattern[i]>>32) & 0xffffffff; | |
226 | patlo = pattern[i] & 0xffffffff; | |
227 | ||
228 | hi = (temp64>>32) & 0xffffffff; | |
229 | lo = temp64 & 0xffffffff; | |
230 | ||
56ce22c0 SA |
231 | post_log("Memory (data line) error at %p, wrote %08x%08x, read %08x%08x !\n", |
232 | pmem, pathi, patlo, hi, lo); | |
ad5bb451 WD |
233 | ret = -1; |
234 | } | |
235 | } | |
236 | return ret; | |
237 | } | |
238 | ||
239 | static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) | |
240 | { | |
241 | ulong *target; | |
242 | ulong *end; | |
243 | ulong readback; | |
244 | ulong xor; | |
245 | int ret = 0; | |
246 | ||
247 | end = (ulong *)((ulong)base + size); /* pointer arith! */ | |
248 | xor = 0; | |
249 | for(xor = sizeof(ulong); xor > 0; xor <<= 1) { | |
250 | target = (ulong *)((ulong)testaddr ^ xor); | |
251 | if((target >= base) && (target < end)) { | |
252 | *testaddr = ~*target; | |
253 | readback = *target; | |
254 | ||
255 | #ifdef INJECT_ADDRESS_ERRORS | |
256 | if(xor == 0x00008000) { | |
257 | readback = *testaddr; | |
258 | } | |
259 | #endif | |
260 | if(readback == *testaddr) { | |
56ce22c0 SA |
261 | post_log("Memory (address line) error at %p<->%p, XOR value %08lx !\n", |
262 | testaddr, target, xor); | |
ad5bb451 WD |
263 | ret = -1; |
264 | } | |
265 | } | |
266 | } | |
267 | return ret; | |
268 | } | |
269 | ||
ca51d057 | 270 | static int memory_post_test1(unsigned long start, |
ad5bb451 WD |
271 | unsigned long size, |
272 | unsigned long val) | |
273 | { | |
274 | unsigned long i; | |
275 | ulong *mem = (ulong *) start; | |
276 | ulong readback; | |
277 | int ret = 0; | |
278 | ||
279 | for (i = 0; i < size / sizeof (ulong); i++) { | |
280 | mem[i] = val; | |
281 | if (i % 1024 == 0) | |
29caf930 | 282 | schedule(); |
ad5bb451 WD |
283 | } |
284 | ||
ca51d057 | 285 | for (i = 0; i < size / sizeof (ulong) && !ret; i++) { |
ad5bb451 WD |
286 | readback = mem[i]; |
287 | if (readback != val) { | |
56ce22c0 SA |
288 | post_log("Memory error at %p, wrote %08lx, read %08lx !\n", |
289 | mem + i, val, readback); | |
ad5bb451 WD |
290 | |
291 | ret = -1; | |
292 | break; | |
293 | } | |
294 | if (i % 1024 == 0) | |
29caf930 | 295 | schedule(); |
ad5bb451 WD |
296 | } |
297 | ||
298 | return ret; | |
299 | } | |
300 | ||
ca51d057 | 301 | static int memory_post_test2(unsigned long start, unsigned long size) |
ad5bb451 WD |
302 | { |
303 | unsigned long i; | |
304 | ulong *mem = (ulong *) start; | |
305 | ulong readback; | |
306 | int ret = 0; | |
307 | ||
308 | for (i = 0; i < size / sizeof (ulong); i++) { | |
309 | mem[i] = 1 << (i % 32); | |
310 | if (i % 1024 == 0) | |
29caf930 | 311 | schedule(); |
ad5bb451 WD |
312 | } |
313 | ||
ca51d057 | 314 | for (i = 0; i < size / sizeof (ulong) && !ret; i++) { |
ad5bb451 WD |
315 | readback = mem[i]; |
316 | if (readback != (1 << (i % 32))) { | |
56ce22c0 SA |
317 | post_log("Memory error at %p, wrote %08lx, read %08lx !\n", |
318 | mem + i, 1UL << (i % 32), readback); | |
ad5bb451 WD |
319 | |
320 | ret = -1; | |
321 | break; | |
322 | } | |
323 | if (i % 1024 == 0) | |
29caf930 | 324 | schedule(); |
ad5bb451 WD |
325 | } |
326 | ||
327 | return ret; | |
328 | } | |
329 | ||
ca51d057 | 330 | static int memory_post_test3(unsigned long start, unsigned long size) |
ad5bb451 WD |
331 | { |
332 | unsigned long i; | |
333 | ulong *mem = (ulong *) start; | |
334 | ulong readback; | |
335 | int ret = 0; | |
336 | ||
337 | for (i = 0; i < size / sizeof (ulong); i++) { | |
338 | mem[i] = i; | |
339 | if (i % 1024 == 0) | |
29caf930 | 340 | schedule(); |
ad5bb451 WD |
341 | } |
342 | ||
ca51d057 | 343 | for (i = 0; i < size / sizeof (ulong) && !ret; i++) { |
ad5bb451 WD |
344 | readback = mem[i]; |
345 | if (readback != i) { | |
56ce22c0 SA |
346 | post_log("Memory error at %p, wrote %08lx, read %08lx !\n", |
347 | mem + i, i, readback); | |
ad5bb451 WD |
348 | |
349 | ret = -1; | |
350 | break; | |
351 | } | |
352 | if (i % 1024 == 0) | |
29caf930 | 353 | schedule(); |
ad5bb451 WD |
354 | } |
355 | ||
356 | return ret; | |
357 | } | |
358 | ||
ca51d057 | 359 | static int memory_post_test4(unsigned long start, unsigned long size) |
ad5bb451 WD |
360 | { |
361 | unsigned long i; | |
362 | ulong *mem = (ulong *) start; | |
363 | ulong readback; | |
364 | int ret = 0; | |
365 | ||
366 | for (i = 0; i < size / sizeof (ulong); i++) { | |
367 | mem[i] = ~i; | |
368 | if (i % 1024 == 0) | |
29caf930 | 369 | schedule(); |
ad5bb451 WD |
370 | } |
371 | ||
ca51d057 | 372 | for (i = 0; i < size / sizeof (ulong) && !ret; i++) { |
ad5bb451 WD |
373 | readback = mem[i]; |
374 | if (readback != ~i) { | |
56ce22c0 SA |
375 | post_log("Memory error at %p, wrote %08lx, read %08lx !\n", |
376 | mem + i, ~i, readback); | |
ad5bb451 WD |
377 | |
378 | ret = -1; | |
379 | break; | |
380 | } | |
381 | if (i % 1024 == 0) | |
29caf930 | 382 | schedule(); |
ad5bb451 WD |
383 | } |
384 | ||
385 | return ret; | |
386 | } | |
387 | ||
8d3fcb5e | 388 | static int memory_post_test_lines(unsigned long start, unsigned long size) |
ad5bb451 WD |
389 | { |
390 | int ret = 0; | |
391 | ||
8d3fcb5e | 392 | ret = memory_post_dataline((unsigned long long *)start); |
29caf930 | 393 | schedule(); |
ca51d057 VL |
394 | if (!ret) |
395 | ret = memory_post_addrline((ulong *)start, (ulong *)start, | |
8d3fcb5e | 396 | size); |
29caf930 | 397 | schedule(); |
ca51d057 | 398 | if (!ret) |
8d3fcb5e VL |
399 | ret = memory_post_addrline((ulong *)(start+size-8), |
400 | (ulong *)start, size); | |
29caf930 | 401 | schedule(); |
8d3fcb5e VL |
402 | |
403 | return ret; | |
404 | } | |
405 | ||
406 | static int memory_post_test_patterns(unsigned long start, unsigned long size) | |
407 | { | |
408 | int ret = 0; | |
409 | ||
410 | ret = memory_post_test1(start, size, 0x00000000); | |
29caf930 | 411 | schedule(); |
ca51d057 VL |
412 | if (!ret) |
413 | ret = memory_post_test1(start, size, 0xffffffff); | |
29caf930 | 414 | schedule(); |
ca51d057 VL |
415 | if (!ret) |
416 | ret = memory_post_test1(start, size, 0x55555555); | |
29caf930 | 417 | schedule(); |
ca51d057 VL |
418 | if (!ret) |
419 | ret = memory_post_test1(start, size, 0xaaaaaaaa); | |
29caf930 | 420 | schedule(); |
ca51d057 VL |
421 | if (!ret) |
422 | ret = memory_post_test2(start, size); | |
29caf930 | 423 | schedule(); |
ca51d057 VL |
424 | if (!ret) |
425 | ret = memory_post_test3(start, size); | |
29caf930 | 426 | schedule(); |
ca51d057 VL |
427 | if (!ret) |
428 | ret = memory_post_test4(start, size); | |
29caf930 | 429 | schedule(); |
ad5bb451 WD |
430 | |
431 | return ret; | |
432 | } | |
433 | ||
8d3fcb5e VL |
434 | static int memory_post_test_regions(unsigned long start, unsigned long size) |
435 | { | |
436 | unsigned long i; | |
437 | int ret = 0; | |
438 | ||
439 | for (i = 0; i < (size >> 20) && (!ret); i++) { | |
440 | if (!ret) | |
7b5d61b5 | 441 | ret = memory_post_test_patterns(start + (i << 20), |
8d3fcb5e | 442 | 0x800); |
7b5d61b5 HS |
443 | if (!ret) |
444 | ret = memory_post_test_patterns(start + (i << 20) + | |
445 | 0xff800, 0x800); | |
8d3fcb5e VL |
446 | } |
447 | ||
448 | return ret; | |
449 | } | |
450 | ||
451 | static int memory_post_tests(unsigned long start, unsigned long size) | |
452 | { | |
453 | int ret = 0; | |
454 | ||
455 | ret = memory_post_test_lines(start, size); | |
456 | if (!ret) | |
457 | ret = memory_post_test_patterns(start, size); | |
458 | ||
459 | return ret; | |
460 | } | |
461 | ||
4204298d HS |
462 | /* |
463 | * !! this is only valid, if you have contiguous memory banks !! | |
464 | */ | |
28417030 YS |
465 | __attribute__((weak)) |
466 | int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) | |
ad5bb451 | 467 | { |
b75d8dc5 | 468 | struct bd_info *bd = gd->bd; |
4204298d | 469 | |
aa6e94de | 470 | *vstart = CFG_SYS_SDRAM_BASE; |
4204298d HS |
471 | *size = (gd->ram_size >= 256 << 20 ? |
472 | 256 << 20 : gd->ram_size) - (1 << 20); | |
ad5bb451 | 473 | |
9c02defc | 474 | /* Limit area to be tested with the board info struct */ |
28417030 YS |
475 | if ((*vstart) + (*size) > (ulong)bd) |
476 | *size = (ulong)bd - *vstart; | |
477 | ||
478 | return 0; | |
479 | } | |
ad5bb451 | 480 | |
28417030 YS |
481 | __attribute__((weak)) |
482 | int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) | |
483 | { | |
484 | return 1; | |
485 | } | |
ad5bb451 | 486 | |
28417030 YS |
487 | __attribute__((weak)) |
488 | int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) | |
489 | { | |
490 | return 0; | |
491 | } | |
ad5bb451 | 492 | |
28417030 YS |
493 | __attribute__((weak)) |
494 | void arch_memory_failure_handle(void) | |
495 | { | |
496 | return; | |
497 | } | |
498 | ||
8d3fcb5e VL |
499 | int memory_regions_post_test(int flags) |
500 | { | |
501 | int ret = 0; | |
502 | phys_addr_t phys_offset = 0; | |
503 | u32 memsize, vstart; | |
504 | ||
505 | arch_memory_test_prepare(&vstart, &memsize, &phys_offset); | |
506 | ||
507 | ret = memory_post_test_lines(vstart, memsize); | |
508 | if (!ret) | |
509 | ret = memory_post_test_regions(vstart, memsize); | |
510 | ||
511 | return ret; | |
512 | } | |
513 | ||
28417030 YS |
514 | int memory_post_test(int flags) |
515 | { | |
516 | int ret = 0; | |
517 | phys_addr_t phys_offset = 0; | |
518 | u32 memsize, vstart; | |
519 | ||
520 | arch_memory_test_prepare(&vstart, &memsize, &phys_offset); | |
521 | ||
522 | do { | |
523 | if (flags & POST_SLOWTEST) { | |
524 | ret = memory_post_tests(vstart, memsize); | |
525 | } else { /* POST_NORMAL */ | |
8d3fcb5e | 526 | ret = memory_post_test_regions(vstart, memsize); |
ad5bb451 | 527 | } |
28417030 YS |
528 | } while (!ret && |
529 | !arch_memory_test_advance(&vstart, &memsize, &phys_offset)); | |
530 | ||
531 | arch_memory_test_cleanup(&vstart, &memsize, &phys_offset); | |
532 | if (ret) | |
533 | arch_memory_failure_handle(); | |
ad5bb451 WD |
534 | |
535 | return ret; | |
536 | } | |
537 | ||
9cebc4ad | 538 | #endif /* CFG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */ |