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1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | ||
26 | /* | |
27 | * CPU test | |
28 | * Shift instructions: srawi | |
29 | * | |
30 | * The test contains a pre-built table of instructions, operands and | |
31 | * expected results. For each table entry, the test will cyclically use | |
32 | * different sets of operand registers and result registers. | |
33 | */ | |
34 | ||
ad5bb451 WD |
35 | #include <post.h> |
36 | #include "cpu_asm.h" | |
37 | ||
6d0f6bcf | 38 | #if CONFIG_POST & CONFIG_SYS_POST_CPU |
ad5bb451 WD |
39 | |
40 | extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); | |
41 | extern ulong cpu_post_makecr (long v); | |
42 | ||
43 | static struct cpu_post_srawi_s | |
44 | { | |
45 | ulong cmd; | |
46 | ulong op1; | |
47 | uchar op2; | |
48 | ulong res; | |
49 | } cpu_post_srawi_table[] = | |
50 | { | |
51 | { | |
53677ef1 | 52 | OP_SRAWI, |
ad5bb451 WD |
53 | 0x8000, |
54 | 3, | |
55 | 0x1000 | |
56 | }, | |
57 | { | |
53677ef1 | 58 | OP_SRAWI, |
ad5bb451 WD |
59 | 0x80000000, |
60 | 3, | |
61 | 0xf0000000 | |
62 | }, | |
63 | }; | |
64 | static unsigned int cpu_post_srawi_size = | |
65 | sizeof (cpu_post_srawi_table) / sizeof (struct cpu_post_srawi_s); | |
66 | ||
67 | int cpu_post_test_srawi (void) | |
68 | { | |
69 | int ret = 0; | |
70 | unsigned int i, reg; | |
71 | int flag = disable_interrupts(); | |
72 | ||
73 | for (i = 0; i < cpu_post_srawi_size && ret == 0; i++) | |
74 | { | |
75 | struct cpu_post_srawi_s *test = cpu_post_srawi_table + i; | |
76 | ||
77 | for (reg = 0; reg < 32 && ret == 0; reg++) | |
78 | { | |
79 | unsigned int reg0 = (reg + 0) % 32; | |
80 | unsigned int reg1 = (reg + 1) % 32; | |
81 | unsigned int stk = reg < 16 ? 31 : 15; | |
53677ef1 | 82 | unsigned long code[] = |
ad5bb451 WD |
83 | { |
84 | ASM_STW(stk, 1, -4), | |
85 | ASM_ADDI(stk, 1, -16), | |
86 | ASM_STW(3, stk, 8), | |
87 | ASM_STW(reg0, stk, 4), | |
88 | ASM_STW(reg1, stk, 0), | |
89 | ASM_LWZ(reg0, stk, 8), | |
90 | ASM_11S(test->cmd, reg1, reg0, test->op2), | |
91 | ASM_STW(reg1, stk, 8), | |
92 | ASM_LWZ(reg1, stk, 0), | |
93 | ASM_LWZ(reg0, stk, 4), | |
94 | ASM_LWZ(3, stk, 8), | |
95 | ASM_ADDI(1, stk, 16), | |
96 | ASM_LWZ(stk, 1, -4), | |
97 | ASM_BLR, | |
98 | }; | |
53677ef1 | 99 | unsigned long codecr[] = |
ad5bb451 WD |
100 | { |
101 | ASM_STW(stk, 1, -4), | |
102 | ASM_ADDI(stk, 1, -16), | |
103 | ASM_STW(3, stk, 8), | |
104 | ASM_STW(reg0, stk, 4), | |
105 | ASM_STW(reg1, stk, 0), | |
106 | ASM_LWZ(reg0, stk, 8), | |
107 | ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, | |
108 | ASM_STW(reg1, stk, 8), | |
109 | ASM_LWZ(reg1, stk, 0), | |
110 | ASM_LWZ(reg0, stk, 4), | |
111 | ASM_LWZ(3, stk, 8), | |
112 | ASM_ADDI(1, stk, 16), | |
113 | ASM_LWZ(stk, 1, -4), | |
114 | ASM_BLR, | |
115 | }; | |
116 | ulong res; | |
117 | ulong cr; | |
118 | ||
119 | if (ret == 0) | |
120 | { | |
53677ef1 WD |
121 | cr = 0; |
122 | cpu_post_exec_21 (code, & cr, & res, test->op1); | |
ad5bb451 | 123 | |
53677ef1 | 124 | ret = res == test->res && cr == 0 ? 0 : -1; |
ad5bb451 | 125 | |
53677ef1 WD |
126 | if (ret != 0) |
127 | { | |
ad5bb451 | 128 | post_log ("Error at srawi test %d !\n", i); |
53677ef1 | 129 | } |
ad5bb451 WD |
130 | } |
131 | ||
132 | if (ret == 0) | |
133 | { | |
53677ef1 | 134 | cpu_post_exec_21 (codecr, & cr, & res, test->op1); |
ad5bb451 | 135 | |
53677ef1 | 136 | ret = res == test->res && |
ad5bb451 WD |
137 | (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; |
138 | ||
53677ef1 WD |
139 | if (ret != 0) |
140 | { | |
ad5bb451 WD |
141 | post_log ("Error at srawi test %d !\n", i); |
142 | } | |
143 | } | |
144 | } | |
145 | } | |
146 | ||
147 | if (flag) | |
53677ef1 | 148 | enable_interrupts(); |
ad5bb451 WD |
149 | |
150 | return ret; | |
151 | } | |
152 | ||
153 | #endif |