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ad5bb451 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | ||
26 | /* | |
27 | * CPU test | |
28 | * Shift instructions: srawi | |
29 | * | |
30 | * The test contains a pre-built table of instructions, operands and | |
31 | * expected results. For each table entry, the test will cyclically use | |
32 | * different sets of operand registers and result registers. | |
33 | */ | |
34 | ||
35 | #ifdef CONFIG_POST | |
36 | ||
37 | #include <post.h> | |
38 | #include "cpu_asm.h" | |
39 | ||
40 | #if CONFIG_POST & CFG_POST_CPU | |
41 | ||
42 | extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); | |
43 | extern ulong cpu_post_makecr (long v); | |
44 | ||
45 | static struct cpu_post_srawi_s | |
46 | { | |
47 | ulong cmd; | |
48 | ulong op1; | |
49 | uchar op2; | |
50 | ulong res; | |
51 | } cpu_post_srawi_table[] = | |
52 | { | |
53 | { | |
54 | OP_SRAWI, | |
55 | 0x8000, | |
56 | 3, | |
57 | 0x1000 | |
58 | }, | |
59 | { | |
60 | OP_SRAWI, | |
61 | 0x80000000, | |
62 | 3, | |
63 | 0xf0000000 | |
64 | }, | |
65 | }; | |
66 | static unsigned int cpu_post_srawi_size = | |
67 | sizeof (cpu_post_srawi_table) / sizeof (struct cpu_post_srawi_s); | |
68 | ||
69 | int cpu_post_test_srawi (void) | |
70 | { | |
71 | int ret = 0; | |
72 | unsigned int i, reg; | |
73 | int flag = disable_interrupts(); | |
74 | ||
75 | for (i = 0; i < cpu_post_srawi_size && ret == 0; i++) | |
76 | { | |
77 | struct cpu_post_srawi_s *test = cpu_post_srawi_table + i; | |
78 | ||
79 | for (reg = 0; reg < 32 && ret == 0; reg++) | |
80 | { | |
81 | unsigned int reg0 = (reg + 0) % 32; | |
82 | unsigned int reg1 = (reg + 1) % 32; | |
83 | unsigned int stk = reg < 16 ? 31 : 15; | |
84 | unsigned long code[] = | |
85 | { | |
86 | ASM_STW(stk, 1, -4), | |
87 | ASM_ADDI(stk, 1, -16), | |
88 | ASM_STW(3, stk, 8), | |
89 | ASM_STW(reg0, stk, 4), | |
90 | ASM_STW(reg1, stk, 0), | |
91 | ASM_LWZ(reg0, stk, 8), | |
92 | ASM_11S(test->cmd, reg1, reg0, test->op2), | |
93 | ASM_STW(reg1, stk, 8), | |
94 | ASM_LWZ(reg1, stk, 0), | |
95 | ASM_LWZ(reg0, stk, 4), | |
96 | ASM_LWZ(3, stk, 8), | |
97 | ASM_ADDI(1, stk, 16), | |
98 | ASM_LWZ(stk, 1, -4), | |
99 | ASM_BLR, | |
100 | }; | |
101 | unsigned long codecr[] = | |
102 | { | |
103 | ASM_STW(stk, 1, -4), | |
104 | ASM_ADDI(stk, 1, -16), | |
105 | ASM_STW(3, stk, 8), | |
106 | ASM_STW(reg0, stk, 4), | |
107 | ASM_STW(reg1, stk, 0), | |
108 | ASM_LWZ(reg0, stk, 8), | |
109 | ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, | |
110 | ASM_STW(reg1, stk, 8), | |
111 | ASM_LWZ(reg1, stk, 0), | |
112 | ASM_LWZ(reg0, stk, 4), | |
113 | ASM_LWZ(3, stk, 8), | |
114 | ASM_ADDI(1, stk, 16), | |
115 | ASM_LWZ(stk, 1, -4), | |
116 | ASM_BLR, | |
117 | }; | |
118 | ulong res; | |
119 | ulong cr; | |
120 | ||
121 | if (ret == 0) | |
122 | { | |
123 | cr = 0; | |
124 | cpu_post_exec_21 (code, & cr, & res, test->op1); | |
125 | ||
126 | ret = res == test->res && cr == 0 ? 0 : -1; | |
127 | ||
128 | if (ret != 0) | |
129 | { | |
130 | post_log ("Error at srawi test %d !\n", i); | |
131 | } | |
132 | } | |
133 | ||
134 | if (ret == 0) | |
135 | { | |
136 | cpu_post_exec_21 (codecr, & cr, & res, test->op1); | |
137 | ||
138 | ret = res == test->res && | |
139 | (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; | |
140 | ||
141 | if (ret != 0) | |
142 | { | |
143 | post_log ("Error at srawi test %d !\n", i); | |
144 | } | |
145 | } | |
146 | } | |
147 | } | |
148 | ||
149 | if (flag) | |
150 | enable_interrupts(); | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
155 | #endif | |
156 | #endif |