projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 0849cfac GKH |
1 | From 3b8803494a0612acdeee714cb72aa142b1e05ce5 Mon Sep 17 00:00:00 2001 |
| 2 | From: Mika Westerberg <mika.westerberg@linux.intel.com> | |
| 3 | Date: Thu, 11 May 2023 15:19:05 +0300 | |
| 4 | Subject: PCI/DPC: Quirk PIO log size for Intel Ice Lake Root Ports | |
| 5 | ||
| 6 | From: Mika Westerberg <mika.westerberg@linux.intel.com> | |
| 7 | ||
| 8 | commit 3b8803494a0612acdeee714cb72aa142b1e05ce5 upstream. | |
| 9 | ||
| 10 | Commit 5459c0b70467 ("PCI/DPC: Quirk PIO log size for certain Intel Root | |
| 11 | Ports") added quirks for Tiger and Alder Lake Root Ports but missed that | |
| 12 | the same issue exists also in the previous generation, Ice Lake. | |
| 13 | ||
| 14 | Apply the quirk for Ice Lake Root Ports as well. This prevents kernel | |
| 15 | complaints like: | |
| 16 | ||
| 17 | DPC: RP PIO log size 0 is invalid | |
| 18 | ||
| 19 | and also enables the DPC driver to dump the RP PIO Log registers when DPC | |
| 20 | is triggered. | |
| 21 | ||
| 22 | [bhelgaas: add dmesg warning and RP PIO Log dump info] | |
| 23 | Closes: https://bugzilla.kernel.org/show_bug.cgi?id=209943 | |
| 24 | Link: https://lore.kernel.org/r/20230511121905.73949-1-mika.westerberg@linux.intel.com | |
| 25 | Reported-by: Mark Blakeney <mark.blakeney@bullet-systems.net> | |
| 26 | Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> | |
| 27 | Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | |
| 28 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 29 | --- | |
| 30 | drivers/pci/quirks.c | 9 +++++++-- | |
| 31 | 1 file changed, 7 insertions(+), 2 deletions(-) | |
| 32 | ||
| 33 | --- a/drivers/pci/quirks.c | |
| 34 | +++ b/drivers/pci/quirks.c | |
| 35 | @@ -5912,8 +5912,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I | |
| 36 | ||
| 37 | #ifdef CONFIG_PCIE_DPC | |
| 38 | /* | |
| 39 | - * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC | |
| 40 | - * RP PIO Log Size of the integrated Thunderbolt PCIe Root Ports. | |
| 41 | + * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears | |
| 42 | + * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root | |
| 43 | + * Ports. | |
| 44 | */ | |
| 45 | static void dpc_log_size(struct pci_dev *dev) | |
| 46 | { | |
| 47 | @@ -5936,6 +5937,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I | |
| 48 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); | |
| 49 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); | |
| 50 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); | |
| 51 | +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); | |
| 52 | +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); | |
| 53 | +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); | |
| 54 | +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); | |
| 55 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); | |
| 56 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); | |
| 57 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); |