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fe504f71 SL |
1 | From e6784e3c217d3500c23af4bf81d540b488178240 Mon Sep 17 00:00:00 2001 |
2 | From: Sasha Levin <sashal@kernel.org> | |
3 | Date: Mon, 25 Mar 2024 13:01:45 +0530 | |
4 | Subject: perf/x86/amd/lbr: Use freeze based on availability | |
5 | ||
6 | From: Sandipan Das <sandipan.das@amd.com> | |
7 | ||
8 | [ Upstream commit 598c2fafc06fe5c56a1a415fb7b544b31453d637 ] | |
9 | ||
10 | Currently, the LBR code assumes that LBR Freeze is supported on all processors | |
11 | when X86_FEATURE_AMD_LBR_V2 is available i.e. CPUID leaf 0x80000022[EAX] | |
12 | bit 1 is set. This is incorrect as the availability of the feature is | |
13 | additionally dependent on CPUID leaf 0x80000022[EAX] bit 2 being set, | |
14 | which may not be set for all Zen 4 processors. | |
15 | ||
16 | Define a new feature bit for LBR and PMC freeze and set the freeze enable bit | |
17 | (FLBRI) in DebugCtl (MSR 0x1d9) conditionally. | |
18 | ||
19 | It should still be possible to use LBR without freeze for profile-guided | |
20 | optimization of user programs by using an user-only branch filter during | |
21 | profiling. When the user-only filter is enabled, branches are no longer | |
22 | recorded after the transition to CPL 0 upon PMI arrival. When branch | |
23 | entries are read in the PMI handler, the branch stack does not change. | |
24 | ||
25 | E.g. | |
26 | ||
27 | $ perf record -j any,u -e ex_ret_brn_tkn ./workload | |
28 | ||
29 | Since the feature bit is visible under flags in /proc/cpuinfo, it can be | |
30 | used to determine the feasibility of use-cases which require LBR Freeze | |
31 | to be supported by the hardware such as profile-guided optimization of | |
32 | kernels. | |
33 | ||
34 | Fixes: ca5b7c0d9621 ("perf/x86/amd/lbr: Add LbrExtV2 branch record support") | |
35 | Signed-off-by: Sandipan Das <sandipan.das@amd.com> | |
36 | Signed-off-by: Ingo Molnar <mingo@kernel.org> | |
37 | Link: https://lore.kernel.org/r/69a453c97cfd11c6f2584b19f937fe6df741510f.1711091584.git.sandipan.das@amd.com | |
38 | Signed-off-by: Sasha Levin <sashal@kernel.org> | |
39 | --- | |
40 | arch/x86/events/amd/core.c | 4 ++-- | |
41 | arch/x86/events/amd/lbr.c | 16 ++++++++++------ | |
42 | arch/x86/include/asm/cpufeatures.h | 8 ++++++++ | |
43 | arch/x86/kernel/cpu/scattered.c | 1 + | |
44 | 4 files changed, 21 insertions(+), 8 deletions(-) | |
45 | ||
46 | diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c | |
47 | index fd091b9dd7067..3ac069a4559b0 100644 | |
48 | --- a/arch/x86/events/amd/core.c | |
49 | +++ b/arch/x86/events/amd/core.c | |
50 | @@ -904,8 +904,8 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs) | |
51 | if (!status) | |
52 | goto done; | |
53 | ||
54 | - /* Read branch records before unfreezing */ | |
55 | - if (status & GLOBAL_STATUS_LBRS_FROZEN) { | |
56 | + /* Read branch records */ | |
57 | + if (x86_pmu.lbr_nr) { | |
58 | amd_pmu_lbr_read(); | |
59 | status &= ~GLOBAL_STATUS_LBRS_FROZEN; | |
60 | } | |
61 | diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c | |
62 | index 38a75216c12cf..b8fe74e8e0a60 100644 | |
63 | --- a/arch/x86/events/amd/lbr.c | |
64 | +++ b/arch/x86/events/amd/lbr.c | |
65 | @@ -400,10 +400,12 @@ void amd_pmu_lbr_enable_all(void) | |
66 | wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select); | |
67 | } | |
68 | ||
69 | - rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl); | |
70 | - rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); | |
71 | + if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) { | |
72 | + rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl); | |
73 | + wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); | |
74 | + } | |
75 | ||
76 | - wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); | |
77 | + rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); | |
78 | wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN); | |
79 | } | |
80 | ||
81 | @@ -416,10 +418,12 @@ void amd_pmu_lbr_disable_all(void) | |
82 | return; | |
83 | ||
84 | rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); | |
85 | - rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl); | |
86 | - | |
87 | wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); | |
88 | - wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); | |
89 | + | |
90 | + if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) { | |
91 | + rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl); | |
92 | + wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); | |
93 | + } | |
94 | } | |
95 | ||
96 | __init int amd_pmu_lbr_init(void) | |
97 | diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h | |
98 | index 09cca23f020eb..1280daa729757 100644 | |
99 | --- a/arch/x86/include/asm/cpufeatures.h | |
100 | +++ b/arch/x86/include/asm/cpufeatures.h | |
101 | @@ -432,6 +432,14 @@ | |
102 | #define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */ | |
103 | #define X86_FEATURE_SRSO_NO (20*32+29) /* "" CPU is not affected by SRSO */ | |
104 | ||
105 | +/* | |
106 | + * Extended auxiliary flags: Linux defined - for features scattered in various | |
107 | + * CPUID levels like 0x80000022, etc. | |
108 | + * | |
109 | + * Reuse free bits when adding new feature flags! | |
110 | + */ | |
111 | +#define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* AMD LBR and PMC Freeze */ | |
112 | + | |
113 | /* | |
114 | * BUG word(s) | |
115 | */ | |
116 | diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c | |
117 | index fc01f81f6e2a3..94e0a42528dcb 100644 | |
118 | --- a/arch/x86/kernel/cpu/scattered.c | |
119 | +++ b/arch/x86/kernel/cpu/scattered.c | |
120 | @@ -46,6 +46,7 @@ static const struct cpuid_bit cpuid_bits[] = { | |
121 | { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, | |
122 | { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, | |
123 | { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, | |
124 | + { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, | |
125 | { 0, 0, 0, 0, 0 } | |
126 | }; | |
127 | ||
128 | -- | |
129 | 2.43.0 | |
130 |