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ac07e81b GKH |
1 | From vegard.nossum@gmail.com Thu Jun 19 07:34:37 2008 |
2 | From: Thomas Gleixner <tglx@linutronix.de> | |
3 | Date: Thu, 19 Jun 2008 16:34:26 +0200 | |
4 | Subject: x86: disable mwait for AMD family 10H/11H CPUs | |
5 | To: stable@kernel.org | |
6 | Cc: Greg KH <greg@kroah.com>, Ingo Molnar <mingo@elte.hu>, Thomas Gleixner <tglx@linutronix.de>, x86@kernel.org, linux-kernel@vger.kernel.org | |
7 | Message-ID: <20080619143426.GB3243@damson.getinternet.no> | |
8 | Content-Disposition: inline | |
9 | ||
10 | ||
11 | From: Thomas Gleixner <tglx@linutronix.de> | |
12 | ||
13 | back-ported from upstream commit e9623b35599fcdbc00c16535cbefbb4d5578f4ab by Vegard Nossum | |
14 | ||
15 | ||
16 | The previous revert of 0c07ee38c9d4eb081758f5ad14bbffa7197e1aec left | |
17 | out the mwait disable condition for AMD family 10H/11H CPUs. | |
18 | ||
19 | Andreas Herrman said: | |
20 | ||
21 | It depends on the CPU. For AMD CPUs that support MWAIT this is wrong. | |
22 | Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings then | |
23 | depend on a clock divisor and current Pstate of the core. | |
24 | ||
25 | If all cores of a processor are in halt state (C1) the processor can | |
26 | enter the C1E (C1 enhanced) state. If mwait is used this will never | |
27 | happen. | |
28 | ||
29 | Thus HLT saves more power than MWAIT here. | |
30 | ||
31 | It might be best to switch off the mwait flag for these AMD CPU | |
32 | families like it was introduced with commit | |
33 | f039b754714a422959027cb18bb33760eb8153f0 (x86: Don't use MWAIT on AMD | |
34 | Family 10) | |
35 | ||
36 | Re-add the AMD families 10H/11H check and disable the mwait usage for | |
37 | those. | |
38 | ||
39 | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> | |
40 | Signed-off-by: Vegard Nossum <vegard.nossum@gmail.com> | |
41 | Cc: Ingo Molnar <mingo@elte.hu> | |
42 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
43 | ||
44 | --- | |
45 | arch/x86/kernel/process_32.c | 29 ++++++++++++++++++++++++++++- | |
46 | arch/x86/kernel/process_64.c | 29 ++++++++++++++++++++++++++++- | |
47 | 2 files changed, 56 insertions(+), 2 deletions(-) | |
48 | ||
49 | --- a/arch/x86/kernel/process_32.c | |
50 | +++ b/arch/x86/kernel/process_32.c | |
51 | @@ -259,6 +259,33 @@ static void mwait_idle(void) | |
52 | mwait_idle_with_hints(0, 0); | |
53 | } | |
54 | ||
55 | +/* | |
56 | + * mwait selection logic: | |
57 | + * | |
58 | + * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
59 | + * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
60 | + * then depend on a clock divisor and current Pstate of the core. If | |
61 | + * all cores of a processor are in halt state (C1) the processor can | |
62 | + * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
63 | + * happen. | |
64 | + * | |
65 | + * idle=mwait overrides this decision and forces the usage of mwait. | |
66 | + */ | |
67 | +static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) | |
68 | +{ | |
69 | + if (force_mwait) | |
70 | + return 1; | |
71 | + | |
72 | + if (c->x86_vendor == X86_VENDOR_AMD) { | |
73 | + switch(c->x86) { | |
74 | + case 0x10: | |
75 | + case 0x11: | |
76 | + return 0; | |
77 | + } | |
78 | + } | |
79 | + return 1; | |
80 | +} | |
81 | + | |
82 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) | |
83 | { | |
84 | static int selected; | |
85 | @@ -271,7 +298,7 @@ void __cpuinit select_idle_routine(const | |
86 | " performance may degrade.\n"); | |
87 | } | |
88 | #endif | |
89 | - if (cpu_has(c, X86_FEATURE_MWAIT)) { | |
90 | + if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { | |
91 | /* | |
92 | * Skip, if setup has overridden idle. | |
93 | * One CPU supports mwait => All CPUs supports mwait | |
94 | --- a/arch/x86/kernel/process_64.c | |
95 | +++ b/arch/x86/kernel/process_64.c | |
96 | @@ -254,6 +254,33 @@ static void mwait_idle(void) | |
97 | } | |
98 | } | |
99 | ||
100 | +/* | |
101 | + * mwait selection logic: | |
102 | + * | |
103 | + * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
104 | + * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
105 | + * then depend on a clock divisor and current Pstate of the core. If | |
106 | + * all cores of a processor are in halt state (C1) the processor can | |
107 | + * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
108 | + * happen. | |
109 | + * | |
110 | + * idle=mwait overrides this decision and forces the usage of mwait. | |
111 | + */ | |
112 | +static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) | |
113 | +{ | |
114 | + if (force_mwait) | |
115 | + return 1; | |
116 | + | |
117 | + if (c->x86_vendor == X86_VENDOR_AMD) { | |
118 | + switch(c->x86) { | |
119 | + case 0x10: | |
120 | + case 0x11: | |
121 | + return 0; | |
122 | + } | |
123 | + } | |
124 | + return 1; | |
125 | +} | |
126 | + | |
127 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) | |
128 | { | |
129 | static int selected; | |
130 | @@ -266,7 +293,7 @@ void __cpuinit select_idle_routine(const | |
131 | " performance may degrade.\n"); | |
132 | } | |
133 | #endif | |
134 | - if (cpu_has(c, X86_FEATURE_MWAIT)) { | |
135 | + if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { | |
136 | /* | |
137 | * Skip, if setup has overridden idle. | |
138 | * One CPU supports mwait => All CPUs supports mwait |