projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 0f118bc7 NC |
1 | 2016-07-21 Nick Clifton <nickc@redhat.com> |
| 2 | ||
| 0c66ea4c | 3 | * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
| 0f118bc7 | 4 | |
| c7be4414 JW |
5 | 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
| 6 | ||
| 7 | * cpustate.h: Include config.h. | |
| 8 | (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code | |
| 9 | use anonymous structs to align members. | |
| 10 | * simulator.c (aarch64_step): Use sim_core_read_buffer and | |
| 11 | endian_le2h_4 to read instruction from pc. | |
| 12 | ||
| fd7ed446 NC |
13 | 2016-05-06 Nick Clifton <nickc@redhat.com> |
| 14 | ||
| 15 | * simulator.c (do_FMLA_by_element): New function. | |
| 16 | (do_vec_op2): Call it. | |
| 17 | ||
| 2cdad34c NC |
18 | 2016-04-27 Nick Clifton <nickc@redhat.com> |
| 19 | ||
| 20 | * simulator.c: Add TRACE_DECODE statements to all emulation | |
| 21 | functions. | |
| 22 | ||
| 7517e550 NC |
23 | 2016-03-30 Nick Clifton <nickc@redhat.com> |
| 24 | ||
| 25 | * cpustate.c (aarch64_set_reg_s32): New function. | |
| 26 | (aarch64_set_reg_u32): New function. | |
| 27 | (aarch64_get_FP_half): Place half precision value into the correct | |
| 28 | slot of the union. | |
| 29 | (aarch64_set_FP_half): Likewise. | |
| 30 | * cpustate.h: Add prototypes for aarch64_set_reg_s32 and | |
| 31 | aarch64_set_reg_u32. | |
| 32 | * memory.c (FETCH_FUNC): Cast the read value to the access type | |
| 33 | before converting it to the return type. Rename to FETCH_FUNC64. | |
| 34 | (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit | |
| 35 | accesses. Use for 32-bit memory access functions. | |
| 36 | * simulator.c (ldrsb_wb): Use sign extension not zero extension. | |
| 37 | (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. | |
| 38 | (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. | |
| 39 | (ldrsh_scale_ext, ldrsw_abs): Likewise. | |
| 40 | (ldrh32_abs): Store 32 bit value not 64-bits. | |
| 41 | (ldrh32_wb, ldrh32_scale_ext): Likewise. | |
| 42 | (do_vec_MOV_immediate): Fix computation of val. | |
| 43 | (do_vec_MVNI): Likewise. | |
| 44 | (DO_VEC_WIDENING_MUL): New macro. | |
| 45 | (do_vec_mull): Use new macro. | |
| 46 | (do_vec_mul): Use new macro. | |
| 47 | (do_vec_MLA): Read values before writing. | |
| 48 | (do_vec_xtl): Likewise. | |
| 49 | (do_vec_SSHL): Select correct shift value. | |
| 50 | (do_vec_USHL): Likewise. | |
| 51 | (do_scalar_UCVTF): New function. | |
| 52 | (do_scalar_vec): Call new function. | |
| 53 | (store_pair_u64): Treat reads of SP as reads of XZR. | |
| 54 | ||
| ef0d8ffc NC |
55 | 2016-03-29 Nick Clifton <nickc@redhat.com> |
| 56 | ||
| 57 | * cpustate.c: Remove space after asterisk in function parameters. | |
| 58 | * decode.h (greg): Delete unused function. | |
| 59 | (vreg, shift, extension, scaling, writeback, condcode): Likewise. | |
| 60 | * simulator.c: Use INSTR macro in more places. | |
| 61 | (HALT_NYI): Use sim_io_eprintf in place of fprintf. | |
| 62 | Remove extraneous whitespace. | |
| 63 | ||
| 5ab6d79e NC |
64 | 2016-03-23 Nick Clifton <nickc@redhat.com> |
| 65 | ||
| 66 | * cpustate.c (aarch64_get_FP_half): New function. Read a vector | |
| 67 | register as a half precision floating point number. | |
| 68 | (aarch64_set_FP_half): New function. Similar, but for setting | |
| 69 | a half precision register. | |
| 70 | (aarch64_get_thread_id): New function. Returns the value of the | |
| 71 | CPU's TPIDR register. | |
| 72 | (aarch64_get_FPCR): New function. Returns the value of the CPU's | |
| 73 | floating point control register. | |
| 74 | (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR | |
| 75 | register. | |
| 76 | * cpustate.h: Add prototypes for new functions. | |
| 77 | * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. | |
| 78 | * memory.c: Use unaligned core access functions for all memory | |
| 79 | reads and writes. | |
| 80 | * simulator.c (HALT_NYI): Generate an error message if tracing | |
| 81 | will not tell the user why the simulator is halting. | |
| 82 | (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. | |
| 83 | (INSTR): New time-saver macro. | |
| 84 | (fldrb_abs): New function. Loads an 8-bit value using a scaled | |
| 85 | offset. | |
| 86 | (fldrh_abs): New function. Likewise for 16-bit values. | |
| 87 | (do_vec_SSHL): Allow for negative shift values. | |
| 88 | (do_vec_USHL): Likewise. | |
| 89 | (do_vec_SHL): Correct computation of shift amount. | |
| 90 | (do_vec_SSHR_USHR): Correct decision of signed vs unsigned | |
| 91 | shifts and computation of shift value. | |
| 92 | (clz): New function. Counts leading zero bits. | |
| 93 | (do_vec_CLZ): New function. Implements CLZ (vector). | |
| 94 | (do_vec_MOV_element): Call do_vec_CLZ. | |
| 95 | (dexSimpleFPCondCompare): Implement. | |
| 96 | (do_FCVT_half_to_single): New function. Implements one of the | |
| 97 | FCVT operations. | |
| 98 | (do_FCVT_half_to_double): New function. Likewise. | |
| 99 | (do_FCVT_single_to_half): New function. Likewise. | |
| 100 | (do_FCVT_double_to_half): New function. Likewise. | |
| 101 | (dexSimpleFPDataProc1Source): Call new FCVT functions. | |
| 102 | (do_scalar_SHL): Handle negative shifts. | |
| 103 | (do_scalar_shift): Handle SSHR. | |
| 104 | (do_scalar_USHL): New function. | |
| 105 | (do_double_add): Simplify to just performing a double precision | |
| 106 | add operation. Move remaining code into... | |
| 107 | (do_scalar_vec): ... New function. | |
| 108 | (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs | |
| 109 | functions. | |
| 110 | (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR | |
| 111 | registers. | |
| 112 | (system_set): New function. | |
| 113 | (do_MSR_immediate): New function. Stub for now. | |
| 114 | (do_MSR_reg): New function. Likewise. Partially implements MSR | |
| 115 | instruction. | |
| 116 | (do_SYS): New function. Stub for now, | |
| 117 | (dexSystem): Call new functions. | |
| 118 | ||
| e101a78b NC |
119 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
| 120 | ||
| 121 | * cpustate.c: Remove spurious spaces from TRACE strings. | |
| 122 | Print hex equivalents of floats and doubles. | |
| 123 | Check element number against array size when accessing vector | |
| 124 | registers. | |
| 4c0ca98e NC |
125 | (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
| 126 | element index. | |
| 127 | (SET_VEC_ELEMENT): Likewise. | |
| 87bba7a5 | 128 | (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
| 4c0ca98e | 129 | |
| e101a78b NC |
130 | * memory.c: Trace memory reads when --trace-memory is enabled. |
| 131 | Remove float and double load and store functions. | |
| 132 | * memory.h (aarch64_get_mem_float): Delete prototype. | |
| 133 | (aarch64_get_mem_double): Likewise. | |
| 134 | (aarch64_set_mem_float): Likewise. | |
| 135 | (aarch64_set_mem_double): Likewise. | |
| 136 | * simulator (IS_SET): Always return either 0 or 1. | |
| 137 | (IS_CLEAR): Likewise. | |
| 138 | (fldrs_pcrel): Load and store floats using 32-bit memory accesses | |
| 139 | and doubles using 64-bit memory accesses. | |
| 140 | (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. | |
| 141 | (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. | |
| 142 | (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. | |
| 143 | (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. | |
| 144 | (store_pair_double, load_pair_float, load_pair_double): Likewise. | |
| 145 | (do_vec_MUL_by_element): New function. | |
| 146 | (do_vec_op2): Call do_vec_MUL_by_element. | |
| 147 | (do_scalar_NEG): New function. | |
| 148 | (do_double_add): Call do_scalar_NEG. | |
| 149 | ||
| 57aa1742 NC |
150 | 2016-03-03 Nick Clifton <nickc@redhat.com> |
| 151 | ||
| 152 | * simulator.c (set_flags_for_sub32): Correct type of signbit. | |
| 153 | (CondCompare): Swap interpretation of bit 30. | |
| 154 | (DO_ADDP): Delete macro. | |
| 155 | (do_vec_ADDP): Copy source registers before starting to update | |
| 156 | destination register. | |
| 157 | (do_vec_FADDP): Likewise. | |
| 158 | (do_vec_load_store): Fix computation of sizeof_operation. | |
| 159 | (rbit64): Fix type of constant. | |
| 160 | (aarch64_step): When displaying insn value, display all 32 bits. | |
| 161 | ||
| ce39bd38 MF |
162 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 163 | ||
| 164 | * config.in, configure: Regenerate. | |
| 165 | ||
| e19418e0 MF |
166 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 167 | ||
| 168 | * configure: Regenerate. | |
| 169 | ||
| 16f7876d MF |
170 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 171 | ||
| 172 | * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. | |
| 173 | * configure: Regenerate. | |
| 174 | ||
| 99d8e879 MF |
175 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 176 | ||
| 177 | * configure: Regenerate. | |
| 35656e95 MF |
178 | |
| 179 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> | |
| 180 | ||
| 181 | * configure: Regenerate. | |
| 99d8e879 | 182 | |
| 347fe5bb MF |
183 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 184 | ||
| 185 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
| 186 | * configure: Regenerate. | |
| 187 | ||
| 22be3fbe MF |
188 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 189 | ||
| 190 | * configure: Regenerate. | |
| 191 | ||
| 0dc73ef7 MF |
192 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 193 | ||
| 194 | * configure: Regenerate. | |
| 195 | ||
| 936df756 MF |
196 | 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
| 197 | ||
| 198 | * config.in, configure: Regenerate. | |
| 199 | ||
| 2e3d4f4d MF |
200 | 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
| 201 | ||
| 202 | * interp.c (sim_create_inferior): Mark argv and env const. | |
| 203 | (sim_open): Mark argv const. | |
| 204 | ||
| 1a846c62 MF |
205 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
| 206 | ||
| 207 | * interp.c: Delete dis-asm.h include. | |
| 208 | (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. | |
| 209 | (sim_create_inferior): Delete disassemble init logic. | |
| 210 | (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. | |
| 211 | (sim_open): Delete sim_add_option_table call. | |
| 212 | * memory.c (mem_error): Delete disas check. | |
| 213 | * simulator.c: Delete dis-asm.h include. | |
| 214 | (disas): Delete. | |
| 215 | (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. | |
| 216 | (HALT_NYI): Likewise. | |
| 217 | (handle_halt): Delete disas call. | |
| 218 | (aarch64_step): Replace disas logic with TRACE_DISASM. | |
| 219 | * simulator.h: Delete dis-asm.h include. | |
| 220 | (aarch64_print_insn): Delete. | |
| 221 | ||
| bc273e17 MF |
222 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| 223 | ||
| 224 | * simulator.c (MAX, MIN): Delete. | |
| 225 | (do_vec_maxv): Change MAX to max and MIN to min. | |
| 226 | (do_vec_fminmaxV): Likewise. | |
| 227 | ||
| ac8eefeb TG |
228 | 2016-01-04 Tristan Gingold <gingold@adacore.com> |
| 229 | ||
| 230 | * simulator.c: Remove syscall.h include. | |
| 231 | ||
| 9bbf6f91 MF |
232 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| 233 | ||
| 234 | * configure: Regenerate. | |
| 235 | ||
| 0cb8d851 MF |
236 | 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
| 237 | ||
| 238 | * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. | |
| 239 | * configure: Regenerate. | |
| 240 | ||
| 1ac72f06 MF |
241 | 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
| 242 | ||
| 243 | * configure: Regenerate. | |
| 244 | ||
| 5d015275 MF |
245 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| 246 | ||
| 247 | * interp.c (sim_dis_read): Change private_data to application_data. | |
| 248 | (sim_create_inferior): Likewise. | |
| 249 | ||
| 5e744ef8 MF |
250 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| 251 | ||
| 252 | * Makefile.in (SIM_OBJS): Delete sim-hload.o. | |
| 253 | ||
| 1b393626 MF |
254 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| 255 | ||
| 256 | * config.in, configure: Regenerate. | |
| 257 | ||
| 0e967299 MF |
258 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| 259 | ||
| 260 | * interp.c (sim_create_inferior): Update comment and argv check. | |
| 261 | ||
| f66affe9 MF |
262 | 2015-12-14 Nick Clifton <nickc@redhat.com> |
| 263 | ||
| 264 | * simulator.c (system_get): New function. Provides read | |
| 265 | access to the dczid system register. | |
| 266 | (do_mrs): New function - implements the MRS instruction. | |
| 267 | (dexSystem): Call do_mrs for the MRS instruction. Halt on | |
| 268 | unimplemented system instructions. | |
| 269 | ||
| 270 | 2015-11-24 Nick Clifton <nickc@redhat.com> | |
| 271 | ||
| 272 | * configure.ac: New configure template. | |
| 273 | * aclocal.m4: Generate. | |
| 274 | * config.in: Generate. | |
| 275 | * configure: Generate. | |
| 276 | * cpustate.c: New file - functions for accessing AArch64 registers. | |
| 277 | * cpustate.h: New header. | |
| 278 | * decode.h: New header. | |
| 279 | * interp.c: New file - interface between GDB and simulator. | |
| 280 | * Makefile.in: New makefile template. | |
| 281 | * memory.c: New file - functions for simulating aarch64 memory | |
| 282 | accesses. | |
| 283 | * memory.h: New header. | |
| 284 | * sim-main.h: New header. | |
| 285 | * simulator.c: New file - aarch64 simulator functions. | |
| 286 | * simulator.h: New header. |