[thirdparty/binutils-gdb.git] / sim / arm / armemu.h

/*  armemu.h -- ARMulator emulation macros:  ARM6 Instruction Emulator.
    Copyright (C) 1994 Advanced RISC Machines Ltd.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */

extern ARMword isize;

/***************************************************************************\
*                           Condition code values                           *
\***************************************************************************/

#define EQ 0
#define NE 1
#define CS 2
#define CC 3
#define MI 4
#define PL 5
#define VS 6
#define VC 7
#define HI 8
#define LS 9
#define GE 10
#define LT 11
#define GT 12
#define LE 13
#define AL 14
#define NV 15

/***************************************************************************\
*                               Shift Opcodes                               *
\***************************************************************************/

#define LSL 0
#define LSR 1
#define ASR 2
#define ROR 3

/***************************************************************************\
*               Macros to twiddle the status flags and mode                 *
\***************************************************************************/

#define NBIT ((unsigned)1L << 31)
#define ZBIT (1L << 30)
#define CBIT (1L << 29)
#define VBIT (1L << 28)
#define IBIT (1L << 7)
#define FBIT (1L << 6)
#define IFBITS (3L << 6)
#define R15IBIT (1L << 27)
#define R15FBIT (1L << 26)
#define R15IFBITS (3L << 26)

#define POS(i) ( (~(i)) >> 31 )
#define NEG(i) ( (i) >> 31 )

#ifdef MODET			/* Thumb support */
/* ??? This bit is actually in the low order bit of the PC in the hardware.
   It isn't clear if the simulator needs to model that or not.  */
#define TBIT (1L << 5)
#define TFLAG state->TFlag
#define SETT state->TFlag = 1
#define CLEART state->TFlag = 0
#define ASSIGNT(res) state->TFlag = res
#endif

#define NFLAG state->NFlag
#define SETN state->NFlag = 1
#define CLEARN state->NFlag = 0
#define ASSIGNN(res) state->NFlag = res

#define ZFLAG state->ZFlag
#define SETZ state->ZFlag = 1
#define CLEARZ state->ZFlag = 0
#define ASSIGNZ(res) state->ZFlag = res

#define CFLAG state->CFlag
#define SETC state->CFlag = 1
#define CLEARC state->CFlag = 0
#define ASSIGNC(res) state->CFlag = res

#define VFLAG state->VFlag
#define SETV state->VFlag = 1
#define CLEARV state->VFlag = 0
#define ASSIGNV(res) state->VFlag = res


#define IFLAG (state->IFFlags >> 1)
#define FFLAG (state->IFFlags & 1)
#define IFFLAGS state->IFFlags
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;

#define PSR_FBITS (0xff000000L)
#define PSR_SBITS (0x00ff0000L)
#define PSR_XBITS (0x0000ff00L)
#define PSR_CBITS (0x000000ffL)

#define CCBITS (0xf0000000L)
#define INTBITS (0xc0L)

#if defined MODET && defined MODE32
#define PCBITS (0xffffffffL)
#else
#define PCBITS (0xfffffffcL)
#endif

#define MODEBITS (0x1fL)
#define R15INTBITS (3L << 26)

#if defined MODET && defined MODE32
#define R15PCBITS (0x03ffffffL)
#else
#define R15PCBITS (0x03fffffcL)
#endif

#define R15PCMODEBITS (0x03ffffffL)
#define R15MODEBITS (0x3L)

#ifdef MODE32
#define PCMASK PCBITS
#define PCWRAP(pc) (pc)
#else
#define PCMASK R15PCBITS
#define PCWRAP(pc) ((pc) & R15PCBITS)
#endif

#define PC (state->Reg[15] & PCMASK)
#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
#define R15INT (state->Reg[15] & R15INTBITS)
#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
#define R15PC (state->Reg[15] & R15PCBITS)
#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
#define R15MODE (state->Reg[15] & R15MODEBITS)

#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28))
#define EINT (IFFLAGS << 6)
#define ER15INT (IFFLAGS << 26)
#define EMODE (state->Mode)

#ifdef MODET
#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
#else
#define CPSR (ECC | EINT | EMODE)
#endif

#ifdef MODE32
#define PATCHR15
#else
#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
#endif

#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
                        state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
                        ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
                        ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
                        ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
                        ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
                        } \
                     else { \
                        state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
                        ARMul_R15Altered (state) ; \
                        }
#define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)

#ifndef MODE32
#define VECTORS 0x20
#define LEGALADDR 0x03ffffff
#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
#endif

#define INTERNALABORT(address) if (address < VECTORS) \
                                  state->Aborted = ARMul_DataAbortV ; \
                               else \
                                  state->Aborted = ARMul_AddrExceptnV ;

#ifdef MODE32
#define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
#else
#define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
                     ARMul_Abort(state,ARMul_AddrExceptnV) ; \
                  else \
                     ARMul_Abort(state,ARMul_DataAbortV)
#endif
#define CPTAKEABORT if (!state->Aborted) \
                       ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
                    else if (state->Aborted == ARMul_AddrExceptnV) \
                       ARMul_Abort(state,ARMul_AddrExceptnV) ; \
                    else \
                       ARMul_Abort(state,ARMul_DataAbortV)


/***************************************************************************\
*               Different ways to start the next instruction                *
\***************************************************************************/

#define SEQ 0
#define NONSEQ 1
#define PCINCEDSEQ 2
#define PCINCEDNONSEQ 3
#define PRIMEPIPE 4
#define RESUME 8

#define NORMALCYCLE state->NextInstr = 0
#define BUSUSEDN state->NextInstr |= 1	/* the next fetch will be an N cycle */
#define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
                      state->NextInstr = (state->NextInstr & 0xff) | 2
#define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
                      state->NextInstr |= 3
#define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
              state->NextInstr |= 2
#define FLUSHPIPE state->NextInstr |= PRIMEPIPE

/***************************************************************************\
*                          Cycle based emulation                            *
\***************************************************************************/

#define OUTPUTCP(i,a,b)
#define NCYCLE
#define SCYCLE
#define ICYCLE
#define CCYCLE
#define NEXTCYCLE(c)

/***************************************************************************\
*                 States of the cycle based state machine                   *
\***************************************************************************/


/***************************************************************************\
*                 Macros to extract parts of instructions                   *
\***************************************************************************/

#define DESTReg (BITS(12,15))
#define LHSReg (BITS(16,19))
#define RHSReg (BITS(0,3))

#define DEST (state->Reg[DESTReg])

#ifdef MODE32
#ifdef MODET
#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
#else
#define LHS (state->Reg[LHSReg])
#endif
#else
#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
#endif

#define MULDESTReg (BITS(16,19))
#define MULLHSReg (BITS(0,3))
#define MULRHSReg (BITS(8,11))
#define MULACCReg (BITS(12,15))

#define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
#define DPSImmRHS temp = BITS(0,11) ; \
                  rhs = ARMul_ImmedTable[temp] ; \
                  if (temp > 255) /* there was a shift */ \
                     ASSIGNC(rhs >> 31) ;

#ifdef MODE32
#define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                  : GetDPRegRHS(state, instr))
#define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                   : GetDPSRegRHS(state, instr))
#else
#define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                  : GetDPRegRHS(state, instr))
#define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                   : GetDPSRegRHS(state, instr))
#endif

#define LSBase state->Reg[LHSReg]
#define LSImmRHS (BITS(0,11))

#ifdef MODE32
#define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                  : GetLSRegRHS(state, instr))
#else
#define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                  : GetLSRegRHS(state, instr))
#endif

#define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
                    (ARMword)ARMul_BitList[BITS(8,15)] )
#define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
                      (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))

#define SWAPSRC (state->Reg[RHSReg])

#define LSCOff (BITS(0,7) << 2)
#define CPNum BITS(8,11)

/***************************************************************************\
*                    Macro to rotate n right by b bits                      *
\***************************************************************************/

#define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))

/***************************************************************************\
*                 Macros to store results of instructions                   *
\***************************************************************************/

#define WRITEDEST(d) if (DESTReg==15) \
                        WriteR15(state, d) ; \
                     else \
                          DEST = d

#define WRITESDEST(d) if (DESTReg == 15) \
                         WriteSR15(state, d) ; \
                      else { \
                         DEST = d ; \
                         ARMul_NegZero(state, d) ; \
                         }

#define WRITEDESTB(d) if (DESTReg == 15) \
                        WriteR15Branch(state, d) ; \
                     else \
                          DEST = d

#define BYTETOBUS(data) ((data & 0xff) | \
                        ((data & 0xff) << 8) | \
                        ((data & 0xff) << 16) | \
                        ((data & 0xff) << 24))
#define BUSTOBYTE(address,data) \
           if (state->bigendSig) \
              temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
           else \
              temp = (data >> ((address & 3) << 3)) & 0xff

#define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
#define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
#define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
#define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)

#define POSBRANCH ((instr & 0x7fffff) << 2)
#define NEGBRANCH (0xfc000000 | ((instr & 0xffffff) << 2))

/***************************************************************************\
*                          Values for Emulate                               *
\***************************************************************************/

#define STOP            0	/* stop */
#define CHANGEMODE      1	/* change mode */
#define ONCE            2	/* execute just one interation */
#define RUN             3	/* continuous execution */

/***************************************************************************\
*                      Stuff that is shared across modes                    *
\***************************************************************************/

extern ARMword ARMul_Emulate26 (ARMul_State * state);
extern ARMword ARMul_Emulate32 (ARMul_State * state);
extern unsigned ARMul_MultTable[];	/* Number of I cycles for a mult */
extern ARMword ARMul_ImmedTable[];	/* immediate DP LHS values */
extern char ARMul_BitList[];	/* number of bits in a byte table */
extern void ARMul_Abort26 (ARMul_State * state, ARMword);
extern void ARMul_Abort32 (ARMul_State * state, ARMword);
extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
extern void ARMul_NegZero (ARMul_State * state, ARMword result);
extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
			    ARMword result);
extern int AddOverflow (ARMword a, ARMword b, ARMword result);
extern int SubOverflow (ARMword a, ARMword b, ARMword result);
extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
			       ARMword result);
extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
			    ARMword result);
extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
			       ARMword result);
extern void ARMul_CPSRAltered (ARMul_State * state);
extern void ARMul_R15Altered (ARMul_State * state);
extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
				 ARMword newmode);
extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
extern void ARMul_CDP (ARMul_State * state, ARMword instr);
extern unsigned IntPending (ARMul_State * state);
extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
			    ARMword data);
#define EVENTLISTSIZE 1024L

/* Thumb support: */

typedef enum
{
  t_undefined,			/* undefined Thumb instruction */
  t_decoded,			/* instruction decoded to ARM equivalent */
  t_branch			/* Thumb branch (already processed) */
}
tdstate;

extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
				  ARMword tinstr, ARMword * ainstr);

/***************************************************************************\
*                      Macros to scrutinize instructions                    *
\***************************************************************************/


#define UNDEF_Test
#define UNDEF_Shift
#define UNDEF_MSRPC
#define UNDEF_MRSPC
#define UNDEF_MULPCDest
#define UNDEF_MULDestEQOp1
#define UNDEF_LSRBPC
#define UNDEF_LSRBaseEQOffWb
#define UNDEF_LSRBaseEQDestWb
#define UNDEF_LSRPCBaseWb
#define UNDEF_LSRPCOffWb
#define UNDEF_LSMNoRegs
#define UNDEF_LSMPCBase
#define UNDEF_LSMUserBankWb
#define UNDEF_LSMBaseInListWb
#define UNDEF_SWPPC
#define UNDEF_CoProHS
#define UNDEF_MCRPC
#define UNDEF_LSCPCBaseWb
#define UNDEF_UndefNotBounced
#define UNDEF_ShortInt
#define UNDEF_IllegalMode
#define UNDEF_Prog32SigChange
#define UNDEF_Data32SigChange
Commit	Line	Data
c906108c SS	1	/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
	2	Copyright (C) 1994 Advanced RISC Machines Ltd.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	extern ARMword isize;
	19
	20	/***************************************************************************\
	21	* Condition code values *
	22	\***************************************************************************/
	23
	24	#define EQ 0
	25	#define NE 1
	26	#define CS 2
	27	#define CC 3
	28	#define MI 4
	29	#define PL 5
	30	#define VS 6
	31	#define VC 7
	32	#define HI 8
	33	#define LS 9
	34	#define GE 10
	35	#define LT 11
	36	#define GT 12
	37	#define LE 13
	38	#define AL 14
	39	#define NV 15
	40
	41	/***************************************************************************\
	42	* Shift Opcodes *
	43	\***************************************************************************/
	44
	45	#define LSL 0
	46	#define LSR 1
	47	#define ASR 2
	48	#define ROR 3
	49
	50	/***************************************************************************\
	51	* Macros to twiddle the status flags and mode *
	52	\***************************************************************************/
	53
	54	#define NBIT ((unsigned)1L << 31)
	55	#define ZBIT (1L << 30)
	56	#define CBIT (1L << 29)
	57	#define VBIT (1L << 28)
	58	#define IBIT (1L << 7)
	59	#define FBIT (1L << 6)
	60	#define IFBITS (3L << 6)
	61	#define R15IBIT (1L << 27)
	62	#define R15FBIT (1L << 26)
	63	#define R15IFBITS (3L << 26)
	64
65	#define POS(i) ( (~(i)) >> 31 )
66	#define NEG(i) ( (i) >> 31 )
67
dfcd3bfb	68	#ifdef MODET /* Thumb support */
c906108c SS	69	/* ??? This bit is actually in the low order bit of the PC in the hardware.
	70	It isn't clear if the simulator needs to model that or not. */
	71	#define TBIT (1L << 5)
	72	#define TFLAG state->TFlag
	73	#define SETT state->TFlag = 1
	74	#define CLEART state->TFlag = 0
	75	#define ASSIGNT(res) state->TFlag = res
	76	#endif
	77
	78	#define NFLAG state->NFlag
	79	#define SETN state->NFlag = 1
	80	#define CLEARN state->NFlag = 0
	81	#define ASSIGNN(res) state->NFlag = res
	82
	83	#define ZFLAG state->ZFlag
	84	#define SETZ state->ZFlag = 1
	85	#define CLEARZ state->ZFlag = 0
	86	#define ASSIGNZ(res) state->ZFlag = res
	87
	88	#define CFLAG state->CFlag
	89	#define SETC state->CFlag = 1
	90	#define CLEARC state->CFlag = 0
	91	#define ASSIGNC(res) state->CFlag = res
	92
	93	#define VFLAG state->VFlag
	94	#define SETV state->VFlag = 1
	95	#define CLEARV state->VFlag = 0
	96	#define ASSIGNV(res) state->VFlag = res
	97
f743149e	98
c906108c SS	99	#define IFLAG (state->IFFlags >> 1)
	100	#define FFLAG (state->IFFlags & 1)
	101	#define IFFLAGS state->IFFlags
	102	#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
	103	#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
	104
4ef2594f AO	105	#define PSR_FBITS (0xff000000L)
	106	#define PSR_SBITS (0x00ff0000L)
	107	#define PSR_XBITS (0x0000ff00L)
	108	#define PSR_CBITS (0x000000ffL)
	109
c906108c SS	110	#define CCBITS (0xf0000000L)
	111	#define INTBITS (0xc0L)
	112
	113	#if defined MODET && defined MODE32
	114	#define PCBITS (0xffffffffL)
	115	#else
	116	#define PCBITS (0xfffffffcL)
	117	#endif
	118
	119	#define MODEBITS (0x1fL)
	120	#define R15INTBITS (3L << 26)
	121
	122	#if defined MODET && defined MODE32
	123	#define R15PCBITS (0x03ffffffL)
	124	#else
	125	#define R15PCBITS (0x03fffffcL)
	126	#endif
	127
	128	#define R15PCMODEBITS (0x03ffffffL)
	129	#define R15MODEBITS (0x3L)
	130
	131	#ifdef MODE32
	132	#define PCMASK PCBITS
	133	#define PCWRAP(pc) (pc)
	134	#else
	135	#define PCMASK R15PCBITS
	136	#define PCWRAP(pc) ((pc) & R15PCBITS)
	137	#endif
	138
	139	#define PC (state->Reg[15] & PCMASK)
	140	#define R15CCINTMODE (state->Reg[15] & (CCBITS \| R15INTBITS \| R15MODEBITS))
	141	#define R15INT (state->Reg[15] & R15INTBITS)
	142	#define R15INTPC (state->Reg[15] & (R15INTBITS \| R15PCBITS))
	143	#define R15INTPCMODE (state->Reg[15] & (R15INTBITS \| R15PCBITS \| R15MODEBITS))
	144	#define R15INTMODE (state->Reg[15] & (R15INTBITS \| R15MODEBITS))
	145	#define R15PC (state->Reg[15] & R15PCBITS)
	146	#define R15PCMODE (state->Reg[15] & (R15PCBITS \| R15MODEBITS))
	147	#define R15MODE (state->Reg[15] & R15MODEBITS)
	148
	149	#define ECC ((NFLAG << 31) \| (ZFLAG << 30) \| (CFLAG << 29) \| (VFLAG << 28))
	150	#define EINT (IFFLAGS << 6)
	151	#define ER15INT (IFFLAGS << 26)
	152	#define EMODE (state->Mode)
	153
	154	#ifdef MODET
	155	#define CPSR (ECC \| EINT \| EMODE \| (TFLAG << 5))
	156	#else
	157	#define CPSR (ECC \| EINT \| EMODE)
	158	#endif
	159
	160	#ifdef MODE32
	161	#define PATCHR15
	162	#else
	163	#define PATCHR15 state->Reg[15] = ECC \| ER15INT \| EMODE \| R15PC
	164	#endif
	165
cf52c765	166	#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
4ef2594f AO	167	#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) \| ((s) & PSR_FBITS)
	168	#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) \| ((s) & PSR_SBITS)
	169	#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) \| ((s) & PSR_XBITS)
	170	#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) \| ((s) & PSR_CBITS)
c906108c SS	171	#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
	172	state->Reg[15] = ((s) & CCBITS) \| R15PC \| ER15INT \| EMODE ; \
	173	ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
	174	ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
	175	ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
	176	ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
	177	} \
	178	else { \
6d358e86 NC	179	state->Reg[15] = R15PC \| ((s) & (CCBITS \| R15INTBITS \| R15MODEBITS)) ; \
6d358e86 NC	180	ARMul_R15Altered (state) ; \
c906108c SS	181	}
	182	#define SETABORT(i,m) state->Cpsr = ECC \| EINT \| (i) \| (m)
	183
	184	#ifndef MODE32
	185	#define VECTORS 0x20
	186	#define LEGALADDR 0x03ffffff
	187	#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
	188	#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
	189	#endif
	190
	191	#define INTERNALABORT(address) if (address < VECTORS) \
	192	state->Aborted = ARMul_DataAbortV ; \
	193	else \
	194	state->Aborted = ARMul_AddrExceptnV ;
	195
	196	#ifdef MODE32
	197	#define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
	198	#else
	199	#define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
	200	ARMul_Abort(state,ARMul_AddrExceptnV) ; \
	201	else \
	202	ARMul_Abort(state,ARMul_DataAbortV)
	203	#endif
	204	#define CPTAKEABORT if (!state->Aborted) \
	205	ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
	206	else if (state->Aborted == ARMul_AddrExceptnV) \
	207	ARMul_Abort(state,ARMul_AddrExceptnV) ; \
	208	else \
	209	ARMul_Abort(state,ARMul_DataAbortV)
	210
	211
	212	/***************************************************************************\
	213	* Different ways to start the next instruction *
	214	\***************************************************************************/
	215
	216	#define SEQ 0
	217	#define NONSEQ 1
	218	#define PCINCEDSEQ 2
	219	#define PCINCEDNONSEQ 3
	220	#define PRIMEPIPE 4
	221	#define RESUME 8
	222
	223	#define NORMALCYCLE state->NextInstr = 0
dfcd3bfb	224	#define BUSUSEDN state->NextInstr \|= 1 /* the next fetch will be an N cycle */
c906108c SS	225	#define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
	226	state->NextInstr = (state->NextInstr & 0xff) \| 2
	227	#define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
	228	state->NextInstr \|= 3
	229	#define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
	230	state->NextInstr \|= 2
	231	#define FLUSHPIPE state->NextInstr \|= PRIMEPIPE
	232
	233	/***************************************************************************\
	234	* Cycle based emulation *
	235	\***************************************************************************/
	236
	237	#define OUTPUTCP(i,a,b)
	238	#define NCYCLE
	239	#define SCYCLE
	240	#define ICYCLE
	241	#define CCYCLE
	242	#define NEXTCYCLE(c)
	243
	244	/***************************************************************************\
	245	* States of the cycle based state machine *
	246	\***************************************************************************/
	247
	248
	249	/***************************************************************************\
	250	* Macros to extract parts of instructions *
	251	\***************************************************************************/
	252
	253	#define DESTReg (BITS(12,15))
	254	#define LHSReg (BITS(16,19))
	255	#define RHSReg (BITS(0,3))
	256
	257	#define DEST (state->Reg[DESTReg])
	258
	259	#ifdef MODE32
	260	#ifdef MODET
	261	#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
	262	#else
	263	#define LHS (state->Reg[LHSReg])
	264	#endif
	265	#else
	266	#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
	267	#endif
	268
	269	#define MULDESTReg (BITS(16,19))
	270	#define MULLHSReg (BITS(0,3))
	271	#define MULRHSReg (BITS(8,11))
	272	#define MULACCReg (BITS(12,15))
	273
	274	#define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
	275	#define DPSImmRHS temp = BITS(0,11) ; \
	276	rhs = ARMul_ImmedTable[temp] ; \
	277	if (temp > 255) /* there was a shift */ \
	278	ASSIGNC(rhs >> 31) ;
	279
	280	#ifdef MODE32
	281	#define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
	282	: GetDPRegRHS(state, instr))
	283	#define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
	284	: GetDPSRegRHS(state, instr))
	285	#else
	286	#define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
	287	: GetDPRegRHS(state, instr))
	288	#define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
289	: GetDPSRegRHS(state, instr))
290	#endif
291
292	#define LSBase state->Reg[LHSReg]
293	#define LSImmRHS (BITS(0,11))
294
295	#ifdef MODE32
296	#define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
297	: GetLSRegRHS(state, instr))
298	#else
299	#define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
300	: GetLSRegRHS(state, instr))
301	#endif
302
303	#define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
304	(ARMword)ARMul_BitList[BITS(8,15)] )
305	#define LSMBaseFirst ((LHSReg == 0 && BIT(0)) \|\| \
306	(BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
307
308	#define SWAPSRC (state->Reg[RHSReg])
309
310	#define LSCOff (BITS(0,7) << 2)
311	#define CPNum BITS(8,11)
312
313	/***************************************************************************\
314	* Macro to rotate n right by b bits *
315	\***************************************************************************/
316
317	#define ROTATER(n,b) (((n)>>(b))\|((n)<<(32-(b))))
318
319	/***************************************************************************\
320	* Macros to store results of instructions *
321	\***************************************************************************/
322
323	#define WRITEDEST(d) if (DESTReg==15) \
324	WriteR15(state, d) ; \
325	else \
326	DEST = d
327
328	#define WRITESDEST(d) if (DESTReg == 15) \
329	WriteSR15(state, d) ; \
330	else { \
331	DEST = d ; \
332	ARMul_NegZero(state, d) ; \
333	}
334
892c6b9d AO	335	#define WRITEDESTB(d) if (DESTReg == 15) \
	336	WriteR15Branch(state, d) ; \
	337	else \
	338	DEST = d
	339
c906108c SS	340	#define BYTETOBUS(data) ((data & 0xff) \| \
	341	((data & 0xff) << 8) \| \
	342	((data & 0xff) << 16) \| \
	343	((data & 0xff) << 24))
	344	#define BUSTOBYTE(address,data) \
	345	if (state->bigendSig) \
	346	temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
	347	else \
	348	temp = (data >> ((address & 3) << 3)) & 0xff
	349
	350	#define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
	351	#define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
	352	#define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
	353	#define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
	354
	355	#define POSBRANCH ((instr & 0x7fffff) << 2)
fe47e8df	356	#define NEGBRANCH (0xfc000000 \| ((instr & 0xffffff) << 2))
c906108c SS	357
	358	/***************************************************************************\
	359	* Values for Emulate *
	360	\***************************************************************************/
	361
dfcd3bfb JM	362	#define STOP 0 /* stop */
	363	#define CHANGEMODE 1 /* change mode */
	364	#define ONCE 2 /* execute just one interation */
	365	#define RUN 3 /* continuous execution */
c906108c SS	366
	367	/***************************************************************************\
	368	* Stuff that is shared across modes *
	369	\***************************************************************************/
	370
dfcd3bfb JM	371	extern ARMword ARMul_Emulate26 (ARMul_State * state);
	372	extern ARMword ARMul_Emulate32 (ARMul_State * state);
	373	extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult */
	374	extern ARMword ARMul_ImmedTable[]; /* immediate DP LHS values */
	375	extern char ARMul_BitList[]; /* number of bits in a byte table */
	376	extern void ARMul_Abort26 (ARMul_State * state, ARMword);
	377	extern void ARMul_Abort32 (ARMul_State * state, ARMword);
	378	extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
	379	extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
	380	extern void ARMul_NegZero (ARMul_State * state, ARMword result);
	381	extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
	382	ARMword result);
	383	extern int AddOverflow (ARMword a, ARMword b, ARMword result);
	384	extern int SubOverflow (ARMword a, ARMword b, ARMword result);
	385	extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
	386	ARMword result);
	387	extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
	388	ARMword result);
	389	extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
	390	ARMword result);
	391	extern void ARMul_CPSRAltered (ARMul_State * state);
	392	extern void ARMul_R15Altered (ARMul_State * state);
	393	extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
	394	ARMword newmode);
	395	extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
	396	extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
	397	extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
	398	extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
	399	extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
	400	extern void ARMul_CDP (ARMul_State * state, ARMword instr);
	401	extern unsigned IntPending (ARMul_State * state);
	402	extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
	403	ARMword data);
c906108c SS	404	#define EVENTLISTSIZE 1024L
	405
	406	/* Thumb support: */
	407
dfcd3bfb JM	408	typedef enum
	409	{
	410	t_undefined, /* undefined Thumb instruction */
	411	t_decoded, /* instruction decoded to ARM equivalent */
	412	t_branch /* Thumb branch (already processed) */
	413	}
	414	tdstate;
c906108c	415
dfcd3bfb JM	416	extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
dfcd3bfb JM	417	ARMword tinstr, ARMword * ainstr);
c906108c SS	418
	419	/***************************************************************************\
	420	* Macros to scrutinize instructions *
	421	\***************************************************************************/
	422
	423
	424	#define UNDEF_Test
	425	#define UNDEF_Shift
	426	#define UNDEF_MSRPC
	427	#define UNDEF_MRSPC
	428	#define UNDEF_MULPCDest
	429	#define UNDEF_MULDestEQOp1
	430	#define UNDEF_LSRBPC
	431	#define UNDEF_LSRBaseEQOffWb
	432	#define UNDEF_LSRBaseEQDestWb
	433	#define UNDEF_LSRPCBaseWb
	434	#define UNDEF_LSRPCOffWb
	435	#define UNDEF_LSMNoRegs
	436	#define UNDEF_LSMPCBase
	437	#define UNDEF_LSMUserBankWb
	438	#define UNDEF_LSMBaseInListWb
	439	#define UNDEF_SWPPC
	440	#define UNDEF_CoProHS
	441	#define UNDEF_MCRPC
	442	#define UNDEF_LSCPCBaseWb
	443	#define UNDEF_UndefNotBounced
	444	#define UNDEF_ShortInt
	445	#define UNDEF_IllegalMode
	446	#define UNDEF_Prog32SigChange
	447	#define UNDEF_Data32SigChange