[thirdparty/binutils-gdb.git] / sim / bfin / dv-bfin_gpio.c

/* Blackfin General Purpose Ports (GPIO) model

   Copyright (C) 2010-2011 Free Software Foundation, Inc.
   Contributed by Analog Devices, Inc.

   This file is part of simulators.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "sim-main.h"
#include "devices.h"
#include "dv-bfin_gpio.h"

struct bfin_gpio
{
  bu32 base;

  /* Order after here is important -- matches hardware MMR layout.  */
  bu16 BFIN_MMR_16(data);
  bu16 BFIN_MMR_16(clear);
  bu16 BFIN_MMR_16(set);
  bu16 BFIN_MMR_16(toggle);
  bu16 BFIN_MMR_16(maska);
  bu16 BFIN_MMR_16(maska_clear);
  bu16 BFIN_MMR_16(maska_set);
  bu16 BFIN_MMR_16(maska_toggle);
  bu16 BFIN_MMR_16(maskb);
  bu16 BFIN_MMR_16(maskb_clear);
  bu16 BFIN_MMR_16(maskb_set);
  bu16 BFIN_MMR_16(maskb_toggle);
  bu16 BFIN_MMR_16(dir);
  bu16 BFIN_MMR_16(polar);
  bu16 BFIN_MMR_16(edge);
  bu16 BFIN_MMR_16(both);
  bu16 BFIN_MMR_16(inen);
};
#define mmr_base()      offsetof(struct bfin_gpio, data)
#define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base())

static const char * const mmr_names[] =
{
  "PORTIO", "PORTIO_CLEAR", "PORTIO_SET", "PORTIO_TOGGLE", "PORTIO_MASKA",
  "PORTIO_MASKA_CLEAR", "PORTIO_MASKA_SET", "PORTIO_MASKA_TOGGLE",
  "PORTIO_MASKB", "PORTIO_MASKB_CLEAR", "PORTIO_MASKB_SET",
  "PORTIO_MASKB_TOGGLE", "PORTIO_DIR", "PORTIO_POLAR", "PORTIO_EDGE",
  "PORTIO_BOTH", "PORTIO_INEN",
};
#define mmr_name(off) mmr_names[(off) / 4]

static unsigned
bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space,
			   address_word addr, unsigned nr_bytes)
{
  struct bfin_gpio *port = hw_data (me);
  bu32 mmr_off;
  bu16 value;
  bu16 *valuep;

  value = dv_load_2 (source);
  mmr_off = addr - port->base;
  valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);

  HW_TRACE_WRITE ();

  dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);

  switch (mmr_off)
    {
    case mmr_offset(data):
    case mmr_offset(maska):
    case mmr_offset(maskb):
    case mmr_offset(dir):
    case mmr_offset(polar):
    case mmr_offset(edge):
    case mmr_offset(both):
    case mmr_offset(inen):
      *valuep = value;
      break;
    case mmr_offset(clear):
    case mmr_offset(maska_clear):
    case mmr_offset(maskb_clear):
      /* We want to clear the related data MMR.  */
      valuep -= 2;
      dv_w1c_2 (valuep, value, -1);
      break;
    case mmr_offset(set):
    case mmr_offset(maska_set):
    case mmr_offset(maskb_set):
      /* We want to set the related data MMR.  */
      valuep -= 4;
      *valuep |= value;
      break;
    case mmr_offset(toggle):
    case mmr_offset(maska_toggle):
    case mmr_offset(maskb_toggle):
      /* We want to toggle the related data MMR.  */
      valuep -= 6;
      *valuep ^= value;
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
      break;
    }

  return nr_bytes;
}

static unsigned
bfin_gpio_io_read_buffer (struct hw *me, void *dest, int space,
			  address_word addr, unsigned nr_bytes)
{
  struct bfin_gpio *port = hw_data (me);
  bu32 mmr_off;
  bu16 *valuep;

  mmr_off = addr - port->base;
  valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);

  HW_TRACE_READ ();

  dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);

  switch (mmr_off)
    {
    case mmr_offset(data):
    case mmr_offset(clear):
    case mmr_offset(set):
    case mmr_offset(toggle):
      dv_store_2 (dest, port->data);
      break;
    case mmr_offset(maska):
    case mmr_offset(maska_clear):
    case mmr_offset(maska_set):
    case mmr_offset(maska_toggle):
      dv_store_2 (dest, port->maska);
      break;
    case mmr_offset(maskb):
    case mmr_offset(maskb_clear):
    case mmr_offset(maskb_set):
    case mmr_offset(maskb_toggle):
      dv_store_2 (dest, port->maskb);
      break;
    case mmr_offset(dir):
    case mmr_offset(polar):
    case mmr_offset(edge):
    case mmr_offset(both):
    case mmr_offset(inen):
      dv_store_2 (dest, *valuep);
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
      break;
    }

  return nr_bytes;
}

static const struct hw_port_descriptor bfin_gpio_ports[] =
{
  { "mask_a", 0, 0, output_port, },
  { "mask_b", 1, 0, output_port, },
  { "p0",     0, 0, input_port, },
  { "p1",     1, 0, input_port, },
  { "p2",     2, 0, input_port, },
  { "p3",     3, 0, input_port, },
  { "p4",     4, 0, input_port, },
  { "p5",     5, 0, input_port, },
  { "p6",     6, 0, input_port, },
  { "p7",     7, 0, input_port, },
  { "p8",     8, 0, input_port, },
  { "p9",     9, 0, input_port, },
  { "p10",   10, 0, input_port, },
  { "p11",   11, 0, input_port, },
  { "p12",   12, 0, input_port, },
  { "p13",   13, 0, input_port, },
  { "p14",   14, 0, input_port, },
  { "p15",   15, 0, input_port, },
  { NULL, 0, 0, 0, },
};

static void
bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source,
		      int source_port, int level)
{
  struct bfin_gpio *port = hw_data (me);
  bool olvl, nlvl;
  bu32 bit = (1 << my_port);

  /* Normalize the level value.  A simulated device can send any value
     it likes to us, but in reality we only care about 0 and 1.  This
     lets us assume only those two values below.  */
  level = !!level;

  HW_TRACE ((me, "pin %i set to %i", my_port, level));

  /* Only screw with state if this pin is set as an input, and the
     input is actually enabled.  */
  if ((port->dir & bit) || !(port->inen & bit))
    {
      HW_TRACE ((me, "ignoring level/int due to DIR=%i INEN=%i",
		 !!(port->dir & bit), !!(port->inen & bit)));
      return;
    }

  /* Get the old pin state for calculating an interrupt.  */
  olvl = !!(port->data & bit);

  /* Update the new pin state.  */
  port->data = (port->data & ~bit) | (level << my_port);

  /* See if this state transition will generate an interrupt.  */
  nlvl = !!(port->data & bit);

  if (port->edge & bit)
    {
      /* Pin is edge triggered.  */
      if (port->both & bit)
	{
	  /* Both edges.  */
	  if (olvl == nlvl)
	    {
	      HW_TRACE ((me, "ignoring int due to EDGE=%i BOTH=%i lvl=%i->%i",
			 !!(port->edge & bit), !!(port->both & bit),
			 olvl, nlvl));
	      return;
	    }
	}
      else
	{
	  /* Just one edge.  */
	  if (!(((port->polar & bit) && olvl > nlvl)
		|| (!(port->polar & bit) && olvl < nlvl)))
	    {
	      HW_TRACE ((me, "ignoring int due to EDGE=%i POLAR=%i lvl=%i->%i",
			 !!(port->edge & bit), !!(port->polar & bit),
			 olvl, nlvl));
	      return;
	    }
	}
    }
  else
    {
      /* Pin is level triggered.  */
      if (nlvl == !!(port->polar & bit))
	{
	  HW_TRACE ((me, "ignoring int due to EDGE=%i POLAR=%i lvl=%i",
		     !!(port->edge & bit), !!(port->polar & bit), nlvl));
	  return;
	}
    }

  /* If the masks allow it, push the interrupt even higher.  */
  if (port->maska & bit)
    {
      HW_TRACE ((me, "pin %i triggered an int via mask a", my_port));
      hw_port_event (me, 0, 1);
    }
  if (port->maskb & bit)
    {
      HW_TRACE ((me, "pin %i triggered an int via mask b", my_port));
      hw_port_event (me, 1, 1);
    }
}

static void
attach_bfin_gpio_regs (struct hw *me, struct bfin_gpio *port)
{
  address_word attach_address;
  int attach_space;
  unsigned attach_size;
  reg_property_spec reg;

  if (hw_find_property (me, "reg") == NULL)
    hw_abort (me, "Missing \"reg\" property");

  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
    hw_abort (me, "\"reg\" property must contain three addr/size entries");

  hw_unit_address_to_attach_address (hw_parent (me),
				     &reg.address,
				     &attach_space, &attach_address, me);
  hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);

  if (attach_size != BFIN_MMR_GPIO_SIZE)
    hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO_SIZE);

  hw_attach_address (hw_parent (me),
		     0, attach_space, attach_address, attach_size, me);

  port->base = attach_address;
}

static void
bfin_gpio_finish (struct hw *me)
{
  struct bfin_gpio *port;

  port = HW_ZALLOC (me, struct bfin_gpio);

  set_hw_data (me, port);
  set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer);
  set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer);
  set_hw_ports (me, bfin_gpio_ports);
  set_hw_port_event (me, bfin_gpio_port_event);

  attach_bfin_gpio_regs (me, port);
}

const struct hw_descriptor dv_bfin_gpio_descriptor[] =
{
  {"bfin_gpio", bfin_gpio_finish,},
  {NULL, NULL},
};
Commit	Line	Data
b5215db0 MF	1	/* Blackfin General Purpose Ports (GPIO) model
	2
	3	Copyright (C) 2010-2011 Free Software Foundation, Inc.
	4	Contributed by Analog Devices, Inc.
	5
	6	This file is part of simulators.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
	21	#include "config.h"
	22
	23	#include "sim-main.h"
	24	#include "devices.h"
	25	#include "dv-bfin_gpio.h"
	26
	27	struct bfin_gpio
	28	{
	29	bu32 base;
	30
	31	/* Order after here is important -- matches hardware MMR layout. */
	32	bu16 BFIN_MMR_16(data);
	33	bu16 BFIN_MMR_16(clear);
	34	bu16 BFIN_MMR_16(set);
	35	bu16 BFIN_MMR_16(toggle);
	36	bu16 BFIN_MMR_16(maska);
	37	bu16 BFIN_MMR_16(maska_clear);
	38	bu16 BFIN_MMR_16(maska_set);
	39	bu16 BFIN_MMR_16(maska_toggle);
	40	bu16 BFIN_MMR_16(maskb);
	41	bu16 BFIN_MMR_16(maskb_clear);
	42	bu16 BFIN_MMR_16(maskb_set);
	43	bu16 BFIN_MMR_16(maskb_toggle);
	44	bu16 BFIN_MMR_16(dir);
	45	bu16 BFIN_MMR_16(polar);
	46	bu16 BFIN_MMR_16(edge);
	47	bu16 BFIN_MMR_16(both);
	48	bu16 BFIN_MMR_16(inen);
	49	};
	50	#define mmr_base() offsetof(struct bfin_gpio, data)
	51	#define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base())
	52
	53	static const char * const mmr_names[] =
	54	{
	55	"PORTIO", "PORTIO_CLEAR", "PORTIO_SET", "PORTIO_TOGGLE", "PORTIO_MASKA",
	56	"PORTIO_MASKA_CLEAR", "PORTIO_MASKA_SET", "PORTIO_MASKA_TOGGLE",
	57	"PORTIO_MASKB", "PORTIO_MASKB_CLEAR", "PORTIO_MASKB_SET",
	58	"PORTIO_MASKB_TOGGLE", "PORTIO_DIR", "PORTIO_POLAR", "PORTIO_EDGE",
	59	"PORTIO_BOTH", "PORTIO_INEN",
	60	};
	61	#define mmr_name(off) mmr_names[(off) / 4]
	62
	63	static unsigned
	64	bfin_gpio_io_write_buffer (struct hw me, const void source, int space,
65	address_word addr, unsigned nr_bytes)
66	{
67	struct bfin_gpio *port = hw_data (me);
68	bu32 mmr_off;
69	bu16 value;
70	bu16 *valuep;
71
72	value = dv_load_2 (source);
73	mmr_off = addr - port->base;
74	valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
75
76	HW_TRACE_WRITE ();
77
78	dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
79
80	switch (mmr_off)
81	{
82	case mmr_offset(data):
83	case mmr_offset(maska):
84	case mmr_offset(maskb):
85	case mmr_offset(dir):
86	case mmr_offset(polar):
87	case mmr_offset(edge):
88	case mmr_offset(both):
89	case mmr_offset(inen):
90	*valuep = value;
91	break;
92	case mmr_offset(clear):
93	case mmr_offset(maska_clear):
94	case mmr_offset(maskb_clear):
eaf863cd MF	95	/* We want to clear the related data MMR. */
eaf863cd MF	96	valuep -= 2;
9922f803	97	dv_w1c_2 (valuep, value, -1);
b5215db0 MF	98	break;
	99	case mmr_offset(set):
	100	case mmr_offset(maska_set):
	101	case mmr_offset(maskb_set):
eaf863cd MF	102	/* We want to set the related data MMR. */
eaf863cd MF	103	valuep -= 4;
b5215db0 MF	104	*valuep \|= value;
	105	break;
	106	case mmr_offset(toggle):
	107	case mmr_offset(maska_toggle):
	108	case mmr_offset(maskb_toggle):
eaf863cd MF	109	/* We want to toggle the related data MMR. */
eaf863cd MF	110	valuep -= 6;
b5215db0 MF	111	*valuep ^= value;
	112	break;
	113	default:
	114	dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
	115	break;
	116	}
	117
	118	return nr_bytes;
	119	}
	120
	121	static unsigned
	122	bfin_gpio_io_read_buffer (struct hw me, void dest, int space,
	123	address_word addr, unsigned nr_bytes)
	124	{
	125	struct bfin_gpio *port = hw_data (me);
	126	bu32 mmr_off;
	127	bu16 *valuep;
	128
	129	mmr_off = addr - port->base;
	130	valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
	131
	132	HW_TRACE_READ ();
	133
	134	dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
	135
	136	switch (mmr_off)
	137	{
	138	case mmr_offset(data):
	139	case mmr_offset(clear):
	140	case mmr_offset(set):
	141	case mmr_offset(toggle):
	142	dv_store_2 (dest, port->data);
	143	break;
	144	case mmr_offset(maska):
	145	case mmr_offset(maska_clear):
	146	case mmr_offset(maska_set):
	147	case mmr_offset(maska_toggle):
	148	dv_store_2 (dest, port->maska);
	149	break;
	150	case mmr_offset(maskb):
	151	case mmr_offset(maskb_clear):
	152	case mmr_offset(maskb_set):
	153	case mmr_offset(maskb_toggle):
	154	dv_store_2 (dest, port->maskb);
	155	break;
	156	case mmr_offset(dir):
	157	case mmr_offset(polar):
	158	case mmr_offset(edge):
	159	case mmr_offset(both):
	160	case mmr_offset(inen):
	161	dv_store_2 (dest, *valuep);
	162	break;
	163	default:
	164	dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
	165	break;
	166	}
	167
	168	return nr_bytes;
	169	}
	170
	171	static const struct hw_port_descriptor bfin_gpio_ports[] =
	172	{
	173	{ "mask_a", 0, 0, output_port, },
	174	{ "mask_b", 1, 0, output_port, },
175	{ "p0", 0, 0, input_port, },
176	{ "p1", 1, 0, input_port, },
177	{ "p2", 2, 0, input_port, },
178	{ "p3", 3, 0, input_port, },
179	{ "p4", 4, 0, input_port, },
180	{ "p5", 5, 0, input_port, },
181	{ "p6", 6, 0, input_port, },
182	{ "p7", 7, 0, input_port, },
183	{ "p8", 8, 0, input_port, },
184	{ "p9", 9, 0, input_port, },
185	{ "p10", 10, 0, input_port, },
186	{ "p11", 11, 0, input_port, },
187	{ "p12", 12, 0, input_port, },
188	{ "p13", 13, 0, input_port, },
189	{ "p14", 14, 0, input_port, },
8aacdaf4	190	{ "p15", 15, 0, input_port, },
b5215db0 MF	191	{ NULL, 0, 0, 0, },
	192	};
	193
	194	static void
	195	bfin_gpio_port_event (struct hw me, int my_port, struct hw source,
	196	int source_port, int level)
	197	{
	198	struct bfin_gpio *port = hw_data (me);
	199	bool olvl, nlvl;
	200	bu32 bit = (1 << my_port);
	201
b72cc8e1 MF	202	/* Normalize the level value. A simulated device can send any value
	203	it likes to us, but in reality we only care about 0 and 1. This
	204	lets us assume only those two values below. */
	205	level = !!level;
	206
a31d4fd9 MF	207	HW_TRACE ((me, "pin %i set to %i", my_port, level));
a31d4fd9 MF	208
b72cc8e1 MF	209	/* Only screw with state if this pin is set as an input, and the
	210	input is actually enabled. */
	211	if ((port->dir & bit) \|\| !(port->inen & bit))
a31d4fd9 MF	212	{
	213	HW_TRACE ((me, "ignoring level/int due to DIR=%i INEN=%i",
	214	!!(port->dir & bit), !!(port->inen & bit)));
	215	return;
	216	}
b5215db0 MF	217
	218	/* Get the old pin state for calculating an interrupt. */
	219	olvl = !!(port->data & bit);
	220
	221	/* Update the new pin state. */
b72cc8e1	222	port->data = (port->data & ~bit) \| (level << my_port);
b5215db0 MF	223
	224	/* See if this state transition will generate an interrupt. */
	225	nlvl = !!(port->data & bit);
	226
	227	if (port->edge & bit)
	228	{
	229	/* Pin is edge triggered. */
b72cc8e1	230	if (port->both & bit)
b5215db0 MF	231	{
	232	/* Both edges. */
	233	if (olvl == nlvl)
a31d4fd9 MF	234	{
	235	HW_TRACE ((me, "ignoring int due to EDGE=%i BOTH=%i lvl=%i->%i",
	236	!!(port->edge & bit), !!(port->both & bit),
	237	olvl, nlvl));
	238	return;
	239	}
b5215db0 MF	240	}
	241	else
	242	{
	243	/* Just one edge. */
	244	if (!(((port->polar & bit) && olvl > nlvl)
	245	\|\| (!(port->polar & bit) && olvl < nlvl)))
a31d4fd9 MF	246	{
	247	HW_TRACE ((me, "ignoring int due to EDGE=%i POLAR=%i lvl=%i->%i",
	248	!!(port->edge & bit), !!(port->polar & bit),
	249	olvl, nlvl));
	250	return;
	251	}
b5215db0 MF	252	}
	253	}
	254	else
	255	{
	256	/* Pin is level triggered. */
	257	if (nlvl == !!(port->polar & bit))
a31d4fd9 MF	258	{
	259	HW_TRACE ((me, "ignoring int due to EDGE=%i POLAR=%i lvl=%i",
	260	!!(port->edge & bit), !!(port->polar & bit), nlvl));
	261	return;
	262	}
b5215db0 MF	263	}
	264
	265	/* If the masks allow it, push the interrupt even higher. */
	266	if (port->maska & bit)
a31d4fd9 MF	267	{
	268	HW_TRACE ((me, "pin %i triggered an int via mask a", my_port));
	269	hw_port_event (me, 0, 1);
	270	}
b5215db0	271	if (port->maskb & bit)
a31d4fd9 MF	272	{
	273	HW_TRACE ((me, "pin %i triggered an int via mask b", my_port));
	274	hw_port_event (me, 1, 1);
	275	}
b5215db0 MF	276	}
	277
	278	static void
	279	attach_bfin_gpio_regs (struct hw me, struct bfin_gpio port)
	280	{
	281	address_word attach_address;
	282	int attach_space;
	283	unsigned attach_size;
	284	reg_property_spec reg;
	285
	286	if (hw_find_property (me, "reg") == NULL)
	287	hw_abort (me, "Missing \"reg\" property");
	288
	289	if (!hw_find_reg_array_property (me, "reg", 0, &reg))
	290	hw_abort (me, "\"reg\" property must contain three addr/size entries");
	291
	292	hw_unit_address_to_attach_address (hw_parent (me),
	293	&reg.address,
	294	&attach_space, &attach_address, me);
	295	hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
	296
	297	if (attach_size != BFIN_MMR_GPIO_SIZE)
	298	hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO_SIZE);
	299
	300	hw_attach_address (hw_parent (me),
	301	0, attach_space, attach_address, attach_size, me);
	302
	303	port->base = attach_address;
	304	}
	305
	306	static void
	307	bfin_gpio_finish (struct hw *me)
	308	{
	309	struct bfin_gpio *port;
	310
	311	port = HW_ZALLOC (me, struct bfin_gpio);
	312
	313	set_hw_data (me, port);
	314	set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer);
	315	set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer);
	316	set_hw_ports (me, bfin_gpio_ports);
	317	set_hw_port_event (me, bfin_gpio_port_event);
	318
	319	attach_bfin_gpio_regs (me, port);
	320	}
	321
	322	const struct hw_descriptor dv_bfin_gpio_descriptor[] =
	323	{
	324	{"bfin_gpio", bfin_gpio_finish,},
	325	{NULL, NULL},
	326	};