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ef016f83 MF |
1 | /* Simulator for Analog Devices Blackfin processors. |
2 | ||
213516ef | 3 | Copyright (C) 2005-2023 Free Software Foundation, Inc. |
050396e5 | 4 | Contributed by Analog Devices, Inc. and Mike Frysinger. |
ef016f83 MF |
5 | |
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
6df01ab8 MF |
21 | /* This must come before any other includes. */ |
22 | #include "defs.h" | |
ef016f83 | 23 | |
3d52735b MF |
24 | #include <stdlib.h> |
25 | ||
ef016f83 | 26 | #include "sim-main.h" |
d026e67e | 27 | #include "sim/sim-bfin.h" |
ef016f83 MF |
28 | #include "bfd.h" |
29 | ||
30 | #include "sim-hw.h" | |
21836669 MF |
31 | #include "sim-options.h" |
32 | ||
ef016f83 | 33 | #include "devices.h" |
21836669 | 34 | #include "arch.h" |
ef016f83 | 35 | #include "dv-bfin_cec.h" |
ef016f83 | 36 | #include "dv-bfin_dmac.h" |
ef016f83 | 37 | |
8a0ebee6 | 38 | static const SIM_MACH bfin_mach; |
ef016f83 MF |
39 | |
40 | struct bfin_memory_layout { | |
41 | address_word addr, len; | |
42 | unsigned mask; /* see mapmask in sim_core_attach() */ | |
43 | }; | |
44 | struct bfin_dev_layout { | |
45 | address_word base, len; | |
46 | unsigned int dmac; | |
47 | const char *dev; | |
48 | }; | |
49 | struct bfin_dmac_layout { | |
50 | address_word base; | |
51 | unsigned int dma_count; | |
52 | }; | |
082e1c4a MF |
53 | struct bfin_port_layout { |
54 | /* Which device this routes to (name/port). */ | |
55 | const char *dst, *dst_port; | |
56 | /* Which device this routes from (name/port). */ | |
57 | const char *src, *src_port; | |
58 | }; | |
ef016f83 MF |
59 | struct bfin_model_data { |
60 | bu32 chipid; | |
61 | int model_num; | |
62 | const struct bfin_memory_layout *mem; | |
63 | size_t mem_count; | |
64 | const struct bfin_dev_layout *dev; | |
65 | size_t dev_count; | |
66 | const struct bfin_dmac_layout *dmac; | |
67 | size_t dmac_count; | |
082e1c4a MF |
68 | const struct bfin_port_layout *port; |
69 | size_t port_count; | |
ef016f83 MF |
70 | }; |
71 | ||
72 | #define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, } | |
73 | #define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, } | |
74 | #define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0) | |
082e1c4a MF |
75 | #define PORT(_dst, _dst_port, _src, _src_port) \ |
76 | { \ | |
77 | .dst = _dst, \ | |
78 | .dst_port = _dst_port, \ | |
79 | .src = _src, \ | |
80 | .src_port = _src_port, \ | |
81 | } | |
82 | #define SIC(_s, _ip, _d, _op) PORT("bfin_sic", "int"#_ip"@"#_s, _d, _op) | |
ef016f83 MF |
83 | |
84 | /* [1] Common sim code can't model exec-only memory. | |
85 | http://sourceware.org/ml/gdb/2010-02/msg00047.html */ | |
86 | ||
87 | #define bf000_chipid 0 | |
88 | static const struct bfin_memory_layout bf000_mem[] = {}; | |
89 | static const struct bfin_dev_layout bf000_dev[] = {}; | |
90 | static const struct bfin_dmac_layout bf000_dmac[] = {}; | |
082e1c4a | 91 | static const struct bfin_port_layout bf000_port[] = {}; |
ef016f83 MF |
92 | |
93 | #define bf50x_chipid 0x2800 | |
94 | #define bf504_chipid bf50x_chipid | |
95 | #define bf506_chipid bf50x_chipid | |
990d19fd MF |
96 | static const struct bfin_memory_layout bf50x_mem[] = |
97 | { | |
ef016f83 MF |
98 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
99 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
100 | LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ |
101 | LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */ | |
102 | LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */ | |
103 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
104 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
105 | LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ | |
106 | LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
107 | }; | |
108 | #define bf504_mem bf50x_mem | |
109 | #define bf506_mem bf50x_mem | |
990d19fd MF |
110 | static const struct bfin_dev_layout bf50x_dev[] = |
111 | { | |
ef016f83 MF |
112 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
113 | DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), | |
114 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
115 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
116 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
117 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
118 | DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
119 | DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
120 | DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
121 | DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
122 | DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
a9c3ef47 | 123 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
124 | DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
125 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
126 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 MF |
127 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
128 | DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), | |
ef016f83 MF |
129 | DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), |
130 | DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), | |
131 | }; | |
132 | #define bf504_dev bf50x_dev | |
133 | #define bf506_dev bf50x_dev | |
990d19fd MF |
134 | static const struct bfin_dmac_layout bf50x_dmac[] = |
135 | { | |
ef016f83 MF |
136 | { BFIN_MMR_DMAC0_BASE, 12, }, |
137 | }; | |
138 | #define bf504_dmac bf50x_dmac | |
139 | #define bf506_dmac bf50x_dmac | |
082e1c4a MF |
140 | static const struct bfin_port_layout bf50x_port[] = |
141 | { | |
142 | SIC (0, 0, "bfin_pll", "pll"), | |
143 | /*SIC (0, 1, "bfin_dmac@0", "stat"),*/ | |
144 | SIC (0, 2, "bfin_ppi@0", "stat"), | |
145 | SIC (0, 3, "bfin_sport@0", "stat"), | |
146 | SIC (0, 4, "bfin_sport@1", "stat"), | |
147 | SIC (0, 5, "bfin_uart2@0", "stat"), | |
148 | SIC (0, 6, "bfin_uart2@1", "stat"), | |
149 | SIC (0, 7, "bfin_spi@0", "stat"), | |
150 | SIC (0, 8, "bfin_spi@1", "stat"), | |
151 | SIC (0, 9, "bfin_can@0", "stat"), | |
152 | SIC (0, 10, "bfin_rsi@0", "int0"), | |
153 | /*SIC (0, 11, reserved),*/ | |
154 | SIC (0, 12, "bfin_counter@0", "stat"), | |
155 | SIC (0, 13, "bfin_counter@1", "stat"), | |
156 | SIC (0, 14, "bfin_dma@0", "di"), | |
157 | SIC (0, 15, "bfin_dma@1", "di"), | |
158 | SIC (0, 16, "bfin_dma@2", "di"), | |
159 | SIC (0, 17, "bfin_dma@3", "di"), | |
160 | SIC (0, 18, "bfin_dma@4", "di"), | |
161 | SIC (0, 19, "bfin_dma@5", "di"), | |
162 | SIC (0, 20, "bfin_dma@6", "di"), | |
163 | SIC (0, 21, "bfin_dma@7", "di"), | |
164 | SIC (0, 22, "bfin_dma@8", "di"), | |
165 | SIC (0, 23, "bfin_dma@9", "di"), | |
166 | SIC (0, 24, "bfin_dma@10", "di"), | |
167 | SIC (0, 25, "bfin_dma@11", "di"), | |
168 | SIC (0, 26, "bfin_can@0", "rx"), | |
169 | SIC (0, 27, "bfin_can@0", "tx"), | |
170 | SIC (0, 28, "bfin_twi@0", "stat"), | |
171 | SIC (0, 29, "bfin_gpio@5", "mask_a"), | |
172 | SIC (0, 30, "bfin_gpio@5", "mask_b"), | |
173 | /*SIC (0, 31, reserved),*/ | |
174 | SIC (1, 0, "bfin_gptimer@0", "stat"), | |
175 | SIC (1, 1, "bfin_gptimer@1", "stat"), | |
176 | SIC (1, 2, "bfin_gptimer@2", "stat"), | |
177 | SIC (1, 3, "bfin_gptimer@3", "stat"), | |
178 | SIC (1, 4, "bfin_gptimer@4", "stat"), | |
179 | SIC (1, 5, "bfin_gptimer@5", "stat"), | |
180 | SIC (1, 6, "bfin_gptimer@6", "stat"), | |
181 | SIC (1, 7, "bfin_gptimer@7", "stat"), | |
182 | SIC (1, 8, "bfin_gpio@6", "mask_a"), | |
183 | SIC (1, 9, "bfin_gpio@6", "mask_b"), | |
184 | SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */ | |
185 | SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */ | |
186 | SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */ | |
187 | SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */ | |
188 | SIC (1, 12, "bfin_wdog@0", "gpi"), | |
189 | SIC (1, 13, "bfin_gpio@7", "mask_a"), | |
190 | SIC (1, 14, "bfin_gpio@7", "mask_b"), | |
191 | SIC (1, 15, "bfin_acm@0", "stat"), | |
192 | SIC (1, 16, "bfin_acm@1", "int"), | |
193 | /*SIC (1, 17, reserved),*/ | |
194 | /*SIC (1, 18, reserved),*/ | |
195 | SIC (1, 19, "bfin_pwm@0", "trip"), | |
196 | SIC (1, 20, "bfin_pwm@0", "sync"), | |
197 | SIC (1, 21, "bfin_pwm@1", "trip"), | |
198 | SIC (1, 22, "bfin_pwm@1", "sync"), | |
199 | SIC (1, 23, "bfin_rsi@0", "int1"), | |
200 | }; | |
201 | #define bf504_port bf50x_port | |
202 | #define bf506_port bf50x_port | |
ef016f83 MF |
203 | |
204 | #define bf51x_chipid 0x27e8 | |
205 | #define bf512_chipid bf51x_chipid | |
206 | #define bf514_chipid bf51x_chipid | |
207 | #define bf516_chipid bf51x_chipid | |
208 | #define bf518_chipid bf51x_chipid | |
990d19fd MF |
209 | static const struct bfin_memory_layout bf51x_mem[] = |
210 | { | |
ef016f83 | 211 | LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ |
ef016f83 MF |
212 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
213 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
214 | LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ |
215 | LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */ | |
216 | LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */ | |
217 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
218 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
219 | LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ | |
220 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
221 | LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ | |
222 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
223 | }; | |
224 | #define bf512_mem bf51x_mem | |
225 | #define bf514_mem bf51x_mem | |
226 | #define bf516_mem bf51x_mem | |
227 | #define bf518_mem bf51x_mem | |
990d19fd MF |
228 | static const struct bfin_dev_layout bf512_dev[] = |
229 | { | |
ef016f83 MF |
230 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
231 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
232 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
233 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
234 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
235 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
236 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
237 | DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
238 | DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
239 | DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
240 | DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
241 | DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
a9c3ef47 | 242 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
243 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
244 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
245 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
246 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 MF |
247 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
248 | DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), | |
ef016f83 MF |
249 | DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), |
250 | DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), | |
251 | DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), | |
252 | }; | |
253 | #define bf514_dev bf512_dev | |
990d19fd MF |
254 | static const struct bfin_dev_layout bf516_dev[] = |
255 | { | |
ef016f83 MF |
256 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
257 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
258 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
259 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
260 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
261 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
262 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
263 | DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
264 | DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
265 | DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
266 | DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
267 | DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
a9c3ef47 | 268 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
269 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
270 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
271 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
272 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 MF |
273 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
274 | DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), | |
ef016f83 MF |
275 | DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), |
276 | DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), | |
277 | DEVICE (0, 0x20, "bfin_emac/eth_phy"), | |
278 | DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), | |
279 | DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), | |
280 | }; | |
281 | #define bf518_dev bf516_dev | |
282 | #define bf512_dmac bf50x_dmac | |
283 | #define bf514_dmac bf50x_dmac | |
284 | #define bf516_dmac bf50x_dmac | |
285 | #define bf518_dmac bf50x_dmac | |
082e1c4a MF |
286 | static const struct bfin_port_layout bf51x_port[] = |
287 | { | |
288 | SIC (0, 0, "bfin_pll", "pll"), | |
289 | /*SIC (0, 1, "bfin_dmac@0", "stat"),*/ | |
290 | SIC (0, 2, "bfin_dmar@0", "block"), | |
291 | SIC (0, 3, "bfin_dmar@1", "block"), | |
292 | SIC (0, 4, "bfin_dmar@0", "overflow"), | |
293 | SIC (0, 5, "bfin_dmar@1", "overflow"), | |
294 | SIC (0, 6, "bfin_ppi@0", "stat"), | |
295 | SIC (0, 7, "bfin_emac", "stat"), | |
296 | SIC (0, 8, "bfin_sport@0", "stat"), | |
297 | SIC (0, 9, "bfin_sport@1", "stat"), | |
298 | SIC (0, 10, "bfin_ptp", "stat"), | |
299 | /*SIC (0, 11, reserved),*/ | |
300 | SIC (0, 12, "bfin_uart@0", "stat"), | |
301 | SIC (0, 13, "bfin_uart@1", "stat"), | |
302 | SIC (0, 14, "bfin_rtc", "rtc"), | |
303 | SIC (0, 15, "bfin_dma@0", "di"), | |
304 | SIC (0, 16, "bfin_dma@3", "di"), | |
305 | SIC (0, 17, "bfin_dma@4", "di"), | |
306 | SIC (0, 18, "bfin_dma@5", "di"), | |
307 | SIC (0, 19, "bfin_dma@6", "di"), | |
308 | SIC (0, 20, "bfin_twi@0", "stat"), | |
309 | SIC (0, 21, "bfin_dma@7", "di"), | |
310 | SIC (0, 22, "bfin_dma@8", "di"), | |
311 | SIC (0, 23, "bfin_dma@9", "di"), | |
312 | SIC (0, 24, "bfin_dma@10", "di"), | |
313 | SIC (0, 25, "bfin_dma@11", "di"), | |
314 | SIC (0, 26, "bfin_otp", "stat"), | |
315 | SIC (0, 27, "bfin_counter@0", "stat"), | |
316 | SIC (0, 28, "bfin_dma@1", "di"), | |
317 | SIC (0, 29, "bfin_gpio@7", "mask_a"), | |
318 | SIC (0, 30, "bfin_dma@2", "di"), | |
319 | SIC (0, 31, "bfin_gpio@7", "mask_b"), | |
320 | SIC (1, 0, "bfin_gptimer@0", "stat"), | |
321 | SIC (1, 1, "bfin_gptimer@1", "stat"), | |
322 | SIC (1, 2, "bfin_gptimer@2", "stat"), | |
323 | SIC (1, 3, "bfin_gptimer@3", "stat"), | |
324 | SIC (1, 4, "bfin_gptimer@4", "stat"), | |
325 | SIC (1, 5, "bfin_gptimer@5", "stat"), | |
326 | SIC (1, 6, "bfin_gptimer@6", "stat"), | |
327 | SIC (1, 7, "bfin_gptimer@7", "stat"), | |
328 | SIC (1, 8, "bfin_gpio@6", "mask_a"), | |
329 | SIC (1, 9, "bfin_gpio@6", "mask_b"), | |
330 | SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */ | |
331 | SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */ | |
332 | SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */ | |
333 | SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */ | |
334 | SIC (1, 12, "bfin_wdog@0", "gpi"), | |
335 | SIC (1, 13, "bfin_gpio@5", "mask_a"), | |
336 | SIC (1, 14, "bfin_gpio@5", "mask_b"), | |
337 | SIC (1, 15, "bfin_spi@0", "stat"), | |
338 | SIC (1, 16, "bfin_spi@1", "stat"), | |
339 | /*SIC (1, 17, reserved),*/ | |
340 | /*SIC (1, 18, reserved),*/ | |
341 | SIC (1, 19, "bfin_rsi@0", "int0"), | |
342 | SIC (1, 20, "bfin_rsi@0", "int1"), | |
343 | SIC (1, 21, "bfin_pwm@0", "trip"), | |
344 | SIC (1, 22, "bfin_pwm@0", "sync"), | |
345 | SIC (1, 23, "bfin_ptp", "stat"), | |
346 | }; | |
347 | #define bf512_port bf51x_port | |
348 | #define bf514_port bf51x_port | |
349 | #define bf516_port bf51x_port | |
350 | #define bf518_port bf51x_port | |
ef016f83 MF |
351 | |
352 | #define bf522_chipid 0x27e4 | |
353 | #define bf523_chipid 0x27e0 | |
354 | #define bf524_chipid bf522_chipid | |
355 | #define bf525_chipid bf523_chipid | |
356 | #define bf526_chipid bf522_chipid | |
357 | #define bf527_chipid bf523_chipid | |
990d19fd MF |
358 | static const struct bfin_memory_layout bf52x_mem[] = |
359 | { | |
ef016f83 | 360 | LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ |
ef016f83 MF |
361 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
362 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
363 | LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ |
364 | LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */ | |
365 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
366 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
367 | LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ | |
368 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
369 | LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ | |
370 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
371 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
372 | }; | |
373 | #define bf522_mem bf52x_mem | |
374 | #define bf523_mem bf52x_mem | |
375 | #define bf524_mem bf52x_mem | |
376 | #define bf525_mem bf52x_mem | |
377 | #define bf526_mem bf52x_mem | |
378 | #define bf527_mem bf52x_mem | |
990d19fd MF |
379 | static const struct bfin_dev_layout bf522_dev[] = |
380 | { | |
ef016f83 MF |
381 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
382 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
383 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
384 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
385 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
386 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
387 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
388 | DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
389 | DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
390 | DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
391 | DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
392 | DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
a9c3ef47 | 393 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
394 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
395 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
396 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
397 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 MF |
398 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
399 | DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), | |
ef016f83 MF |
400 | DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), |
401 | DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), | |
402 | DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"), | |
403 | }; | |
404 | #define bf523_dev bf522_dev | |
405 | #define bf524_dev bf522_dev | |
406 | #define bf525_dev bf522_dev | |
990d19fd MF |
407 | static const struct bfin_dev_layout bf526_dev[] = |
408 | { | |
ef016f83 MF |
409 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
410 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
411 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
412 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
413 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
414 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
415 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
416 | DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
417 | DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
418 | DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
419 | DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
420 | DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
a9c3ef47 | 421 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
422 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
423 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
424 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
425 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 MF |
426 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
427 | DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), | |
ef016f83 MF |
428 | DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), |
429 | DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), | |
430 | DEVICE (0, 0x20, "bfin_emac/eth_phy"), | |
431 | DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), | |
432 | DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"), | |
433 | }; | |
434 | #define bf527_dev bf526_dev | |
435 | #define bf522_dmac bf50x_dmac | |
436 | #define bf523_dmac bf50x_dmac | |
437 | #define bf524_dmac bf50x_dmac | |
438 | #define bf525_dmac bf50x_dmac | |
439 | #define bf526_dmac bf50x_dmac | |
440 | #define bf527_dmac bf50x_dmac | |
082e1c4a MF |
441 | static const struct bfin_port_layout bf52x_port[] = |
442 | { | |
443 | SIC (0, 0, "bfin_pll", "pll"), | |
444 | /*SIC (0, 1, "bfin_dmac@0", "stat"),*/ | |
445 | SIC (0, 2, "bfin_dmar@0", "block"), | |
446 | SIC (0, 3, "bfin_dmar@1", "block"), | |
447 | SIC (0, 4, "bfin_dmar@0", "overflow"), | |
448 | SIC (0, 5, "bfin_dmar@1", "overflow"), | |
449 | SIC (0, 6, "bfin_ppi@0", "stat"), | |
450 | SIC (0, 7, "bfin_emac", "stat"), | |
451 | SIC (0, 8, "bfin_sport@0", "stat"), | |
452 | SIC (0, 9, "bfin_sport@1", "stat"), | |
453 | /*SIC (0, 10, reserved),*/ | |
454 | /*SIC (0, 11, reserved),*/ | |
455 | SIC (0, 12, "bfin_uart@0", "stat"), | |
456 | SIC (0, 13, "bfin_uart@1", "stat"), | |
457 | SIC (0, 14, "bfin_rtc", "rtc"), | |
458 | SIC (0, 15, "bfin_dma@0", "di"), | |
459 | SIC (0, 16, "bfin_dma@3", "di"), | |
460 | SIC (0, 17, "bfin_dma@4", "di"), | |
461 | SIC (0, 18, "bfin_dma@5", "di"), | |
462 | SIC (0, 19, "bfin_dma@6", "di"), | |
463 | SIC (0, 20, "bfin_twi@0", "stat"), | |
464 | SIC (0, 21, "bfin_dma@7", "di"), | |
465 | SIC (0, 22, "bfin_dma@8", "di"), | |
466 | SIC (0, 23, "bfin_dma@9", "di"), | |
467 | SIC (0, 24, "bfin_dma@10", "di"), | |
468 | SIC (0, 25, "bfin_dma@11", "di"), | |
469 | SIC (0, 26, "bfin_otp", "stat"), | |
470 | SIC (0, 27, "bfin_counter@0", "stat"), | |
471 | SIC (0, 28, "bfin_dma@1", "di"), | |
472 | SIC (0, 29, "bfin_gpio@7", "mask_a"), | |
473 | SIC (0, 30, "bfin_dma@2", "di"), | |
474 | SIC (0, 31, "bfin_gpio@7", "mask_b"), | |
475 | SIC (1, 0, "bfin_gptimer@0", "stat"), | |
476 | SIC (1, 1, "bfin_gptimer@1", "stat"), | |
477 | SIC (1, 2, "bfin_gptimer@2", "stat"), | |
478 | SIC (1, 3, "bfin_gptimer@3", "stat"), | |
479 | SIC (1, 4, "bfin_gptimer@4", "stat"), | |
480 | SIC (1, 5, "bfin_gptimer@5", "stat"), | |
481 | SIC (1, 6, "bfin_gptimer@6", "stat"), | |
482 | SIC (1, 7, "bfin_gptimer@7", "stat"), | |
483 | SIC (1, 8, "bfin_gpio@6", "mask_a"), | |
484 | SIC (1, 9, "bfin_gpio@6", "mask_b"), | |
485 | SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */ | |
486 | SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */ | |
487 | SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */ | |
488 | SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */ | |
489 | SIC (1, 12, "bfin_wdog@0", "gpi"), | |
490 | SIC (1, 13, "bfin_gpio@5", "mask_a"), | |
491 | SIC (1, 14, "bfin_gpio@5", "mask_b"), | |
492 | SIC (1, 15, "bfin_spi@0", "stat"), | |
493 | SIC (1, 16, "bfin_nfc", "stat"), | |
494 | SIC (1, 17, "bfin_hostdp", "stat"), | |
495 | SIC (1, 18, "bfin_hostdp", "done"), | |
496 | SIC (1, 20, "bfin_usb", "int0"), | |
497 | SIC (1, 21, "bfin_usb", "int1"), | |
498 | SIC (1, 22, "bfin_usb", "int2"), | |
499 | }; | |
500 | #define bf522_port bf51x_port | |
501 | #define bf523_port bf51x_port | |
502 | #define bf524_port bf51x_port | |
503 | #define bf525_port bf51x_port | |
504 | #define bf526_port bf51x_port | |
505 | #define bf527_port bf51x_port | |
ef016f83 MF |
506 | |
507 | #define bf531_chipid 0x27a5 | |
508 | #define bf532_chipid bf531_chipid | |
509 | #define bf533_chipid bf531_chipid | |
990d19fd MF |
510 | static const struct bfin_memory_layout bf531_mem[] = |
511 | { | |
ef016f83 | 512 | LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ |
ef016f83 MF |
513 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
514 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
515 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
516 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
517 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
518 | }; | |
990d19fd MF |
519 | static const struct bfin_memory_layout bf532_mem[] = |
520 | { | |
ef016f83 | 521 | LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ |
ef016f83 MF |
522 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
523 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
524 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
525 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
526 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
527 | LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ | |
528 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
529 | }; | |
990d19fd MF |
530 | static const struct bfin_memory_layout bf533_mem[] = |
531 | { | |
ef016f83 | 532 | LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ |
ef016f83 MF |
533 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
534 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
535 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
536 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
537 | LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ | |
538 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
539 | LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ | |
540 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
541 | LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ | |
542 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
543 | }; | |
990d19fd MF |
544 | static const struct bfin_dev_layout bf533_dev[] = |
545 | { | |
ef016f83 MF |
546 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
547 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
548 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
549 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
550 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
551 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
552 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
a9c3ef47 | 553 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
554 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
555 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
556 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
557 | }; | |
558 | #define bf531_dev bf533_dev | |
559 | #define bf532_dev bf533_dev | |
990d19fd MF |
560 | static const struct bfin_dmac_layout bf533_dmac[] = |
561 | { | |
ef016f83 MF |
562 | { BFIN_MMR_DMAC0_BASE, 8, }, |
563 | }; | |
564 | #define bf531_dmac bf533_dmac | |
565 | #define bf532_dmac bf533_dmac | |
082e1c4a MF |
566 | static const struct bfin_port_layout bf533_port[] = |
567 | { | |
568 | SIC (0, 0, "bfin_pll", "pll"), | |
569 | /*SIC (0, 1, "bfin_dmac@0", "stat"),*/ | |
570 | SIC (0, 2, "bfin_ppi@0", "stat"), | |
571 | SIC (0, 3, "bfin_sport@0", "stat"), | |
572 | SIC (0, 4, "bfin_sport@1", "stat"), | |
573 | SIC (0, 5, "bfin_spi@0", "stat"), | |
574 | SIC (0, 6, "bfin_uart@0", "stat"), | |
575 | SIC (0, 7, "bfin_rtc", "rtc"), | |
576 | SIC (0, 8, "bfin_dma@0", "di"), | |
577 | SIC (0, 9, "bfin_dma@1", "di"), | |
578 | SIC (0, 10, "bfin_dma@2", "di"), | |
579 | SIC (0, 11, "bfin_dma@3", "di"), | |
580 | SIC (0, 12, "bfin_dma@4", "di"), | |
581 | SIC (0, 13, "bfin_dma@5", "di"), | |
582 | SIC (0, 14, "bfin_dma@6", "di"), | |
583 | SIC (0, 15, "bfin_dma@7", "di"), | |
584 | SIC (0, 16, "bfin_gptimer@0", "stat"), | |
585 | SIC (0, 17, "bfin_gptimer@1", "stat"), | |
586 | SIC (0, 18, "bfin_gptimer@2", "stat"), | |
587 | SIC (0, 19, "bfin_gpio@5", "mask_a"), | |
588 | SIC (0, 20, "bfin_gpio@5", "mask_b"), | |
589 | SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */ | |
590 | SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */ | |
591 | SIC (0, 22, "bfin_dma@258", "di"), /* mdma */ | |
592 | SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */ | |
593 | SIC (0, 23, "bfin_wdog@0", "gpi"), | |
594 | }; | |
595 | #define bf531_port bf533_port | |
596 | #define bf532_port bf533_port | |
ef016f83 MF |
597 | |
598 | #define bf534_chipid 0x27c6 | |
599 | #define bf536_chipid 0x27c8 | |
600 | #define bf537_chipid bf536_chipid | |
990d19fd MF |
601 | static const struct bfin_memory_layout bf534_mem[] = |
602 | { | |
ef016f83 | 603 | LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ |
ef016f83 MF |
604 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
605 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
606 | LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ |
607 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
608 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
609 | LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ | |
610 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
611 | LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ | |
612 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
613 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
614 | }; | |
990d19fd MF |
615 | static const struct bfin_memory_layout bf536_mem[] = |
616 | { | |
ef016f83 | 617 | LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ |
ef016f83 MF |
618 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
619 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
620 | LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ |
621 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
622 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
623 | LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ | |
624 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
625 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
626 | }; | |
990d19fd MF |
627 | static const struct bfin_memory_layout bf537_mem[] = |
628 | { | |
ef016f83 | 629 | LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ |
ef016f83 MF |
630 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
631 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
632 | LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ |
633 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
634 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
635 | LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ | |
636 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
637 | LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ | |
638 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
639 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
640 | }; | |
990d19fd MF |
641 | static const struct bfin_dev_layout bf534_dev[] = |
642 | { | |
ef016f83 MF |
643 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
644 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
645 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
646 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
647 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
648 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
649 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
650 | DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
651 | DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
652 | DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
653 | DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
654 | DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
a9c3ef47 | 655 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
656 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
657 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
658 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
659 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 MF |
660 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
661 | DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), | |
ef016f83 | 662 | DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), |
eb324344 MF |
663 | DEVICE (0, 0, "glue-or@1"), |
664 | DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"), | |
665 | DEVICE (0, 0, "glue-or@2"), | |
666 | DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"), | |
667 | DEVICE (0, 0, "glue-or@17"), | |
668 | DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"), | |
669 | DEVICE (0, 0, "glue-or@18"), | |
670 | DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"), | |
671 | DEVICE (0, 0, "glue-or@27"), | |
672 | DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"), | |
673 | DEVICE (0, 0, "glue-or@31"), | |
674 | DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"), | |
ef016f83 | 675 | }; |
990d19fd MF |
676 | static const struct bfin_dev_layout bf537_dev[] = |
677 | { | |
ef016f83 MF |
678 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
679 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
680 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
681 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
682 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
683 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
684 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
685 | DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
686 | DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
687 | DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
688 | DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
689 | DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
a9c3ef47 | 690 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
691 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
692 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
693 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
694 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 MF |
695 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
696 | DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), | |
ef016f83 MF |
697 | DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), |
698 | DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), | |
699 | DEVICE (0, 0x20, "bfin_emac/eth_phy"), | |
eb324344 MF |
700 | DEVICE (0, 0, "glue-or@1"), |
701 | DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"), | |
702 | DEVICE (0, 0, "glue-or@2"), | |
703 | DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"), | |
704 | DEVICE (0, 0, "glue-or@17"), | |
705 | DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"), | |
706 | DEVICE (0, 0, "glue-or@18"), | |
707 | DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"), | |
708 | DEVICE (0, 0, "glue-or@27"), | |
709 | DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"), | |
710 | DEVICE (0, 0, "glue-or@31"), | |
711 | DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"), | |
ef016f83 MF |
712 | }; |
713 | #define bf536_dev bf537_dev | |
714 | #define bf534_dmac bf50x_dmac | |
715 | #define bf536_dmac bf50x_dmac | |
716 | #define bf537_dmac bf50x_dmac | |
082e1c4a MF |
717 | static const struct bfin_port_layout bf537_port[] = |
718 | { | |
719 | SIC (0, 0, "bfin_pll", "pll"), | |
eb324344 MF |
720 | SIC (0, 1, "glue-or@1", "int"), |
721 | /*PORT ("glue-or@1", "int", "bfin_dmac@0", "stat"),*/ | |
722 | PORT ("glue-or@1", "int", "bfin_dmar@0", "block"), | |
723 | PORT ("glue-or@1", "int", "bfin_dmar@1", "block"), | |
724 | PORT ("glue-or@1", "int", "bfin_dmar@0", "overflow"), | |
725 | PORT ("glue-or@1", "int", "bfin_dmar@1", "overflow"), | |
726 | SIC (0, 2, "glue-or@2", "int"), | |
727 | PORT ("glue-or@2", "int", "bfin_can@0", "stat"), | |
728 | PORT ("glue-or@2", "int", "bfin_emac", "stat"), | |
729 | PORT ("glue-or@2", "int", "bfin_sport@0", "stat"), | |
730 | PORT ("glue-or@2", "int", "bfin_sport@1", "stat"), | |
731 | PORT ("glue-or@2", "int", "bfin_ppi@0", "stat"), | |
732 | PORT ("glue-or@2", "int", "bfin_spi@0", "stat"), | |
733 | PORT ("glue-or@2", "int", "bfin_uart@0", "stat"), | |
734 | PORT ("glue-or@2", "int", "bfin_uart@1", "stat"), | |
082e1c4a MF |
735 | SIC (0, 3, "bfin_rtc", "rtc"), |
736 | SIC (0, 4, "bfin_dma@0", "di"), | |
737 | SIC (0, 5, "bfin_dma@3", "di"), | |
738 | SIC (0, 6, "bfin_dma@4", "di"), | |
739 | SIC (0, 7, "bfin_dma@5", "di"), | |
740 | SIC (0, 8, "bfin_dma@6", "di"), | |
741 | SIC (0, 9, "bfin_twi@0", "stat"), | |
742 | SIC (0, 10, "bfin_dma@7", "di"), | |
743 | SIC (0, 11, "bfin_dma@8", "di"), | |
744 | SIC (0, 12, "bfin_dma@9", "di"), | |
745 | SIC (0, 13, "bfin_dma@10", "di"), | |
746 | SIC (0, 14, "bfin_dma@11", "di"), | |
747 | SIC (0, 15, "bfin_can@0", "rx"), | |
748 | SIC (0, 16, "bfin_can@0", "tx"), | |
eb324344 MF |
749 | SIC (0, 17, "glue-or@17", "int"), |
750 | PORT ("glue-or@17", "int", "bfin_dma@1", "di"), | |
751 | PORT ("glue-or@17", "int", "bfin_gpio@7", "mask_a"), | |
752 | SIC (0, 18, "glue-or@18", "int"), | |
753 | PORT ("glue-or@18", "int", "bfin_dma@2", "di"), | |
754 | PORT ("glue-or@18", "int", "bfin_gpio@7", "mask_b"), | |
082e1c4a MF |
755 | SIC (0, 19, "bfin_gptimer@0", "stat"), |
756 | SIC (0, 20, "bfin_gptimer@1", "stat"), | |
757 | SIC (0, 21, "bfin_gptimer@2", "stat"), | |
758 | SIC (0, 22, "bfin_gptimer@3", "stat"), | |
759 | SIC (0, 23, "bfin_gptimer@4", "stat"), | |
760 | SIC (0, 24, "bfin_gptimer@5", "stat"), | |
761 | SIC (0, 25, "bfin_gptimer@6", "stat"), | |
762 | SIC (0, 26, "bfin_gptimer@7", "stat"), | |
eb324344 MF |
763 | SIC (0, 27, "glue-or@27", "int"), |
764 | PORT ("glue-or@27", "int", "bfin_gpio@5", "mask_a"), | |
765 | PORT ("glue-or@27", "int", "bfin_gpio@6", "mask_a"), | |
082e1c4a MF |
766 | SIC (0, 28, "bfin_gpio@6", "mask_b"), |
767 | SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */ | |
768 | SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */ | |
769 | SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */ | |
770 | SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */ | |
eb324344 MF |
771 | SIC (0, 31, "glue-or@31", "int"), |
772 | PORT ("glue-or@31", "int", "bfin_wdog@0", "gpi"), | |
773 | PORT ("glue-or@31", "int", "bfin_gpio@5", "mask_b"), | |
082e1c4a MF |
774 | }; |
775 | #define bf534_port bf537_port | |
776 | #define bf536_port bf537_port | |
ef016f83 MF |
777 | |
778 | #define bf538_chipid 0x27c4 | |
779 | #define bf539_chipid bf538_chipid | |
990d19fd MF |
780 | static const struct bfin_memory_layout bf538_mem[] = |
781 | { | |
ef016f83 MF |
782 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
783 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
784 | LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */ | |
785 | LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */ | |
786 | LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */ | |
787 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
788 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
789 | LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ | |
790 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
791 | LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ | |
792 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
793 | LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ | |
794 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
795 | }; | |
796 | #define bf539_mem bf538_mem | |
990d19fd MF |
797 | static const struct bfin_dev_layout bf538_dev[] = |
798 | { | |
ef016f83 MF |
799 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
800 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
801 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
802 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
803 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
804 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
805 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
806 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), | |
807 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
808 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), | |
809 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 | 810 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
811 | _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1), |
812 | _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1), | |
813 | DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), | |
814 | _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1), | |
815 | _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1), | |
816 | }; | |
817 | #define bf539_dev bf538_dev | |
990d19fd MF |
818 | static const struct bfin_dmac_layout bf538_dmac[] = |
819 | { | |
ef016f83 MF |
820 | { BFIN_MMR_DMAC0_BASE, 8, }, |
821 | { BFIN_MMR_DMAC1_BASE, 12, }, | |
822 | }; | |
823 | #define bf539_dmac bf538_dmac | |
082e1c4a MF |
824 | static const struct bfin_port_layout bf538_port[] = |
825 | { | |
826 | SIC (0, 0, "bfin_pll", "pll"), | |
827 | SIC (0, 1, "bfin_dmac@0", "stat"), | |
828 | SIC (0, 2, "bfin_ppi@0", "stat"), | |
829 | SIC (0, 3, "bfin_sport@0", "stat"), | |
830 | SIC (0, 4, "bfin_sport@1", "stat"), | |
831 | SIC (0, 5, "bfin_spi@0", "stat"), | |
832 | SIC (0, 6, "bfin_uart@0", "stat"), | |
833 | SIC (0, 7, "bfin_rtc", "rtc"), | |
834 | SIC (0, 8, "bfin_dma@0", "di"), | |
835 | SIC (0, 9, "bfin_dma@1", "di"), | |
836 | SIC (0, 10, "bfin_dma@2", "di"), | |
837 | SIC (0, 11, "bfin_dma@3", "di"), | |
838 | SIC (0, 12, "bfin_dma@4", "di"), | |
839 | SIC (0, 13, "bfin_dma@5", "di"), | |
840 | SIC (0, 14, "bfin_dma@6", "di"), | |
841 | SIC (0, 15, "bfin_dma@7", "di"), | |
842 | SIC (0, 16, "bfin_gptimer@0", "stat"), | |
843 | SIC (0, 17, "bfin_gptimer@1", "stat"), | |
844 | SIC (0, 18, "bfin_gptimer@2", "stat"), | |
845 | SIC (0, 19, "bfin_gpio@5", "mask_a"), | |
846 | SIC (0, 20, "bfin_gpio@5", "mask_b"), | |
847 | SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */ | |
848 | SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */ | |
849 | SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */ | |
850 | SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */ | |
851 | SIC (0, 23, "bfin_wdog@0", "gpi"), | |
852 | SIC (0, 24, "bfin_dmac@1", "stat"), | |
853 | SIC (0, 25, "bfin_sport@2", "stat"), | |
854 | SIC (0, 26, "bfin_sport@3", "stat"), | |
855 | /*SIC (0, 27, reserved),*/ | |
856 | SIC (0, 28, "bfin_spi@1", "stat"), | |
857 | SIC (0, 29, "bfin_spi@2", "stat"), | |
858 | SIC (0, 30, "bfin_uart@1", "stat"), | |
859 | SIC (0, 31, "bfin_uart@2", "stat"), | |
860 | SIC (1, 0, "bfin_can@0", "stat"), | |
861 | SIC (1, 1, "bfin_dma@8", "di"), | |
862 | SIC (1, 2, "bfin_dma@9", "di"), | |
863 | SIC (1, 3, "bfin_dma@10", "di"), | |
864 | SIC (1, 4, "bfin_dma@11", "di"), | |
865 | SIC (1, 5, "bfin_dma@12", "di"), | |
866 | SIC (1, 6, "bfin_dma@13", "di"), | |
867 | SIC (1, 7, "bfin_dma@14", "di"), | |
868 | SIC (1, 8, "bfin_dma@15", "di"), | |
869 | SIC (1, 9, "bfin_dma@16", "di"), | |
870 | SIC (1, 10, "bfin_dma@17", "di"), | |
871 | SIC (1, 11, "bfin_dma@18", "di"), | |
872 | SIC (1, 12, "bfin_dma@19", "di"), | |
873 | SIC (1, 13, "bfin_twi@0", "stat"), | |
874 | SIC (1, 14, "bfin_twi@1", "stat"), | |
875 | SIC (1, 15, "bfin_can@0", "rx"), | |
876 | SIC (1, 16, "bfin_can@0", "tx"), | |
877 | SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */ | |
878 | SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */ | |
879 | SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */ | |
880 | SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */ | |
881 | }; | |
882 | #define bf539_port bf538_port | |
ef016f83 MF |
883 | |
884 | #define bf54x_chipid 0x27de | |
885 | #define bf542_chipid bf54x_chipid | |
886 | #define bf544_chipid bf54x_chipid | |
887 | #define bf547_chipid bf54x_chipid | |
888 | #define bf548_chipid bf54x_chipid | |
889 | #define bf549_chipid bf54x_chipid | |
990d19fd MF |
890 | static const struct bfin_memory_layout bf54x_mem[] = |
891 | { | |
ef016f83 MF |
892 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */ |
893 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
894 | LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */ |
895 | LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */ | |
896 | LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */ | |
897 | LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */ | |
898 | LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */ | |
899 | LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */ | |
900 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
901 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
902 | LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ | |
903 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
904 | LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ | |
905 | LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ | |
906 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
907 | }; | |
908 | #define bf542_mem bf54x_mem | |
909 | #define bf544_mem bf54x_mem | |
910 | #define bf547_mem bf54x_mem | |
911 | #define bf548_mem bf54x_mem | |
912 | #define bf549_mem bf54x_mem | |
990d19fd MF |
913 | static const struct bfin_dev_layout bf542_dev[] = |
914 | { | |
ef016f83 MF |
915 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
916 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
917 | DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), | |
918 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
919 | DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
920 | DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), | |
921 | DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), | |
922 | _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), | |
050396e5 MF |
923 | DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"), |
924 | DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"), | |
925 | _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2), | |
926 | _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2), | |
07c5891d MF |
927 | DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), |
928 | DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), | |
929 | DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), | |
930 | DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), | |
931 | DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), | |
932 | DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), | |
933 | DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), | |
934 | DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), | |
935 | DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), | |
936 | DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), | |
ef016f83 MF |
937 | DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), |
938 | DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
939 | DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
940 | DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
941 | DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
942 | DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
943 | DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
944 | DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
945 | DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), | |
946 | _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), | |
947 | DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), | |
948 | _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), | |
949 | _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), | |
950 | DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), | |
951 | DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"), | |
952 | }; | |
990d19fd MF |
953 | static const struct bfin_dev_layout bf544_dev[] = |
954 | { | |
ef016f83 MF |
955 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
956 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
957 | DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), | |
958 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
959 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), | |
960 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), | |
961 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), | |
962 | DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
963 | DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), | |
964 | DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), | |
965 | _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1), | |
966 | _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), | |
050396e5 MF |
967 | DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"), |
968 | DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"), | |
969 | _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2), | |
970 | _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2), | |
07c5891d MF |
971 | DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), |
972 | DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), | |
973 | DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), | |
974 | DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), | |
975 | DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), | |
976 | DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), | |
977 | DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), | |
978 | DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), | |
979 | DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), | |
980 | DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), | |
ef016f83 MF |
981 | DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), |
982 | DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
983 | DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
984 | DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
985 | DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
986 | DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
987 | DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
988 | DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
989 | DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), | |
990 | _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), | |
991 | DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), | |
992 | DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), | |
993 | _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), | |
994 | _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), | |
995 | DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), | |
996 | DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"), | |
997 | }; | |
990d19fd MF |
998 | static const struct bfin_dev_layout bf547_dev[] = |
999 | { | |
ef016f83 MF |
1000 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
1001 | DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), | |
1002 | DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), | |
1003 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
1004 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), | |
1005 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), | |
1006 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), | |
1007 | DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
1008 | DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), | |
1009 | DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), | |
1010 | _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1), | |
1011 | _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), | |
050396e5 MF |
1012 | DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"), |
1013 | DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"), | |
1014 | _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2), | |
1015 | _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2), | |
07c5891d MF |
1016 | DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), |
1017 | DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), | |
1018 | DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), | |
1019 | DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), | |
1020 | DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), | |
1021 | DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), | |
1022 | DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), | |
1023 | DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), | |
1024 | DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), | |
1025 | DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), | |
ef016f83 MF |
1026 | DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), |
1027 | DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
1028 | DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
1029 | DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
1030 | DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
1031 | DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
1032 | DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
1033 | DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
1034 | DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), | |
1035 | _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), | |
1036 | DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), | |
1037 | DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), | |
1038 | _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1), | |
1039 | _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), | |
1040 | _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), | |
1041 | DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), | |
1042 | }; | |
1043 | #define bf548_dev bf547_dev | |
1044 | #define bf549_dev bf547_dev | |
990d19fd MF |
1045 | static const struct bfin_dmac_layout bf54x_dmac[] = |
1046 | { | |
ef016f83 MF |
1047 | { BFIN_MMR_DMAC0_BASE, 12, }, |
1048 | { BFIN_MMR_DMAC1_BASE, 12, }, | |
1049 | }; | |
1050 | #define bf542_dmac bf54x_dmac | |
1051 | #define bf544_dmac bf54x_dmac | |
1052 | #define bf547_dmac bf54x_dmac | |
1053 | #define bf548_dmac bf54x_dmac | |
1054 | #define bf549_dmac bf54x_dmac | |
050396e5 MF |
1055 | #define PINT_PIQS(p, b, g) \ |
1056 | PORT (p, "piq0@"#b, g, "p0"), \ | |
1057 | PORT (p, "piq1@"#b, g, "p1"), \ | |
1058 | PORT (p, "piq2@"#b, g, "p2"), \ | |
1059 | PORT (p, "piq3@"#b, g, "p3"), \ | |
1060 | PORT (p, "piq4@"#b, g, "p4"), \ | |
1061 | PORT (p, "piq5@"#b, g, "p5"), \ | |
1062 | PORT (p, "piq6@"#b, g, "p6"), \ | |
1063 | PORT (p, "piq7@"#b, g, "p7"), \ | |
1064 | PORT (p, "piq8@"#b, g, "p8"), \ | |
1065 | PORT (p, "piq9@"#b, g, "p9"), \ | |
1066 | PORT (p, "piq10@"#b, g, "p10"), \ | |
1067 | PORT (p, "piq11@"#b, g, "p11"), \ | |
1068 | PORT (p, "piq12@"#b, g, "p12"), \ | |
1069 | PORT (p, "piq13@"#b, g, "p13"), \ | |
1070 | PORT (p, "piq14@"#b, g, "p14"), \ | |
1071 | PORT (p, "piq15@"#b, g, "p15") | |
082e1c4a MF |
1072 | static const struct bfin_port_layout bf54x_port[] = |
1073 | { | |
1074 | SIC (0, 0, "bfin_pll", "pll"), | |
1075 | SIC (0, 1, "bfin_dmac@0", "stat"), | |
1076 | SIC (0, 2, "bfin_eppi@0", "stat"), | |
1077 | SIC (0, 3, "bfin_sport@0", "stat"), | |
1078 | SIC (0, 4, "bfin_sport@1", "stat"), | |
1079 | SIC (0, 5, "bfin_spi@0", "stat"), | |
1080 | SIC (0, 6, "bfin_uart2@0", "stat"), | |
1081 | SIC (0, 7, "bfin_rtc", "rtc"), | |
1082 | SIC (0, 8, "bfin_dma@12", "di"), | |
1083 | SIC (0, 9, "bfin_dma@0", "di"), | |
1084 | SIC (0, 10, "bfin_dma@1", "di"), | |
1085 | SIC (0, 11, "bfin_dma@2", "di"), | |
1086 | SIC (0, 12, "bfin_dma@3", "di"), | |
1087 | SIC (0, 13, "bfin_dma@4", "di"), | |
1088 | SIC (0, 14, "bfin_dma@6", "di"), | |
1089 | SIC (0, 15, "bfin_dma@7", "di"), | |
1090 | SIC (0, 16, "bfin_gptimer@8", "stat"), | |
1091 | SIC (0, 17, "bfin_gptimer@9", "stat"), | |
1092 | SIC (0, 18, "bfin_gptimer@10", "stat"), | |
1093 | SIC (0, 19, "bfin_pint@0", "stat"), | |
050396e5 MF |
1094 | PINT_PIQS ("bfin_pint@0", 0, "bfin_gpio2@0"), |
1095 | PINT_PIQS ("bfin_pint@0", 1, "bfin_gpio2@1"), | |
082e1c4a | 1096 | SIC (0, 20, "bfin_pint@1", "stat"), |
050396e5 MF |
1097 | PINT_PIQS ("bfin_pint@1", 0, "bfin_gpio2@0"), |
1098 | PINT_PIQS ("bfin_pint@1", 1, "bfin_gpio2@1"), | |
082e1c4a MF |
1099 | SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */ |
1100 | SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */ | |
1101 | SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */ | |
1102 | SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */ | |
1103 | SIC (0, 23, "bfin_wdog@0", "gpi"), | |
1104 | SIC (0, 24, "bfin_dmac@1", "stat"), | |
1105 | SIC (0, 25, "bfin_sport@2", "stat"), | |
1106 | SIC (0, 26, "bfin_sport@3", "stat"), | |
1107 | SIC (0, 27, "bfin_mxvr", "data"), | |
1108 | SIC (0, 28, "bfin_spi@1", "stat"), | |
1109 | SIC (0, 29, "bfin_spi@2", "stat"), | |
1110 | SIC (0, 30, "bfin_uart2@1", "stat"), | |
1111 | SIC (0, 31, "bfin_uart2@2", "stat"), | |
1112 | SIC (1, 0, "bfin_can@0", "stat"), | |
1113 | SIC (1, 1, "bfin_dma@18", "di"), | |
1114 | SIC (1, 2, "bfin_dma@19", "di"), | |
1115 | SIC (1, 3, "bfin_dma@20", "di"), | |
1116 | SIC (1, 4, "bfin_dma@21", "di"), | |
1117 | SIC (1, 5, "bfin_dma@13", "di"), | |
1118 | SIC (1, 6, "bfin_dma@14", "di"), | |
1119 | SIC (1, 7, "bfin_dma@5", "di"), | |
1120 | SIC (1, 8, "bfin_dma@23", "di"), | |
1121 | SIC (1, 9, "bfin_dma@8", "di"), | |
1122 | SIC (1, 10, "bfin_dma@9", "di"), | |
1123 | SIC (1, 11, "bfin_dma@10", "di"), | |
1124 | SIC (1, 12, "bfin_dma@11", "di"), | |
1125 | SIC (1, 13, "bfin_twi@0", "stat"), | |
1126 | SIC (1, 14, "bfin_twi@1", "stat"), | |
1127 | SIC (1, 15, "bfin_can@0", "rx"), | |
1128 | SIC (1, 16, "bfin_can@0", "tx"), | |
1129 | SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */ | |
1130 | SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */ | |
1131 | SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */ | |
1132 | SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */ | |
1133 | SIC (1, 19, "bfin_mxvr", "stat"), | |
1134 | SIC (1, 20, "bfin_mxvr", "message"), | |
1135 | SIC (1, 21, "bfin_mxvr", "packet"), | |
1136 | SIC (1, 22, "bfin_eppi@1", "stat"), | |
1137 | SIC (1, 23, "bfin_eppi@2", "stat"), | |
1138 | SIC (1, 24, "bfin_uart2@3", "stat"), | |
1139 | SIC (1, 25, "bfin_hostdp", "stat"), | |
1140 | /*SIC (1, 26, reserved),*/ | |
1141 | SIC (1, 27, "bfin_pixc", "stat"), | |
1142 | SIC (1, 28, "bfin_nfc", "stat"), | |
1143 | SIC (1, 29, "bfin_atapi", "stat"), | |
1144 | SIC (1, 30, "bfin_can@1", "stat"), | |
1145 | SIC (1, 31, "bfin_dmar@0", "block"), | |
1146 | SIC (1, 31, "bfin_dmar@1", "block"), | |
1147 | SIC (1, 31, "bfin_dmar@0", "overflow"), | |
1148 | SIC (1, 31, "bfin_dmar@1", "overflow"), | |
1149 | SIC (2, 0, "bfin_dma@15", "di"), | |
1150 | SIC (2, 1, "bfin_dma@16", "di"), | |
1151 | SIC (2, 2, "bfin_dma@17", "di"), | |
1152 | SIC (2, 3, "bfin_dma@22", "di"), | |
1153 | SIC (2, 4, "bfin_counter@0", "stat"), | |
1154 | SIC (2, 5, "bfin_kpad@0", "stat"), | |
1155 | SIC (2, 6, "bfin_can@1", "rx"), | |
1156 | SIC (2, 7, "bfin_can@1", "tx"), | |
1157 | SIC (2, 8, "bfin_sdh", "mask0"), | |
1158 | SIC (2, 9, "bfin_sdh", "mask1"), | |
1159 | /*SIC (2, 10, reserved),*/ | |
1160 | SIC (2, 11, "bfin_usb", "int0"), | |
1161 | SIC (2, 12, "bfin_usb", "int1"), | |
1162 | SIC (2, 13, "bfin_usb", "int2"), | |
1163 | SIC (2, 14, "bfin_usb", "dma"), | |
1164 | SIC (2, 15, "bfin_otp", "stat"), | |
1165 | /*SIC (2, 16, reserved),*/ | |
1166 | /*SIC (2, 17, reserved),*/ | |
1167 | /*SIC (2, 18, reserved),*/ | |
1168 | /*SIC (2, 19, reserved),*/ | |
1169 | /*SIC (2, 20, reserved),*/ | |
1170 | /*SIC (2, 21, reserved),*/ | |
1171 | SIC (2, 22, "bfin_gptimer@0", "stat"), | |
1172 | SIC (2, 23, "bfin_gptimer@1", "stat"), | |
1173 | SIC (2, 24, "bfin_gptimer@2", "stat"), | |
1174 | SIC (2, 25, "bfin_gptimer@3", "stat"), | |
1175 | SIC (2, 26, "bfin_gptimer@4", "stat"), | |
1176 | SIC (2, 27, "bfin_gptimer@5", "stat"), | |
1177 | SIC (2, 28, "bfin_gptimer@6", "stat"), | |
1178 | SIC (2, 29, "bfin_gptimer@7", "stat"), | |
1179 | SIC (2, 30, "bfin_pint@2", "stat"), | |
050396e5 MF |
1180 | PINT_PIQS ("bfin_pint@2", 0, "bfin_gpio2@2"), |
1181 | PINT_PIQS ("bfin_pint@2", 1, "bfin_gpio2@3"), | |
1182 | PINT_PIQS ("bfin_pint@2", 2, "bfin_gpio2@4"), | |
1183 | PINT_PIQS ("bfin_pint@2", 3, "bfin_gpio2@5"), | |
1184 | PINT_PIQS ("bfin_pint@2", 4, "bfin_gpio2@6"), | |
1185 | PINT_PIQS ("bfin_pint@2", 5, "bfin_gpio2@7"), | |
1186 | PINT_PIQS ("bfin_pint@2", 6, "bfin_gpio2@8"), | |
1187 | PINT_PIQS ("bfin_pint@2", 7, "bfin_gpio2@9"), | |
082e1c4a | 1188 | SIC (2, 31, "bfin_pint@3", "stat"), |
050396e5 MF |
1189 | PINT_PIQS ("bfin_pint@3", 0, "bfin_gpio2@2"), |
1190 | PINT_PIQS ("bfin_pint@3", 1, "bfin_gpio2@3"), | |
1191 | PINT_PIQS ("bfin_pint@3", 2, "bfin_gpio2@4"), | |
1192 | PINT_PIQS ("bfin_pint@3", 3, "bfin_gpio2@5"), | |
1193 | PINT_PIQS ("bfin_pint@3", 4, "bfin_gpio2@6"), | |
1194 | PINT_PIQS ("bfin_pint@3", 5, "bfin_gpio2@7"), | |
1195 | PINT_PIQS ("bfin_pint@3", 6, "bfin_gpio2@8"), | |
1196 | PINT_PIQS ("bfin_pint@3", 7, "bfin_gpio2@9"), | |
082e1c4a MF |
1197 | }; |
1198 | #define bf542_port bf54x_port | |
1199 | #define bf544_port bf54x_port | |
1200 | #define bf547_port bf54x_port | |
1201 | #define bf548_port bf54x_port | |
1202 | #define bf549_port bf54x_port | |
ef016f83 MF |
1203 | |
1204 | /* This is only Core A of course ... */ | |
1205 | #define bf561_chipid 0x27bb | |
990d19fd MF |
1206 | static const struct bfin_memory_layout bf561_mem[] = |
1207 | { | |
ef016f83 MF |
1208 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
1209 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
1210 | LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */ |
1211 | LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ | |
1212 | LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ | |
1213 | LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ | |
1214 | LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ | |
1215 | LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ | |
1216 | LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ | |
1217 | }; | |
990d19fd MF |
1218 | static const struct bfin_dev_layout bf561_dev[] = |
1219 | { | |
ef016f83 MF |
1220 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
1221 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
1222 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
1223 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
1224 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
1225 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
1226 | DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), | |
1227 | DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), | |
1228 | DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), | |
1229 | DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), | |
1230 | DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), | |
a9c3ef47 | 1231 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
1232 | DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), |
1233 | DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), | |
1234 | _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1), | |
1235 | DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"), | |
1236 | _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1), | |
a9c3ef47 | 1237 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
ef016f83 MF |
1238 | DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), |
1239 | DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), | |
1240 | DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), | |
1241 | DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"), | |
a9c3ef47 | 1242 | DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), |
ef016f83 | 1243 | }; |
990d19fd MF |
1244 | static const struct bfin_dmac_layout bf561_dmac[] = |
1245 | { | |
ef016f83 MF |
1246 | { BFIN_MMR_DMAC0_BASE, 12, }, |
1247 | { BFIN_MMR_DMAC1_BASE, 12, }, | |
1248 | /* XXX: IMDMA: { 0xFFC01800, 4, }, */ | |
1249 | }; | |
082e1c4a MF |
1250 | static const struct bfin_port_layout bf561_port[] = |
1251 | { | |
1252 | /* SIC0 */ | |
1253 | SIC (0, 0, "bfin_pll", "pll"), | |
1254 | /*SIC (0, 1, "bfin_dmac@0", "stat"),*/ | |
1255 | /*SIC (0, 2, "bfin_dmac@1", "stat"),*/ | |
1256 | /*SIC (0, 3, "bfin_imdmac", "stat"),*/ | |
1257 | SIC (0, 4, "bfin_ppi@0", "stat"), | |
1258 | SIC (0, 5, "bfin_ppi@1", "stat"), | |
1259 | SIC (0, 6, "bfin_sport@0", "stat"), | |
1260 | SIC (0, 7, "bfin_sport@1", "stat"), | |
1261 | SIC (0, 8, "bfin_spi@0", "stat"), | |
1262 | SIC (0, 9, "bfin_uart@0", "stat"), | |
1263 | /*SIC (0, 10, reserved),*/ | |
1264 | SIC (0, 11, "bfin_dma@12", "di"), | |
1265 | SIC (0, 12, "bfin_dma@13", "di"), | |
1266 | SIC (0, 13, "bfin_dma@14", "di"), | |
1267 | SIC (0, 14, "bfin_dma@15", "di"), | |
1268 | SIC (0, 15, "bfin_dma@16", "di"), | |
1269 | SIC (0, 16, "bfin_dma@17", "di"), | |
1270 | SIC (0, 17, "bfin_dma@18", "di"), | |
1271 | SIC (0, 18, "bfin_dma@19", "di"), | |
1272 | SIC (0, 19, "bfin_dma@20", "di"), | |
1273 | SIC (0, 20, "bfin_dma@21", "di"), | |
1274 | SIC (0, 21, "bfin_dma@22", "di"), | |
1275 | SIC (0, 22, "bfin_dma@23", "di"), | |
1276 | SIC (0, 23, "bfin_dma@0", "di"), | |
1277 | SIC (0, 24, "bfin_dma@1", "di"), | |
1278 | SIC (0, 25, "bfin_dma@2", "di"), | |
1279 | SIC (0, 26, "bfin_dma@3", "di"), | |
1280 | SIC (0, 27, "bfin_dma@4", "di"), | |
1281 | SIC (0, 28, "bfin_dma@5", "di"), | |
1282 | SIC (0, 29, "bfin_dma@6", "di"), | |
1283 | SIC (0, 30, "bfin_dma@7", "di"), | |
1284 | SIC (0, 31, "bfin_dma@8", "di"), | |
1285 | SIC (1, 0, "bfin_dma@9", "di"), | |
1286 | SIC (1, 1, "bfin_dma@10", "di"), | |
1287 | SIC (1, 2, "bfin_dma@11", "di"), | |
1288 | SIC (1, 3, "bfin_gptimer@0", "stat"), | |
1289 | SIC (1, 4, "bfin_gptimer@1", "stat"), | |
1290 | SIC (1, 5, "bfin_gptimer@2", "stat"), | |
1291 | SIC (1, 6, "bfin_gptimer@3", "stat"), | |
1292 | SIC (1, 7, "bfin_gptimer@4", "stat"), | |
1293 | SIC (1, 8, "bfin_gptimer@5", "stat"), | |
1294 | SIC (1, 9, "bfin_gptimer@6", "stat"), | |
1295 | SIC (1, 10, "bfin_gptimer@7", "stat"), | |
1296 | SIC (1, 11, "bfin_gptimer@8", "stat"), | |
1297 | SIC (1, 12, "bfin_gptimer@9", "stat"), | |
1298 | SIC (1, 13, "bfin_gptimer@10", "stat"), | |
1299 | SIC (1, 14, "bfin_gptimer@11", "stat"), | |
1300 | SIC (1, 15, "bfin_gpio@5", "mask_a"), | |
1301 | SIC (1, 16, "bfin_gpio@5", "mask_b"), | |
1302 | SIC (1, 17, "bfin_gpio@6", "mask_a"), | |
1303 | SIC (1, 18, "bfin_gpio@6", "mask_b"), | |
1304 | SIC (1, 19, "bfin_gpio@7", "mask_a"), | |
1305 | SIC (1, 20, "bfin_gpio@7", "mask_b"), | |
1306 | SIC (1, 21, "bfin_dma@256", "di"), /* mdma0 */ | |
1307 | SIC (1, 21, "bfin_dma@257", "di"), /* mdma0 */ | |
1308 | SIC (1, 22, "bfin_dma@258", "di"), /* mdma1 */ | |
1309 | SIC (1, 22, "bfin_dma@259", "di"), /* mdma1 */ | |
1310 | SIC (1, 23, "bfin_dma@260", "di"), /* mdma2 */ | |
1311 | SIC (1, 23, "bfin_dma@261", "di"), /* mdma2 */ | |
1312 | SIC (1, 24, "bfin_dma@262", "di"), /* mdma3 */ | |
1313 | SIC (1, 24, "bfin_dma@263", "di"), /* mdma3 */ | |
1314 | SIC (1, 25, "bfin_imdma@0", "di"), | |
1315 | SIC (1, 26, "bfin_imdma@1", "di"), | |
1316 | SIC (1, 27, "bfin_wdog@0", "gpi"), | |
1317 | SIC (1, 27, "bfin_wdog@1", "gpi"), | |
1318 | /*SIC (1, 28, reserved),*/ | |
1319 | /*SIC (1, 29, reserved),*/ | |
1320 | SIC (1, 30, "bfin_sic", "sup_irq@0"), | |
1321 | SIC (1, 31, "bfin_sic", "sup_irq@1"), | |
1322 | }; | |
ef016f83 MF |
1323 | |
1324 | #define bf592_chipid 0x20cb | |
990d19fd MF |
1325 | static const struct bfin_memory_layout bf592_mem[] = |
1326 | { | |
ef016f83 MF |
1327 | LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ |
1328 | LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ | |
ef016f83 MF |
1329 | LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */ |
1330 | LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ | |
1331 | LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */ | |
1332 | }; | |
990d19fd MF |
1333 | static const struct bfin_dev_layout bf592_dev[] = |
1334 | { | |
ef016f83 MF |
1335 | DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), |
1336 | DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), | |
1337 | DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), | |
1338 | DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), | |
1339 | DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), | |
1340 | DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), | |
a9c3ef47 | 1341 | DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), |
ef016f83 MF |
1342 | DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), |
1343 | DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), | |
1344 | DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), | |
a9c3ef47 | 1345 | DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), |
ef016f83 | 1346 | }; |
990d19fd MF |
1347 | static const struct bfin_dmac_layout bf592_dmac[] = |
1348 | { | |
ef016f83 MF |
1349 | /* XXX: there are only 9 channels, but mdma code below assumes that they |
1350 | start right after the dma channels ... */ | |
1351 | { BFIN_MMR_DMAC0_BASE, 12, }, | |
1352 | }; | |
082e1c4a MF |
1353 | static const struct bfin_port_layout bf592_port[] = |
1354 | { | |
1355 | SIC (0, 0, "bfin_pll", "pll"), | |
1356 | /*SIC (0, 1, "bfin_dmac@0", "stat"),*/ | |
1357 | SIC (0, 2, "bfin_ppi@0", "stat"), | |
1358 | SIC (0, 3, "bfin_sport@0", "stat"), | |
1359 | SIC (0, 4, "bfin_sport@1", "stat"), | |
1360 | SIC (0, 5, "bfin_spi@0", "stat"), | |
1361 | SIC (0, 6, "bfin_spi@1", "stat"), | |
1362 | SIC (0, 7, "bfin_uart@0", "stat"), | |
1363 | SIC (0, 8, "bfin_dma@0", "di"), | |
1364 | SIC (0, 9, "bfin_dma@1", "di"), | |
1365 | SIC (0, 10, "bfin_dma@2", "di"), | |
1366 | SIC (0, 11, "bfin_dma@3", "di"), | |
1367 | SIC (0, 12, "bfin_dma@4", "di"), | |
1368 | SIC (0, 13, "bfin_dma@5", "di"), | |
1369 | SIC (0, 14, "bfin_dma@6", "di"), | |
1370 | SIC (0, 15, "bfin_dma@7", "di"), | |
1371 | SIC (0, 16, "bfin_dma@8", "di"), | |
1372 | SIC (0, 17, "bfin_gpio@5", "mask_a"), | |
1373 | SIC (0, 18, "bfin_gpio@5", "mask_b"), | |
1374 | SIC (0, 19, "bfin_gptimer@0", "stat"), | |
1375 | SIC (0, 20, "bfin_gptimer@1", "stat"), | |
1376 | SIC (0, 21, "bfin_gptimer@2", "stat"), | |
1377 | SIC (0, 22, "bfin_gpio@6", "mask_a"), | |
1378 | SIC (0, 23, "bfin_gpio@6", "mask_b"), | |
1379 | SIC (0, 24, "bfin_twi@0", "stat"), | |
1380 | /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */ | |
1381 | SIC (0, 25, "bfin_dma@9", "di"), | |
1382 | SIC (0, 26, "bfin_dma@10", "di"), | |
1383 | SIC (0, 27, "bfin_dma@11", "di"), | |
1384 | SIC (0, 28, "bfin_dma@12", "di"), | |
1385 | /*SIC (0, 25, reserved),*/ | |
1386 | /*SIC (0, 26, reserved),*/ | |
1387 | /*SIC (0, 27, reserved),*/ | |
1388 | /*SIC (0, 28, reserved),*/ | |
1389 | SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */ | |
1390 | SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */ | |
1391 | SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */ | |
1392 | SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */ | |
1393 | SIC (0, 31, "bfin_wdog", "gpi"), | |
1394 | }; | |
ef016f83 MF |
1395 | |
1396 | static const struct bfin_model_data bfin_model_data[] = | |
1397 | { | |
1398 | #define P(n) \ | |
1399 | [MODEL_BF##n] = { \ | |
1400 | bf##n##_chipid, n, \ | |
1401 | bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \ | |
1402 | bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \ | |
1403 | bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \ | |
082e1c4a | 1404 | bf##n##_port, ARRAY_SIZE (bf##n##_port), \ |
ef016f83 MF |
1405 | }, |
1406 | #include "proc_list.def" | |
1407 | #undef P | |
1408 | }; | |
1409 | ||
1410 | #define CORE_DEVICE(dev, DEV) \ | |
1411 | DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev) | |
990d19fd MF |
1412 | static const struct bfin_dev_layout bfin_core_dev[] = |
1413 | { | |
ef016f83 MF |
1414 | CORE_DEVICE (cec, CEC), |
1415 | CORE_DEVICE (ctimer, CTIMER), | |
1416 | CORE_DEVICE (evt, EVT), | |
1417 | CORE_DEVICE (jtag, JTAG), | |
1418 | CORE_DEVICE (mmu, MMU), | |
c43aadca | 1419 | CORE_DEVICE (pfmon, PFMON), |
ef016f83 MF |
1420 | CORE_DEVICE (trace, TRACE), |
1421 | CORE_DEVICE (wp, WP), | |
1422 | }; | |
1423 | ||
082e1c4a MF |
1424 | static void |
1425 | dv_bfin_hw_port_parse (SIM_DESC sd, const struct bfin_model_data *mdata, | |
1426 | const char *dev) | |
1427 | { | |
1428 | size_t i; | |
1429 | const char *sdev; | |
1430 | ||
1431 | sdev = strchr (dev, '/'); | |
1432 | if (sdev) | |
1433 | ++sdev; | |
1434 | else | |
1435 | sdev = dev; | |
1436 | ||
1437 | for (i = 0; i < mdata->port_count; ++i) | |
1438 | { | |
1439 | const struct bfin_port_layout *port = &mdata->port[i]; | |
1440 | ||
1441 | /* There might be more than one mapping. */ | |
1442 | if (!strcmp (sdev, port->src)) | |
1443 | sim_hw_parse (sd, "/core/%s > %s %s /core/%s", dev, | |
1444 | port->src_port, port->dst_port, port->dst); | |
1445 | } | |
1446 | } | |
1447 | ||
ef016f83 MF |
1448 | #define dv_bfin_hw_parse(sd, dv, DV) \ |
1449 | do { \ | |
1450 | bu32 base = BFIN_MMR_##DV##_BASE; \ | |
1451 | bu32 size = BFIN_MMR_##DV##_SIZE; \ | |
1452 | sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \ | |
1453 | sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \ | |
082e1c4a | 1454 | dv_bfin_hw_port_parse (sd, mdata, "bfin_"#dv); \ |
ef016f83 MF |
1455 | } while (0) |
1456 | ||
1457 | static void | |
1458 | bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu) | |
1459 | { | |
8a0ebee6 | 1460 | const SIM_MODEL *model = CPU_MODEL (cpu); |
ef016f83 MF |
1461 | const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); |
1462 | const struct bfin_board_data *board = STATE_BOARD_DATA (sd); | |
1463 | int mnum = MODEL_NUM (model); | |
1464 | unsigned i, j, dma_chan; | |
1465 | ||
1466 | /* Map the core devices. */ | |
1467 | for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i) | |
1468 | { | |
1469 | const struct bfin_dev_layout *dev = &bfin_core_dev[i]; | |
1470 | sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len); | |
1471 | } | |
1472 | sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec"); | |
1473 | ||
1474 | if (mnum == MODEL_BF000) | |
1475 | goto done; | |
1476 | ||
1477 | /* Map the system devices. */ | |
1478 | dv_bfin_hw_parse (sd, sic, SIC); | |
ef016f83 MF |
1479 | for (i = 7; i < 16; ++i) |
1480 | sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i); | |
1481 | ||
1482 | dv_bfin_hw_parse (sd, pll, PLL); | |
ef016f83 MF |
1483 | |
1484 | dma_chan = 0; | |
1485 | for (i = 0; i < mdata->dmac_count; ++i) | |
1486 | { | |
1487 | const struct bfin_dmac_layout *dmac = &mdata->dmac[i]; | |
1488 | ||
1489 | sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num); | |
1490 | ||
1491 | /* Hook up the non-mdma channels. */ | |
1492 | for (j = 0; j < dmac->dma_count; ++j) | |
1493 | { | |
082e1c4a | 1494 | char dev[64]; |
ef016f83 | 1495 | |
082e1c4a MF |
1496 | sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, dma_chan); |
1497 | sim_hw_parse (sd, "/core/%s/reg %#x %i", dev, | |
1498 | dmac->base + j * BFIN_MMR_DMA_SIZE, BFIN_MMR_DMA_SIZE); | |
1499 | dv_bfin_hw_port_parse (sd, mdata, dev); | |
ef016f83 MF |
1500 | |
1501 | ++dma_chan; | |
1502 | } | |
1503 | ||
1504 | /* Hook up the mdma channels -- assume every DMAC has 4. */ | |
1505 | for (j = 0; j < 4; ++j) | |
1506 | { | |
082e1c4a MF |
1507 | char dev[64]; |
1508 | ||
1509 | sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, j + BFIN_DMAC_MDMA_BASE); | |
1510 | sim_hw_parse (sd, "/core/%s/reg %#x %i", dev, | |
ef016f83 MF |
1511 | dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE, |
1512 | BFIN_MMR_DMA_SIZE); | |
082e1c4a | 1513 | dv_bfin_hw_port_parse (sd, mdata, dev); |
ef016f83 MF |
1514 | } |
1515 | } | |
1516 | ||
1517 | for (i = 0; i < mdata->dev_count; ++i) | |
1518 | { | |
1519 | const struct bfin_dev_layout *dev = &mdata->dev[i]; | |
082e1c4a | 1520 | |
eb324344 MF |
1521 | if (dev->len) |
1522 | { | |
1523 | sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len); | |
1524 | sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num); | |
1525 | } | |
1526 | else | |
1527 | { | |
1528 | sim_hw_parse (sd, "/core/%s", dev->dev); | |
1529 | } | |
1530 | ||
1531 | dv_bfin_hw_port_parse (sd, mdata, dev->dev); | |
ef016f83 MF |
1532 | if (strchr (dev->dev, '/')) |
1533 | continue; | |
082e1c4a | 1534 | |
ef016f83 MF |
1535 | if (!strncmp (dev->dev, "bfin_uart", 9) |
1536 | || !strncmp (dev->dev, "bfin_emac", 9) | |
1537 | || !strncmp (dev->dev, "bfin_sport", 10)) | |
1538 | { | |
1539 | const char *sint = dev->dev + 5; | |
1540 | sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac); | |
1541 | sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac); | |
ef016f83 MF |
1542 | } |
1543 | else if (!strncmp (dev->dev, "bfin_wdog", 9)) | |
1544 | { | |
1545 | sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev); | |
1546 | sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev); | |
b5215db0 | 1547 | } |
ef016f83 MF |
1548 | } |
1549 | ||
1550 | done: | |
1551 | /* Add any additional user board content. */ | |
1552 | if (board->hw_file) | |
1553 | sim_do_commandf (sd, "hw-file %s", board->hw_file); | |
1554 | ||
1555 | /* Trigger all the new devices' finish func. */ | |
1556 | hw_tree_finish (dv_get_device (cpu, "/")); | |
1557 | } | |
1558 | ||
1559 | #include "bfroms/all.h" | |
1560 | ||
1561 | struct bfrom { | |
1562 | bu32 addr, len, alias_len; | |
1563 | int sirev; | |
1564 | const char *buf; | |
1565 | }; | |
1566 | ||
1567 | #define BFROMA(addr, rom, sirev, alias_len) \ | |
1568 | { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \ | |
1569 | sirev, bfrom_bf##rom##_0_##sirev, } | |
1570 | #define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len) | |
1571 | #define BFROM_STUB { 0, 0, 0, 0, NULL, } | |
990d19fd MF |
1572 | static const struct bfrom bf50x_roms[] = |
1573 | { | |
ef016f83 MF |
1574 | BFROM (50x, 0, 0x1000000), |
1575 | BFROM_STUB, | |
1576 | }; | |
990d19fd MF |
1577 | static const struct bfrom bf51x_roms[] = |
1578 | { | |
ef016f83 MF |
1579 | BFROM (51x, 2, 0x1000000), |
1580 | BFROM (51x, 1, 0x1000000), | |
1581 | BFROM (51x, 0, 0x1000000), | |
1582 | BFROM_STUB, | |
1583 | }; | |
990d19fd MF |
1584 | static const struct bfrom bf526_roms[] = |
1585 | { | |
dfb61fb6 | 1586 | BFROM (526, 2, 0x1000000), |
ef016f83 MF |
1587 | BFROM (526, 1, 0x1000000), |
1588 | BFROM (526, 0, 0x1000000), | |
1589 | BFROM_STUB, | |
1590 | }; | |
990d19fd MF |
1591 | static const struct bfrom bf527_roms[] = |
1592 | { | |
ef016f83 MF |
1593 | BFROM (527, 2, 0x1000000), |
1594 | BFROM (527, 1, 0x1000000), | |
1595 | BFROM (527, 0, 0x1000000), | |
1596 | BFROM_STUB, | |
1597 | }; | |
990d19fd MF |
1598 | static const struct bfrom bf533_roms[] = |
1599 | { | |
ef016f83 MF |
1600 | BFROM (533, 6, 0x1000000), |
1601 | BFROM (533, 5, 0x1000000), | |
1602 | BFROM (533, 4, 0x1000000), | |
1603 | BFROM (533, 3, 0x1000000), | |
1604 | BFROM (533, 2, 0x1000000), | |
1605 | BFROM (533, 1, 0x1000000), | |
1606 | BFROM_STUB, | |
1607 | }; | |
990d19fd MF |
1608 | static const struct bfrom bf537_roms[] = |
1609 | { | |
ef016f83 MF |
1610 | BFROM (537, 3, 0x100000), |
1611 | BFROM (537, 2, 0x100000), | |
1612 | BFROM (537, 1, 0x100000), | |
1613 | BFROM (537, 0, 0x100000), | |
1614 | BFROM_STUB, | |
1615 | }; | |
990d19fd MF |
1616 | static const struct bfrom bf538_roms[] = |
1617 | { | |
ef016f83 MF |
1618 | BFROM (538, 5, 0x1000000), |
1619 | BFROM (538, 4, 0x1000000), | |
1620 | BFROM (538, 3, 0x1000000), | |
1621 | BFROM (538, 2, 0x1000000), | |
1622 | BFROM (538, 1, 0x1000000), | |
1623 | BFROM (538, 0, 0x1000000), | |
1624 | BFROM_STUB, | |
1625 | }; | |
990d19fd MF |
1626 | static const struct bfrom bf54x_roms[] = |
1627 | { | |
040a4d10 MF |
1628 | BFROM (54x, 4, 0x1000), |
1629 | BFROM (54x, 2, 0x1000), | |
1630 | BFROM (54x, 1, 0x1000), | |
1631 | BFROM (54x, 0, 0x1000), | |
1632 | BFROMA (0xffa14000, 54x_l1, 4, 0x10000), | |
1633 | BFROMA (0xffa14000, 54x_l1, 2, 0x10000), | |
1634 | BFROMA (0xffa14000, 54x_l1, 1, 0x10000), | |
1635 | BFROMA (0xffa14000, 54x_l1, 0, 0x10000), | |
ef016f83 MF |
1636 | BFROM_STUB, |
1637 | }; | |
990d19fd MF |
1638 | static const struct bfrom bf561_roms[] = |
1639 | { | |
ef016f83 | 1640 | /* XXX: No idea what the actual wrap limit is here. */ |
040a4d10 | 1641 | BFROM (561, 5, 0x1000), |
ef016f83 MF |
1642 | BFROM_STUB, |
1643 | }; | |
990d19fd MF |
1644 | static const struct bfrom bf59x_roms[] = |
1645 | { | |
ef016f83 MF |
1646 | BFROM (59x, 1, 0x1000000), |
1647 | BFROM (59x, 0, 0x1000000), | |
040a4d10 | 1648 | BFROMA (0xffa10000, 59x_l1, 1, 0x10000), |
ef016f83 MF |
1649 | BFROM_STUB, |
1650 | }; | |
1651 | ||
1652 | static void | |
1653 | bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu) | |
1654 | { | |
1655 | const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); | |
1656 | const struct bfin_board_data *board = STATE_BOARD_DATA (sd); | |
1657 | int mnum = mdata->model_num; | |
1658 | const struct bfrom *bfrom; | |
1659 | unsigned int sirev; | |
1660 | ||
1661 | if (mnum >= 500 && mnum <= 509) | |
1662 | bfrom = bf50x_roms; | |
1663 | else if (mnum >= 510 && mnum <= 519) | |
1664 | bfrom = bf51x_roms; | |
1665 | else if (mnum >= 520 && mnum <= 529) | |
1666 | bfrom = (mnum & 1) ? bf527_roms : bf526_roms; | |
1667 | else if (mnum >= 531 && mnum <= 533) | |
1668 | bfrom = bf533_roms; | |
1669 | else if (mnum == 535) | |
02bb38cc | 1670 | return; /* Stub. */ |
ef016f83 MF |
1671 | else if (mnum >= 534 && mnum <= 537) |
1672 | bfrom = bf537_roms; | |
1673 | else if (mnum >= 538 && mnum <= 539) | |
1674 | bfrom = bf538_roms; | |
1675 | else if (mnum >= 540 && mnum <= 549) | |
1676 | bfrom = bf54x_roms; | |
1677 | else if (mnum == 561) | |
1678 | bfrom = bf561_roms; | |
1679 | else if (mnum >= 590 && mnum <= 599) | |
1680 | bfrom = bf59x_roms; | |
1681 | else | |
1682 | return; | |
1683 | ||
1684 | if (board->sirev_valid) | |
1685 | sirev = board->sirev; | |
1686 | else | |
1687 | sirev = bfrom->sirev; | |
1688 | while (bfrom->buf) | |
1689 | { | |
1690 | /* Map all the ranges for this model/sirev. */ | |
1691 | if (bfrom->sirev == sirev) | |
1692 | sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr, | |
1693 | bfrom->alias_len ? : bfrom->len, bfrom->len, NULL, | |
1694 | (char *)bfrom->buf); | |
1695 | ++bfrom; | |
1696 | } | |
1697 | } | |
1698 | ||
1699 | void | |
1700 | bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu) | |
1701 | { | |
8a0ebee6 | 1702 | const SIM_MODEL *model = CPU_MODEL (cpu); |
ef016f83 MF |
1703 | const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); |
1704 | int mnum = MODEL_NUM (model); | |
1705 | size_t idx; | |
1706 | ||
1707 | /* These memory maps are supposed to be cpu-specific, but the common sim | |
1708 | code does not yet allow that (2nd arg is "cpu" rather than "NULL". */ | |
1709 | sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH, | |
1710 | BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL); | |
1711 | ||
1712 | if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT) | |
1713 | return; | |
1714 | ||
1715 | if (mnum == MODEL_BF000) | |
1716 | goto core_only; | |
1717 | ||
1718 | /* Map in the on-chip memories (SRAMs). */ | |
1719 | mdata = &bfin_model_data[MODEL_NUM (model)]; | |
1720 | for (idx = 0; idx < mdata->mem_count; ++idx) | |
1721 | { | |
1722 | const struct bfin_memory_layout *mem = &mdata->mem[idx]; | |
1723 | sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr, | |
1724 | mem->len, 0, NULL, NULL); | |
1725 | } | |
1726 | ||
1727 | /* Map the on-chip ROMs. */ | |
1728 | bfin_model_map_bfrom (sd, cpu); | |
1729 | ||
1730 | core_only: | |
1731 | /* Finally, build up the tree for this cpu model. */ | |
1732 | bfin_model_hw_tree_init (sd, cpu); | |
1733 | } | |
1734 | ||
1735 | bu32 | |
1736 | bfin_model_get_chipid (SIM_DESC sd) | |
1737 | { | |
1738 | SIM_CPU *cpu = STATE_CPU (sd, 0); | |
1739 | const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); | |
1740 | const struct bfin_board_data *board = STATE_BOARD_DATA (sd); | |
1741 | return | |
1742 | (board->sirev << 28) | | |
1743 | (mdata->chipid << 12) | | |
1744 | (((0xE5 << 1) | 1) & 0xFF); | |
1745 | } | |
1746 | ||
1747 | bu32 | |
1748 | bfin_model_get_dspid (SIM_DESC sd) | |
1749 | { | |
1750 | const struct bfin_board_data *board = STATE_BOARD_DATA (sd); | |
1751 | return | |
1752 | (0xE5 << 24) | | |
1753 | (0x04 << 16) | | |
1754 | (board->sirev); | |
1755 | } | |
1756 | ||
1757 | static void | |
1758 | bfin_model_init (SIM_CPU *cpu) | |
1759 | { | |
1760 | CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))]; | |
1761 | } | |
1762 | ||
1763 | static bu32 | |
ed60d3ed | 1764 | bfin_extract_unsigned_integer (const unsigned char *addr, int len) |
ef016f83 MF |
1765 | { |
1766 | bu32 retval; | |
1767 | unsigned char * p; | |
1768 | unsigned char * startaddr = (unsigned char *)addr; | |
1769 | unsigned char * endaddr = startaddr + len; | |
1770 | ||
1771 | retval = 0; | |
1772 | ||
1773 | for (p = endaddr; p > startaddr;) | |
1774 | retval = (retval << 8) | *--p; | |
1775 | ||
1776 | return retval; | |
1777 | } | |
1778 | ||
1779 | static void | |
1780 | bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val) | |
1781 | { | |
1782 | unsigned char *p; | |
1783 | unsigned char *startaddr = addr; | |
1784 | unsigned char *endaddr = startaddr + len; | |
1785 | ||
1786 | for (p = startaddr; p < endaddr;) | |
1787 | { | |
1788 | *p++ = val & 0xff; | |
1789 | val >>= 8; | |
1790 | } | |
1791 | } | |
1792 | ||
1793 | static bu32 * | |
1794 | bfin_get_reg (SIM_CPU *cpu, int rn) | |
1795 | { | |
1796 | switch (rn) | |
1797 | { | |
1798 | case SIM_BFIN_R0_REGNUM: return &DREG (0); | |
1799 | case SIM_BFIN_R1_REGNUM: return &DREG (1); | |
1800 | case SIM_BFIN_R2_REGNUM: return &DREG (2); | |
1801 | case SIM_BFIN_R3_REGNUM: return &DREG (3); | |
1802 | case SIM_BFIN_R4_REGNUM: return &DREG (4); | |
1803 | case SIM_BFIN_R5_REGNUM: return &DREG (5); | |
1804 | case SIM_BFIN_R6_REGNUM: return &DREG (6); | |
1805 | case SIM_BFIN_R7_REGNUM: return &DREG (7); | |
1806 | case SIM_BFIN_P0_REGNUM: return &PREG (0); | |
1807 | case SIM_BFIN_P1_REGNUM: return &PREG (1); | |
1808 | case SIM_BFIN_P2_REGNUM: return &PREG (2); | |
1809 | case SIM_BFIN_P3_REGNUM: return &PREG (3); | |
1810 | case SIM_BFIN_P4_REGNUM: return &PREG (4); | |
1811 | case SIM_BFIN_P5_REGNUM: return &PREG (5); | |
1812 | case SIM_BFIN_SP_REGNUM: return &SPREG; | |
1813 | case SIM_BFIN_FP_REGNUM: return &FPREG; | |
1814 | case SIM_BFIN_I0_REGNUM: return &IREG (0); | |
1815 | case SIM_BFIN_I1_REGNUM: return &IREG (1); | |
1816 | case SIM_BFIN_I2_REGNUM: return &IREG (2); | |
1817 | case SIM_BFIN_I3_REGNUM: return &IREG (3); | |
1818 | case SIM_BFIN_M0_REGNUM: return &MREG (0); | |
1819 | case SIM_BFIN_M1_REGNUM: return &MREG (1); | |
1820 | case SIM_BFIN_M2_REGNUM: return &MREG (2); | |
1821 | case SIM_BFIN_M3_REGNUM: return &MREG (3); | |
1822 | case SIM_BFIN_B0_REGNUM: return &BREG (0); | |
1823 | case SIM_BFIN_B1_REGNUM: return &BREG (1); | |
1824 | case SIM_BFIN_B2_REGNUM: return &BREG (2); | |
1825 | case SIM_BFIN_B3_REGNUM: return &BREG (3); | |
1826 | case SIM_BFIN_L0_REGNUM: return &LREG (0); | |
1827 | case SIM_BFIN_L1_REGNUM: return &LREG (1); | |
1828 | case SIM_BFIN_L2_REGNUM: return &LREG (2); | |
1829 | case SIM_BFIN_L3_REGNUM: return &LREG (3); | |
1830 | case SIM_BFIN_RETS_REGNUM: return &RETSREG; | |
1831 | case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0); | |
1832 | case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0); | |
1833 | case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1); | |
1834 | case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1); | |
1835 | case SIM_BFIN_LC0_REGNUM: return &LCREG (0); | |
1836 | case SIM_BFIN_LT0_REGNUM: return <REG (0); | |
1837 | case SIM_BFIN_LB0_REGNUM: return &LBREG (0); | |
1838 | case SIM_BFIN_LC1_REGNUM: return &LCREG (1); | |
1839 | case SIM_BFIN_LT1_REGNUM: return <REG (1); | |
1840 | case SIM_BFIN_LB1_REGNUM: return &LBREG (1); | |
1841 | case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG; | |
1842 | case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG; | |
1843 | case SIM_BFIN_USP_REGNUM: return &USPREG; | |
1844 | case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG; | |
1845 | case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG; | |
1846 | case SIM_BFIN_RETI_REGNUM: return &RETIREG; | |
1847 | case SIM_BFIN_RETX_REGNUM: return &RETXREG; | |
1848 | case SIM_BFIN_RETN_REGNUM: return &RETNREG; | |
1849 | case SIM_BFIN_RETE_REGNUM: return &RETEREG; | |
1850 | case SIM_BFIN_PC_REGNUM: return &PCREG; | |
1851 | default: return NULL; | |
1852 | } | |
1853 | } | |
1854 | ||
1855 | static int | |
ee1cffd3 | 1856 | bfin_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int len) |
ef016f83 MF |
1857 | { |
1858 | bu32 value, *reg; | |
1859 | ||
1860 | reg = bfin_get_reg (cpu, rn); | |
1861 | if (reg) | |
1862 | value = *reg; | |
1863 | else if (rn == SIM_BFIN_ASTAT_REGNUM) | |
1864 | value = ASTAT; | |
1865 | else if (rn == SIM_BFIN_CC_REGNUM) | |
1866 | value = CCREG; | |
1867 | else | |
b5539f23 | 1868 | return -1; |
ef016f83 MF |
1869 | |
1870 | /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we | |
1871 | have the normal SP/USP behavior. User mode is tricky though. */ | |
1872 | if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT | |
1873 | && cec_is_user_mode (cpu)) | |
1874 | { | |
1875 | if (rn == SIM_BFIN_SP_REGNUM) | |
1876 | value = KSPREG; | |
1877 | else if (rn == SIM_BFIN_USP_REGNUM) | |
1878 | value = SPREG; | |
1879 | } | |
1880 | ||
1881 | bfin_store_unsigned_integer (buf, 4, value); | |
1882 | ||
b5539f23 | 1883 | return 4; |
ef016f83 MF |
1884 | } |
1885 | ||
1886 | static int | |
ee1cffd3 | 1887 | bfin_reg_store (SIM_CPU *cpu, int rn, const void *buf, int len) |
ef016f83 MF |
1888 | { |
1889 | bu32 value, *reg; | |
1890 | ||
1891 | value = bfin_extract_unsigned_integer (buf, 4); | |
1892 | reg = bfin_get_reg (cpu, rn); | |
1893 | ||
1894 | if (reg) | |
1895 | /* XXX: Need register trace ? */ | |
1896 | *reg = value; | |
1897 | else if (rn == SIM_BFIN_ASTAT_REGNUM) | |
1898 | SET_ASTAT (value); | |
1899 | else if (rn == SIM_BFIN_CC_REGNUM) | |
1900 | SET_CCREG (value); | |
1901 | else | |
b5539f23 | 1902 | return -1; |
ef016f83 | 1903 | |
b5539f23 | 1904 | return 4; |
ef016f83 MF |
1905 | } |
1906 | ||
1907 | static sim_cia | |
1908 | bfin_pc_get (SIM_CPU *cpu) | |
1909 | { | |
1910 | return PCREG; | |
1911 | } | |
1912 | ||
1913 | static void | |
1914 | bfin_pc_set (SIM_CPU *cpu, sim_cia newpc) | |
1915 | { | |
1916 | SET_PCREG (newpc); | |
1917 | } | |
1918 | ||
1919 | static const char * | |
1920 | bfin_insn_name (SIM_CPU *cpu, int i) | |
1921 | { | |
1922 | static const char * const insn_name[] = { | |
1923 | #define I(insn) #insn, | |
1924 | #include "insn_list.def" | |
1925 | #undef I | |
1926 | }; | |
1927 | return insn_name[i]; | |
1928 | } | |
1929 | ||
1930 | static void | |
1931 | bfin_init_cpu (SIM_CPU *cpu) | |
1932 | { | |
1933 | CPU_REG_FETCH (cpu) = bfin_reg_fetch; | |
1934 | CPU_REG_STORE (cpu) = bfin_reg_store; | |
1935 | CPU_PC_FETCH (cpu) = bfin_pc_get; | |
1936 | CPU_PC_STORE (cpu) = bfin_pc_set; | |
1937 | CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX; | |
1938 | CPU_INSN_NAME (cpu) = bfin_insn_name; | |
1939 | } | |
1940 | ||
1941 | static void | |
1942 | bfin_prepare_run (SIM_CPU *cpu) | |
1943 | { | |
1944 | } | |
1945 | ||
8a0ebee6 | 1946 | static const SIM_MODEL bfin_models[] = |
ef016f83 MF |
1947 | { |
1948 | #define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init }, | |
1949 | #include "proc_list.def" | |
1950 | #undef P | |
1951 | { 0, NULL, 0, NULL, NULL, } | |
1952 | }; | |
1953 | ||
8a0ebee6 | 1954 | static const SIM_MACH_IMP_PROPERTIES bfin_imp_properties = |
ef016f83 MF |
1955 | { |
1956 | sizeof (SIM_CPU), | |
1957 | 0, | |
1958 | }; | |
1959 | ||
8a0ebee6 | 1960 | static const SIM_MACH bfin_mach = |
ef016f83 MF |
1961 | { |
1962 | "bfin", "bfin", MACH_BFIN, | |
1963 | 32, 32, & bfin_models[0], & bfin_imp_properties, | |
1964 | bfin_init_cpu, | |
1965 | bfin_prepare_run | |
1966 | }; | |
1967 | ||
1c636da0 | 1968 | const SIM_MACH * const bfin_sim_machs[] = |
ef016f83 MF |
1969 | { |
1970 | & bfin_mach, | |
1971 | NULL | |
1972 | }; | |
1973 | \f | |
1974 | /* Device option parsing. */ | |
1975 | ||
1976 | static DECLARE_OPTION_HANDLER (bfin_mach_option_handler); | |
1977 | ||
1978 | enum { | |
1979 | OPTION_MACH_SIREV = OPTION_START, | |
1980 | OPTION_MACH_HW_BOARD_FILE, | |
1981 | }; | |
1982 | ||
d89a87ba | 1983 | static const OPTION bfin_mach_options[] = |
ef016f83 MF |
1984 | { |
1985 | { {"sirev", required_argument, NULL, OPTION_MACH_SIREV }, | |
1986 | '\0', "NUMBER", "Set CPU silicon revision", | |
1987 | bfin_mach_option_handler, NULL }, | |
1988 | ||
1989 | { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE }, | |
1990 | '\0', "FILE", "Add the supplemental devices listed in the file", | |
1991 | bfin_mach_option_handler, NULL }, | |
1992 | ||
1993 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL } | |
1994 | }; | |
1995 | ||
1996 | static SIM_RC | |
1997 | bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt, | |
1998 | char *arg, int is_command) | |
1999 | { | |
2000 | struct bfin_board_data *board = STATE_BOARD_DATA (sd); | |
2001 | ||
2002 | switch (opt) | |
2003 | { | |
2004 | case OPTION_MACH_SIREV: | |
2005 | board->sirev_valid = 1; | |
2006 | /* Accept (and throw away) a leading "0." in the version. */ | |
2007 | if (!strncmp (arg, "0.", 2)) | |
2008 | arg += 2; | |
2009 | board->sirev = atoi (arg); | |
2010 | if (board->sirev > 0xf) | |
2011 | { | |
2012 | sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg); | |
2013 | return SIM_RC_FAIL; | |
2014 | } | |
2015 | return SIM_RC_OK; | |
2016 | ||
2017 | case OPTION_MACH_HW_BOARD_FILE: | |
2018 | board->hw_file = xstrdup (arg); | |
2019 | return SIM_RC_OK; | |
2020 | ||
2021 | default: | |
2022 | sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt); | |
2023 | return SIM_RC_FAIL; | |
2024 | } | |
2025 | } | |
d89a87ba MF |
2026 | |
2027 | /* Provide a prototype to silence -Wmissing-prototypes. */ | |
2028 | extern MODULE_INIT_FN sim_install_bfin_mach; | |
2029 | ||
2030 | SIM_RC | |
2031 | sim_install_bfin_mach (SIM_DESC sd) | |
2032 | { | |
2033 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
2034 | return sim_add_option_table (sd, NULL, bfin_mach_options); | |
2035 | } |