[thirdparty/binutils-gdb.git] / sim / common / cgen-par.h

/* Simulator header for cgen parallel support.
   Copyright (C) 1999 Free Software Foundation, Inc.
   Contributed by Cygnus Solutions.

This file is part of the GNU instruction set simulator.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef CGEN_PAR_H
#define CGEN_PAR_H

/* Kinds of writes stored on the write queue.  */
enum cgen_write_queue_kind {
  CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
  CGEN_PC_WRITE,
  CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
  CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
  CGEN_NUM_WRITE_KINDS
};

/* Element of the write queue.  */
typedef struct {
  enum cgen_write_queue_kind kind; /* Used to select union member below.  */
  union {
    struct {
      UQI *target;
      QI   value;
    } qi_write;
    struct {
      SI *target;
      SI  value;
    } si_write;
    struct {
      SI *target;
      SF  value;
    } sf_write;
    struct {
      USI value;
    } pc_write;
    struct {
      UINT regno;
      SI   value;
      void (*function)(SIM_CPU *, UINT, USI);
    } fn_si_write;
    struct {
      UINT regno;
      DI   value;
      void (*function)(SIM_CPU *, UINT, DI);
    } fn_di_write;
    struct {
      UINT regno;
      DI   value;
      void (*function)(SIM_CPU *, UINT, DI);
    } fn_df_write;
    struct {
      SI   address;
      QI   value;
    } mem_qi_write;
    struct {
      SI   address;
      HI   value;
    } mem_hi_write;
    struct {
      SI   address;
      SI   value;
    } mem_si_write;
  } kinds;
} CGEN_WRITE_QUEUE_ELEMENT;

#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)

extern void cgen_write_queue_element_execute (
  SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
);

/* Instance of the queue for parallel write-after support.  */
/* FIXME: Should be dynamic?  */
#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now.  */

typedef struct {
  int index;
  CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
} CGEN_WRITE_QUEUE;

#define CGEN_WRITE_QUEUE_CLEAR(queue)       ((queue)->index = 0)
#define CGEN_WRITE_QUEUE_INDEX(queue)       ((queue)->index)
#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])

#define CGEN_WRITE_QUEUE_NEXT(queue) (   \
  (queue)->index < CGEN_WRITE_QUEUE_SIZE \
    ? &(queue)->q[(queue)->index++]      \
    : cgen_write_queue_overflow (queue)  \
)

extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);

/* Functions for queuing writes.  Used by semantic code.  */
extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);

extern void sim_queue_pc_write (SIM_CPU *, USI);

extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);

extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);

#endif /* CGEN_PAR_H */
Commit	Line	Data
d4f3574e SS	1	/* Simulator header for cgen parallel support.
	2	Copyright (C) 1999 Free Software Foundation, Inc.
	3	Contributed by Cygnus Solutions.
	4
	5	This file is part of the GNU instruction set simulator.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#ifndef CGEN_PAR_H
	22	#define CGEN_PAR_H
	23
	24	/* Kinds of writes stored on the write queue. */
	25	enum cgen_write_queue_kind {
	26	CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
	27	CGEN_PC_WRITE,
	28	CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
	29	CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
	30	CGEN_NUM_WRITE_KINDS
	31	};
	32
	33	/* Element of the write queue. */
	34	typedef struct {
	35	enum cgen_write_queue_kind kind; /* Used to select union member below. */
	36	union {
	37	struct {
	38	UQI *target;
	39	QI value;
	40	} qi_write;
	41	struct {
	42	SI *target;
	43	SI value;
	44	} si_write;
	45	struct {
	46	SI *target;
	47	SF value;
	48	} sf_write;
	49	struct {
	50	USI value;
	51	} pc_write;
	52	struct {
	53	UINT regno;
	54	SI value;
	55	void (function)(SIM_CPU , UINT, USI);
	56	} fn_si_write;
	57	struct {
	58	UINT regno;
	59	DI value;
	60	void (function)(SIM_CPU , UINT, DI);
	61	} fn_di_write;
	62	struct {
	63	UINT regno;
	64	DI value;
65	void (function)(SIM_CPU , UINT, DI);
66	} fn_df_write;
67	struct {
68	SI address;
69	QI value;
70	} mem_qi_write;
71	struct {
72	SI address;
73	HI value;
74	} mem_hi_write;
75	struct {
76	SI address;
77	SI value;
78	} mem_si_write;
79	} kinds;
80	} CGEN_WRITE_QUEUE_ELEMENT;
81
82	#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
83
84	extern void cgen_write_queue_element_execute (
85	SIM_CPU , CGEN_WRITE_QUEUE_ELEMENT
86	);
87
88	/* Instance of the queue for parallel write-after support. */
89	/* FIXME: Should be dynamic? */
90	#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now. */
91
92	typedef struct {
93	int index;
94	CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
95	} CGEN_WRITE_QUEUE;
96
97	#define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0)
98	#define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index)
99	#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
100
101	#define CGEN_WRITE_QUEUE_NEXT(queue) ( \
102	(queue)->index < CGEN_WRITE_QUEUE_SIZE \
103	? &(queue)->q[(queue)->index++] \
104	: cgen_write_queue_overflow (queue) \
105	)
106
107	extern CGEN_WRITE_QUEUE_ELEMENT cgen_write_queue_overflow (CGEN_WRITE_QUEUE );
108
109	/* Functions for queuing writes. Used by semantic code. */
110	extern void sim_queue_qi_write (SIM_CPU , UQI , UQI);
111	extern void sim_queue_si_write (SIM_CPU , SI , SI);
112	extern void sim_queue_sf_write (SIM_CPU , SI , SF);
113
114	extern void sim_queue_pc_write (SIM_CPU *, USI);
115
116	extern void sim_queue_fn_si_write (SIM_CPU , void ()(SIM_CPU *, UINT, USI), UINT, SI);
117	extern void sim_queue_fn_di_write (SIM_CPU , void ()(SIM_CPU *, UINT, DI), UINT, DI);
118	extern void sim_queue_fn_df_write (SIM_CPU , void ()(SIM_CPU *, UINT, DI), UINT, DF);
119
120	extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
121	extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
122	extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
123
124	#endif /* CGEN_PAR_H */