[thirdparty/binutils-gdb.git] / sim / common / cgen-par.h

/* Simulator header for cgen parallel support.
   Copyright (C) 1999, 2000, 2007 Free Software Foundation, Inc.
   Contributed by Cygnus Solutions.

This file is part of the GNU instruction set simulator.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef CGEN_PAR_H
#define CGEN_PAR_H

/* Kinds of writes stored on the write queue.  */
enum cgen_write_queue_kind {
  CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
  CGEN_PC_WRITE,
  CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_SF_WRITE,
  CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
  CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE,
  CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE,
  CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE,
  CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE,
  CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE,
  CGEN_NUM_WRITE_KINDS
};

/* Element of the write queue.  */
typedef struct {
  enum cgen_write_queue_kind kind; /* Used to select union member below.  */
  IADDR insn_address;       /* Address of the insn performing the write.  */
  unsigned32 flags;         /* Target specific flags.  */
  long       word1;         /* Target specific field.  */
  union {
    struct {
      BI  *target;
      BI   value;
    } bi_write;
    struct {
      UQI *target;
      QI   value;
    } qi_write;
    struct {
      SI *target;
      SI  value;
    } si_write;
    struct {
      SI *target;
      SF  value;
    } sf_write;
    struct {
      USI value;
    } pc_write;
    struct {
      UINT regno;
      UHI   value;
      void (*function)(SIM_CPU *, UINT, UHI);
    } fn_hi_write;
    struct {
      UINT regno;
      SI   value;
      void (*function)(SIM_CPU *, UINT, USI);
    } fn_si_write;
    struct {
      UINT regno;
      SF   value;
      void (*function)(SIM_CPU *, UINT, SF);
    } fn_sf_write;
    struct {
      UINT regno;
      DI   value;
      void (*function)(SIM_CPU *, UINT, DI);
    } fn_di_write;
    struct {
      UINT regno;
      DF   value;
      void (*function)(SIM_CPU *, UINT, DF);
    } fn_df_write;
    struct {
      UINT regno;
      SI   value[4];
      void (*function)(SIM_CPU *, UINT, SI *);
    } fn_xi_write;
    struct {
      USI  value;
      void (*function)(SIM_CPU *, USI);
    } fn_pc_write;
    struct {
      SI   address;
      QI   value;
    } mem_qi_write;
    struct {
      SI   address;
      HI   value;
    } mem_hi_write;
    struct {
      SI   address;
      SI   value;
    } mem_si_write;
    struct {
      SI   address;
      DI   value;
    } mem_di_write;
    struct {
      SI   address;
      DF   value;
    } mem_df_write;
    struct {
      SI   address;
      SI   value[4];
    } mem_xi_write;
    struct {
      SI   address;
      QI   value;
      void (*function)(SIM_CPU *, IADDR, SI, QI);
    } fn_mem_qi_write;
    struct {
      SI   address;
      HI   value;
      void (*function)(SIM_CPU *, IADDR, SI, HI);
    } fn_mem_hi_write;
    struct {
      SI   address;
      SI   value;
      void (*function)(SIM_CPU *, IADDR, SI, SI);
    } fn_mem_si_write;
    struct {
      SI   address;
      DI   value;
      void (*function)(SIM_CPU *, IADDR, SI, DI);
    } fn_mem_di_write;
    struct {
      SI   address;
      DF   value;
      void (*function)(SIM_CPU *, IADDR, SI, DF);
    } fn_mem_df_write;
    struct {
      SI   address;
      SI   value[4];
      void (*function)(SIM_CPU *, IADDR, SI, SI *);
    } fn_mem_xi_write;
  } kinds;
} CGEN_WRITE_QUEUE_ELEMENT;

#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
#define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
#define CGEN_WRITE_QUEUE_ELEMENT_FLAGS(element) ((element)->flags)
#define CGEN_WRITE_QUEUE_ELEMENT_WORD1(element) ((element)->word1)

extern void cgen_write_queue_element_execute (
  SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
);

/* Instance of the queue for parallel write-after support.  */
/* FIXME: Should be dynamic?  */
#define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now.  */

typedef struct {
  int index;
  CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
} CGEN_WRITE_QUEUE;

#define CGEN_WRITE_QUEUE_CLEAR(queue)       ((queue)->index = 0)
#define CGEN_WRITE_QUEUE_INDEX(queue)       ((queue)->index)
#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])

#define CGEN_WRITE_QUEUE_NEXT(queue) (   \
  (queue)->index < CGEN_WRITE_QUEUE_SIZE \
    ? &(queue)->q[(queue)->index++]      \
    : cgen_write_queue_overflow (queue)  \
)

extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);

/* Functions for queuing writes.  Used by semantic code.  */
extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);

extern void sim_queue_pc_write (SIM_CPU *, USI);

extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, USI);
extern void sim_queue_fn_sf_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SF), UINT, SF);
extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF);
extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *);
extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI);

extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI);
extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF);
extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *);

extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI);
extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI);
extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI);
extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI);
extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF);
extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *);

#endif /* CGEN_PAR_H */
Commit	Line	Data
d4f3574e	1	/* Simulator header for cgen parallel support.
6aba47ca	2	Copyright (C) 1999, 2000, 2007 Free Software Foundation, Inc.
d4f3574e SS	3	Contributed by Cygnus Solutions.
	4
	5	This file is part of the GNU instruction set simulator.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#ifndef CGEN_PAR_H
	22	#define CGEN_PAR_H
	23
	24	/* Kinds of writes stored on the write queue. */
	25	enum cgen_write_queue_kind {
c2c6d25f	26	CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
d4f3574e	27	CGEN_PC_WRITE,
e88acae7 FCE	28	CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_SF_WRITE,
e88acae7 FCE	29	CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
11cf8741	30	CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE,
917317f4	31	CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE,
11cf8741	32	CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE,
de57eccd JM	33	CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE,
de57eccd JM	34	CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE,
d4f3574e SS	35	CGEN_NUM_WRITE_KINDS
	36	};
	37
	38	/* Element of the write queue. */
	39	typedef struct {
	40	enum cgen_write_queue_kind kind; /* Used to select union member below. */
e514a9d6	41	IADDR insn_address; /* Address of the insn performing the write. */
33319edb DB	42	unsigned32 flags; /* Target specific flags. */
33319edb DB	43	long word1; /* Target specific field. */
d4f3574e	44	union {
c2c6d25f JM	45	struct {
	46	BI *target;
	47	BI value;
	48	} bi_write;
d4f3574e SS	49	struct {
	50	UQI *target;
	51	QI value;
	52	} qi_write;
	53	struct {
	54	SI *target;
	55	SI value;
	56	} si_write;
	57	struct {
	58	SI *target;
	59	SF value;
	60	} sf_write;
	61	struct {
	62	USI value;
	63	} pc_write;
2df3850c JM	64	struct {
	65	UINT regno;
	66	UHI value;
	67	void (function)(SIM_CPU , UINT, UHI);
	68	} fn_hi_write;
d4f3574e SS	69	struct {
	70	UINT regno;
	71	SI value;
	72	void (function)(SIM_CPU , UINT, USI);
	73	} fn_si_write;
e88acae7 FCE	74	struct {
	75	UINT regno;
	76	SF value;
	77	void (function)(SIM_CPU , UINT, SF);
	78	} fn_sf_write;
d4f3574e SS	79	struct {
	80	UINT regno;
	81	DI value;
	82	void (function)(SIM_CPU , UINT, DI);
	83	} fn_di_write;
	84	struct {
	85	UINT regno;
c2d11a7d JM	86	DF value;
c2d11a7d JM	87	void (function)(SIM_CPU , UINT, DF);
d4f3574e	88	} fn_df_write;
11cf8741 JM	89	struct {
	90	UINT regno;
	91	SI value[4];
	92	void (function)(SIM_CPU , UINT, SI *);
	93	} fn_xi_write;
e514a9d6 JM	94	struct {
	95	USI value;
	96	void (function)(SIM_CPU , USI);
	97	} fn_pc_write;
d4f3574e SS	98	struct {
	99	SI address;
	100	QI value;
	101	} mem_qi_write;
	102	struct {
	103	SI address;
	104	HI value;
	105	} mem_hi_write;
	106	struct {
	107	SI address;
	108	SI value;
	109	} mem_si_write;
917317f4 JM	110	struct {
	111	SI address;
	112	DI value;
	113	} mem_di_write;
	114	struct {
	115	SI address;
de57eccd	116	DF value;
917317f4	117	} mem_df_write;
11cf8741 JM	118	struct {
	119	SI address;
	120	SI value[4];
	121	} mem_xi_write;
de57eccd JM	122	struct {
	123	SI address;
	124	QI value;
	125	void (function)(SIM_CPU , IADDR, SI, QI);
	126	} fn_mem_qi_write;
	127	struct {
	128	SI address;
	129	HI value;
	130	void (function)(SIM_CPU , IADDR, SI, HI);
	131	} fn_mem_hi_write;
	132	struct {
	133	SI address;
	134	SI value;
	135	void (function)(SIM_CPU , IADDR, SI, SI);
	136	} fn_mem_si_write;
	137	struct {
	138	SI address;
	139	DI value;
	140	void (function)(SIM_CPU , IADDR, SI, DI);
	141	} fn_mem_di_write;
	142	struct {
	143	SI address;
	144	DF value;
	145	void (function)(SIM_CPU , IADDR, SI, DF);
	146	} fn_mem_df_write;
	147	struct {
	148	SI address;
	149	SI value[4];
	150	void (function)(SIM_CPU , IADDR, SI, SI *);
	151	} fn_mem_xi_write;
d4f3574e SS	152	} kinds;
	153	} CGEN_WRITE_QUEUE_ELEMENT;
	154
	155	#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
e514a9d6	156	#define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
33319edb DB	157	#define CGEN_WRITE_QUEUE_ELEMENT_FLAGS(element) ((element)->flags)
33319edb DB	158	#define CGEN_WRITE_QUEUE_ELEMENT_WORD1(element) ((element)->word1)
d4f3574e SS	159
	160	extern void cgen_write_queue_element_execute (
	161	SIM_CPU , CGEN_WRITE_QUEUE_ELEMENT
	162	);
	163
	164	/* Instance of the queue for parallel write-after support. */
	165	/* FIXME: Should be dynamic? */
c2d11a7d	166	#define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now. */
d4f3574e SS	167
	168	typedef struct {
	169	int index;
	170	CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
	171	} CGEN_WRITE_QUEUE;
	172
	173	#define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0)
	174	#define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index)
	175	#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
	176
	177	#define CGEN_WRITE_QUEUE_NEXT(queue) ( \
	178	(queue)->index < CGEN_WRITE_QUEUE_SIZE \
	179	? &(queue)->q[(queue)->index++] \
	180	: cgen_write_queue_overflow (queue) \
	181	)
	182
	183	extern CGEN_WRITE_QUEUE_ELEMENT cgen_write_queue_overflow (CGEN_WRITE_QUEUE );
	184
	185	/* Functions for queuing writes. Used by semantic code. */
c2c6d25f	186	extern void sim_queue_bi_write (SIM_CPU , BI , BI);
d4f3574e SS	187	extern void sim_queue_qi_write (SIM_CPU , UQI , UQI);
	188	extern void sim_queue_si_write (SIM_CPU , SI , SI);
	189	extern void sim_queue_sf_write (SIM_CPU , SI , SF);
	190
	191	extern void sim_queue_pc_write (SIM_CPU *, USI);
	192
2df3850c	193	extern void sim_queue_fn_hi_write (SIM_CPU , void ()(SIM_CPU *, UINT, UHI), UINT, UHI);
e88acae7 FCE	194	extern void sim_queue_fn_si_write (SIM_CPU , void ()(SIM_CPU *, UINT, USI), UINT, USI);
e88acae7 FCE	195	extern void sim_queue_fn_sf_write (SIM_CPU , void ()(SIM_CPU *, UINT, SF), UINT, SF);
d4f3574e	196	extern void sim_queue_fn_di_write (SIM_CPU , void ()(SIM_CPU *, UINT, DI), UINT, DI);
c2d11a7d	197	extern void sim_queue_fn_df_write (SIM_CPU , void ()(SIM_CPU *, UINT, DF), UINT, DF);
11cf8741	198	extern void sim_queue_fn_xi_write (SIM_CPU , void ()(SIM_CPU , UINT, SI ), UINT, SI *);
e514a9d6	199	extern void sim_queue_fn_pc_write (SIM_CPU , void ()(SIM_CPU *, USI), USI);
d4f3574e SS	200
	201	extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
	202	extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
	203	extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
917317f4 JM	204	extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI);
917317f4 JM	205	extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF);
11cf8741	206	extern void sim_queue_mem_xi_write (SIM_CPU , SI, SI );
d4f3574e	207
de57eccd JM	208	extern void sim_queue_fn_mem_qi_write (SIM_CPU , void ()(SIM_CPU *, IADDR, SI, QI), SI, QI);
	209	extern void sim_queue_fn_mem_hi_write (SIM_CPU , void ()(SIM_CPU *, IADDR, SI, HI), SI, HI);
	210	extern void sim_queue_fn_mem_si_write (SIM_CPU , void ()(SIM_CPU *, IADDR, SI, SI), SI, SI);
	211	extern void sim_queue_fn_mem_di_write (SIM_CPU , void ()(SIM_CPU *, IADDR, SI, DI), SI, DI);
	212	extern void sim_queue_fn_mem_df_write (SIM_CPU , void ()(SIM_CPU *, IADDR, SI, DF), SI, DF);
	213	extern void sim_queue_fn_mem_xi_write (SIM_CPU , void ()(SIM_CPU , IADDR, SI, SI ), SI, SI *);
	214
d4f3574e	215	#endif /* CGEN_PAR_H */