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[thirdparty/binutils-gdb.git] / sim / cr16 / simops.c
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fee8ec00 1/* Simulation code for the CR16 processor.
213516ef 2 Copyright (C) 2008-2023 Free Software Foundation, Inc.
fee8ec00
SR		 3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
dc3cf14f 9 the Free Software Foundation; either version 3, or (at your option)
fee8ec00
SR		 10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
537e4bb9
SR		 17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
fee8ec00 19
6df01ab8
MF		 20/* This must come before any other includes. */
21#include "defs.h"
fee8ec00
SR		 22
23#include <signal.h>
24#include <errno.h>
25#include <sys/types.h>
26#include <sys/stat.h>
27#ifdef HAVE_UNISTD_H
28#include <unistd.h>
29#endif
fee8ec00 30#include <string.h>
5aedb83b 31#include <time.h>
5aedb83b 32#include <sys/time.h>
fee8ec00 33
6cf3ddd2
MF		 34#include "bfd.h"
35
247ac9ee 36#include "sim-main.h"
1fef66b0 37#include "sim-signal.h"
fee8ec00 38#include "simops.h"
ab230d13 39#include "target-newlib-syscall.h"
fee8ec00 40
e79b75a3
MF		 41#include "cr16-sim.h"
42
ab230d13 43#ifdef HAVE_UTIME_H
5aedb83b
MF		 44#include <utime.h>
45#endif
5aedb83b 46#include <sys/wait.h>
fee8ec00 47
0ef7f981
MF		 48#define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
49
fee8ec00
SR		 50enum op_types {
51 OP_VOID,
52 OP_CONSTANT3,
fee8ec00 53 OP_UCONSTANT3,
fee8ec00 54 OP_CONSTANT4,
fee8ec00 55 OP_CONSTANT4_1,
fee8ec00 56 OP_CONSTANT5,
fee8ec00 57 OP_CONSTANT6,
fee8ec00 58 OP_CONSTANT16,
fee8ec00 59 OP_UCONSTANT16,
fee8ec00 60 OP_CONSTANT20,
fee8ec00 61 OP_UCONSTANT20,
fee8ec00 62 OP_CONSTANT32,
fee8ec00 63 OP_UCONSTANT32,
fee8ec00
SR		 64 OP_MEMREF,
65 OP_MEMREF2,
66 OP_MEMREF3,
67
68 OP_DISP5,
fee8ec00 69 OP_DISP17,
fee8ec00 70 OP_DISP25,
fee8ec00 71 OP_DISPE9,
fee8ec00
SR		 72 //OP_ABS20,
73 OP_ABS20_OUTPUT,
74 //OP_ABS24,
75 OP_ABS24_OUTPUT,
76
77 OP_R_BASE_DISPS16,
fee8ec00 78 OP_R_BASE_DISP20,
fee8ec00 79 OP_R_BASE_DISPS20,
fee8ec00 80 OP_R_BASE_DISPE20,
fee8ec00
SR		 81
82 OP_RP_BASE_DISPE0,
fee8ec00 83 OP_RP_BASE_DISP4,
fee8ec00 84 OP_RP_BASE_DISPE4,
fee8ec00 85 OP_RP_BASE_DISP14,
fee8ec00 86 OP_RP_BASE_DISP16,
fee8ec00 87 OP_RP_BASE_DISP20,
fee8ec00 88 OP_RP_BASE_DISPS20,
fee8ec00 89 OP_RP_BASE_DISPE20,
fee8ec00
SR		 90
91 OP_R_INDEX7_ABS20,
fee8ec00 92 OP_R_INDEX8_ABS20,
fee8ec00
SR		 93
94 OP_RP_INDEX_DISP0,
fee8ec00 95 OP_RP_INDEX_DISP14,
fee8ec00 96 OP_RP_INDEX_DISP20,
fee8ec00 97 OP_RP_INDEX_DISPS20,
fee8ec00
SR		 98
99 OP_REG,
fee8ec00 100 OP_REGP,
fee8ec00 101 OP_PROC_REG,
fee8ec00 102 OP_PROC_REGP,
fee8ec00 103 OP_COND,
537e4bb9 104 OP_RA
fee8ec00
SR		 105};
106
107
108enum {
109 PSR_MASK = (PSR_I_BIT
110 | PSR_P_BIT
111 | PSR_E_BIT
112 | PSR_N_BIT
113 | PSR_Z_BIT
114 | PSR_F_BIT
115 | PSR_U_BIT
116 | PSR_L_BIT
117 | PSR_T_BIT
118 | PSR_C_BIT),
119 /* The following bits in the PSR _can't_ be set by instructions such
120 as mvtc. */
121 PSR_HW_MASK = (PSR_MASK)
122};
123
124/* cond Code Condition True State
125 * EQ Equal Z flag is 1
126 * NE Not Equal Z flag is 0
127 * CS Carry Set C flag is 1
128 * CC Carry Clear C flag is 0
129 * HI Higher L flag is 1
130 * LS Lower or Same L flag is 0
131 * GT Greater Than N flag is 1
132 * LE Less Than or Equal To N flag is 0
133 * FS Flag Set F flag is 1
134 * FC Flag Clear F flag is 0
135 * LO Lower Z and L flags are 0
136 * HS Higher or Same Z or L flag is 1
137 * LT Less Than Z and N flags are 0
138 * GE Greater Than or Equal To Z or N flag is 1. */
139
5aedb83b 140static int cond_stat(int cc)
fee8ec00
SR		 141{
142 switch (cc)
143 {
144 case 0: return PSR_Z; break;
145 case 1: return !PSR_Z; break;
146 case 2: return PSR_C; break;
147 case 3: return !PSR_C; break;
148 case 4: return PSR_L; break;
149 case 5: return !PSR_L; break;
150 case 6: return PSR_N; break;
151 case 7: return !PSR_N; break;
152 case 8: return PSR_F; break;
153 case 9: return !PSR_F; break;
154 case 10: return !PSR_Z && !PSR_L; break;
155 case 11: return PSR_Z || PSR_L; break;
156 case 12: return !PSR_Z && !PSR_N; break;
157 case 13: return PSR_Z || PSR_N; break;
158 case 14: return 1; break; /*ALWAYS. */
159 default:
160 // case NEVER: return false; break;
161 //case NO_COND_CODE:
162 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
163 return 0; break;
164 }
165 return 0;
166}
167
168
169creg_t
267b3b8e 170move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
fee8ec00
SR		 171{
172 /* A MASK bit is set when the corresponding bit in the CR should
173 be left alone. */
174 /* This assumes that (VAL & MASK) == 0. */
175 switch (cr)
176 {
177 case PSR_CR:
178 if (psw_hw_p)
179 val &= PSR_HW_MASK;
180#if 0
181 else
182 val &= PSR_MASK;
9db36cf8
MF		 183 sim_io_printf
184 (sd,
fee8ec00 185 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
0ef7f981 186 EXCEPTION (SIM_SIGILL);
fee8ec00
SR		 187#endif
188 /* keep an up-to-date psw around for tracing. */
189 State.trace.psw = (State.trace.psw & mask) | val;
190 break;
191 default:
192 break;
193 }
194 /* only issue an update if the register is being changed. */
195 if ((State.cregs[cr] & ~mask) != val)
196 SLOT_PEND_MASK (State.cregs[cr], mask, val);
537e4bb9 197
fee8ec00
SR		 198 return val;
199}
200
201#ifdef DEBUG
267b3b8e
MF		 202static void trace_input_func (SIM_DESC sd,
203 const char *name,
bdca5ee4
TT		 204 enum op_types in1,
205 enum op_types in2,
206 enum op_types in3);
fee8ec00 207
267b3b8e 208#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
fee8ec00
SR		 209
210#ifndef SIZE_INSTRUCTION
211#define SIZE_INSTRUCTION 8
212#endif
213
214#ifndef SIZE_OPERANDS
215#define SIZE_OPERANDS 18
216#endif
217
218#ifndef SIZE_VALUES
219#define SIZE_VALUES 13
220#endif
221
222#ifndef SIZE_LOCATION
223#define SIZE_LOCATION 20
224#endif
225
226#ifndef SIZE_PC
227#define SIZE_PC 4
228#endif
229
230#ifndef SIZE_LINE_NUMBER
231#define SIZE_LINE_NUMBER 2
232#endif
233
234static void
267b3b8e 235trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
fee8ec00
SR		 236{
237 char *comma;
238 enum op_types in[3];
239 int i;
240 char buf[1024];
241 char *p;
242 long tmp;
243 char *type;
244 const char *filename;
245 const char *functionname;
246 unsigned int linenumber;
247 bfd_vma byte_pc;
248
249 if ((cr16_debug & DEBUG_TRACE) == 0)
250 return;
251
252 switch (State.ins_type)
253 {
254 default:
255 case INS_UNKNOWN: type = " ?"; break;
256 }
257
258 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
9db36cf8 259 sim_io_printf (sd,
fee8ec00
SR		 260 "0x%.*x %s: %-*s ",
261 SIZE_PC, (unsigned)PC,
262 type,
263 SIZE_INSTRUCTION, name);
264
265 else
266 {
267 buf[0] = '\0';
247ac9ee 268 byte_pc = PC;
267b3b8e
MF		 269 if (STATE_TEXT_SECTION (sd)
270 && byte_pc >= STATE_TEXT_START (sd)
271 && byte_pc < STATE_TEXT_END (sd))
fee8ec00
SR		 272 {
273 filename = (const char *)0;
274 functionname = (const char *)0;
275 linenumber = 0;
267b3b8e
MF		 276 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
277 STATE_TEXT_SECTION (sd),
247ac9ee 278 (struct bfd_symbol **)0,
267b3b8e 279 byte_pc - STATE_TEXT_START (sd),
fee8ec00
SR		 280 &filename, &functionname, &linenumber))
281 {
282 p = buf;
283 if (linenumber)
284 {
285 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
286 p += strlen (p);
287 }
288 else
289 {
290 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
291 p += SIZE_LINE_NUMBER+2;
292 }
293
294 if (functionname)
295 {
296 sprintf (p, "%s ", functionname);
297 p += strlen (p);
298 }
299 else if (filename)
300 {
301 char *q = strrchr (filename, '/');
302 sprintf (p, "%s ", (q) ? q+1 : filename);
303 p += strlen (p);
304 }
305
306 if (*p == ' ')
307 *p = '\0';
308 }
309 }
310
9db36cf8 311 sim_io_printf (sd,
fee8ec00
SR		 312 "0x%.*x %s: %-*.*s %-*s ",
313 SIZE_PC, (unsigned)PC,
314 type,
315 SIZE_LOCATION, SIZE_LOCATION, buf,
316 SIZE_INSTRUCTION, name);
317 }
318
319 in[0] = in1;
320 in[1] = in2;
321 in[2] = in3;
322 comma = "";
323 p = buf;
324 for (i = 0; i < 3; i++)
325 {
326 switch (in[i])
327 {
328 case OP_VOID:
329 break;
330
331 case OP_REG:
fee8ec00 332 case OP_REGP:
fee8ec00
SR		 333 sprintf (p, "%sr%d", comma, OP[i]);
334 p += strlen (p);
335 comma = ",";
336 break;
337
338 case OP_PROC_REG:
fee8ec00
SR		 339 sprintf (p, "%scr%d", comma, OP[i]);
340 p += strlen (p);
341 comma = ",";
342 break;
343
344 case OP_CONSTANT16:
345 sprintf (p, "%s%d", comma, OP[i]);
346 p += strlen (p);
347 comma = ",";
348 break;
349
350 case OP_CONSTANT4:
351 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
352 p += strlen (p);
353 comma = ",";
354 break;
355
356 case OP_CONSTANT3:
357 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
358 p += strlen (p);
359 comma = ",";
360 break;
361
362 case OP_MEMREF:
363 sprintf (p, "%s@r%d", comma, OP[i]);
364 p += strlen (p);
365 comma = ",";
366 break;
367
368 case OP_MEMREF2:
32267d59 369 sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
fee8ec00
SR		 370 p += strlen (p);
371 comma = ",";
372 break;
373
374 case OP_MEMREF3:
375 sprintf (p, "%s@%d", comma, OP[i]);
376 p += strlen (p);
377 comma = ",";
378 break;
379 }
380 }
381
382 if ((cr16_debug & DEBUG_VALUES) == 0)
383 {
384 *p++ = '\n';
385 *p = '\0';
9db36cf8 386 sim_io_printf (sd, "%s", buf);
fee8ec00
SR		 387 }
388 else
389 {
390 *p = '\0';
9db36cf8 391 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
fee8ec00
SR		 392
393 p = buf;
394 for (i = 0; i < 3; i++)
395 {
396 buf[0] = '\0';
397 switch (in[i])
398 {
399 case OP_VOID:
9db36cf8 400 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
fee8ec00
SR		 401 break;
402
fee8ec00 403 case OP_REG:
9db36cf8 404 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
32267d59 405 (uint16_t) GPR (OP[i]));
fee8ec00
SR		 406 break;
407
408 case OP_REGP:
32267d59 409 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
9db36cf8 410 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
fee8ec00
SR		 411 break;
412
413 case OP_PROC_REG:
9db36cf8 414 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
32267d59 415 (uint16_t) CREG (OP[i]));
fee8ec00
SR		 416 break;
417
418 case OP_CONSTANT16:
9db36cf8 419 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
32267d59 420 (uint16_t)OP[i]);
fee8ec00
SR		 421 break;
422
423 case OP_CONSTANT4:
9db36cf8 424 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
32267d59 425 (uint16_t)SEXT4(OP[i]));
fee8ec00
SR		 426 break;
427
428 case OP_CONSTANT3:
9db36cf8 429 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
32267d59 430 (uint16_t)SEXT3(OP[i]));
fee8ec00
SR		 431 break;
432
433 case OP_MEMREF2:
9db36cf8 434 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
32267d59 435 (uint16_t)OP[i]);
9db36cf8 436 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
32267d59 437 (uint16_t)GPR (OP[i + 1]));
fee8ec00
SR		 438 i++;
439 break;
440 }
441 }
442 }
443
9db36cf8 444 sim_io_flush_stdout (sd);
fee8ec00
SR		 445}
446
447static void
267b3b8e 448do_trace_output_flush (SIM_DESC sd)
fee8ec00 449{
9db36cf8 450 sim_io_flush_stdout (sd);
fee8ec00
SR		 451}
452
453static void
267b3b8e 454do_trace_output_finish (SIM_DESC sd)
fee8ec00 455{
9db36cf8 456 sim_io_printf (sd,
fee8ec00
SR		 457 " F0=%d F1=%d C=%d\n",
458 (State.trace.psw & PSR_F_BIT) != 0,
459 (State.trace.psw & PSR_F_BIT) != 0,
460 (State.trace.psw & PSR_C_BIT) != 0);
9db36cf8 461 sim_io_flush_stdout (sd);
fee8ec00
SR		 462}
463
5aedb83b 464#if 0
fee8ec00 465static void
32267d59 466trace_output_40 (SIM_DESC sd, uint64_t val)
fee8ec00
SR		 467{
468 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
469 {
9db36cf8 470 sim_io_printf (sd,
fee8ec00
SR		 471 " :: %*s0x%.2x%.8lx",
472 SIZE_VALUES - 12,
473 "",
474 ((int)(val >> 32) & 0xff),
475 ((unsigned long) val) & 0xffffffff);
476 do_trace_output_finish ();
477 }
478}
5aedb83b 479#endif
fee8ec00
SR		 480
481static void
32267d59 482trace_output_32 (SIM_DESC sd, uint32_t val)
fee8ec00
SR		 483{
484 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
485 {
9db36cf8 486 sim_io_printf (sd,
fee8ec00
SR		 487 " :: %*s0x%.8x",
488 SIZE_VALUES - 10,
489 "",
490 (int) val);
267b3b8e 491 do_trace_output_finish (sd);
fee8ec00
SR		 492 }
493}
494
495static void
32267d59 496trace_output_16 (SIM_DESC sd, uint16_t val)
fee8ec00
SR		 497{
498 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
499 {
9db36cf8 500 sim_io_printf (sd,
fee8ec00
SR		 501 " :: %*s0x%.4x",
502 SIZE_VALUES - 6,
503 "",
504 (int) val);
267b3b8e 505 do_trace_output_finish (sd);
fee8ec00
SR		 506 }
507}
508
509static void
267b3b8e 510trace_output_void (SIM_DESC sd)
fee8ec00
SR		 511{
512 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
513 {
9db36cf8 514 sim_io_printf (sd, "\n");
267b3b8e 515 do_trace_output_flush (sd);
fee8ec00
SR		 516 }
517}
518
519static void
267b3b8e 520trace_output_flag (SIM_DESC sd)
fee8ec00
SR		 521{
522 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
523 {
9db36cf8 524 sim_io_printf (sd,
fee8ec00
SR		 525 " :: %*s",
526 SIZE_VALUES,
527 "");
267b3b8e 528 do_trace_output_finish (sd);
fee8ec00
SR		 529 }
530}
531
532
533
534
535#else
536#define trace_input(NAME, IN1, IN2, IN3)
537#define trace_output(RESULT)
538#endif
539
540/* addub. */
541void
267b3b8e 542OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 543{
32267d59
MF		 544 uint8_t tmp;
545 uint8_t a = OP[0] & 0xff;
546 uint16_t b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 547 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
548 tmp = (a + b) & 0xff;
549 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 550 trace_output_16 (sd, tmp);
fee8ec00
SR		 551}
552
553/* addub. */
554void
267b3b8e 555OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 556{
32267d59
MF		 557 uint16_t tmp;
558 uint8_t a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 559 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
560 tmp = (a + b) & 0xff;
561 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 562 trace_output_16 (sd, tmp);
fee8ec00
SR		 563}
564
565/* addub. */
566void
267b3b8e 567OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 568{
32267d59
MF		 569 uint8_t a = (GPR (OP[0])) & 0xff;
570 uint8_t b = (GPR (OP[1])) & 0xff;
571 uint16_t tmp = (a + b) & 0xff;
fee8ec00
SR		 572 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
573 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 574 trace_output_16 (sd, tmp);
fee8ec00
SR		 575}
576
577/* adduw. */
578void
267b3b8e 579OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 580{
32267d59
MF		 581 uint16_t a = OP[0];
582 uint16_t b = GPR (OP[1]);
583 uint16_t tmp = (a + b);
fee8ec00
SR		 584 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
585 SET_GPR (OP[1], tmp);
267b3b8e 586 trace_output_16 (sd, tmp);
fee8ec00
SR		 587}
588
589/* adduw. */
590void
267b3b8e 591OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 592{
32267d59
MF		 593 uint16_t a = OP[0];
594 uint16_t b = GPR (OP[1]);
595 uint16_t tmp = (a + b);
fee8ec00
SR		 596 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
597 SET_GPR (OP[1], tmp);
267b3b8e 598 trace_output_16 (sd, tmp);
fee8ec00
SR		 599}
600
601/* adduw. */
602void
267b3b8e 603OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 604{
32267d59
MF		 605 uint16_t a = GPR (OP[0]);
606 uint16_t b = GPR (OP[1]);
607 uint16_t tmp = (a + b);
fee8ec00
SR		 608 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
609 SET_GPR (OP[1], tmp);
267b3b8e 610 trace_output_16 (sd, tmp);
fee8ec00
SR		 611}
612
613/* addb. */
614void
267b3b8e 615OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 616{
32267d59
MF		 617 uint8_t a = OP[0];
618 uint8_t b = (GPR (OP[1]) & 0xff);
619 uint16_t tmp = (a + b) & 0xff;
5aedb83b 620 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 621 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
622 SET_PSR_C (tmp > 0xFF);
623 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 624 trace_output_16 (sd, tmp);
fee8ec00
SR		 625}
626
627/* addb. */
628void
267b3b8e 629OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 630{
32267d59
MF		 631 uint8_t a = (OP[0]) & 0xff;
632 uint8_t b = (GPR (OP[1]) & 0xff);
633 uint16_t tmp = (a + b) & 0xff;
5aedb83b 634 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 635 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
636 SET_PSR_C (tmp > 0xFF);
637 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 638 trace_output_16 (sd, tmp);
fee8ec00
SR		 639}
640
641/* addb. */
642void
267b3b8e 643OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 644{
32267d59
MF		 645 uint8_t a = (GPR (OP[0]) & 0xff);
646 uint8_t b = (GPR (OP[1]) & 0xff);
647 uint16_t tmp = (a + b) & 0xff;
5aedb83b 648 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 649 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
650 SET_PSR_C (tmp > 0xFF);
651 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 652 trace_output_16 (sd, tmp);
fee8ec00
SR		 653}
654
655/* addw. */
656void
267b3b8e 657OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 658{
32267d59
MF		 659 int16_t a = OP[0];
660 uint16_t tmp, b = GPR (OP[1]);
fee8ec00 661 tmp = (a + b);
5aedb83b 662 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 663 SET_GPR (OP[1], tmp);
664 SET_PSR_C (tmp > 0xFFFF);
665 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 666 trace_output_16 (sd, tmp);
fee8ec00
SR		 667}
668
669/* addw. */
670void
267b3b8e 671OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 672{
32267d59
MF		 673 int16_t a = OP[0];
674 uint16_t tmp, b = GPR (OP[1]);
fee8ec00
SR		 675 tmp = (a + b);
676 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
677 SET_GPR (OP[1], tmp);
678 SET_PSR_C (tmp > 0xFFFF);
679 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 680 trace_output_16 (sd, tmp);
fee8ec00
SR		 681}
682
683/* addw. */
684void
267b3b8e 685OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 686{
32267d59 687 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 688 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
689 tmp = (a + b);
690 SET_GPR (OP[1], tmp);
691 SET_PSR_C (tmp > 0xFFFF);
692 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 693 trace_output_16 (sd, tmp);
fee8ec00
SR		 694}
695
696/* addcb. */
697void
267b3b8e 698OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 699{
32267d59 700 uint8_t tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 701 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
702 tmp = (a + b + PSR_C) & 0xff;
703 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
704 SET_PSR_C (tmp > 0xFF);
705 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 706 trace_output_16 (sd, tmp);
fee8ec00
SR		 707}
708
709/* addcb. */
710void
267b3b8e 711OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 712{
32267d59
MF		 713 int8_t a = OP[0] & 0xff;
714 uint8_t b = (GPR (OP[1])) & 0xff;
715 uint8_t tmp = (a + b + PSR_C) & 0xff;
5aedb83b 716 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 717 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
718 SET_PSR_C (tmp > 0xFF);
719 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 720 trace_output_16 (sd, tmp);
fee8ec00
SR		 721}
722
723/* addcb. */
724void
267b3b8e 725OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 726{
32267d59
MF		 727 uint8_t a = (GPR (OP[0])) & 0xff;
728 uint8_t b = (GPR (OP[1])) & 0xff;
729 uint8_t tmp = (a + b + PSR_C) & 0xff;
5aedb83b 730 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 731 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
732 SET_PSR_C (tmp > 0xFF);
733 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 734 trace_output_16 (sd, tmp);
fee8ec00
SR		 735}
736
737/* addcw. */
738void
267b3b8e 739OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 740{
32267d59
MF		 741 uint16_t a = OP[0];
742 uint16_t b = GPR (OP[1]);
743 uint16_t tmp = (a + b + PSR_C);
5aedb83b 744 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 745 SET_GPR (OP[1], tmp);
746 SET_PSR_C (tmp > 0xFFFF);
747 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 748 trace_output_16 (sd, tmp);
fee8ec00
SR		 749}
750
751/* addcw. */
752void
267b3b8e 753OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 754{
32267d59
MF		 755 int16_t a = OP[0];
756 uint16_t b = GPR (OP[1]);
757 uint16_t tmp = (a + b + PSR_C);
5aedb83b 758 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 759 SET_GPR (OP[1], tmp);
760 SET_PSR_C (tmp > 0xFFFF);
761 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 762 trace_output_16 (sd, tmp);
fee8ec00
SR		 763}
764
765/* addcw. */
766void
267b3b8e 767OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 768{
32267d59
MF		 769 uint16_t a = GPR (OP[1]);
770 uint16_t b = GPR (OP[1]);
771 uint16_t tmp = (a + b + PSR_C);
5aedb83b 772 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 773 SET_GPR (OP[1], tmp);
774 SET_PSR_C (tmp > 0xFFFF);
775 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 776 trace_output_16 (sd, tmp);
fee8ec00
SR		 777}
778
779/* addd. */
780void
267b3b8e 781OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 782{
32267d59
MF		 783 int16_t a = (OP[0]);
784 uint32_t b = GPR32 (OP[1]);
785 uint32_t tmp = (a + b);
5aedb83b 786 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
fee8ec00
SR		 787 SET_GPR32 (OP[1], tmp);
788 SET_PSR_C (tmp > 0xFFFFFFFF);
789 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 790 trace_output_32 (sd, tmp);
fee8ec00
SR		 791}
792
793/* addd. */
794void
267b3b8e 795OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 796{
32267d59
MF		 797 int32_t a = (SEXT16(OP[0]));
798 uint32_t b = GPR32 (OP[1]);
799 uint32_t tmp = (a + b);
5aedb83b 800 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
fee8ec00
SR		 801 SET_GPR32 (OP[1], tmp);
802 SET_PSR_C (tmp > 0xFFFFFFFF);
803 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 804 trace_output_32 (sd, tmp);
fee8ec00
SR		 805}
806
807/* addd. */
808void
267b3b8e 809OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 810{
32267d59
MF		 811 uint32_t a = GPR32 (OP[0]);
812 uint32_t b = GPR32 (OP[1]);
813 uint32_t tmp = (a + b);
5aedb83b 814 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
fee8ec00 815 SET_GPR32 (OP[1], tmp);
267b3b8e 816 trace_output_32 (sd, tmp);
fee8ec00
SR		 817 SET_PSR_C (tmp > 0xFFFFFFFF);
818 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
819}
820
821/* addd. */
822void
267b3b8e 823OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 824{
32267d59
MF		 825 uint32_t a = OP[0];
826 uint32_t b = GPR32 (OP[1]);
827 uint32_t tmp;
fee8ec00
SR		 828 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
829 tmp = (a + b);
830 SET_GPR32 (OP[1], tmp);
831 SET_PSR_C (tmp > 0xFFFFFFFF);
832 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 833 trace_output_32 (sd, tmp);
fee8ec00
SR		 834}
835
836/* addd. */
837void
267b3b8e 838OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 839{
32267d59
MF		 840 int32_t a = OP[0];
841 uint32_t b = GPR32 (OP[1]);
842 uint32_t tmp;
fee8ec00
SR		 843 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
844 tmp = (a + b);
845 SET_GPR32 (OP[1], tmp);
846 SET_PSR_C (tmp > 0xFFFFFFFF);
847 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 848 trace_output_32 (sd, tmp);
fee8ec00
SR		 849}
850
851/* andb. */
852void
267b3b8e 853OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 854{
32267d59 855 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 856 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
857 tmp = a & b;
858 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 859 trace_output_16 (sd, tmp);
fee8ec00
SR		 860}
861
862/* andb. */
863void
267b3b8e 864OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 865{
32267d59 866 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 867 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
868 tmp = a & b;
869 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 870 trace_output_16 (sd, tmp);
fee8ec00
SR		 871}
872
873/* andb. */
874void
267b3b8e 875OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 876{
32267d59 877 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 878 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
879 tmp = a & b;
880 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 881 trace_output_16 (sd, tmp);
fee8ec00
SR		 882}
883
884/* andw. */
885void
267b3b8e 886OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 887{
32267d59 888 uint16_t tmp, a = OP[0], b = GPR (OP[1]);
fee8ec00
SR		 889 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
890 tmp = a & b;
891 SET_GPR (OP[1], tmp);
267b3b8e 892 trace_output_16 (sd, tmp);
fee8ec00
SR		 893}
894
895/* andw. */
896void
267b3b8e 897OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 898{
32267d59 899 uint16_t tmp, a = OP[0], b = GPR (OP[1]);
fee8ec00
SR		 900 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
901 tmp = a & b;
902 SET_GPR (OP[1], tmp);
267b3b8e 903 trace_output_16 (sd, tmp);
fee8ec00
SR		 904}
905
906/* andw. */
907void
267b3b8e 908OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 909{
32267d59 910 uint16_t tmp, a = GPR (OP[0]), b = GPR (OP[1]);
fee8ec00
SR		 911 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
912 tmp = a & b;
913 SET_GPR (OP[1], tmp);
267b3b8e 914 trace_output_16 (sd, tmp);
fee8ec00
SR		 915}
916
917/* andd. */
918void
267b3b8e 919OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 920{
32267d59 921 uint32_t tmp, a = OP[0], b = GPR32 (OP[1]);
fee8ec00
SR		 922 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
923 tmp = a & b;
924 SET_GPR32 (OP[1], tmp);
267b3b8e 925 trace_output_32 (sd, tmp);
fee8ec00
SR		 926}
927
928/* andd. */
929void
267b3b8e 930OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 931{
32267d59 932 uint32_t tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
fee8ec00
SR		 933 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
934 tmp = a & b;
935 SET_GPR32 (OP[1], tmp);
267b3b8e 936 trace_output_32 (sd, tmp);
fee8ec00
SR		 937}
938
939/* ord. */
940void
267b3b8e 941OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 942{
32267d59 943 uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
fee8ec00
SR		 944 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
945 tmp = a | b;
946 SET_GPR32 (OP[1], tmp);
267b3b8e 947 trace_output_32 (sd, tmp);
fee8ec00
SR		 948}
949
950/* ord. */
951void
267b3b8e 952OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 953{
32267d59 954 uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
fee8ec00
SR		 955 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
956 tmp = a | b;
957 SET_GPR32 (OP[1], tmp);
267b3b8e 958 trace_output_32 (sd, tmp);
fee8ec00
SR		 959}
960
961/* xord. */
962void
267b3b8e 963OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 964{
32267d59 965 uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
fee8ec00
SR		 966 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
967 tmp = a ^ b;
968 SET_GPR32 (OP[1], tmp);
267b3b8e 969 trace_output_32 (sd, tmp);
fee8ec00
SR		 970}
971
972/* xord. */
973void
267b3b8e 974OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 975{
32267d59 976 uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
fee8ec00
SR		 977 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
978 tmp = a ^ b;
979 SET_GPR32 (OP[1], tmp);
267b3b8e 980 trace_output_32 (sd, tmp);
fee8ec00
SR		 981}
982
983
984/* b. */
985void
267b3b8e 986OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 987{
32267d59 988 uint32_t tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 989 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
990 if (cc)
991 {
992 if (sign_flag)
993 tmp = (PC - (OP[1]));
994 else
995 tmp = (PC + (OP[1]));
996 /* If the resulting PC value is less than 0x00_0000 or greater
997 than 0xFF_FFFF, this instruction causes an IAD trap.*/
998
999 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1000 {
267b3b8e 1001 trace_output_void (sd);
0ef7f981 1002 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1003 }
1004 else
1005 JMP (tmp);
1006 }
1007 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1008 trace_output_32 (sd, tmp);
fee8ec00
SR		 1009}
1010
1011/* b. */
1012void
267b3b8e 1013OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1014{
32267d59 1015 uint32_t tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 1016 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1017 if (cc)
1018 {
1019 if (sign_flag)
1020 tmp = (PC - OP[1]);
1021 else
1022 tmp = (PC + OP[1]);
1023 /* If the resulting PC value is less than 0x00_0000 or greater
1024 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1025
1026 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1027 {
267b3b8e 1028 trace_output_void (sd);
0ef7f981 1029 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1030 }
1031 else
1032 JMP (tmp);
1033 }
1034 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1035 trace_output_32 (sd, tmp);
fee8ec00
SR		 1036}
1037
1038/* b. */
1039void
267b3b8e 1040OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1041{
32267d59 1042 uint32_t tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 1043 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1044 if (cc)
1045 {
1046 if (sign_flag)
1047 tmp = (PC - (OP[1]));
1048 else
1049 tmp = (PC + (OP[1]));
1050 /* If the resulting PC value is less than 0x00_0000 or greater
1051 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1052
1053 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1054 {
267b3b8e 1055 trace_output_void (sd);
0ef7f981 1056 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1057 }
1058 else
1059 JMP (tmp);
1060 }
1061 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1062 trace_output_32 (sd, tmp);
fee8ec00
SR		 1063}
1064
1065/* bal. */
1066void
267b3b8e 1067OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1068{
32267d59 1069 uint32_t tmp;
fee8ec00
SR		 1070 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1071 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1072 SET_GPR32 (14, tmp);
1073 if (sign_flag)
1074 tmp = (PC - (OP[1]));
1075 else
1076 tmp = (PC + (OP[1]));
1077
1078 /* If the resulting PC value is less than 0x00_0000 or greater
1079 than 0xFF_FFFF, this instruction causes an IAD trap. */
1080
1081 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1082 {
267b3b8e 1083 trace_output_void (sd);
0ef7f981 1084 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1085 }
1086 else
1087 JMP (tmp);
1088 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1089 trace_output_32 (sd, tmp);
fee8ec00
SR		 1090}
1091
1092
1093/* bal. */
1094void
267b3b8e 1095OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1096{
32267d59 1097 uint32_t tmp;
fee8ec00
SR		 1098 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1099 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1100 SET_GPR32 (OP[0], tmp);
1101 if (sign_flag)
1102 tmp = ((PC) - (OP[1]));
1103 else
1104 tmp = ((PC) + (OP[1]));
1105 /* If the resulting PC value is less than 0x00_0000 or greater
1106 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1107
1108 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1109 {
267b3b8e 1110 trace_output_void (sd);
0ef7f981 1111 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1112 }
1113 else
1114 JMP (tmp);
1115 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1116 trace_output_32 (sd, tmp);
fee8ec00
SR		 1117}
1118
1119/* jal. */
1120void
267b3b8e 1121OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1122{
32267d59 1123 uint32_t tmp;
fee8ec00
SR		 1124 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1125 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1126 tmp = GPR32 (OP[1]);
1127 tmp = SEXT24(tmp << 1);
1128 /* If the resulting PC value is less than 0x00_0000 or greater
1129 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1130
1131 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1132 {
267b3b8e 1133 trace_output_void (sd);
0ef7f981 1134 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1135 }
1136 else
1137 JMP (tmp);
1138
267b3b8e 1139 trace_output_32 (sd, tmp);
fee8ec00
SR		 1140}
1141
1142
1143/* jal. */
1144void
267b3b8e 1145OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1146{
32267d59 1147 uint32_t tmp;
fee8ec00
SR		 1148 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1149 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1150 tmp = GPR32 (OP[0]);
1151 tmp = SEXT24(tmp << 1);
1152 /* If the resulting PC value is less than 0x00_0000 or greater
1153 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1154
1155 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1156 {
267b3b8e 1157 trace_output_void (sd);
0ef7f981 1158 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1159 }
1160 else
1161 JMP (tmp);
1162
267b3b8e 1163 trace_output_32 (sd, tmp);
fee8ec00
SR		 1164}
1165
1166
1167/* beq0b. */
1168void
267b3b8e 1169OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1170{
32267d59
MF		 1171 uint32_t addr;
1172 uint8_t a = (GPR (OP[0]) & 0xFF);
fee8ec00
SR		 1173 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1174 addr = OP[1];
1175 if (a == 0)
1176 {
1177 if (sign_flag)
1178 addr = (PC - OP[1]);
1179 else
1180 addr = (PC + OP[1]);
1181
1182 JMP (addr);
1183 }
1184 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1185 trace_output_void (sd);
fee8ec00
SR		 1186}
1187
1188/* bne0b. */
1189void
267b3b8e 1190OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1191{
32267d59
MF		 1192 uint32_t addr;
1193 uint8_t a = (GPR (OP[0]) & 0xFF);
fee8ec00
SR		 1194 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1195 addr = OP[1];
1196 if (a != 0)
1197 {
1198 if (sign_flag)
1199 addr = (PC - OP[1]);
1200 else
1201 addr = (PC + OP[1]);
1202
1203 JMP (addr);
1204 }
1205 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1206 trace_output_void (sd);
fee8ec00
SR		 1207}
1208
1209/* beq0w. */
1210void
267b3b8e 1211OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1212{
32267d59
MF		 1213 uint32_t addr;
1214 uint16_t a = GPR (OP[0]);
fee8ec00
SR		 1215 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1216 addr = OP[1];
1217 if (a == 0)
1218 {
1219 if (sign_flag)
1220 addr = (PC - OP[1]);
1221 else
1222 addr = (PC + OP[1]);
1223
1224 JMP (addr);
1225 }
1226 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1227 trace_output_void (sd);
fee8ec00
SR		 1228}
1229
1230/* bne0w. */
1231void
267b3b8e 1232OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1233{
32267d59
MF		 1234 uint32_t addr;
1235 uint16_t a = GPR (OP[0]);
fee8ec00
SR		 1236 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1237 addr = OP[1];
1238 if (a != 0)
1239 {
1240 if (sign_flag)
1241 addr = (PC - OP[1]);
1242 else
1243 addr = (PC + OP[1]);
1244
1245 JMP (addr);
1246 }
1247 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1248 trace_output_void (sd);
fee8ec00
SR		 1249}
1250
1251
1252/* jeq. */
1253void
267b3b8e 1254OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1255{
32267d59 1256 uint32_t tmp = 0;
fee8ec00
SR		 1257 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1258 if ((PSR_Z) == 1)
1259 {
1260 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1261 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1262 }
267b3b8e 1263 trace_output_32 (sd, tmp);
fee8ec00
SR		 1264}
1265
1266/* jne. */
1267void
267b3b8e 1268OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1269{
32267d59 1270 uint32_t tmp = 0;
fee8ec00
SR		 1271 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1272 if ((PSR_Z) == 0)
1273 {
1274 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1275 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1276 }
267b3b8e 1277 trace_output_32 (sd, tmp);
fee8ec00
SR		 1278}
1279
1280/* jcs. */
1281void
267b3b8e 1282OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1283{
32267d59 1284 uint32_t tmp = 0;
fee8ec00
SR		 1285 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1286 if ((PSR_C) == 1)
1287 {
1288 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1289 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1290 }
267b3b8e 1291 trace_output_32 (sd, tmp);
fee8ec00
SR		 1292}
1293
1294/* jcc. */
1295void
267b3b8e 1296OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1297{
32267d59 1298 uint32_t tmp = 0;
fee8ec00
SR		 1299 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1300 if ((PSR_C) == 0)
1301 {
1302 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1303 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1304 }
267b3b8e 1305 trace_output_32 (sd, tmp);
fee8ec00
SR		 1306}
1307
1308/* jhi. */
1309void
267b3b8e 1310OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1311{
32267d59 1312 uint32_t tmp = 0;
fee8ec00
SR		 1313 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1314 if ((PSR_L) == 1)
1315 {
1316 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1317 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1318 }
267b3b8e 1319 trace_output_32 (sd, tmp);
fee8ec00
SR		 1320}
1321
1322/* jls. */
1323void
267b3b8e 1324OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1325{
32267d59 1326 uint32_t tmp = 0;
fee8ec00
SR		 1327 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1328 if ((PSR_L) == 0)
1329 {
1330 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1331 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1332 }
267b3b8e 1333 trace_output_32 (sd, tmp);
fee8ec00
SR		 1334}
1335
1336/* jgt. */
1337void
267b3b8e 1338OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1339{
32267d59 1340 uint32_t tmp = 0;
fee8ec00
SR		 1341 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1342 if ((PSR_N) == 1)
1343 {
1344 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1345 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1346 }
267b3b8e 1347 trace_output_32 (sd, tmp);
fee8ec00
SR		 1348}
1349
1350/* jle. */
1351void
267b3b8e 1352OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1353{
32267d59 1354 uint32_t tmp = 0;
fee8ec00
SR		 1355 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1356 if ((PSR_N) == 0)
1357 {
1358 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1359 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1360 }
267b3b8e 1361 trace_output_32 (sd, tmp);
fee8ec00
SR		 1362}
1363
1364
1365/* jfs. */
1366void
267b3b8e 1367OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1368{
32267d59 1369 uint32_t tmp = 0;
fee8ec00
SR		 1370 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1371 if ((PSR_F) == 1)
1372 {
1373 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1374 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1375 }
267b3b8e 1376 trace_output_32 (sd, tmp);
fee8ec00
SR		 1377}
1378
1379/* jfc. */
1380void
267b3b8e 1381OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1382{
32267d59 1383 uint32_t tmp = 0;
fee8ec00
SR		 1384 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1385 if ((PSR_F) == 0)
1386 {
1387 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1388 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1389 }
267b3b8e 1390 trace_output_32 (sd, tmp);
fee8ec00
SR		 1391}
1392
1393/* jlo. */
1394void
267b3b8e 1395OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1396{
32267d59 1397 uint32_t tmp = 0;
fee8ec00
SR		 1398 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1399 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1400 {
1401 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1402 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1403 }
267b3b8e 1404 trace_output_32 (sd, tmp);
fee8ec00
SR		 1405}
1406
1407/* jhs. */
1408void
267b3b8e 1409OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1410{
32267d59 1411 uint32_t tmp = 0;
fee8ec00
SR		 1412 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1413 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1414 {
1415 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1416 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1417 }
267b3b8e 1418 trace_output_32 (sd, tmp);
fee8ec00
SR		 1419}
1420
1421/* jlt. */
1422void
267b3b8e 1423OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1424{
32267d59 1425 uint32_t tmp = 0;
fee8ec00
SR		 1426 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1427 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1428 {
1429 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1430 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1431 }
267b3b8e 1432 trace_output_32 (sd, tmp);
fee8ec00
SR		 1433}
1434
1435/* jge. */
1436void
267b3b8e 1437OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1438{
32267d59 1439 uint32_t tmp = 0;
fee8ec00
SR		 1440 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1441 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1442 {
1443 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1444 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1445 }
267b3b8e 1446 trace_output_32 (sd, tmp);
fee8ec00
SR		 1447}
1448
1449/* jump. */
1450void
267b3b8e 1451OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1452{
32267d59 1453 uint32_t tmp;
fee8ec00
SR		 1454 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1455 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1456 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
267b3b8e 1457 trace_output_32 (sd, tmp);
fee8ec00
SR		 1458}
1459
1460/* jusr. */
1461void
267b3b8e 1462OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1463{
32267d59 1464 uint32_t tmp;
fee8ec00
SR		 1465 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1466 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1467 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1468 SET_PSR_U(1);
267b3b8e 1469 trace_output_32 (sd, tmp);
fee8ec00
SR		 1470}
1471
1472/* seq. */
1473void
267b3b8e 1474OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1475{
1476 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1477 if ((PSR_Z) == 1)
1478 SET_GPR (OP[0], 1);
1479 else
1480 SET_GPR (OP[0], 0);
267b3b8e 1481 trace_output_void (sd);
fee8ec00
SR		 1482}
1483/* sne. */
1484void
267b3b8e 1485OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1486{
1487 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1488 if ((PSR_Z) == 0)
1489 SET_GPR (OP[0], 1);
1490 else
1491 SET_GPR (OP[0], 0);
267b3b8e 1492 trace_output_void (sd);
fee8ec00
SR		 1493}
1494
1495/* scs. */
1496void
267b3b8e 1497OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1498{
1499 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1500 if ((PSR_C) == 1)
1501 SET_GPR (OP[0], 1);
1502 else
1503 SET_GPR (OP[0], 0);
267b3b8e 1504 trace_output_void (sd);
fee8ec00
SR		 1505}
1506
1507/* scc. */
1508void
267b3b8e 1509OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1510{
1511 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1512 if ((PSR_C) == 0)
1513 SET_GPR (OP[0], 1);
1514 else
1515 SET_GPR (OP[0], 0);
267b3b8e 1516 trace_output_void (sd);
fee8ec00
SR		 1517}
1518
1519/* shi. */
1520void
267b3b8e 1521OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1522{
1523 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1524 if ((PSR_L) == 1)
1525 SET_GPR (OP[0], 1);
1526 else
1527 SET_GPR (OP[0], 0);
267b3b8e 1528 trace_output_void (sd);
fee8ec00
SR		 1529}
1530
1531/* sls. */
1532void
267b3b8e 1533OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1534{
1535 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1536 if ((PSR_L) == 0)
1537 SET_GPR (OP[0], 1);
1538 else
1539 SET_GPR (OP[0], 0);
267b3b8e 1540 trace_output_void (sd);
fee8ec00
SR		 1541}
1542
1543/* sgt. */
1544void
267b3b8e 1545OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1546{
1547 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1548 if ((PSR_N) == 1)
1549 SET_GPR (OP[0], 1);
1550 else
1551 SET_GPR (OP[0], 0);
267b3b8e 1552 trace_output_void (sd);
fee8ec00
SR		 1553}
1554
1555/* sle. */
1556void
267b3b8e 1557OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1558{
1559 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1560 if ((PSR_N) == 0)
1561 SET_GPR (OP[0], 1);
1562 else
1563 SET_GPR (OP[0], 0);
267b3b8e 1564 trace_output_void (sd);
fee8ec00
SR		 1565}
1566
1567/* sfs. */
1568void
267b3b8e 1569OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1570{
1571 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1572 if ((PSR_F) == 1)
1573 SET_GPR (OP[0], 1);
1574 else
1575 SET_GPR (OP[0], 0);
267b3b8e 1576 trace_output_void (sd);
fee8ec00
SR		 1577}
1578
1579/* sfc. */
1580void
267b3b8e 1581OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1582{
1583 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1584 if ((PSR_F) == 0)
1585 SET_GPR (OP[0], 1);
1586 else
1587 SET_GPR (OP[0], 0);
267b3b8e 1588 trace_output_void (sd);
fee8ec00
SR		 1589}
1590
1591
1592/* slo. */
1593void
267b3b8e 1594OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1595{
1596 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1597 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1598 SET_GPR (OP[0], 1);
1599 else
1600 SET_GPR (OP[0], 0);
267b3b8e 1601 trace_output_void (sd);
fee8ec00
SR		 1602}
1603
1604/* shs. */
1605void
267b3b8e 1606OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1607{
1608 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1609 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1610 SET_GPR (OP[0], 1);
1611 else
1612 SET_GPR (OP[0], 0);
267b3b8e 1613 trace_output_void (sd);
fee8ec00
SR		 1614}
1615
1616/* slt. */
1617void
267b3b8e 1618OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1619{
1620 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1621 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1622 SET_GPR (OP[0], 1);
1623 else
1624 SET_GPR (OP[0], 0);
267b3b8e 1625 trace_output_void (sd);
fee8ec00
SR		 1626}
1627
1628/* sge. */
1629void
267b3b8e 1630OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1631{
1632 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1633 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1634 SET_GPR (OP[0], 1);
1635 else
1636 SET_GPR (OP[0], 0);
267b3b8e 1637 trace_output_void (sd);
fee8ec00
SR		 1638}
1639
1640/* cbitb. */
1641void
267b3b8e 1642OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1643{
32267d59
MF		 1644 uint8_t a = OP[0] & 0xff;
1645 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 1646 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1647 tmp = RB (addr);
1648 SET_PSR_F (tmp & (1 << a));
1649 tmp = tmp & ~(1 << a);
1650 SB (addr, tmp);
267b3b8e 1651 trace_output_32 (sd, tmp);
fee8ec00
SR		 1652}
1653
1654/* cbitb. */
1655void
267b3b8e 1656OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1657{
32267d59
MF		 1658 uint8_t a = OP[0] & 0xff;
1659 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 1660 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1661 tmp = RB (addr);
1662 SET_PSR_F (tmp & (1 << a));
1663 tmp = tmp & ~(1 << a);
1664 SB (addr, tmp);
267b3b8e 1665 trace_output_32 (sd, tmp);
fee8ec00
SR		 1666}
1667
1668/* cbitb. */
1669void
267b3b8e 1670OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1671{
32267d59
MF		 1672 uint8_t a = (OP[0]) & 0xff;
1673 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1674 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1675 tmp = RB (addr);
1676 SET_PSR_F (tmp & (1 << a));
1677 tmp = tmp & ~(1 << a);
1678 SB (addr, tmp);
267b3b8e 1679 trace_output_32 (sd, addr);
fee8ec00
SR		 1680}
1681
1682/* cbitb. */
1683void
267b3b8e 1684OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1685{
32267d59
MF		 1686 uint8_t a = (OP[0]) & 0xff;
1687 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1688 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1689 tmp = RB (addr);
1690 SET_PSR_F (tmp & (1 << a));
1691 tmp = tmp & ~(1 << a);
1692 SB (addr, tmp);
267b3b8e 1693 trace_output_32 (sd, addr);
fee8ec00
SR		 1694}
1695
1696/* cbitb. */
1697void
267b3b8e 1698OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1699{
32267d59
MF		 1700 uint8_t a = (OP[0]) & 0xff;
1701 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1702 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1703 tmp = RB (addr);
1704 SET_PSR_F (tmp & (1 << a));
1705 tmp = tmp & ~(1 << a);
1706 SB (addr, tmp);
267b3b8e 1707 trace_output_32 (sd, addr);
fee8ec00
SR		 1708}
1709
1710/* cbitb. */
1711void
267b3b8e 1712OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1713{
32267d59
MF		 1714 uint8_t a = (OP[0]) & 0xff;
1715 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1716 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1717 tmp = RB (addr);
1718 SET_PSR_F (tmp & (1 << a));
1719 tmp = tmp & ~(1 << a);
1720 SB (addr, tmp);
267b3b8e 1721 trace_output_32 (sd, addr);
fee8ec00
SR		 1722}
1723
1724/* cbitb. */
1725void
267b3b8e 1726OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1727{
32267d59
MF		 1728 uint8_t a = (OP[0]) & 0xff;
1729 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1730 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1731 tmp = RB (addr);
1732 SET_PSR_F (tmp & (1 << a));
1733 tmp = tmp & ~(1 << a);
1734 SB (addr, tmp);
267b3b8e 1735 trace_output_32 (sd, addr);
fee8ec00
SR		 1736
1737}
1738
1739/* cbitb. */
1740void
267b3b8e 1741OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1742{
32267d59
MF		 1743 uint8_t a = (OP[0]) & 0xff;
1744 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1745 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1746 tmp = RB (addr);
1747 SET_PSR_F (tmp & (1 << a));
1748 tmp = tmp & ~(1 << a);
1749 SB (addr, tmp);
267b3b8e 1750 trace_output_32 (sd, addr);
fee8ec00
SR		 1751}
1752
1753/* cbitb. */
1754void
267b3b8e 1755OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1756{
32267d59
MF		 1757 uint8_t a = (OP[0]) & 0xff;
1758 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1759 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1760 tmp = RB (addr);
1761 SET_PSR_F (tmp & (1 << a));
1762 tmp = tmp & ~(1 << a);
1763 SB (addr, tmp);
267b3b8e 1764 trace_output_32 (sd, addr);
fee8ec00
SR		 1765}
1766
1767
1768/* cbitw. */
1769void
267b3b8e 1770OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1771{
32267d59
MF		 1772 uint16_t a = OP[0];
1773 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 1774 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1775 tmp = RW (addr);
1776 SET_PSR_F (tmp & (1 << a));
1777 tmp = tmp & ~(1 << a);
1778 SW (addr, tmp);
267b3b8e 1779 trace_output_32 (sd, tmp);
fee8ec00
SR		 1780}
1781
1782/* cbitw. */
1783void
267b3b8e 1784OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1785{
32267d59
MF		 1786 uint16_t a = OP[0];
1787 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 1788 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1789 tmp = RW (addr);
1790 SET_PSR_F (tmp & (1 << a));
1791 tmp = tmp & ~(1 << a);
1792 SW (addr, tmp);
267b3b8e 1793 trace_output_32 (sd, tmp);
fee8ec00
SR		 1794}
1795
1796/* cbitw. */
1797void
267b3b8e 1798OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1799{
32267d59
MF		 1800 uint32_t addr;
1801 uint16_t a = (OP[0]), tmp;
fee8ec00
SR		 1802 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1803
1804 if (OP[1] == 0)
1805 addr = (GPR32 (12)) + OP[2];
1806 else
1807 addr = (GPR32 (13)) + OP[2];
1808
1809 tmp = RW (addr);
1810 SET_PSR_F (tmp & (1 << a));
1811 tmp = tmp & ~(1 << a);
1812 SW (addr, tmp);
267b3b8e 1813 trace_output_32 (sd, addr);
fee8ec00
SR		 1814
1815}
1816
1817/* cbitw. */
1818void
267b3b8e 1819OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1820{
32267d59
MF		 1821 uint16_t a = (OP[0]);
1822 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1823 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1824 tmp = RW (addr);
1825 SET_PSR_F (tmp & (1 << a));
1826 tmp = tmp & ~(1 << a);
1827 SW (addr, tmp);
267b3b8e 1828 trace_output_32 (sd, addr);
fee8ec00
SR		 1829}
1830
1831/* cbitw. */
1832void
267b3b8e 1833OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1834{
32267d59
MF		 1835 uint16_t a = (OP[0]);
1836 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1837 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1838 tmp = RW (addr);
1839 SET_PSR_F (tmp & (1 << a));
1840 tmp = tmp & ~(1 << a);
1841 SW (addr, tmp);
267b3b8e 1842 trace_output_32 (sd, addr);
fee8ec00
SR		 1843}
1844
1845
1846/* cbitw. */
1847void
267b3b8e 1848OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1849{
32267d59
MF		 1850 uint16_t a = (OP[0]);
1851 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1852 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1853 tmp = RW (addr);
1854 SET_PSR_F (tmp & (1 << a));
1855 tmp = tmp & ~(1 << a);
1856 SW (addr, tmp);
267b3b8e 1857 trace_output_32 (sd, addr);
fee8ec00
SR		 1858}
1859
1860/* cbitw. */
1861void
267b3b8e 1862OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1863{
32267d59
MF		 1864 uint16_t a = (OP[0]);
1865 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1866 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1867 tmp = RW (addr);
1868 SET_PSR_F (tmp & (1 << a));
1869 tmp = tmp & ~(1 << a);
1870 SW (addr, tmp);
267b3b8e 1871 trace_output_32 (sd, addr);
fee8ec00
SR		 1872}
1873
1874
1875/* cbitw. */
1876void
267b3b8e 1877OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1878{
32267d59
MF		 1879 uint16_t a = (OP[0]);
1880 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1881 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1882 tmp = RW (addr);
1883 SET_PSR_F (tmp & (1 << a));
1884 tmp = tmp & ~(1 << a);
1885 SW (addr, tmp);
267b3b8e 1886 trace_output_32 (sd, addr);
fee8ec00
SR		 1887}
1888
1889/* cbitw. */
1890void
267b3b8e 1891OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1892{
32267d59
MF		 1893 uint16_t a = (OP[0]);
1894 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1895 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1896 tmp = RW (addr);
1897 SET_PSR_F (tmp & (1 << a));
1898 tmp = tmp & ~(1 << a);
1899 SW (addr, tmp);
267b3b8e 1900 trace_output_32 (sd, addr);
fee8ec00
SR		 1901}
1902
1903/* sbitb. */
1904void
267b3b8e 1905OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1906{
32267d59
MF		 1907 uint8_t a = OP[0] & 0xff;
1908 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 1909 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1910 tmp = RB (addr);
1911 SET_PSR_F (tmp & (1 << a));
1912 tmp = tmp | (1 << a);
1913 SB (addr, tmp);
267b3b8e 1914 trace_output_32 (sd, tmp);
fee8ec00
SR		 1915}
1916
1917/* sbitb. */
1918void
267b3b8e 1919OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1920{
32267d59
MF		 1921 uint8_t a = OP[0] & 0xff;
1922 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 1923 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1924 tmp = RB (addr);
1925 SET_PSR_F (tmp & (1 << a));
1926 tmp = tmp | (1 << a);
1927 SB (addr, tmp);
267b3b8e 1928 trace_output_32 (sd, tmp);
fee8ec00
SR		 1929}
1930
1931/* sbitb. */
1932void
267b3b8e 1933OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1934{
32267d59
MF		 1935 uint8_t a = OP[0] & 0xff;
1936 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1937 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1938 tmp = RB (addr);
1939 SET_PSR_F (tmp & (1 << a));
1940 tmp = tmp | (1 << a);
1941 SB (addr, tmp);
267b3b8e 1942 trace_output_32 (sd, tmp);
fee8ec00
SR		 1943}
1944
1945/* sbitb. */
1946void
267b3b8e 1947OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1948{
32267d59
MF		 1949 uint8_t a = OP[0] & 0xff;
1950 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1951 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1952 tmp = RB (addr);
1953 SET_PSR_F (tmp & (1 << a));
1954 tmp = tmp | (1 << a);
1955 SB (addr, tmp);
267b3b8e 1956 trace_output_32 (sd, tmp);
fee8ec00
SR		 1957}
1958
1959/* sbitb. */
1960void
267b3b8e 1961OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1962{
32267d59
MF		 1963 uint8_t a = OP[0] & 0xff;
1964 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1965 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1966 tmp = RB (addr);
1967 SET_PSR_F (tmp & (1 << a));
1968 tmp = tmp | (1 << a);
1969 SB (addr, tmp);
267b3b8e 1970 trace_output_32 (sd, tmp);
fee8ec00
SR		 1971}
1972
1973
1974/* sbitb. */
1975void
267b3b8e 1976OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1977{
32267d59
MF		 1978 uint8_t a = OP[0] & 0xff;
1979 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1980 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1981 tmp = RB (addr);
1982 SET_PSR_F (tmp & (1 << a));
1983 tmp = tmp | (1 << a);
1984 SB (addr, tmp);
267b3b8e 1985 trace_output_32 (sd, tmp);
fee8ec00
SR		 1986}
1987
1988/* sbitb. */
1989void
267b3b8e 1990OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1991{
32267d59
MF		 1992 uint8_t a = OP[0] & 0xff;
1993 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 1994 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1995 tmp = RB (addr);
1996 SET_PSR_F (tmp & (1 << a));
1997 tmp = tmp | (1 << a);
1998 SB (addr, tmp);
267b3b8e 1999 trace_output_32 (sd, tmp);
fee8ec00
SR		 2000}
2001
2002
2003/* sbitb. */
2004void
267b3b8e 2005OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2006{
32267d59
MF		 2007 uint8_t a = OP[0] & 0xff;
2008 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2009 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2010 tmp = RB (addr);
2011 SET_PSR_F (tmp & (1 << a));
2012 tmp = tmp | (1 << a);
2013 SB (addr, tmp);
267b3b8e 2014 trace_output_32 (sd, tmp);
fee8ec00
SR		 2015}
2016
2017
2018/* sbitb. */
2019void
267b3b8e 2020OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2021{
32267d59
MF		 2022 uint8_t a = OP[0] & 0xff;
2023 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2024 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2025 tmp = RB (addr);
2026 SET_PSR_F (tmp & (1 << a));
2027 tmp = tmp | (1 << a);
2028 SB (addr, tmp);
267b3b8e 2029 trace_output_32 (sd, tmp);
fee8ec00
SR		 2030}
2031
2032
2033/* sbitw. */
2034void
267b3b8e 2035OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2036{
32267d59
MF		 2037 uint16_t a = OP[0];
2038 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 2039 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2040 tmp = RW (addr);
2041 SET_PSR_F (tmp & (1 << a));
2042 tmp = tmp | (1 << a);
2043 SW (addr, tmp);
267b3b8e 2044 trace_output_32 (sd, tmp);
fee8ec00
SR		 2045}
2046
2047/* sbitw. */
2048void
267b3b8e 2049OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2050{
32267d59
MF		 2051 uint16_t a = OP[0];
2052 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 2053 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2054 tmp = RW (addr);
2055 SET_PSR_F (tmp & (1 << a));
2056 tmp = tmp | (1 << a);
2057 SW (addr, tmp);
267b3b8e 2058 trace_output_32 (sd, tmp);
fee8ec00
SR		 2059}
2060
2061/* sbitw. */
2062void
267b3b8e 2063OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2064{
32267d59
MF		 2065 uint32_t addr;
2066 uint16_t a = (OP[0]), tmp;
fee8ec00
SR		 2067 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2068
2069 if (OP[1] == 0)
2070 addr = (GPR32 (12)) + OP[2];
2071 else
2072 addr = (GPR32 (13)) + OP[2];
2073
2074 tmp = RW (addr);
2075 SET_PSR_F (tmp & (1 << a));
2076 tmp = tmp | (1 << a);
2077 SW (addr, tmp);
267b3b8e 2078 trace_output_32 (sd, addr);
fee8ec00
SR		 2079}
2080
2081/* sbitw. */
2082void
267b3b8e 2083OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2084{
32267d59
MF		 2085 uint16_t a = (OP[0]);
2086 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2087 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2088 tmp = RW (addr);
2089 SET_PSR_F (tmp & (1 << a));
2090 tmp = tmp | (1 << a);
2091 SW (addr, tmp);
267b3b8e 2092 trace_output_32 (sd, addr);
fee8ec00
SR		 2093}
2094
2095/* sbitw. */
2096void
267b3b8e 2097OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2098{
32267d59
MF		 2099 uint16_t a = (OP[0]);
2100 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2101 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2102 tmp = RW (addr);
2103 SET_PSR_F (tmp & (1 << a));
2104 tmp = tmp | (1 << a);
2105 SW (addr, tmp);
267b3b8e 2106 trace_output_32 (sd, addr);
fee8ec00
SR		 2107}
2108
2109/* sbitw. */
2110void
267b3b8e 2111OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2112{
32267d59
MF		 2113 uint16_t a = (OP[0]);
2114 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2115 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2116 tmp = RW (addr);
2117 SET_PSR_F (tmp & (1 << a));
2118 tmp = tmp | (1 << a);
2119 SW (addr, tmp);
267b3b8e 2120 trace_output_32 (sd, addr);
fee8ec00
SR		 2121}
2122
2123/* sbitw. */
2124void
267b3b8e 2125OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2126{
32267d59
MF		 2127 uint16_t a = (OP[0]);
2128 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2129 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2130 tmp = RW (addr);
2131 SET_PSR_F (tmp & (1 << a));
2132 tmp = tmp | (1 << a);
2133 SW (addr, tmp);
267b3b8e 2134 trace_output_32 (sd, addr);
fee8ec00
SR		 2135}
2136
2137/* sbitw. */
2138void
267b3b8e 2139OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2140{
32267d59
MF		 2141 uint16_t a = (OP[0]);
2142 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2143 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2144 tmp = RW (addr);
2145 SET_PSR_F (tmp & (1 << a));
2146 tmp = tmp | (1 << a);
2147 SW (addr, tmp);
267b3b8e 2148 trace_output_32 (sd, addr);
fee8ec00
SR		 2149}
2150
2151/* sbitw. */
2152void
267b3b8e 2153OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2154{
32267d59
MF		 2155 uint16_t a = (OP[0]);
2156 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2157 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2158 tmp = RW (addr);
2159 SET_PSR_F (tmp & (1 << a));
2160 tmp = tmp | (1 << a);
2161 SW (addr, tmp);
267b3b8e 2162 trace_output_32 (sd, addr);
fee8ec00
SR		 2163}
2164
2165
2166/* tbitb. */
2167void
267b3b8e 2168OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2169{
32267d59
MF		 2170 uint8_t a = OP[0] & 0xff;
2171 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 2172 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2173 tmp = RB (addr);
2174 SET_PSR_F (tmp & (1 << a));
267b3b8e 2175 trace_output_32 (sd, tmp);
fee8ec00
SR		 2176}
2177
2178/* tbitb. */
2179void
267b3b8e 2180OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2181{
32267d59
MF		 2182 uint8_t a = OP[0] & 0xff;
2183 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 2184 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2185 tmp = RB (addr);
2186 SET_PSR_F (tmp & (1 << a));
267b3b8e 2187 trace_output_32 (sd, tmp);
fee8ec00
SR		 2188}
2189
2190/* tbitb. */
2191void
267b3b8e 2192OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2193{
32267d59
MF		 2194 uint8_t a = (OP[0]) & 0xff;
2195 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2196 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2197 tmp = RB (addr);
2198 SET_PSR_F (tmp & (1 << a));
267b3b8e 2199 trace_output_32 (sd, addr);
fee8ec00
SR		 2200}
2201
2202/* tbitb. */
2203void
267b3b8e 2204OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2205{
32267d59
MF		 2206 uint8_t a = (OP[0]) & 0xff;
2207 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2208 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2209 tmp = RB (addr);
2210 SET_PSR_F (tmp & (1 << a));
267b3b8e 2211 trace_output_32 (sd, addr);
fee8ec00
SR		 2212}
2213
2214/* tbitb. */
2215void
267b3b8e 2216OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2217{
32267d59
MF		 2218 uint8_t a = (OP[0]) & 0xff;
2219 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2220 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2221 tmp = RB (addr);
2222 SET_PSR_F (tmp & (1 << a));
267b3b8e 2223 trace_output_32 (sd, addr);
fee8ec00
SR		 2224}
2225
2226/* tbitb. */
2227void
267b3b8e 2228OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2229{
32267d59
MF		 2230 uint8_t a = (OP[0]) & 0xff;
2231 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2232 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2233 tmp = RB (addr);
2234 SET_PSR_F (tmp & (1 << a));
267b3b8e 2235 trace_output_32 (sd, addr);
fee8ec00
SR		 2236}
2237
2238/* tbitb. */
2239void
267b3b8e 2240OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2241{
32267d59
MF		 2242 uint8_t a = (OP[0]) & 0xff;
2243 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2244 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2245 tmp = RB (addr);
2246 SET_PSR_F (tmp & (1 << a));
267b3b8e 2247 trace_output_32 (sd, addr);
fee8ec00
SR		 2248}
2249
2250/* tbitb. */
2251void
267b3b8e 2252OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2253{
32267d59
MF		 2254 uint8_t a = (OP[0]) & 0xff;
2255 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2256 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2257 tmp = RB (addr);
2258 SET_PSR_F (tmp & (1 << a));
267b3b8e 2259 trace_output_32 (sd, addr);
fee8ec00
SR		 2260}
2261
2262/* tbitb. */
2263void
267b3b8e 2264OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2265{
32267d59
MF		 2266 uint8_t a = (OP[0]) & 0xff;
2267 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2268 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2269 tmp = RB (addr);
2270 SET_PSR_F (tmp & (1 << a));
267b3b8e 2271 trace_output_32 (sd, addr);
fee8ec00
SR		 2272}
2273
2274
2275/* tbitw. */
2276void
267b3b8e 2277OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2278{
32267d59
MF		 2279 uint16_t a = OP[0];
2280 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 2281 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2282 tmp = RW (addr);
2283 SET_PSR_F (tmp & (1 << a));
267b3b8e 2284 trace_output_32 (sd, tmp);
fee8ec00
SR		 2285}
2286
2287/* tbitw. */
2288void
267b3b8e 2289OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2290{
32267d59
MF		 2291 uint16_t a = OP[0];
2292 uint32_t addr = OP[1], tmp;
fee8ec00
SR		 2293 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2294 tmp = RW (addr);
2295 SET_PSR_F (tmp & (1 << a));
267b3b8e 2296 trace_output_32 (sd, tmp);
fee8ec00
SR		 2297}
2298
2299
2300/* tbitw. */
2301void
267b3b8e 2302OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2303{
32267d59
MF		 2304 uint32_t addr;
2305 uint16_t a = (OP[0]), tmp;
fee8ec00
SR		 2306 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2307
2308 if (OP[1] == 0)
2309 addr = (GPR32 (12)) + OP[2];
2310 else
2311 addr = (GPR32 (13)) + OP[2];
2312
2313 tmp = RW (addr);
2314 SET_PSR_F (tmp & (1 << a));
267b3b8e 2315 trace_output_32 (sd, addr);
fee8ec00
SR		 2316}
2317
2318/* tbitw. */
2319void
267b3b8e 2320OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2321{
32267d59
MF		 2322 uint16_t a = (OP[0]);
2323 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2324 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2325 tmp = RW (addr);
2326 SET_PSR_F (tmp & (1 << a));
267b3b8e 2327 trace_output_32 (sd, addr);
fee8ec00
SR		 2328}
2329
2330/* tbitw. */
2331void
267b3b8e 2332OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2333{
32267d59
MF		 2334 uint16_t a = (OP[0]);
2335 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2336 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2337 tmp = RW (addr);
2338 SET_PSR_F (tmp & (1 << a));
267b3b8e 2339 trace_output_32 (sd, addr);
fee8ec00
SR		 2340}
2341
2342/* tbitw. */
2343void
267b3b8e 2344OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2345{
32267d59
MF		 2346 uint16_t a = (OP[0]);
2347 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2348 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2349 tmp = RW (addr);
2350 SET_PSR_F (tmp & (1 << a));
267b3b8e 2351 trace_output_32 (sd, addr);
fee8ec00
SR		 2352}
2353
2354/* tbitw. */
2355void
267b3b8e 2356OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2357{
32267d59
MF		 2358 uint16_t a = (OP[0]);
2359 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2360 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2361 tmp = RW (addr);
2362 SET_PSR_F (tmp & (1 << a));
267b3b8e 2363 trace_output_32 (sd, addr);
fee8ec00
SR		 2364}
2365
2366/* tbitw. */
2367void
267b3b8e 2368OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2369{
32267d59
MF		 2370 uint16_t a = (OP[0]);
2371 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2372 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2373 tmp = RW (addr);
2374 SET_PSR_F (tmp & (1 << a));
267b3b8e 2375 trace_output_32 (sd, addr);
fee8ec00
SR		 2376}
2377
2378
2379/* tbitw. */
2380void
267b3b8e 2381OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2382{
32267d59
MF		 2383 uint16_t a = (OP[0]);
2384 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
fee8ec00
SR		 2385 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2386 tmp = RW (addr);
2387 SET_PSR_F (tmp & (1 << a));
267b3b8e 2388 trace_output_32 (sd, addr);
fee8ec00
SR		 2389}
2390
2391
2392/* tbit. */
2393void
267b3b8e 2394OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2395{
32267d59
MF		 2396 uint16_t a = OP[0];
2397 uint16_t b = (GPR (OP[1]));
fee8ec00 2398 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
537e4bb9 2399 SET_PSR_F (b & (1 << a));
267b3b8e 2400 trace_output_16 (sd, b);
fee8ec00
SR		 2401}
2402
2403/* tbit. */
2404void
267b3b8e 2405OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2406{
32267d59
MF		 2407 uint16_t a = GPR (OP[0]);
2408 uint16_t b = (GPR (OP[1]));
fee8ec00 2409 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
537e4bb9 2410 SET_PSR_F (b & (1 << a));
267b3b8e 2411 trace_output_16 (sd, b);
fee8ec00
SR		 2412}
2413
2414
2415/* cmpb. */
2416void
267b3b8e 2417OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2418{
32267d59
MF		 2419 uint8_t a = (OP[0]) & 0xFF;
2420 uint8_t b = (GPR (OP[1])) & 0xFF;
fee8ec00
SR		 2421 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2422 SET_PSR_Z (a == b);
32267d59 2423 SET_PSR_N ((int8_t)a > (int8_t)b);
fee8ec00 2424 SET_PSR_L (a > b);
267b3b8e 2425 trace_output_flag (sd);
fee8ec00
SR		 2426}
2427
2428/* cmpb. */
2429void
267b3b8e 2430OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2431{
32267d59
MF		 2432 uint8_t a = (OP[0]) & 0xFF;
2433 uint8_t b = (GPR (OP[1])) & 0xFF;
fee8ec00
SR		 2434 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2435 SET_PSR_Z (a == b);
32267d59 2436 SET_PSR_N ((int8_t)a > (int8_t)b);
fee8ec00 2437 SET_PSR_L (a > b);
267b3b8e 2438 trace_output_flag (sd);
fee8ec00
SR		 2439}
2440
2441/* cmpb. */
2442void
267b3b8e 2443OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2444{
32267d59
MF		 2445 uint8_t a = (GPR (OP[0])) & 0xFF;
2446 uint8_t b = (GPR (OP[1])) & 0xFF;
fee8ec00
SR		 2447 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2448 SET_PSR_Z (a == b);
32267d59 2449 SET_PSR_N ((int8_t)a > (int8_t)b);
fee8ec00 2450 SET_PSR_L (a > b);
267b3b8e 2451 trace_output_flag (sd);
fee8ec00
SR		 2452}
2453
2454/* cmpw. */
2455void
267b3b8e 2456OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2457{
32267d59
MF		 2458 uint16_t a = (OP[0]);
2459 uint16_t b = GPR (OP[1]);
fee8ec00
SR		 2460 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2461 SET_PSR_Z (a == b);
32267d59 2462 SET_PSR_N ((int16_t)a > (int16_t)b);
fee8ec00 2463 SET_PSR_L (a > b);
267b3b8e 2464 trace_output_flag (sd);
fee8ec00
SR		 2465}
2466
2467/* cmpw. */
2468void
267b3b8e 2469OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2470{
32267d59
MF		 2471 uint16_t a = (OP[0]);
2472 uint16_t b = GPR (OP[1]);
fee8ec00
SR		 2473 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2474 SET_PSR_Z (a == b);
32267d59 2475 SET_PSR_N ((int16_t)a > (int16_t)b);
fee8ec00 2476 SET_PSR_L (a > b);
267b3b8e 2477 trace_output_flag (sd);
fee8ec00
SR		 2478}
2479
2480/* cmpw. */
2481void
267b3b8e 2482OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2483{
32267d59
MF		 2484 uint16_t a = GPR (OP[0]) ;
2485 uint16_t b = GPR (OP[1]) ;
fee8ec00
SR		 2486 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2487 SET_PSR_Z (a == b);
32267d59 2488 SET_PSR_N ((int16_t)a > (int16_t)b);
fee8ec00 2489 SET_PSR_L (a > b);
267b3b8e 2490 trace_output_flag (sd);
fee8ec00
SR		 2491}
2492
2493/* cmpd. */
2494void
267b3b8e 2495OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2496{
32267d59
MF		 2497 uint32_t a = (OP[0]);
2498 uint32_t b = GPR32 (OP[1]);
fee8ec00
SR		 2499 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2500 SET_PSR_Z (a == b);
32267d59 2501 SET_PSR_N ((int32_t)a > (int32_t)b);
fee8ec00 2502 SET_PSR_L (a > b);
267b3b8e 2503 trace_output_flag (sd);
fee8ec00
SR		 2504}
2505
2506/* cmpd. */
2507void
267b3b8e 2508OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2509{
32267d59
MF		 2510 uint32_t a = (SEXT16(OP[0]));
2511 uint32_t b = GPR32 (OP[1]);
fee8ec00
SR		 2512 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2513 SET_PSR_Z (a == b);
32267d59 2514 SET_PSR_N ((int32_t)a > (int32_t)b);
fee8ec00 2515 SET_PSR_L (a > b);
267b3b8e 2516 trace_output_flag (sd);
fee8ec00
SR		 2517}
2518
2519/* cmpd. */
2520void
267b3b8e 2521OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2522{
32267d59
MF		 2523 uint32_t a = GPR32 (OP[0]) ;
2524 uint32_t b = GPR32 (OP[1]) ;
fee8ec00
SR		 2525 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2526 SET_PSR_Z (a == b);
32267d59 2527 SET_PSR_N ((int32_t)a > (int32_t)b);
fee8ec00 2528 SET_PSR_L (a > b);
267b3b8e 2529 trace_output_flag (sd);
fee8ec00
SR		 2530}
2531
2532/* cmpd. */
2533void
267b3b8e 2534OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2535{
32267d59
MF		 2536 uint32_t a = (OP[0]);
2537 uint32_t b = GPR32 (OP[1]);
fee8ec00
SR		 2538 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2539 SET_PSR_Z (a == b);
32267d59 2540 SET_PSR_N ((int32_t)a > (int32_t)b);
fee8ec00 2541 SET_PSR_L (a > b);
267b3b8e 2542 trace_output_flag (sd);
fee8ec00
SR		 2543}
2544
2545
2546/* movb. */
2547void
267b3b8e 2548OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2549{
32267d59
MF		 2550 uint8_t tmp = OP[0] & 0xFF;
2551 uint16_t a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2552 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
fee8ec00 2553 SET_GPR (OP[1], (a | tmp));
267b3b8e 2554 trace_output_16 (sd, tmp);
fee8ec00
SR		 2555}
2556
2557/* movb. */
2558void
267b3b8e 2559OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2560{
32267d59
MF		 2561 uint8_t tmp = OP[0] & 0xFF;
2562 uint16_t a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2563 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00 2564 SET_GPR (OP[1], (a | tmp));
267b3b8e 2565 trace_output_16 (sd, tmp);
fee8ec00
SR		 2566}
2567
2568/* movb. */
2569void
267b3b8e 2570OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2571{
32267d59
MF		 2572 uint8_t tmp = (GPR (OP[0])) & 0xFF;
2573 uint16_t a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2574 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
fee8ec00 2575 SET_GPR (OP[1], (a | tmp));
267b3b8e 2576 trace_output_16 (sd, tmp);
fee8ec00
SR		 2577}
2578
2579/* movw. */
2580void
267b3b8e 2581OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2582{
32267d59 2583 uint16_t tmp = OP[0];
fee8ec00
SR		 2584 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2585 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 2586 trace_output_16 (sd, tmp);
fee8ec00
SR		 2587}
2588
2589/* movw. */
2590void
267b3b8e 2591OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2592{
32267d59 2593 int16_t tmp = OP[0];
fee8ec00
SR		 2594 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2595 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 2596 trace_output_16 (sd, tmp);
fee8ec00
SR		 2597}
2598
2599/* movw. */
2600void
267b3b8e 2601OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2602{
32267d59
MF		 2603 uint16_t tmp = GPR (OP[0]);
2604 uint32_t a = GPR32 (OP[1]);
5aedb83b 2605 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
fee8ec00
SR		 2606 a = (a & 0xffff0000) | tmp;
2607 SET_GPR32 (OP[1], a);
267b3b8e 2608 trace_output_16 (sd, tmp);
fee8ec00
SR		 2609}
2610
2611/* movxb. */
2612void
267b3b8e 2613OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2614{
32267d59 2615 uint8_t tmp = (GPR (OP[0])) & 0xFF;
fee8ec00
SR		 2616 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2617 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
267b3b8e 2618 trace_output_16 (sd, tmp);
fee8ec00
SR		 2619}
2620
2621/* movzb. */
2622void
267b3b8e 2623OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2624{
32267d59 2625 uint8_t tmp = (GPR (OP[0])) & 0xFF;
fee8ec00
SR		 2626 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2627 SET_GPR (OP[1], tmp);
267b3b8e 2628 trace_output_16 (sd, tmp);
fee8ec00
SR		 2629}
2630
2631/* movxw. */
2632void
267b3b8e 2633OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2634{
32267d59 2635 uint16_t tmp = GPR (OP[0]);
fee8ec00
SR		 2636 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2637 SET_GPR32 (OP[1], SEXT16(tmp));
267b3b8e 2638 trace_output_16 (sd, tmp);
fee8ec00
SR		 2639}
2640
2641/* movzw. */
2642void
267b3b8e 2643OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2644{
32267d59 2645 uint16_t tmp = GPR (OP[0]);
fee8ec00
SR		 2646 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2647 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
267b3b8e 2648 trace_output_16 (sd, tmp);
fee8ec00
SR		 2649}
2650
2651/* movd. */
2652void
267b3b8e 2653OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2654{
32267d59 2655 int32_t tmp = OP[0];
fee8ec00
SR		 2656 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2657 SET_GPR32 (OP[1], tmp);
267b3b8e 2658 trace_output_32 (sd, tmp);
fee8ec00
SR		 2659}
2660
2661/* movd. */
2662void
267b3b8e 2663OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2664{
32267d59 2665 int32_t tmp = SEXT16(OP[0]);
fee8ec00
SR		 2666 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2667 SET_GPR32 (OP[1], tmp);
267b3b8e 2668 trace_output_32 (sd, tmp);
fee8ec00
SR		 2669}
2670
2671/* movd. */
2672void
267b3b8e 2673OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2674{
32267d59 2675 uint32_t tmp = GPR32 (OP[0]);
fee8ec00
SR		 2676 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2677 SET_GPR32 (OP[1], tmp);
267b3b8e 2678 trace_output_32 (sd, tmp);
fee8ec00
SR		 2679}
2680
2681/* movd. */
2682void
267b3b8e 2683OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2684{
32267d59 2685 uint32_t tmp = OP[0];
fee8ec00
SR		 2686 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2687 SET_GPR32 (OP[1], tmp);
267b3b8e 2688 trace_output_32 (sd, tmp);
fee8ec00
SR		 2689}
2690
2691/* movd. */
2692void
267b3b8e 2693OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2694{
32267d59 2695 int32_t tmp = OP[0];
fee8ec00
SR		 2696 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2697 SET_GPR32 (OP[1], tmp);
267b3b8e 2698 trace_output_32 (sd, tmp);
fee8ec00
SR		 2699}
2700
2701/* loadm. */
2702void
267b3b8e 2703OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2704{
32267d59
MF		 2705 uint32_t addr = GPR (0);
2706 uint16_t count = OP[0], reg = 2, tmp;
fee8ec00
SR		 2707 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2708 if ((addr & 1))
2709 {
267b3b8e 2710 trace_output_void (sd);
0ef7f981 2711 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 2712 }
2713
2714 while (count)
2715 {
2716 tmp = RW (addr);
2717 SET_GPR (reg, tmp);
2718 addr +=2;
2719 --count;
2720 reg++;
2721 if (reg == 6) reg = 8;
2722 };
2723
2724 SET_GPR (0, addr);
267b3b8e 2725 trace_output_void (sd);
fee8ec00
SR		 2726}
2727
2728
2729/* loadmp. */
2730void
267b3b8e 2731OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 2732{
32267d59
MF		 2733 uint32_t addr = GPR32 (0);
2734 uint16_t count = OP[0], reg = 2, tmp;
fee8ec00
SR		 2735 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2736 if ((addr & 1))
2737 {
267b3b8e 2738 trace_output_void (sd);
0ef7f981 2739 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 2740 }
2741
2742 while (count)
2743 {
2744 tmp = RW (addr);
2745 SET_GPR (reg, tmp);
2746 addr +=2;
2747 --count;
2748 reg++;
2749 if (reg == 6) reg = 8;
2750 };
2751
2752 SET_GPR32 (0, addr);
267b3b8e 2753 trace_output_void (sd);
fee8ec00
SR		 2754}
2755
2756
2757/* loadb. */
2758void
267b3b8e 2759OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2760{
2761 /* loadb ABS20, REG
2762 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2763 * REG = [ADDR]
2764 * NOTE: remap is
2765 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2766 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2767 * by the core to 16M-64k to 16M. */
2768
32267d59
MF		 2769 uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
2770 uint32_t addr = OP[0];
fee8ec00
SR		 2771 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2772 if (addr > 0xEFFFF) addr |= 0xF00000;
2773 tmp = (RB (addr));
2774 SET_GPR (OP[1], (a | tmp));
267b3b8e 2775 trace_output_16 (sd, tmp);
fee8ec00
SR		 2776}
2777
2778/* loadb. */
2779void
267b3b8e 2780OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2781{
2782 /* loadb ABS24, REG
2783 * ADDR = abs24
2784 * REGR = [ADDR]. */
2785
32267d59
MF		 2786 uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
2787 uint32_t addr = OP[0];
fee8ec00
SR		 2788 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2789 tmp = (RB (addr));
2790 SET_GPR (OP[1], (a | tmp));
267b3b8e 2791 trace_output_16 (sd, tmp);
fee8ec00
SR		 2792}
2793
2794/* loadb. */
2795void
267b3b8e 2796OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2797{
2798 /* loadb [Rindex]ABS20 REG
2799 * ADDR = Rindex + zext24(disp20)
2800 * REGR = [ADDR]. */
2801
32267d59
MF		 2802 uint32_t addr;
2803 uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
fee8ec00
SR		 2804 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2805
2806 if (OP[0] == 0)
2807 addr = (GPR32 (12)) + OP[1];
2808 else
2809 addr = (GPR32 (13)) + OP[1];
2810
2811 tmp = (RB (addr));
2812 SET_GPR (OP[2], (a | tmp));
267b3b8e 2813 trace_output_16 (sd, tmp);
fee8ec00
SR		 2814}
2815
2816
2817/* loadb. */
2818void
267b3b8e 2819OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2820{
2821 /* loadb DIPS4(REGP) REG
2822 * ADDR = RPBASE + zext24(DISP4)
2823 * REG = [ADDR]. */
32267d59
MF		 2824 uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
2825 uint32_t addr = (GPR32 (OP[1])) + OP[0];
fee8ec00
SR		 2826 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2827 tmp = (RB (addr));
2828 SET_GPR (OP[2], (a | tmp));
267b3b8e 2829 trace_output_16 (sd, tmp);
fee8ec00
SR		 2830}
2831
2832/* loadb. */
2833void
267b3b8e 2834OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2835{
2836 /* loadb [Rindex]disp0(RPbasex) REG
2837 * ADDR = Rpbasex + Rindex
2838 * REGR = [ADDR] */
2839
32267d59
MF		 2840 uint32_t addr;
2841 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
fee8ec00
SR		 2842 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2843
2844 addr = (GPR32 (OP[2])) + OP[1];
2845
2846 if (OP[0] == 0)
2847 addr = (GPR32 (12)) + addr;
2848 else
2849 addr = (GPR32 (13)) + addr;
2850
2851 tmp = (RB (addr));
2852 SET_GPR (OP[3], (a | tmp));
267b3b8e 2853 trace_output_16 (sd, tmp);
fee8ec00
SR		 2854}
2855
2856/* loadb. */
2857void
267b3b8e 2858OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2859{
2860 /* loadb [Rindex]disp14(RPbasex) REG
2861 * ADDR = Rpbasex + Rindex + zext24(disp14)
2862 * REGR = [ADDR] */
2863
32267d59
MF		 2864 uint32_t addr;
2865 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
fee8ec00
SR		 2866
2867 addr = (GPR32 (OP[2])) + OP[1];
2868
2869 if (OP[0] == 0)
2870 addr = (GPR32 (12)) + addr;
2871 else
2872 addr = (GPR32 (13)) + addr;
2873
2874 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2875 tmp = (RB (addr));
2876 SET_GPR (OP[3], (a | tmp));
267b3b8e 2877 trace_output_16 (sd, tmp);
fee8ec00
SR		 2878}
2879
2880
2881/* loadb. */
2882void
267b3b8e 2883OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2884{
2885 /* loadb DISPE20(REG) REG
2886 * zext24(Rbase) + zext24(dispe20)
2887 * REG = [ADDR] */
2888
32267d59
MF		 2889 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2890 uint32_t addr = OP[0] + (GPR (OP[1]));
fee8ec00
SR		 2891 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2892 tmp = (RB (addr));
2893 SET_GPR (OP[2], (a | tmp));
267b3b8e 2894 trace_output_16 (sd, tmp);
fee8ec00
SR		 2895}
2896
2897/* loadb. */
2898void
267b3b8e 2899OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2900{
2901 /* loadb DISP20(REG) REG
2902 * ADDR = zext24(Rbase) + zext24(disp20)
2903 * REG = [ADDR] */
2904
32267d59
MF		 2905 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2906 uint32_t addr = OP[0] + (GPR (OP[1]));
fee8ec00
SR		 2907 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2908 tmp = (RB (addr));
2909 SET_GPR (OP[2], (a | tmp));
267b3b8e 2910 trace_output_16 (sd, tmp);
fee8ec00
SR		 2911}
2912
2913/* loadb. */
2914void
267b3b8e 2915OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2916{
2917 /* loadb disp16(REGP) REG
2918 * ADDR = RPbase + zext24(disp16)
2919 * REGR = [ADDR] */
2920
32267d59
MF		 2921 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2922 uint32_t addr = (GPR32 (OP[1])) + OP[0];
fee8ec00
SR		 2923 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2924 tmp = (RB (addr));
2925 SET_GPR (OP[2], (a | tmp));
267b3b8e 2926 trace_output_16 (sd, tmp);
fee8ec00
SR		 2927}
2928
2929/* loadb. */
2930void
267b3b8e 2931OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2932{
2933 /* loadb disp20(REGP) REG
2934 * ADDR = RPbase + zext24(disp20)
2935 * REGR = [ADDR] */
32267d59
MF		 2936 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2937 uint32_t addr = (GPR32 (OP[1])) + OP[0];
fee8ec00
SR		 2938 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2939 tmp = (RB (addr));
2940 SET_GPR (OP[2], (a | tmp));
267b3b8e 2941 trace_output_16 (sd, tmp);
fee8ec00
SR		 2942}
2943
2944
2945/* loadb. */
2946void
267b3b8e 2947OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2948{
2949 /* loadb -disp20(REGP) REG
2950 * ADDR = RPbase + zext24(-disp20)
2951 * REGR = [ADDR] */
32267d59
MF		 2952 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2953 uint32_t addr = (GPR32 (OP[1])) + OP[1];
fee8ec00
SR		 2954 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2955 tmp = (RB (addr));
2956 SET_GPR (OP[2], (a | tmp));
267b3b8e 2957 trace_output_16 (sd, tmp);
fee8ec00
SR		 2958}
2959
2960/* loadb. */
2961void
267b3b8e 2962OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2963{
2964 /* loadb [Rindex]disp20(RPbasexb) REG
2965 * ADDR = RPbasex + Rindex + zext24(disp20)
2966 * REGR = [ADDR] */
2967
32267d59
MF		 2968 uint32_t addr;
2969 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
fee8ec00
SR		 2970 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2971
2972 addr = (GPR32 (OP[2])) + OP[1];
2973
2974 if (OP[0] == 0)
2975 addr = (GPR32 (12)) + addr;
2976 else
2977 addr = (GPR32 (13)) + addr;
2978
2979 tmp = (RB (addr));
2980 SET_GPR (OP[3], (a | tmp));
267b3b8e 2981 trace_output_16 (sd, tmp);
fee8ec00
SR		 2982}
2983
2984
2985/* loadw. */
2986void
267b3b8e 2987OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2988{
2989 /* loadw ABS20, REG
2990 * ADDR = zext24(abs20) | remap
2991 * REGR = [ADDR]
2992 * NOTE: remap is
2993 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2994 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2995 * by the core to 16M-64k to 16M. */
2996
32267d59
MF		 2997 uint16_t tmp;
2998 uint32_t addr = OP[0];
fee8ec00
SR		 2999 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
3000 if (addr > 0xEFFFF) addr |= 0xF00000;
3001 tmp = (RW (addr));
3002 SET_GPR (OP[1], tmp);
267b3b8e 3003 trace_output_16 (sd, tmp);
fee8ec00
SR		 3004}
3005
3006
3007/* loadw. */
3008void
267b3b8e 3009OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3010{
3011 /* loadw ABS24, REG
3012 * ADDR = abs24
3013 * REGR = [ADDR] */
32267d59
MF		 3014 uint16_t tmp;
3015 uint32_t addr = OP[0];
fee8ec00
SR		 3016 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3017 tmp = (RW (addr));
3018 SET_GPR (OP[1], tmp);
267b3b8e 3019 trace_output_16 (sd, tmp);
fee8ec00
SR		 3020}
3021
3022/* loadw. */
3023void
267b3b8e 3024OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3025{
3026 /* loadw [Rindex]ABS20 REG
3027 * ADDR = Rindex + zext24(disp20)
3028 * REGR = [ADDR] */
3029
32267d59
MF		 3030 uint32_t addr;
3031 uint16_t tmp;
fee8ec00
SR		 3032 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3033
3034 if (OP[0] == 0)
3035 addr = (GPR32 (12)) + OP[1];
3036 else
3037 addr = (GPR32 (13)) + OP[1];
3038
3039 tmp = (RW (addr));
3040 SET_GPR (OP[2], tmp);
267b3b8e 3041 trace_output_16 (sd, tmp);
fee8ec00
SR		 3042}
3043
3044
3045/* loadw. */
3046void
267b3b8e 3047OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3048{
3049 /* loadw DIPS4(REGP) REGP
3050 * ADDR = RPBASE + zext24(DISP4)
3051 * REGP = [ADDR]. */
32267d59
MF		 3052 uint16_t tmp;
3053 uint32_t addr, a;
fee8ec00
SR		 3054 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3055 addr = (GPR32 (OP[1])) + OP[0];
3056 tmp = (RW (addr));
3057 if (OP[2] > 11)
3058 {
3059 a = (GPR32 (OP[2])) & 0xffff0000;
3060 SET_GPR32 (OP[2], (a | tmp));
3061 }
3062 else
3063 SET_GPR (OP[2], tmp);
3064
267b3b8e 3065 trace_output_16 (sd, tmp);
fee8ec00
SR		 3066}
3067
3068
3069/* loadw. */
3070void
267b3b8e 3071OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3072{
3073 /* loadw [Rindex]disp0(RPbasex) REG
3074 * ADDR = Rpbasex + Rindex
3075 * REGR = [ADDR] */
3076
32267d59
MF		 3077 uint32_t addr;
3078 uint16_t tmp;
fee8ec00
SR		 3079 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3080
3081 addr = (GPR32 (OP[2])) + OP[1];
3082
3083 if (OP[0] == 0)
3084 addr = (GPR32 (12)) + addr;
3085 else
3086 addr = (GPR32 (13)) + addr;
3087
3088 tmp = RW (addr);
3089 SET_GPR (OP[3], tmp);
267b3b8e 3090 trace_output_16 (sd, tmp);
fee8ec00
SR		 3091}
3092
3093
3094/* loadw. */
3095void
267b3b8e 3096OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3097{
3098 /* loadw [Rindex]disp14(RPbasex) REG
3099 * ADDR = Rpbasex + Rindex + zext24(disp14)
3100 * REGR = [ADDR] */
3101
32267d59
MF		 3102 uint32_t addr;
3103 uint16_t tmp;
fee8ec00
SR		 3104 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3105 addr = (GPR32 (OP[2])) + OP[1];
3106
3107 if (OP[0] == 0)
3108 addr = (GPR32 (12)) + addr;
3109 else
3110 addr = (GPR32 (13)) + addr;
3111
3112 tmp = (RW (addr));
3113 SET_GPR (OP[3], tmp);
267b3b8e 3114 trace_output_16 (sd, tmp);
fee8ec00
SR		 3115}
3116
3117/* loadw. */
3118void
267b3b8e 3119OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3120{
3121 /* loadw dispe20(REG) REGP
3122 * REGP = [DISPE20+[REG]] */
3123
32267d59
MF		 3124 uint16_t tmp;
3125 uint32_t addr, a;
fee8ec00
SR		 3126 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3127 addr = OP[0] + (GPR (OP[1]));
3128 tmp = (RW (addr));
3129 if (OP[2] > 11)
3130 {
3131 a = (GPR32 (OP[2])) & 0xffff0000;
3132 SET_GPR32 (OP[2], (a | tmp));
3133 }
3134 else
3135 SET_GPR (OP[2], tmp);
3136
267b3b8e 3137 trace_output_16 (sd, tmp);
fee8ec00
SR		 3138}
3139
3140
3141/* loadw. */
3142void
267b3b8e 3143OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3144{
3145 /* loadw DISP20(REG) REGP
3146 * ADDR = zext24(Rbase) + zext24(disp20)
3147 * REGP = [ADDR] */
3148
32267d59
MF		 3149 uint16_t tmp;
3150 uint32_t addr, a;
fee8ec00
SR		 3151 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3152 addr = OP[0] + (GPR (OP[1]));
3153 tmp = (RW (addr));
3154 if (OP[2] > 11)
3155 {
3156 a = (GPR32 (OP[2])) & 0xffff0000;
3157 SET_GPR32 (OP[2], (a | tmp));
3158 }
3159 else
3160 SET_GPR (OP[2], tmp);
3161
267b3b8e 3162 trace_output_16 (sd, tmp);
fee8ec00
SR		 3163}
3164
3165/* loadw. */
3166void
267b3b8e 3167OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3168{
3169 /* loadw disp16(REGP) REGP
3170 * ADDR = RPbase + zext24(disp16)
3171 * REGP = [ADDR] */
32267d59
MF		 3172 uint16_t tmp;
3173 uint32_t addr, a;
fee8ec00
SR		 3174 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3175 addr = (GPR32 (OP[1])) + OP[0];
3176 tmp = (RW (addr));
3177 if (OP[2] > 11)
3178 {
3179 a = (GPR32 (OP[2])) & 0xffff0000;
3180 SET_GPR32 (OP[2], (a | tmp));
3181 }
3182 else
3183 SET_GPR (OP[2], tmp);
3184
267b3b8e 3185 trace_output_16 (sd, tmp);
fee8ec00
SR		 3186}
3187
3188/* loadw. */
3189void
267b3b8e 3190OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3191{
3192 /* loadw disp20(REGP) REGP
3193 * ADDR = RPbase + zext24(disp20)
3194 * REGP = [ADDR] */
32267d59
MF		 3195 uint16_t tmp;
3196 uint32_t addr, a;
fee8ec00
SR		 3197 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3198 addr = (GPR32 (OP[1])) + OP[0];
3199 tmp = (RW (addr));
3200 if (OP[2] > 11)
3201 {
3202 a = (GPR32 (OP[2])) & 0xffff0000;
3203 SET_GPR32 (OP[2], (a | tmp));
3204 }
3205 else
3206 SET_GPR (OP[2], tmp);
3207
267b3b8e 3208 trace_output_16 (sd, tmp);
fee8ec00
SR		 3209}
3210
3211/* loadw. */
3212void
267b3b8e 3213OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3214{
3215 /* loadw -disp20(REGP) REG
3216 * ADDR = RPbase + zext24(-disp20)
3217 * REGR = [ADDR] */
3218
32267d59
MF		 3219 uint16_t tmp;
3220 uint32_t addr, a;
fee8ec00
SR		 3221 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3222 addr = (GPR32 (OP[1])) + OP[0];
3223 tmp = (RB (addr));
3224 if (OP[2] > 11)
3225 {
3226 a = (GPR32 (OP[2])) & 0xffff0000;
3227 SET_GPR32 (OP[2], (a | tmp));
3228 }
3229 else
3230 SET_GPR (OP[2], tmp);
3231
267b3b8e 3232 trace_output_16 (sd, tmp);
fee8ec00
SR		 3233}
3234
3235
3236/* loadw. */
3237void
267b3b8e 3238OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3239{
3240 /* loadw [Rindex]disp20(RPbasexb) REG
3241 * ADDR = RPbasex + Rindex + zext24(disp20)
3242 * REGR = [ADDR] */
3243
32267d59
MF		 3244 uint32_t addr;
3245 uint16_t tmp;
fee8ec00
SR		 3246 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3247
3248 if (OP[0] == 0)
3249 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3250 else
3251 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3252
3253 tmp = (RW (addr));
3254 SET_GPR (OP[3], tmp);
267b3b8e 3255 trace_output_16 (sd, tmp);
fee8ec00
SR		 3256}
3257
3258
3259/* loadd. */
3260void
267b3b8e 3261OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3262{
3263 /* loadd ABS20, REGP
3264 * ADDR = zext24(abs20) | remap
3265 * REGP = [ADDR]
3266 * NOTE: remap is
3267 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3268 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3269 * by the core to 16M-64k to 16M. */
3270
32267d59 3271 uint32_t addr, tmp;
fee8ec00
SR		 3272 addr = OP[0];
3273 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3274 if (addr > 0xEFFFF) addr |= 0xF00000;
3275 tmp = RLW (addr);
3276 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3277 SET_GPR32 (OP[1], tmp);
267b3b8e 3278 trace_output_32 (sd, tmp);
fee8ec00
SR		 3279}
3280
3281/* loadd. */
3282void
267b3b8e 3283OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3284{
3285 /* loadd ABS24, REGP
3286 * ADDR = abs24
3287 * REGP = [ADDR] */
3288
32267d59
MF		 3289 uint32_t addr = OP[0];
3290 uint32_t tmp;
fee8ec00
SR		 3291 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3292 tmp = RLW (addr);
3293 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3294 SET_GPR32 (OP[1],tmp);
267b3b8e 3295 trace_output_32 (sd, tmp);
fee8ec00
SR		 3296}
3297
3298
3299/* loadd. */
3300void
267b3b8e 3301OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3302{
3303 /* loadd [Rindex]ABS20 REGP
3304 * ADDR = Rindex + zext24(disp20)
3305 * REGP = [ADDR] */
3306
32267d59 3307 uint32_t addr, tmp;
fee8ec00
SR		 3308 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3309
3310 if (OP[0] == 0)
3311 addr = (GPR32 (12)) + OP[1];
3312 else
3313 addr = (GPR32 (13)) + OP[1];
3314
3315 tmp = RLW (addr);
3316 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3317 SET_GPR32 (OP[2], tmp);
267b3b8e 3318 trace_output_32 (sd, tmp);
fee8ec00
SR		 3319}
3320
3321
3322/* loadd. */
3323void
267b3b8e 3324OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3325{
3326 /* loadd dips4(regp) REGP
3327 * ADDR = Rpbase + zext24(disp4)
3328 * REGP = [ADDR] */
3329
32267d59 3330 uint32_t tmp, addr = (GPR32 (OP[1])) + OP[0];
fee8ec00
SR		 3331 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3332 tmp = RLW (addr);
3333 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3334 SET_GPR32 (OP[2], tmp);
267b3b8e 3335 trace_output_32 (sd, tmp);
fee8ec00
SR		 3336}
3337
3338
3339/* loadd. */
3340void
267b3b8e 3341OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3342{
3343 /* loadd [Rindex]disp0(RPbasex) REGP
3344 * ADDR = Rpbasex + Rindex
3345 * REGP = [ADDR] */
3346
32267d59 3347 uint32_t addr, tmp;
fee8ec00
SR		 3348 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3349
3350 if (OP[0] == 0)
3351 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3352 else
3353 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3354
3355 tmp = RLW (addr);
3356 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3357 SET_GPR32 (OP[3], tmp);
267b3b8e 3358 trace_output_32 (sd, tmp);
fee8ec00
SR		 3359}
3360
3361
3362/* loadd. */
3363void
267b3b8e 3364OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3365{
3366 /* loadd [Rindex]disp14(RPbasex) REGP
3367 * ADDR = Rpbasex + Rindex + zext24(disp14)
3368 * REGR = [ADDR] */
3369
32267d59 3370 uint32_t addr, tmp;
fee8ec00
SR		 3371 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3372
3373 if (OP[0] == 0)
3374 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3375 else
3376 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3377
3378 tmp = RLW (addr);
3379 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3380 SET_GPR (OP[3],tmp);
267b3b8e 3381 trace_output_32 (sd, tmp);
fee8ec00
SR		 3382}
3383
3384
3385/* loadd. */
3386void
267b3b8e 3387OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3388{
3389 /* loadd dispe20(REG) REG
3390 * zext24(Rbase) + zext24(dispe20)
3391 * REG = [ADDR] */
3392
32267d59 3393 uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
fee8ec00
SR		 3394 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3395 tmp = RLW (addr);
3396 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3397 SET_GPR32 (OP[2], tmp);
267b3b8e 3398 trace_output_32 (sd, tmp);
fee8ec00
SR		 3399}
3400
3401
3402/* loadd. */
3403void
267b3b8e 3404OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3405{
3406 /* loadd DISP20(REG) REG
3407 * ADDR = zext24(Rbase) + zext24(disp20)
3408 * REG = [ADDR] */
3409
32267d59 3410 uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
fee8ec00
SR		 3411 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3412 tmp = RLW (addr);
3413 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3414 SET_GPR32 (OP[2], tmp);
267b3b8e 3415 trace_output_32 (sd, tmp);
fee8ec00
SR		 3416}
3417
3418/* loadd. */
3419void
267b3b8e 3420OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3421{
3422 /* loadd disp16(REGP) REGP
3423 * ADDR = RPbase + zext24(disp16)
3424 * REGR = [ADDR] */
32267d59 3425 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
fee8ec00
SR		 3426 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3427 tmp = RLW (addr);
3428 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3429 SET_GPR32 (OP[2], tmp);
267b3b8e 3430 trace_output_32 (sd, tmp);
fee8ec00
SR		 3431}
3432
3433
3434/* loadd. */
3435void
267b3b8e 3436OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3437{
3438 /* loadd disp20(REGP) REGP
3439 * ADDR = RPbase + zext24(disp20)
3440 * REGP = [ADDR] */
32267d59 3441 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
fee8ec00
SR		 3442 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3443 tmp = RLW (addr);
3444 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3445 SET_GPR32 (OP[2], tmp);
267b3b8e 3446 trace_output_32 (sd, tmp);
fee8ec00
SR		 3447}
3448
3449/* loadd. */
3450void
267b3b8e 3451OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3452{
3453 /* loadd -disp20(REGP) REGP
3454 * ADDR = RPbase + zext24(-disp20)
3455 * REGP = [ADDR] */
3456
32267d59 3457 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
fee8ec00
SR		 3458 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3459 tmp = RLW (addr);
3460 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3461 SET_GPR32 (OP[2], tmp);
267b3b8e 3462 trace_output_32 (sd, tmp);
fee8ec00
SR		 3463}
3464
3465/* loadd. */
3466void
267b3b8e 3467OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3468{
3469 /* loadd [Rindex]disp20(RPbasexb) REGP
3470 * ADDR = RPbasex + Rindex + zext24(disp20)
3471 * REGP = [ADDR] */
3472
32267d59 3473 uint32_t addr, tmp;
fee8ec00
SR		 3474 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3475
3476 if (OP[0] == 0)
3477 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3478 else
3479 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3480
3481 tmp = RLW (addr);
3482 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3483 SET_GPR32 (OP[3], tmp);
267b3b8e 3484 trace_output_32 (sd, tmp);
fee8ec00
SR		 3485}
3486
3487
3488/* storb. */
3489void
267b3b8e 3490OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3491{
3492 /* storb REG, ABS20
3493 * ADDR = zext24(abs20) | remap
3494 * [ADDR] = REGR
3495 * NOTE: remap is
3496 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3497 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3498 * by the core to 16M-64k to 16M. */
3499
32267d59
MF		 3500 uint8_t a = ((GPR (OP[0])) & 0xff);
3501 uint32_t addr = OP[1];
fee8ec00
SR		 3502 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3503 SB (addr, a);
267b3b8e 3504 trace_output_32 (sd, addr);
fee8ec00
SR		 3505}
3506
3507/* storb. */
3508void
267b3b8e 3509OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3510{
3511 /* storb REG, ABS24
3512 * ADDR = abs24
3513 * [ADDR] = REGR. */
3514
32267d59
MF		 3515 uint8_t a = ((GPR (OP[0])) & 0xff);
3516 uint32_t addr = OP[1];
fee8ec00
SR		 3517 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3518 SB (addr, a);
267b3b8e 3519 trace_output_32 (sd, addr);
fee8ec00
SR		 3520}
3521
3522/* storb. */
3523void
267b3b8e 3524OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3525{
3526 /* storb REG, [Rindex]ABS20
3527 * ADDR = Rindex + zext24(disp20)
3528 * [ADDR] = REGR */
3529
32267d59
MF		 3530 uint32_t addr;
3531 uint8_t a = ((GPR (OP[0])) & 0xff);
fee8ec00
SR		 3532 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3533
3534 if (OP[1] == 0)
3535 addr = (GPR32 (12)) + OP[2];
3536 else
3537 addr = (GPR32 (13)) + OP[2];
3538
3539 SB (addr, a);
267b3b8e 3540 trace_output_32 (sd, addr);
fee8ec00
SR		 3541}
3542
3543/* storb. */
3544void
267b3b8e 3545OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3546{
3547 /* storb REG, DIPS4(REGP)
3548 * ADDR = RPBASE + zext24(DISP4)
3549 * [ADDR] = REG. */
3550
32267d59
MF		 3551 uint16_t a = ((GPR (OP[0])) & 0xff);
3552 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3553 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 3554 SB (addr, a);
267b3b8e 3555 trace_output_32 (sd, addr);
fee8ec00
SR		 3556}
3557
3558/* storb. */
3559void
267b3b8e 3560OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3561{
3562 /* storb [Rindex]disp0(RPbasex) REG
3563 * ADDR = Rpbasex + Rindex
3564 * [ADDR] = REGR */
3565
32267d59
MF		 3566 uint32_t addr;
3567 uint8_t a = ((GPR (OP[0])) & 0xff);
fee8ec00
SR		 3568 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3569
3570 if (OP[1] == 0)
3571 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3572 else
3573 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3574
3575 SB (addr, a);
267b3b8e 3576 trace_output_32 (sd, addr);
fee8ec00
SR		 3577}
3578
3579/* storb. */
3580void
267b3b8e 3581OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3582{
3583 /* storb REG, [Rindex]disp14(RPbasex)
3584 * ADDR = Rpbasex + Rindex + zext24(disp14)
3585 * [ADDR] = REGR */
3586
32267d59
MF		 3587 uint8_t a = ((GPR (OP[0])) & 0xff);
3588 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3589 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 3590 SB (addr, a);
267b3b8e 3591 trace_output_32 (sd, addr);
fee8ec00
SR		 3592}
3593
3594/* storb. */
3595void
267b3b8e 3596OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3597{
3598 /* storb REG, DISPE20(REG)
3599 * zext24(Rbase) + zext24(dispe20)
3600 * [ADDR] = REG */
3601
32267d59
MF		 3602 uint8_t a = ((GPR (OP[0])) & 0xff);
3603 uint32_t addr = OP[1] + (GPR (OP[2]));
5aedb83b 3604 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
fee8ec00 3605 SB (addr, a);
267b3b8e 3606 trace_output_32 (sd, addr);
fee8ec00
SR		 3607}
3608
3609/* storb. */
3610void
267b3b8e 3611OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3612{
3613 /* storb REG, DISP20(REG)
3614 * ADDR = zext24(Rbase) + zext24(disp20)
3615 * [ADDR] = REG */
3616
32267d59
MF		 3617 uint8_t a = (GPR (OP[0]) & 0xff);
3618 uint32_t addr = OP[1] + (GPR (OP[2]));
fee8ec00 3619 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3620 SB (addr, a);
267b3b8e 3621 trace_output_32 (sd, addr);
fee8ec00
SR		 3622}
3623
3624/* storb. */
3625void
267b3b8e 3626OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3627{
3628 /* storb REG, disp16(REGP)
3629 * ADDR = RPbase + zext24(disp16)
3630 * [ADDR] = REGP */
3631
32267d59
MF		 3632 uint8_t a = ((GPR (OP[0])) & 0xff);
3633 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3634 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3635 SB (addr, a);
267b3b8e 3636 trace_output_32 (sd, addr);
fee8ec00
SR		 3637}
3638
3639/* storb. */
3640void
267b3b8e 3641OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3642{
3643 /* storb REG, disp20(REGP)
3644 * ADDR = RPbase + zext24(disp20)
3645 * [ADDR] = REGP */
3646
32267d59
MF		 3647 uint8_t a = ((GPR (OP[0])) & 0xff);
3648 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3649 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3650 SB (addr, a);
267b3b8e 3651 trace_output_32 (sd, addr);
fee8ec00
SR		 3652}
3653
3654/* storb. */
3655void
267b3b8e 3656OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3657{
3658 /* storb REG, -disp20(REGP)
3659 * ADDR = RPbase + zext24(-disp20)
3660 * [ADDR] = REGP */
3661
32267d59
MF		 3662 uint8_t a = (GPR (OP[0]) & 0xff);
3663 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3664 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3665 SB (addr, a);
267b3b8e 3666 trace_output_32 (sd, addr);
fee8ec00
SR		 3667}
3668
3669/* storb. */
3670void
267b3b8e 3671OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3672{
3673 /* storb REG, [Rindex]disp20(RPbase)
3674 * ADDR = RPbasex + Rindex + zext24(disp20)
3675 * [ADDR] = REGP */
3676
32267d59
MF		 3677 uint8_t a = (GPR (OP[0])) & 0xff;
3678 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3679 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3680 SB (addr, a);
267b3b8e 3681 trace_output_32 (sd, addr);
fee8ec00
SR		 3682}
3683
3684/* STR_IMM instructions. */
3685/* storb . */
3686void
267b3b8e 3687OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3688{
32267d59
MF		 3689 uint8_t a = (OP[0]) & 0xff;
3690 uint32_t addr = OP[1];
5aedb83b 3691 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3692 SB (addr, a);
267b3b8e 3693 trace_output_32 (sd, addr);
fee8ec00
SR		 3694}
3695
3696/* storb. */
3697void
267b3b8e 3698OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3699{
32267d59
MF		 3700 uint8_t a = (OP[0]) & 0xff;
3701 uint32_t addr = OP[1];
5aedb83b 3702 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3703 SB (addr, a);
267b3b8e 3704 trace_output_32 (sd, addr);
fee8ec00
SR		 3705}
3706
3707/* storb. */
3708void
267b3b8e 3709OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3710{
32267d59
MF		 3711 uint32_t addr;
3712 uint8_t a = (OP[0]) & 0xff;
fee8ec00
SR		 3713 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3714
3715 if (OP[1] == 0)
3716 addr = (GPR32 (12)) + OP[2];
3717 else
3718 addr = (GPR32 (13)) + OP[2];
3719
3720 SB (addr, a);
267b3b8e 3721 trace_output_32 (sd, addr);
fee8ec00
SR		 3722}
3723
3724/* storb. */
3725void
267b3b8e 3726OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3727{
32267d59
MF		 3728 uint8_t a = (OP[0]) & 0xff;
3729 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3730 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
fee8ec00 3731 SB (addr, a);
267b3b8e 3732 trace_output_32 (sd, addr);
fee8ec00
SR		 3733}
3734
3735/* storb. */
3736void
267b3b8e 3737OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3738{
32267d59
MF		 3739 uint8_t a = (OP[0]) & 0xff;
3740 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3741 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3742 SB (addr, a);
267b3b8e 3743 trace_output_32 (sd, addr);
fee8ec00
SR		 3744}
3745
3746/* storb. */
3747void
267b3b8e 3748OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3749{
32267d59
MF		 3750 uint8_t a = (OP[0]) & 0xff;
3751 uint32_t addr = (GPR (OP[2])) + OP[1];
5aedb83b 3752 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3753 SB (addr, a);
267b3b8e 3754 trace_output_32 (sd, addr);
fee8ec00
SR		 3755}
3756
3757/* storb. */
3758void
267b3b8e 3759OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3760{
32267d59
MF		 3761 uint8_t a = (OP[0]) & 0xff;
3762 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3763 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3764 SB (addr, a);
267b3b8e 3765 trace_output_32 (sd, addr);
fee8ec00
SR		 3766}
3767
3768/* storb. */
3769void
267b3b8e 3770OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3771{
32267d59
MF		 3772 uint8_t a = (OP[0]) & 0xff;
3773 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3774 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3775 SB (addr, a);
267b3b8e 3776 trace_output_32 (sd, addr);
fee8ec00
SR		 3777}
3778
3779/* storb. */
3780void
267b3b8e 3781OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3782{
32267d59
MF		 3783 uint8_t a = (OP[0]) & 0xff;
3784 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3785 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3786 SB (addr, a);
267b3b8e 3787 trace_output_32 (sd, addr);
fee8ec00
SR		 3788}
3789/* endif for STR_IMM. */
3790
3791/* storw . */
3792void
267b3b8e 3793OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3794{
32267d59
MF		 3795 uint16_t a = GPR (OP[0]);
3796 uint32_t addr = OP[1];
5aedb83b 3797 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3798 SW (addr, a);
267b3b8e 3799 trace_output_32 (sd, addr);
fee8ec00
SR		 3800}
3801
3802/* storw. */
3803void
267b3b8e 3804OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3805{
32267d59
MF		 3806 uint16_t a = GPR (OP[0]);
3807 uint32_t addr = OP[1];
5aedb83b 3808 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3809 SW (addr, a);
267b3b8e 3810 trace_output_32 (sd, addr);
fee8ec00
SR		 3811}
3812
3813/* storw. */
3814void
267b3b8e 3815OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3816{
32267d59
MF		 3817 uint32_t addr;
3818 uint16_t a = GPR (OP[0]);
fee8ec00
SR		 3819 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3820
3821 if (OP[1] == 0)
3822 addr = (GPR32 (12)) + OP[2];
3823 else
3824 addr = (GPR32 (13)) + OP[2];
3825
3826 SW (addr, a);
267b3b8e 3827 trace_output_32 (sd, addr);
fee8ec00
SR		 3828}
3829
3830
3831/* storw. */
3832void
267b3b8e 3833OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3834{
32267d59
MF		 3835 uint16_t a = (GPR (OP[0]));
3836 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3837 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 3838 SW (addr, a);
267b3b8e 3839 trace_output_32 (sd, addr);
fee8ec00
SR		 3840}
3841
3842/* storw. */
3843void
267b3b8e 3844OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3845{
32267d59
MF		 3846 uint16_t a = GPR (OP[0]);
3847 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3848 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3849 SW (addr, a);
267b3b8e 3850 trace_output_32 (sd, addr);
fee8ec00
SR		 3851}
3852
3853/* storw. */
3854void
267b3b8e 3855OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3856{
32267d59
MF		 3857 uint16_t a = GPR (OP[0]);
3858 uint32_t addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3859 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 3860 SW (addr, a);
267b3b8e 3861 trace_output_32 (sd, addr);
fee8ec00
SR		 3862}
3863
3864/* storw. */
3865void
267b3b8e 3866OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3867{
32267d59
MF		 3868 uint16_t a = (GPR (OP[0]));
3869 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3870 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3871 SW (addr, a);
267b3b8e 3872 trace_output_32 (sd, addr);
fee8ec00
SR		 3873}
3874
3875/* storw. */
3876void
267b3b8e 3877OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3878{
32267d59
MF		 3879 uint16_t a = (GPR (OP[0]));
3880 uint32_t addr = (GPR (OP[2])) + OP[1];
fee8ec00 3881 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3882 SW (addr, a);
267b3b8e 3883 trace_output_32 (sd, addr);
fee8ec00
SR		 3884}
3885
3886/* storw. */
3887void
267b3b8e 3888OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3889{
32267d59
MF		 3890 uint16_t a = (GPR (OP[0]));
3891 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3892 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3893 SW (addr, a);
267b3b8e 3894 trace_output_32 (sd, addr);
fee8ec00
SR		 3895}
3896
3897/* storw. */
3898void
267b3b8e 3899OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3900{
32267d59
MF		 3901 uint16_t a = (GPR (OP[0]));
3902 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3903 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3904 SW (addr, a);
267b3b8e 3905 trace_output_32 (sd, addr);
fee8ec00
SR		 3906}
3907
3908/* storw. */
3909void
267b3b8e 3910OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3911{
32267d59
MF		 3912 uint16_t a = (GPR (OP[0]));
3913 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3914 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3915 SW (addr, a);
267b3b8e 3916 trace_output_32 (sd, addr);
fee8ec00
SR		 3917}
3918
3919/* storw. */
3920void
267b3b8e 3921OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3922{
32267d59
MF		 3923 uint16_t a = (GPR (OP[0]));
3924 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3925 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3926 SW (addr, a);
267b3b8e 3927 trace_output_32 (sd, addr);
fee8ec00
SR		 3928}
3929
3930/* STORE-w IMM instruction *****/
3931/* storw . */
3932void
267b3b8e 3933OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3934{
32267d59
MF		 3935 uint16_t a = OP[0];
3936 uint32_t addr = OP[1];
fee8ec00 3937 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3938 SW (addr, a);
267b3b8e 3939 trace_output_32 (sd, addr);
fee8ec00
SR		 3940}
3941
3942/* storw. */
3943void
267b3b8e 3944OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3945{
32267d59
MF		 3946 uint16_t a = OP[0];
3947 uint32_t addr = OP[1];
fee8ec00 3948 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3949 SW (addr, a);
267b3b8e 3950 trace_output_32 (sd, addr);
fee8ec00
SR		 3951}
3952
3953/* storw. */
3954void
267b3b8e 3955OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3956{
32267d59
MF		 3957 uint32_t addr;
3958 uint16_t a = OP[0];
fee8ec00
SR		 3959 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3960
3961 if (OP[1] == 0)
3962 addr = (GPR32 (12)) + OP[2];
3963 else
3964 addr = (GPR32 (13)) + OP[2];
3965
3966 SW (addr, a);
267b3b8e 3967 trace_output_32 (sd, addr);
fee8ec00
SR		 3968}
3969
3970/* storw. */
3971void
267b3b8e 3972OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3973{
32267d59
MF		 3974 uint16_t a = OP[0];
3975 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3976 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
fee8ec00 3977 SW (addr, a);
267b3b8e 3978 trace_output_32 (sd, addr);
fee8ec00
SR		 3979}
3980
3981/* storw. */
3982void
267b3b8e 3983OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3984{
32267d59
MF		 3985 uint16_t a = OP[0];
3986 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3987 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3988 SW (addr, a);
267b3b8e 3989 trace_output_32 (sd, addr);
fee8ec00
SR		 3990}
3991
3992/* storw. */
3993void
267b3b8e 3994OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 3995{
32267d59
MF		 3996 uint16_t a = OP[0];
3997 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3998 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3999 SW (addr, a);
267b3b8e 4000 trace_output_32 (sd, addr);
fee8ec00
SR		 4001}
4002
4003/* storw. */
4004void
267b3b8e 4005OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4006{
32267d59
MF		 4007 uint16_t a = OP[0];
4008 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4009 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 4010 SW (addr, a);
267b3b8e 4011 trace_output_32 (sd, addr);
fee8ec00
SR		 4012}
4013
4014
4015/* storw. */
4016void
267b3b8e 4017OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4018{
32267d59
MF		 4019 uint16_t a = OP[0];
4020 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4021 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 4022 SW (addr, a);
267b3b8e 4023 trace_output_32 (sd, addr);
fee8ec00
SR		 4024}
4025
4026/* storw. */
4027void
267b3b8e 4028OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4029{
32267d59
MF		 4030 uint16_t a = OP[0];
4031 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4032 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 4033 SW (addr, a);
267b3b8e 4034 trace_output_32 (sd, addr);
fee8ec00
SR		 4035}
4036
4037
4038/* stord. */
4039void
267b3b8e 4040OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4041{
32267d59
MF		 4042 uint32_t a = GPR32 (OP[0]);
4043 uint32_t addr = OP[1];
fee8ec00 4044 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 4045 SLW (addr, a);
267b3b8e 4046 trace_output_32 (sd, addr);
fee8ec00
SR		 4047}
4048
4049/* stord. */
4050void
267b3b8e 4051OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4052{
32267d59
MF		 4053 uint32_t a = GPR32 (OP[0]);
4054 uint32_t addr = OP[1];
fee8ec00 4055 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 4056 SLW (addr, a);
267b3b8e 4057 trace_output_32 (sd, addr);
fee8ec00
SR		 4058}
4059
4060/* stord. */
4061void
267b3b8e 4062OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4063{
32267d59 4064 uint32_t addr, a = GPR32 (OP[0]);
fee8ec00
SR		 4065 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4066
4067 if (OP[1] == 0)
4068 addr = (GPR32 (12)) + OP[2];
4069 else
4070 addr = (GPR32 (13)) + OP[2];
4071
4072 SLW (addr, a);
267b3b8e 4073 trace_output_32 (sd, addr);
fee8ec00
SR		 4074}
4075
4076/* stord. */
4077void
267b3b8e 4078OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4079{
32267d59
MF		 4080 uint32_t a = GPR32 (OP[0]);
4081 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4082 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 4083 SLW (addr, a);
267b3b8e 4084 trace_output_32 (sd, addr);
fee8ec00
SR		 4085}
4086
4087/* stord. */
4088void
267b3b8e 4089OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4090{
32267d59
MF		 4091 uint32_t a = GPR32 (OP[0]);
4092 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4093 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 4094 SLW (addr, a);
267b3b8e 4095 trace_output_32 (sd, addr);
fee8ec00
SR		 4096}
4097
4098/* stord. */
4099void
267b3b8e 4100OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4101{
32267d59
MF		 4102 uint32_t a = GPR32 (OP[0]);
4103 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4104 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 4105 SLW (addr, a);
267b3b8e 4106 trace_output_32 (sd, addr);
fee8ec00
SR		 4107}
4108
4109/* stord. */
4110void
267b3b8e 4111OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4112{
32267d59
MF		 4113 uint32_t a = GPR32 (OP[0]);
4114 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4115 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
fee8ec00 4116 SLW (addr, a);
267b3b8e 4117 trace_output_32 (sd, addr);
fee8ec00
SR		 4118}
4119
4120/* stord. */
4121void
267b3b8e 4122OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4123{
32267d59
MF		 4124 uint32_t a = GPR32 (OP[0]);
4125 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4126 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 4127 SLW (addr, a);
267b3b8e 4128 trace_output_32 (sd, addr);
fee8ec00
SR		 4129}
4130
4131/* stord. */
4132void
267b3b8e 4133OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4134{
32267d59
MF		 4135 uint32_t a = GPR32 (OP[0]);
4136 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4137 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 4138 SLW (addr, a);
267b3b8e 4139 trace_output_32 (sd, addr);
fee8ec00
SR		 4140}
4141
4142/* stord. */
4143void
267b3b8e 4144OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4145{
32267d59
MF		 4146 uint32_t a = GPR32 (OP[0]);
4147 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4148 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 4149 SLW (addr, a);
267b3b8e 4150 trace_output_32 (sd, addr);
fee8ec00
SR		 4151}
4152
4153/* stord. */
4154void
267b3b8e 4155OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4156{
32267d59
MF		 4157 uint32_t a = GPR32 (OP[0]);
4158 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4159 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 4160 SLW (addr, a);
267b3b8e 4161 trace_output_32 (sd, addr);
fee8ec00
SR		 4162}
4163
4164/* stord. */
4165void
267b3b8e 4166OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4167{
32267d59
MF		 4168 uint32_t a = GPR32 (OP[0]);
4169 uint32_t addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4170 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 4171 SLW (addr, a);
267b3b8e 4172 trace_output_32 (sd, addr);
fee8ec00
SR		 4173}
4174
4175/* macqu. */
4176void
267b3b8e 4177OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4178{
32267d59
MF		 4179 int32_t tmp;
4180 int16_t src1, src2;
fee8ec00
SR		 4181 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4182 src1 = GPR (OP[0]);
4183 src2 = GPR (OP[1]);
4184 tmp = src1 * src2;
4185 /*REVISIT FOR SATURATION and Q FORMAT. */
4186 SET_GPR32 (OP[2], tmp);
267b3b8e 4187 trace_output_32 (sd, tmp);
fee8ec00
SR		 4188}
4189
4190/* macuw. */
4191void
267b3b8e 4192OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4193{
32267d59
MF		 4194 uint32_t tmp;
4195 uint16_t src1, src2;
fee8ec00
SR		 4196 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4197 src1 = GPR (OP[0]);
4198 src2 = GPR (OP[1]);
4199 tmp = src1 * src2;
4200 /*REVISIT FOR SATURATION. */
4201 SET_GPR32 (OP[2], tmp);
267b3b8e 4202 trace_output_32 (sd, tmp);
fee8ec00
SR		 4203}
4204
4205/* macsw. */
4206void
267b3b8e 4207OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4208{
32267d59
MF		 4209 int32_t tmp;
4210 int16_t src1, src2;
fee8ec00
SR		 4211 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4212 src1 = GPR (OP[0]);
4213 src2 = GPR (OP[1]);
4214 tmp = src1 * src2;
4215 /*REVISIT FOR SATURATION. */
4216 SET_GPR32 (OP[2], tmp);
267b3b8e 4217 trace_output_32 (sd, tmp);
fee8ec00
SR		 4218}
4219
4220
4221/* mulb. */
4222void
267b3b8e 4223OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4224{
32267d59
MF		 4225 int16_t tmp;
4226 int8_t a = (OP[0]) & 0xff;
4227 int8_t b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 4228 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4229 tmp = (a * b) & 0xff;
4230 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4231 trace_output_16 (sd, tmp);
fee8ec00
SR		 4232}
4233
4234/* mulb. */
4235void
267b3b8e 4236OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4237{
32267d59
MF		 4238 int16_t tmp;
4239 int8_t a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 4240 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4241 tmp = (a * b) & 0xff;
4242 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4243 trace_output_16 (sd, tmp);
fee8ec00
SR		 4244}
4245
4246
4247/* mulb. */
4248void
267b3b8e 4249OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4250{
32267d59
MF		 4251 int16_t tmp;
4252 int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 4253 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4254 tmp = (a * b) & 0xff;
4255 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4256 trace_output_16 (sd, tmp);
fee8ec00
SR		 4257}
4258
4259
4260/* mulw. */
4261void
267b3b8e 4262OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4263{
32267d59
MF		 4264 int32_t tmp;
4265 uint16_t a = OP[0];
4266 int16_t b = (GPR (OP[1]));
fee8ec00
SR		 4267 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4268 tmp = (a * b) & 0xffff;
4269 SET_GPR (OP[1], tmp);
267b3b8e 4270 trace_output_32 (sd, tmp);
fee8ec00
SR		 4271}
4272
4273/* mulw. */
4274void
267b3b8e 4275OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4276{
32267d59
MF		 4277 int32_t tmp;
4278 int16_t a = OP[0], b = (GPR (OP[1]));
fee8ec00
SR		 4279 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4280 tmp = (a * b) & 0xffff;
4281 SET_GPR (OP[1], tmp);
267b3b8e 4282 trace_output_32 (sd, tmp);
fee8ec00
SR		 4283}
4284
4285
4286/* mulw. */
4287void
267b3b8e 4288OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4289{
32267d59
MF		 4290 int32_t tmp;
4291 int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 4292 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4293 tmp = (a * b) & 0xffff;
4294 SET_GPR (OP[1], tmp);
267b3b8e 4295 trace_output_32 (sd, tmp);
fee8ec00
SR		 4296}
4297
4298
4299/* mulsb. */
4300void
267b3b8e 4301OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4302{
32267d59
MF		 4303 int16_t tmp;
4304 int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 4305 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4306 tmp = a * b;
4307 SET_GPR (OP[1], tmp);
267b3b8e 4308 trace_output_32 (sd, tmp);
fee8ec00
SR		 4309}
4310
4311/* mulsw. */
4312void
267b3b8e 4313OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4314{
32267d59
MF		 4315 int32_t tmp;
4316 int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 4317 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4318 tmp = a * b;
4319 SET_GPR32 (OP[1], tmp);
267b3b8e 4320 trace_output_32 (sd, tmp);
fee8ec00
SR		 4321}
4322
4323/* muluw. */
4324void
267b3b8e 4325OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4326{
32267d59
MF		 4327 uint32_t tmp;
4328 uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 4329 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4330 tmp = a * b;
4331 SET_GPR32 (OP[1], tmp);
267b3b8e 4332 trace_output_32 (sd, tmp);
fee8ec00
SR		 4333}
4334
4335
4336/* nop. */
4337void
267b3b8e 4338OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4339{
4340 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4341
4342#if 0
fee8ec00
SR		 4343 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4344 switch (State.ins_type)
4345 {
4346 default:
4347 ins_type_counters[ (int)INS_UNKNOWN ]++;
4348 break;
4349
4350 }
0ef7f981 4351 EXCEPTION (SIM_SIGTRAP);
fee8ec00 4352#endif
267b3b8e 4353 trace_output_void (sd);
fee8ec00
SR		 4354}
4355
4356
4357/* orb. */
4358void
267b3b8e 4359OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4360{
32267d59 4361 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 4362 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4363 tmp = a | b;
4364 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4365 trace_output_16 (sd, tmp);
fee8ec00
SR		 4366}
4367
4368/* orb. */
4369void
267b3b8e 4370OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4371{
32267d59 4372 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 4373 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4374 tmp = a | b;
4375 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4376 trace_output_16 (sd, tmp);
fee8ec00
SR		 4377}
4378
4379/* orb. */
4380void
267b3b8e 4381OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4382{
32267d59 4383 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 4384 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4385 tmp = a | b;
4386 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4387 trace_output_16 (sd, tmp);
fee8ec00
SR		 4388}
4389
4390/* orw. */
4391void
267b3b8e 4392OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4393{
32267d59 4394 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
fee8ec00
SR		 4395 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4396 tmp = a | b;
4397 SET_GPR (OP[1], tmp);
267b3b8e 4398 trace_output_16 (sd, tmp);
fee8ec00
SR		 4399}
4400
4401
4402/* orw. */
4403void
267b3b8e 4404OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4405{
32267d59 4406 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
fee8ec00
SR		 4407 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4408 tmp = a | b;
4409 SET_GPR (OP[1], tmp);
267b3b8e 4410 trace_output_16 (sd, tmp);
fee8ec00
SR		 4411}
4412
4413/* orw. */
4414void
267b3b8e 4415OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4416{
32267d59 4417 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 4418 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4419 tmp = a | b;
4420 SET_GPR (OP[1], tmp);
267b3b8e 4421 trace_output_16 (sd, tmp);
fee8ec00
SR		 4422}
4423
4424
4425/* lshb. */
4426void
267b3b8e 4427OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4428{
32267d59
MF		 4429 uint16_t a = OP[0];
4430 uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
fee8ec00
SR		 4431 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4432 /* A positive count specifies a shift to the left;
4433 * A negative count specifies a shift to the right. */
4434 if (sign_flag)
4435 tmp = b >> a;
4436 else
4437 tmp = b << a;
4438
4439 sign_flag = 0; /* Reset sign_flag. */
4440
4441 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4442 trace_output_16 (sd, tmp);
fee8ec00
SR		 4443}
4444
4445/* lshb. */
4446void
267b3b8e 4447OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4448{
32267d59
MF		 4449 uint16_t a = (GPR (OP[0])) & 0xff;
4450 uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
fee8ec00
SR		 4451 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4452 if (a & ((long)1 << 3))
4453 {
4454 sign_flag = 1;
4455 a = ~(a) + 1;
4456 }
4457 a = (unsigned int) (a & 0x7);
4458
4459 /* A positive count specifies a shift to the left;
4460 * A negative count specifies a shift to the right. */
4461 if (sign_flag)
4462 tmp = b >> a;
4463 else
4464 tmp = b << a;
4465
4466 sign_flag = 0; /* Reset sign_flag. */
4467 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4468 trace_output_16 (sd, tmp);
fee8ec00
SR		 4469}
4470
4471/* lshw. */
4472void
267b3b8e 4473OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4474{
32267d59
MF		 4475 uint16_t tmp, b = GPR (OP[1]);
4476 int16_t a = GPR (OP[0]);
fee8ec00
SR		 4477 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4478 if (a & ((long)1 << 4))
4479 {
4480 sign_flag = 1;
4481 a = ~(a) + 1;
4482 }
4483 a = (unsigned int) (a & 0xf);
4484
4485 /* A positive count specifies a shift to the left;
4486 * A negative count specifies a shift to the right. */
4487 if (sign_flag)
4488 tmp = b >> a;
4489 else
4490 tmp = b << a;
4491
4492 sign_flag = 0; /* Reset sign_flag. */
4493 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4494 trace_output_16 (sd, tmp);
fee8ec00
SR		 4495}
4496
4497/* lshw. */
4498void
267b3b8e 4499OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4500{
32267d59
MF		 4501 uint16_t tmp, b = GPR (OP[1]);
4502 uint16_t a = OP[0];
fee8ec00
SR		 4503 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4504 /* A positive count specifies a shift to the left;
4505 * A negative count specifies a shift to the right. */
4506 if (sign_flag)
4507 tmp = b >> a;
4508 else
4509 tmp = b << a;
4510
4511 sign_flag = 0; /* Reset sign_flag. */
4512 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4513 trace_output_16 (sd, tmp);
fee8ec00
SR		 4514}
4515
4516/* lshd. */
4517void
267b3b8e 4518OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4519{
32267d59
MF		 4520 uint32_t tmp, b = GPR32 (OP[1]);
4521 uint16_t a = OP[0];
fee8ec00
SR		 4522 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4523 /* A positive count specifies a shift to the left;
4524 * A negative count specifies a shift to the right. */
4525 if (sign_flag)
4526 tmp = b >> a;
4527 else
4528 tmp = b << a;
4529
4530 sign_flag = 0; /* Reset sign flag. */
4531
4532 SET_GPR32 (OP[1], tmp);
267b3b8e 4533 trace_output_32 (sd, tmp);
fee8ec00
SR		 4534}
4535
4536/* lshd. */
4537void
267b3b8e 4538OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4539{
32267d59
MF		 4540 uint32_t tmp, b = GPR32 (OP[1]);
4541 uint16_t a = GPR (OP[0]);
fee8ec00
SR		 4542 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4543 if (a & ((long)1 << 5))
4544 {
4545 sign_flag = 1;
4546 a = ~(a) + 1;
4547 }
4548 a = (unsigned int) (a & 0x1f);
4549 /* A positive count specifies a shift to the left;
4550 * A negative count specifies a shift to the right. */
4551 if (sign_flag)
4552 tmp = b >> a;
4553 else
4554 tmp = b << a;
4555
4556 sign_flag = 0; /* Reset sign flag. */
4557
4558 SET_GPR32 (OP[1], tmp);
267b3b8e 4559 trace_output_32 (sd, tmp);
fee8ec00
SR		 4560}
4561
4562/* ashub. */
4563void
267b3b8e 4564OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4565{
32267d59
MF		 4566 uint16_t a = OP[0];
4567 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
fee8ec00
SR		 4568 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4569 /* A positive count specifies a shift to the left;
4570 * A negative count specifies a shift to the right. */
4571 if (sign_flag)
4572 tmp = b >> a;
4573 else
4574 tmp = b << a;
4575
4576 sign_flag = 0; /* Reset sign flag. */
4577
4578 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4579 trace_output_16 (sd, tmp);
fee8ec00
SR		 4580}
4581
4582/* ashub. */
4583void
267b3b8e 4584OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4585{
32267d59
MF		 4586 uint16_t a = OP[0];
4587 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
fee8ec00
SR		 4588 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4589 /* A positive count specifies a shift to the left;
4590 * A negative count specifies a shift to the right. */
4591 if (sign_flag)
4592 tmp = b >> a;
4593 else
4594 tmp = b << a;
4595
4596 sign_flag = 0; /* Reset sign flag. */
4597
4598 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4599 trace_output_16 (sd, tmp);
fee8ec00
SR		 4600}
4601
4602
4603/* ashub. */
4604void
267b3b8e 4605OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4606{
32267d59
MF		 4607 int16_t a = (GPR (OP[0]));
4608 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
fee8ec00
SR		 4609 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4610
4611 if (a & ((long)1 << 3))
4612 {
4613 sign_flag = 1;
4614 a = ~(a) + 1;
4615 }
4616 a = (unsigned int) (a & 0x7);
4617
4618 /* A positive count specifies a shift to the left;
4619 * A negative count specifies a shift to the right. */
4620 if (sign_flag)
4621 tmp = b >> a;
4622 else
4623 tmp = b << a;
4624
4625 sign_flag = 0; /* Reset sign flag. */
4626
4627 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4628 trace_output_16 (sd, tmp);
fee8ec00
SR		 4629}
4630
4631
4632/* ashuw. */
4633void
267b3b8e 4634OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4635{
32267d59
MF		 4636 int16_t tmp, b = GPR (OP[1]);
4637 uint16_t a = OP[0];
fee8ec00
SR		 4638 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4639 /* A positive count specifies a shift to the left;
4640 * A negative count specifies a shift to the right. */
4641 if (sign_flag)
4642 tmp = b >> a;
4643 else
4644 tmp = b << a;
4645
4646 sign_flag = 0; /* Reset sign flag. */
4647
4648 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4649 trace_output_16 (sd, tmp);
fee8ec00
SR		 4650}
4651
4652/* ashuw. */
4653void
267b3b8e 4654OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4655{
32267d59
MF		 4656 int16_t tmp, b = GPR (OP[1]);
4657 uint16_t a = OP[0];
fee8ec00
SR		 4658 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4659 /* A positive count specifies a shift to the left;
4660 * A negative count specifies a shift to the right. */
4661 if (sign_flag)
4662 tmp = b >> a;
4663 else
4664 tmp = b << a;
4665
4666 sign_flag = 0; /* Reset sign flag. */
4667 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4668 trace_output_16 (sd, tmp);
fee8ec00
SR		 4669}
4670
4671/* ashuw. */
4672void
267b3b8e 4673OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4674{
32267d59
MF		 4675 int16_t tmp;
4676 int16_t a = GPR (OP[0]), b = GPR (OP[1]);
fee8ec00
SR		 4677 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4678
4679 if (a & ((long)1 << 4))
4680 {
4681 sign_flag = 1;
4682 a = ~(a) + 1;
4683 }
4684 a = (unsigned int) (a & 0xf);
4685 /* A positive count specifies a shift to the left;
4686 * A negative count specifies a shift to the right. */
4687
4688 if (sign_flag)
4689 tmp = b >> a;
4690 else
4691 tmp = b << a;
4692
4693 sign_flag = 0; /* Reset sign flag. */
4694 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4695 trace_output_16 (sd, tmp);
fee8ec00
SR		 4696}
4697
4698/* ashud. */
4699void
267b3b8e 4700OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4701{
32267d59
MF		 4702 int32_t tmp,b = GPR32 (OP[1]);
4703 uint32_t a = OP[0];
fee8ec00
SR		 4704 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4705 /* A positive count specifies a shift to the left;
4706 * A negative count specifies a shift to the right. */
4707 if (sign_flag)
4708 tmp = b >> a;
4709 else
4710 tmp = b << a;
4711
4712 sign_flag = 0; /* Reset sign flag. */
4713 SET_GPR32 (OP[1], tmp);
267b3b8e 4714 trace_output_32 (sd, tmp);
fee8ec00
SR		 4715}
4716
4717/* ashud. */
4718void
267b3b8e 4719OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4720{
32267d59
MF		 4721 int32_t tmp;
4722 int32_t a = OP[0], b = GPR32 (OP[1]);
fee8ec00
SR		 4723 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4724 /* A positive count specifies a shift to the left;
4725 * A negative count specifies a shift to the right. */
4726 if (sign_flag)
4727 tmp = b >> a;
4728 else
4729 tmp = b << a;
4730
4731 sign_flag = 0; /* Reset sign flag. */
4732 SET_GPR32 (OP[1], tmp);
267b3b8e 4733 trace_output_32 (sd, tmp);
fee8ec00
SR		 4734}
4735
4736/* ashud. */
4737void
267b3b8e 4738OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4739{
32267d59
MF		 4740 int32_t tmp;
4741 int32_t a = GPR32 (OP[0]), b = GPR32 (OP[1]);
fee8ec00
SR		 4742 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4743
4744 if (a & ((long)1 << 5))
4745 {
4746 sign_flag = 1;
4747 a = ~(a) + 1;
4748 }
4749 a = (unsigned int) (a & 0x1f);
4750 /* A positive count specifies a shift to the left;
4751 * A negative count specifies a shift to the right. */
4752 if (sign_flag)
4753 tmp = b >> a;
4754 else
4755 tmp = b << a;
4756
4757 sign_flag = 0; /* Reset sign flag. */
4758 SET_GPR32 (OP[1], tmp);
267b3b8e 4759 trace_output_32 (sd, tmp);
fee8ec00
SR		 4760}
4761
4762
4763/* storm. */
4764void
267b3b8e 4765OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4766{
32267d59
MF		 4767 uint32_t addr = GPR (1);
4768 uint16_t count = OP[0], reg = 2;
fee8ec00
SR		 4769 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4770 if ((addr & 1))
4771 {
267b3b8e 4772 trace_output_void (sd);
0ef7f981 4773 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 4774 }
4775
4776 while (count)
4777 {
4778 SW (addr, (GPR (reg)));
4779 addr +=2;
4780 --count;
4781 reg++;
4782 if (reg == 6) reg = 8;
4783 };
4784
4785 SET_GPR (1, addr);
4786
267b3b8e 4787 trace_output_void (sd);
fee8ec00
SR		 4788}
4789
4790
4791/* stormp. */
4792void
267b3b8e 4793OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4794{
32267d59
MF		 4795 uint32_t addr = GPR32 (6);
4796 uint16_t count = OP[0], reg = 2;
fee8ec00
SR		 4797 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4798 if ((addr & 1))
4799 {
267b3b8e 4800 trace_output_void (sd);
0ef7f981 4801 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 4802 }
4803
4804 while (count)
4805 {
4806 SW (addr, (GPR (reg)));
4807 addr +=2;
4808 --count;
4809 reg++;
4810 if (reg == 6) reg = 8;
4811 };
4812
4813 SET_GPR32 (6, addr);
267b3b8e 4814 trace_output_void (sd);
fee8ec00
SR		 4815}
4816
4817/* subb. */
4818void
267b3b8e 4819OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4820{
32267d59
MF		 4821 uint8_t a = OP[0];
4822 uint8_t b = (GPR (OP[1])) & 0xff;
4823 uint16_t tmp = (~a + 1 + b) & 0xff;
fee8ec00
SR		 4824 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4825 /* see ../common/sim-alu.h for a more extensive discussion on how to
4826 compute the carry/overflow bits. */
4827 SET_PSR_C (tmp > 0xff);
4828 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4829 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4830 trace_output_16 (sd, tmp);
fee8ec00
SR		 4831}
4832
4833/* subb. */
4834void
267b3b8e 4835OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4836{
32267d59
MF		 4837 uint8_t a = OP[0] & 0xFF;
4838 uint8_t b = (GPR (OP[1])) & 0xFF;
4839 uint16_t tmp = (~a + 1 + b) & 0xFF;
fee8ec00
SR		 4840 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4841 /* see ../common/sim-alu.h for a more extensive discussion on how to
4842 compute the carry/overflow bits. */
4843 SET_PSR_C (tmp > 0xff);
4844 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4845 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4846 trace_output_16 (sd, tmp);
fee8ec00
SR		 4847}
4848
4849/* subb. */
4850void
267b3b8e 4851OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4852{
32267d59
MF		 4853 uint8_t a = (GPR (OP[0])) & 0xFF;
4854 uint8_t b = (GPR (OP[1])) & 0xFF;
4855 uint16_t tmp = (~a + 1 + b) & 0xff;
fee8ec00
SR		 4856 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4857 /* see ../common/sim-alu.h for a more extensive discussion on how to
4858 compute the carry/overflow bits. */
4859 SET_PSR_C (tmp > 0xff);
4860 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4861 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4862 trace_output_16 (sd, tmp);
fee8ec00
SR		 4863}
4864
4865/* subw. */
4866void
267b3b8e 4867OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4868{
32267d59
MF		 4869 uint16_t a = OP[0];
4870 uint16_t b = GPR (OP[1]);
4871 uint16_t tmp = (~a + 1 + b);
fee8ec00
SR		 4872 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4873 /* see ../common/sim-alu.h for a more extensive discussion on how to
4874 compute the carry/overflow bits. */
4875 SET_PSR_C (tmp > 0xffff);
4876 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4877 SET_GPR (OP[1], tmp);
267b3b8e 4878 trace_output_16 (sd, tmp);
fee8ec00
SR		 4879}
4880
4881/* subw. */
4882void
267b3b8e 4883OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4884{
32267d59
MF		 4885 uint16_t a = OP[0];
4886 uint16_t b = GPR (OP[1]);
4887 uint32_t tmp = (~a + 1 + b);
fee8ec00
SR		 4888 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4889 /* see ../common/sim-alu.h for a more extensive discussion on how to
4890 compute the carry/overflow bits. */
4891 SET_PSR_C (tmp > 0xffff);
4892 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4893 SET_GPR (OP[1], tmp & 0xffff);
267b3b8e 4894 trace_output_16 (sd, tmp);
fee8ec00
SR		 4895}
4896
4897/* subw. */
4898void
267b3b8e 4899OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4900{
32267d59
MF		 4901 uint16_t a = GPR (OP[0]);
4902 uint16_t b = GPR (OP[1]);
4903 uint32_t tmp = (~a + 1 + b);
fee8ec00
SR		 4904 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4905 /* see ../common/sim-alu.h for a more extensive discussion on how to
4906 compute the carry/overflow bits. */
4907 SET_PSR_C (tmp > 0xffff);
4908 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4909 SET_GPR (OP[1], tmp & 0xffff);
267b3b8e 4910 trace_output_16 (sd, tmp);
fee8ec00
SR		 4911}
4912
4913/* subcb. */
4914void
267b3b8e 4915OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4916{
32267d59
MF		 4917 uint8_t a = OP[0];
4918 uint8_t b = (GPR (OP[1])) & 0xff;
4919 //uint16_t tmp1 = a + 1;
4920 uint16_t tmp1 = a + (PSR_C);
4921 uint16_t tmp = (~tmp1 + 1 + b);
fee8ec00
SR		 4922 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4923 /* see ../common/sim-alu.h for a more extensive discussion on how to
4924 compute the carry/overflow bits. */
4925 SET_PSR_C (tmp > 0xff);
4926 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4927 SET_GPR (OP[1], tmp);
267b3b8e 4928 trace_output_16 (sd, tmp);
fee8ec00
SR		 4929}
4930
4931/* subcb. */
4932void
267b3b8e 4933OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4934{
32267d59
MF		 4935 uint16_t a = OP[0];
4936 uint16_t b = (GPR (OP[1])) & 0xff;
4937 //uint16_t tmp1 = a + 1;
4938 uint16_t tmp1 = a + (PSR_C);
4939 uint16_t tmp = (~tmp1 + 1 + b);
fee8ec00
SR		 4940 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4941 /* see ../common/sim-alu.h for a more extensive discussion on how to
4942 compute the carry/overflow bits. */
4943 SET_PSR_C (tmp > 0xff);
4944 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4945 SET_GPR (OP[1], tmp);
267b3b8e 4946 trace_output_16 (sd, tmp);
fee8ec00
SR		 4947}
4948
4949/* subcb. */
4950void
267b3b8e 4951OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4952{
32267d59
MF		 4953 uint16_t a = (GPR (OP[0])) & 0xff;
4954 uint16_t b = (GPR (OP[1])) & 0xff;
4955 uint16_t tmp1 = a + (PSR_C);
4956 uint16_t tmp = (~tmp1 + 1 + b);
fee8ec00
SR		 4957 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4958 /* see ../common/sim-alu.h for a more extensive discussion on how to
4959 compute the carry/overflow bits. */
4960 SET_PSR_C (tmp > 0xff);
4961 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4962 SET_GPR (OP[1], tmp);
267b3b8e 4963 trace_output_16 (sd, tmp);
fee8ec00
SR		 4964}
4965
4966/* subcw. */
4967void
267b3b8e 4968OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4969{
32267d59
MF		 4970 uint16_t a = OP[0], b = (GPR (OP[1]));
4971 uint16_t tmp1 = a + (PSR_C);
4972 uint16_t tmp = (~tmp1 + 1 + b);
fee8ec00
SR		 4973 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4974 /* see ../common/sim-alu.h for a more extensive discussion on how to
4975 compute the carry/overflow bits. */
4976 SET_PSR_C (tmp > 0xffff);
4977 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4978 SET_GPR (OP[1], tmp);
267b3b8e 4979 trace_output_16 (sd, tmp);
fee8ec00
SR		 4980}
4981
4982/* subcw. */
4983void
267b3b8e 4984OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4985{
32267d59
MF		 4986 int16_t a = OP[0];
4987 uint16_t b = GPR (OP[1]);
4988 uint16_t tmp1 = a + (PSR_C);
4989 uint16_t tmp = (~tmp1 + 1 + b);
fee8ec00
SR		 4990 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
4991 /* see ../common/sim-alu.h for a more extensive discussion on how to
4992 compute the carry/overflow bits. */
4993 SET_PSR_C (tmp > 0xffff);
4994 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4995 SET_GPR (OP[1], tmp);
267b3b8e 4996 trace_output_16 (sd, tmp);
fee8ec00
SR		 4997}
4998
4999/* subcw. */
5000void
267b3b8e 5001OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5002{
32267d59
MF		 5003 uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
5004 uint16_t tmp1 = a + (PSR_C);
5005 uint16_t tmp = (~tmp1 + 1 + b);
fee8ec00
SR		 5006 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5007 /* see ../common/sim-alu.h for a more extensive discussion on how to
5008 compute the carry/overflow bits. */
5009 SET_PSR_C (tmp > 0xffff);
5010 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5011 SET_GPR (OP[1], tmp);
267b3b8e 5012 trace_output_16 (sd, tmp);
fee8ec00
SR		 5013}
5014
5015/* subd. */
5016void
267b3b8e 5017OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5018{
32267d59
MF		 5019 int32_t a = OP[0];
5020 uint32_t b = GPR32 (OP[1]);
5021 uint32_t tmp = (~a + 1 + b);
fee8ec00
SR		 5022 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5023 /* see ../common/sim-alu.h for a more extensive discussion on how to
5024 compute the carry/overflow bits. */
5025 SET_PSR_C (tmp > 0xffffffff);
5026 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5027 ((b & 0x80000000) != (tmp & 0x80000000)));
5028 SET_GPR32 (OP[1], tmp);
267b3b8e 5029 trace_output_32 (sd, tmp);
fee8ec00
SR		 5030}
5031
5032/* subd. */
5033void
267b3b8e 5034OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5035{
32267d59
MF		 5036 uint32_t a = GPR32 (OP[0]);
5037 uint32_t b = GPR32 (OP[1]);
5038 uint32_t tmp = (~a + 1 + b);
fee8ec00
SR		 5039 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5040 /* see ../common/sim-alu.h for a more extensive discussion on how to
5041 compute the carry/overflow bits. */
5042 SET_PSR_C (tmp > 0xffffffff);
5043 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5044 ((b & 0x80000000) != (tmp & 0x80000000)));
5045 SET_GPR32 (OP[1], tmp);
267b3b8e 5046 trace_output_32 (sd, tmp);
fee8ec00
SR		 5047}
5048
5049/* excp. */
5050void
267b3b8e 5051OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5052{
9db36cf8 5053 host_callback *cb = STATE_CALLBACK (sd);
32267d59
MF		 5054 uint32_t tmp;
5055 uint16_t a;
fee8ec00
SR		 5056 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5057 switch (OP[0])
5058 {
5059 default:
5060#if (DEBUG & DEBUG_TRAP) == 0
5061 {
5062#if 0
32267d59 5063 uint16_t vec = OP[0] + TRAP_VECTOR_START;
fee8ec00
SR		 5064 SET_BPC (PC + 1);
5065 SET_BPSR (PSR);
5066 SET_PSR (PSR & PSR_SM_BIT);
5067 JMP (vec);
5068 break;
5069#endif
5070 }
5071#else /* if debugging use trap to print registers */
5072 {
5073 int i;
5074 static int first_time = 1;
5075
5076 if (first_time)
5077 {
5078 first_time = 0;
9db36cf8 5079 sim_io_printf (sd, "Trap # PC ");
fee8ec00 5080 for (i = 0; i < 16; i++)
9db36cf8
MF		 5081 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
5082 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
fee8ec00
SR		 5083 }
5084
9db36cf8 5085 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
fee8ec00
SR		 5086
5087 for (i = 0; i < 16; i++)
9db36cf8 5088 sim_io_printf (sd, " %.4x", (int) GPR (i));
fee8ec00
SR		 5089
5090 for (i = 0; i < 2; i++)
9db36cf8 5091 sim_io_printf (sd, " %.2x%.8lx",
fee8ec00
SR		 5092 ((int)(ACC (i) >> 32) & 0xff),
5093 ((unsigned long) ACC (i)) & 0xffffffff);
5094
9db36cf8 5095 sim_io_printf (sd, " %d %d %d\n",
fee8ec00 5096 PSR_F != 0, PSR_F != 0, PSR_C != 0);
9db36cf8 5097 sim_io_flush_stdout (sd);
fee8ec00
SR		 5098 break;
5099 }
5100#endif
5101 case 8: /* new system call trap */
5102 /* Trap 8 is used for simulating low-level I/O */
5103 {
32267d59 5104 uint32_t result = 0;
fee8ec00
SR		 5105 errno = 0;
5106
5107/* Registers passed to trap 0. */
5108
5109#define FUNC GPR (0) /* function number. */
5110#define PARM1 GPR (2) /* optional parm 1. */
5111#define PARM2 GPR (3) /* optional parm 2. */
5112#define PARM3 GPR (4) /* optional parm 3. */
5113#define PARM4 GPR (5) /* optional parm 4. */
5114
5115/* Registers set by trap 0 */
5116
5117#define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5118#define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5119#define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5120
5121/* Turn a pointer in a register into a pointer into real memory. */
5122
761e171a 5123#define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
fee8ec00
SR		 5124
5125 switch (FUNC)
5126 {
5127#if !defined(__GO32__) && !defined(_WIN32)
ab230d13 5128 case TARGET_NEWLIB_CR16_SYS_fork:
fee8ec00
SR		 5129 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5130 RETVAL (fork ());
267b3b8e 5131 trace_output_16 (sd, result);
fee8ec00
SR		 5132 break;
5133
5134#define getpid() 47
ab230d13 5135 case TARGET_NEWLIB_CR16_SYS_getpid:
fee8ec00
SR		 5136 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5137 RETVAL (getpid ());
267b3b8e 5138 trace_output_16 (sd, result);
fee8ec00
SR		 5139 break;
5140
ab230d13 5141 case TARGET_NEWLIB_CR16_SYS_kill:
fee8ec00
SR		 5142 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5143 if (PARM1 == getpid ())
5144 {
267b3b8e 5145 trace_output_void (sd);
0ef7f981 5146 EXCEPTION (PARM2);
fee8ec00
SR		 5147 }
5148 else
5149 {
5150 int os_sig = -1;
5151 switch (PARM2)
5152 {
5153#ifdef SIGHUP
5154 case 1: os_sig = SIGHUP; break;
5155#endif
5156#ifdef SIGINT
5157 case 2: os_sig = SIGINT; break;
5158#endif
5159#ifdef SIGQUIT
5160 case 3: os_sig = SIGQUIT; break;
5161#endif
5162#ifdef SIGILL
5163 case 4: os_sig = SIGILL; break;
5164#endif
5165#ifdef SIGTRAP
5166 case 5: os_sig = SIGTRAP; break;
5167#endif
5168#ifdef SIGABRT
5169 case 6: os_sig = SIGABRT; break;
5170#elif defined(SIGIOT)
5171 case 6: os_sig = SIGIOT; break;
5172#endif
5173#ifdef SIGEMT
5174 case 7: os_sig = SIGEMT; break;
5175#endif
5176#ifdef SIGFPE
5177 case 8: os_sig = SIGFPE; break;
5178#endif
5179#ifdef SIGKILL
5180 case 9: os_sig = SIGKILL; break;
5181#endif
5182#ifdef SIGBUS
5183 case 10: os_sig = SIGBUS; break;
5184#endif
5185#ifdef SIGSEGV
5186 case 11: os_sig = SIGSEGV; break;
5187#endif
5188#ifdef SIGSYS
5189 case 12: os_sig = SIGSYS; break;
5190#endif
5191#ifdef SIGPIPE
5192 case 13: os_sig = SIGPIPE; break;
5193#endif
5194#ifdef SIGALRM
5195 case 14: os_sig = SIGALRM; break;
5196#endif
5197#ifdef SIGTERM
5198 case 15: os_sig = SIGTERM; break;
5199#endif
5200#ifdef SIGURG
5201 case 16: os_sig = SIGURG; break;
5202#endif
5203#ifdef SIGSTOP
5204 case 17: os_sig = SIGSTOP; break;
5205#endif
5206#ifdef SIGTSTP
5207 case 18: os_sig = SIGTSTP; break;
5208#endif
5209#ifdef SIGCONT
5210 case 19: os_sig = SIGCONT; break;
5211#endif
5212#ifdef SIGCHLD
5213 case 20: os_sig = SIGCHLD; break;
5214#elif defined(SIGCLD)
5215 case 20: os_sig = SIGCLD; break;
5216#endif
5217#ifdef SIGTTIN
5218 case 21: os_sig = SIGTTIN; break;
5219#endif
5220#ifdef SIGTTOU
5221 case 22: os_sig = SIGTTOU; break;
5222#endif
5223#ifdef SIGIO
5224 case 23: os_sig = SIGIO; break;
5225#elif defined (SIGPOLL)
5226 case 23: os_sig = SIGPOLL; break;
5227#endif
5228#ifdef SIGXCPU
5229 case 24: os_sig = SIGXCPU; break;
5230#endif
5231#ifdef SIGXFSZ
5232 case 25: os_sig = SIGXFSZ; break;
5233#endif
5234#ifdef SIGVTALRM
5235 case 26: os_sig = SIGVTALRM; break;
5236#endif
5237#ifdef SIGPROF
5238 case 27: os_sig = SIGPROF; break;
5239#endif
5240#ifdef SIGWINCH
5241 case 28: os_sig = SIGWINCH; break;
5242#endif
5243#ifdef SIGLOST
5244 case 29: os_sig = SIGLOST; break;
5245#endif
5246#ifdef SIGUSR1
5247 case 30: os_sig = SIGUSR1; break;
5248#endif
5249#ifdef SIGUSR2
5250 case 31: os_sig = SIGUSR2; break;
5251#endif
5252 }
5253
5254 if (os_sig == -1)
5255 {
267b3b8e 5256 trace_output_void (sd);
9db36cf8
MF		 5257 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
5258 sim_io_flush_stdout (sd);
0ef7f981 5259 EXCEPTION (SIM_SIGILL);
fee8ec00
SR		 5260 }
5261 else
5262 {
5263 RETVAL (kill (PARM1, PARM2));
267b3b8e 5264 trace_output_16 (sd, result);
fee8ec00
SR		 5265 }
5266 }
5267 break;
5268
ab230d13 5269 case TARGET_NEWLIB_CR16_SYS_execve:
fee8ec00
SR		 5270 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5271 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5272 (char **)MEMPTR (PARM4)));
267b3b8e 5273 trace_output_16 (sd, result);
fee8ec00
SR		 5274 break;
5275
ab230d13 5276 case TARGET_NEWLIB_CR16_SYS_execv:
fee8ec00
SR		 5277 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5278 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
267b3b8e 5279 trace_output_16 (sd, result);
fee8ec00 5280 break;
fee8ec00 5281
ab230d13 5282 case TARGET_NEWLIB_CR16_SYS_pipe:
fee8ec00
SR		 5283 {
5284 reg_t buf;
5285 int host_fd[2];
5286
5287 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5288 buf = PARM1;
5289 RETVAL (pipe (host_fd));
5290 SW (buf, host_fd[0]);
32267d59 5291 buf += sizeof(uint16_t);
fee8ec00 5292 SW (buf, host_fd[1]);
267b3b8e 5293 trace_output_16 (sd, result);
fee8ec00
SR		 5294 }
5295 break;
5296
ab230d13 5297 case TARGET_NEWLIB_CR16_SYS_wait:
fee8ec00
SR		 5298 {
5299 int status;
5300 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5301 RETVAL (wait (&status));
5302 if (PARM1)
5303 SW (PARM1, status);
267b3b8e 5304 trace_output_16 (sd, result);
fee8ec00
SR		 5305 }
5306 break;
fee8ec00 5307#else
ab230d13 5308 case TARGET_NEWLIB_CR16_SYS_getpid:
fee8ec00
SR		 5309 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5310 RETVAL (1);
267b3b8e 5311 trace_output_16 (sd, result);
fee8ec00
SR		 5312 break;
5313
ab230d13 5314 case TARGET_NEWLIB_CR16_SYS_kill:
fee8ec00 5315 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
267b3b8e 5316 trace_output_void (sd);
0ef7f981 5317 EXCEPTION (PARM2);
fee8ec00
SR		 5318 break;
5319#endif
5320
ab230d13 5321 case TARGET_NEWLIB_CR16_SYS_read:
fee8ec00 5322 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
9db36cf8
MF		 5323 RETVAL (cb->read (cb, PARM1,
5324 MEMPTR (((unsigned long)PARM3 << 16)
5325 | ((unsigned long)PARM2)), PARM4));
267b3b8e 5326 trace_output_16 (sd, result);
fee8ec00
SR		 5327 break;
5328
ab230d13 5329 case TARGET_NEWLIB_CR16_SYS_write:
fee8ec00 5330 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
9db36cf8
MF		 5331 RETVAL ((int)cb->write (cb, PARM1,
5332 MEMPTR (((unsigned long)PARM3 << 16)
5333 | PARM2), PARM4));
267b3b8e 5334 trace_output_16 (sd, result);
fee8ec00
SR		 5335 break;
5336
ab230d13 5337 case TARGET_NEWLIB_CR16_SYS_lseek:
fee8ec00 5338 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
9db36cf8
MF		 5339 RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2),
5340 PARM4));
267b3b8e 5341 trace_output_32 (sd, result);
fee8ec00
SR		 5342 break;
5343
ab230d13 5344 case TARGET_NEWLIB_CR16_SYS_close:
fee8ec00 5345 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
9db36cf8 5346 RETVAL (cb->close (cb, PARM1));
267b3b8e 5347 trace_output_16 (sd, result);
fee8ec00
SR		 5348 break;
5349
ab230d13 5350 case TARGET_NEWLIB_CR16_SYS_open:
fee8ec00 5351 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
9db36cf8
MF		 5352 RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16)
5353 | PARM1), PARM3));
267b3b8e 5354 trace_output_32 (sd, result);
fee8ec00
SR		 5355 break;
5356
ab230d13 5357 case TARGET_NEWLIB_CR16_SYS_rename:
fee8ec00 5358 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
9db36cf8
MF		 5359 RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1),
5360 MEMPTR ((((unsigned long)PARM4) << 16) | PARM3)));
267b3b8e 5361 trace_output_16 (sd, result);
fee8ec00
SR		 5362 break;
5363
5364 case 0x408: /* REVISIT: Added a dummy getenv call. */
5365 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5aedb83b 5366 RETVAL32 (0);
267b3b8e 5367 trace_output_32 (sd, result);
fee8ec00
SR		 5368 break;
5369
ab230d13 5370 case TARGET_NEWLIB_CR16_SYS_exit:
fee8ec00 5371 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5372 trace_output_void (sd);
0ef7f981 5373 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
fee8ec00
SR		 5374 break;
5375
ab230d13 5376 case TARGET_NEWLIB_CR16_SYS_unlink:
fee8ec00 5377 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
9db36cf8 5378 RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1)));
267b3b8e 5379 trace_output_16 (sd, result);
fee8ec00
SR		 5380 break;
5381
ab230d13 5382 case TARGET_NEWLIB_CR16_SYS_stat:
fee8ec00
SR		 5383 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5384 /* stat system call. */
5385 {
5386 struct stat host_stat;
5387 reg_t buf;
5388
5389 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5390
5391 buf = PARM2;
5392
5393 /* The hard-coded offsets and sizes were determined by using
5394 * the CR16 compiler on a test program that used struct stat.
5395 */
5396 SW (buf, host_stat.st_dev);
5397 SW (buf+2, host_stat.st_ino);
5398 SW (buf+4, host_stat.st_mode);
5399 SW (buf+6, host_stat.st_nlink);
5400 SW (buf+8, host_stat.st_uid);
5401 SW (buf+10, host_stat.st_gid);
5402 SW (buf+12, host_stat.st_rdev);
5403 SLW (buf+16, host_stat.st_size);
5404 SLW (buf+20, host_stat.st_atime);
5405 SLW (buf+28, host_stat.st_mtime);
5406 SLW (buf+36, host_stat.st_ctime);
5407 }
267b3b8e 5408 trace_output_16 (sd, result);
fee8ec00 5409 break;
fee8ec00 5410
ab230d13 5411 case TARGET_NEWLIB_CR16_SYS_chown:
fee8ec00
SR		 5412 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5413 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
267b3b8e 5414 trace_output_16 (sd, result);
fee8ec00
SR		 5415 break;
5416
ab230d13 5417 case TARGET_NEWLIB_CR16_SYS_chmod:
fee8ec00
SR		 5418 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5419 RETVAL (chmod (MEMPTR (PARM1), PARM2));
267b3b8e 5420 trace_output_16 (sd, result);
fee8ec00
SR		 5421 break;
5422
ab230d13 5423 case TARGET_NEWLIB_CR16_SYS_utime:
fee8ec00
SR		 5424 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5425 /* Cast the second argument to void *, to avoid type mismatch
5426 if a prototype is present. */
5427 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
267b3b8e 5428 trace_output_16 (sd, result);
fee8ec00 5429 break;
fee8ec00 5430
ab230d13 5431 case TARGET_NEWLIB_CR16_SYS_time:
fee8ec00
SR		 5432 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5433 RETVAL32 (time (NULL));
267b3b8e 5434 trace_output_32 (sd, result);
fee8ec00 5435 break;
ab230d13 5436
fee8ec00 5437 default:
5a06d7c4
MF		 5438 a = OP[0];
5439 switch (a)
5440 {
5441 case TRAP_BREAKPOINT:
5a06d7c4
MF		 5442 tmp = (PC);
5443 JMP(tmp);
267b3b8e 5444 trace_output_void (sd);
0ef7f981 5445 EXCEPTION (SIM_SIGTRAP);
5a06d7c4
MF		 5446 break;
5447 case SIGTRAP: /* supervisor call ? */
267b3b8e 5448 trace_output_void (sd);
0ef7f981 5449 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5a06d7c4
MF		 5450 break;
5451 default:
9db36cf8 5452 cb->error (cb, "Unknown syscall %d", FUNC);
5a06d7c4
MF		 5453 break;
5454 }
fee8ec00 5455 }
32267d59 5456 if ((uint16_t) result == (uint16_t) -1)
9db36cf8 5457 RETERR (cb->get_errno (cb));
fee8ec00
SR		 5458 else
5459 RETERR (0);
5460 break;
5461 }
5462 }
5463}
5464
5465
5466/* push. */
5467void
267b3b8e 5468OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5469{
32267d59
MF		 5470 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5471 uint32_t tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
fee8ec00
SR		 5472 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5473
5474 for (; i < a; ++i)
5475 {
5476 if ((b+i) <= 11)
5477 {
5478 SW (sp_addr, (GPR (b+i)));
5479 sp_addr +=2;
5480 }
5481 else
5482 {
5483 if (is_regp == 0)
5484 tmp = (GPR32 (b+i));
5485 else
5486 tmp = (GPR32 (b+i-1));
5487
5488 if ((a-i) > 1)
5489 {
5490 SLW (sp_addr, tmp);
5491 sp_addr +=4;
5492 }
5493 else
5494 {
5495 SW (sp_addr, tmp);
5496 sp_addr +=2;
5497 }
5498 ++i;
5499 is_regp = 1;
5500 }
5501 }
5502
5503 sp_addr +=4;
5504
5505 /* Store RA address. */
5506 tmp = (GPR32 (14));
5507 SLW(sp_addr,tmp);
5508
5509 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5510 SET_GPR32 (15, sp_addr); /* Update SP address. */
5511
267b3b8e 5512 trace_output_void (sd);
fee8ec00
SR		 5513}
5514
5515/* push. */
5516void
267b3b8e 5517OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5518{
32267d59
MF		 5519 uint32_t sp_addr, tmp, is_regp = 0;
5520 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
fee8ec00
SR		 5521 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5522
5523 if (c == 1)
5524 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5525 else
5526 sp_addr = (GPR32 (15)) - (a * 2);
5527
5528 for (; i < a; ++i)
5529 {
5530 if ((b+i) <= 11)
5531 {
5532 SW (sp_addr, (GPR (b+i)));
5533 sp_addr +=2;
5534 }
5535 else
5536 {
5537 if (is_regp == 0)
5538 tmp = (GPR32 (b+i));
5539 else
5540 tmp = (GPR32 (b+i-1));
5541
5542 if ((a-i) > 1)
5543 {
5544 SLW (sp_addr, tmp);
5545 sp_addr +=4;
5546 }
5547 else
5548 {
5549 SW (sp_addr, tmp);
5550 sp_addr +=2;
5551 }
5552 ++i;
5553 is_regp = 1;
5554 }
5555 }
5556
5557 if (c == 1)
5558 {
5559 /* Store RA address. */
5560 tmp = (GPR32 (14));
5561 SLW(sp_addr,tmp);
5562 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5563 }
5564 else
5565 sp_addr = (GPR32 (15)) - (a * 2);
5566
5567 SET_GPR32 (15, sp_addr); /* Update SP address. */
5568
267b3b8e 5569 trace_output_void (sd);
fee8ec00
SR		 5570}
5571
5572
5573/* push. */
5574void
267b3b8e 5575OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5576{
32267d59 5577 uint32_t sp_addr = (GPR32 (15)), tmp;
fee8ec00
SR		 5578 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5579 tmp = (GPR32 (14));
5580 SLW(sp_addr-4,tmp); /* Store RA address. */
5581 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
267b3b8e 5582 trace_output_void (sd);
fee8ec00
SR		 5583}
5584
5585
5586/* pop. */
5587void
267b3b8e 5588OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5589{
32267d59
MF		 5590 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5591 uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
fee8ec00
SR		 5592 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5593
5594 for (; i < a; ++i)
5595 {
5596 if ((b+i) <= 11)
5597 {
5598 SET_GPR ((b+i), RW(sp_addr));
5599 sp_addr +=2;
5600 }
5601 else
5602 {
5603 if ((a-i) > 1)
5604 {
5605 tmp = RLW(sp_addr);
5606 sp_addr +=4;
5607 }
5608 else
5609 {
5610 tmp = RW(sp_addr);
5611 sp_addr +=2;
5612
5613 if (is_regp == 0)
5614 tmp = (tmp << 16) | (GPR32 (b+i));
5615 else
5616 tmp = (tmp << 16) | (GPR32 (b+i-1));
5617 }
5618
5619 if (is_regp == 0)
5620 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5621 | ((tmp >> 16) & 0xffff)));
5622 else
5623 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5624 | ((tmp >> 16) & 0xffff)));
5625
5626 ++i;
5627 is_regp = 1;
5628 }
5629 }
5630
5631 tmp = RLW(sp_addr); /* store RA also. */
5632 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5633
5634 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5635
267b3b8e 5636 trace_output_void (sd);
fee8ec00
SR		 5637}
5638
5639/* pop. */
5640void
267b3b8e 5641OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5642{
32267d59
MF		 5643 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5644 uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;
fee8ec00
SR		 5645 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5646
5647 for (; i < a; ++i)
5648 {
5649 if ((b+i) <= 11)
5650 {
5651 SET_GPR ((b+i), RW(sp_addr));
5652 sp_addr +=2;
5653 }
5654 else
5655 {
5656 if ((a-i) > 1)
5657 {
5658 tmp = RLW(sp_addr);
5659 sp_addr +=4;
5660 }
5661 else
5662 {
5663 tmp = RW(sp_addr);
5664 sp_addr +=2;
5665
5666 if (is_regp == 0)
5667 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5668 else
5669 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5670 }
5671
5672 if (is_regp == 0)
5673 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5674 else
5675 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5676 ++i;
5677 is_regp = 1;
5678 }
5679 }
5680
5681 if (c == 1)
5682 {
5683 tmp = RLW(sp_addr); /* Store RA Reg. */
5684 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5685 sp_addr +=4;
5686 }
5687
5688 SET_GPR32 (15, sp_addr); /* Update SP address. */
5689
267b3b8e 5690 trace_output_void (sd);
fee8ec00
SR		 5691}
5692
5693/* pop. */
5694void
267b3b8e 5695OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5696{
32267d59
MF		 5697 uint32_t sp_addr = GPR32 (15);
5698 uint32_t tmp;
fee8ec00
SR		 5699 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5700
5701 tmp = RLW(sp_addr);
5702 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5703 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5704
267b3b8e 5705 trace_output_void (sd);
fee8ec00
SR		 5706}
5707
5708/* popret. */
5709void
267b3b8e 5710OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5711{
32267d59 5712 uint16_t a = OP[0], b = OP[1];
fee8ec00 5713 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
267b3b8e 5714 OP_5_9 (sd, cpu);
fee8ec00
SR		 5715 JMP(((GPR32(14)) << 1) & 0xffffff);
5716
267b3b8e 5717 trace_output_void (sd);
fee8ec00
SR		 5718}
5719
5720/* popret. */
5721void
267b3b8e 5722OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5723{
32267d59 5724 uint16_t a = OP[0], b = OP[1];
fee8ec00 5725 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
267b3b8e 5726 OP_2_8 (sd, cpu);
fee8ec00
SR		 5727 JMP(((GPR32(14)) << 1) & 0xffffff);
5728
267b3b8e 5729 trace_output_void (sd);
fee8ec00
SR		 5730}
5731
5732/* popret. */
5733void
267b3b8e 5734OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5735{
32267d59 5736 uint32_t tmp;
fee8ec00 5737 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5738 OP_21E_10 (sd, cpu);
fee8ec00
SR		 5739 tmp = (((GPR32(14)) << 1) & 0xffffff);
5740 /* If the resulting PC value is less than 0x00_0000 or greater
5741 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5742
5743 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5744 {
267b3b8e 5745 trace_output_void (sd);
0ef7f981 5746 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 5747 }
5748 else
5749 JMP (tmp);
5750
267b3b8e 5751 trace_output_32 (sd, tmp);
fee8ec00
SR		 5752}
5753
5754
5755/* cinv[i]. */
5756void
267b3b8e 5757OP_A_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5758{
5759 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5760 SET_PSR_I (1);
267b3b8e 5761 trace_output_void (sd);
fee8ec00
SR		 5762}
5763
5764/* cinv[i,u]. */
5765void
267b3b8e 5766OP_B_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5767{
5768 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5769 SET_PSR_I (1);
267b3b8e 5770 trace_output_void (sd);
fee8ec00
SR		 5771}
5772
5773/* cinv[d]. */
5774void
267b3b8e 5775OP_C_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5776{
5777 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5778 SET_PSR_I (1);
267b3b8e 5779 trace_output_void (sd);
fee8ec00
SR		 5780}
5781
5782/* cinv[d,u]. */
5783void
267b3b8e 5784OP_D_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5785{
5786 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5787 SET_PSR_I (1);
267b3b8e 5788 trace_output_void (sd);
fee8ec00
SR		 5789}
5790
5791/* cinv[d,i]. */
5792void
267b3b8e 5793OP_E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5794{
5795 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5796 SET_PSR_I (1);
267b3b8e 5797 trace_output_void (sd);
fee8ec00
SR		 5798}
5799
5800/* cinv[d,i,u]. */
5801void
267b3b8e 5802OP_F_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5803{
5804 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5805 SET_PSR_I (1);
267b3b8e 5806 trace_output_void (sd);
fee8ec00
SR		 5807}
5808
5809/* retx. */
5810void
267b3b8e 5811OP_3_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5812{
5813 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5814 SET_PSR_I (1);
267b3b8e 5815 trace_output_void (sd);
fee8ec00
SR		 5816}
5817
5818/* di. */
5819void
267b3b8e 5820OP_4_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5821{
5822 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5823 SET_PSR_I (1);
267b3b8e 5824 trace_output_void (sd);
fee8ec00
SR		 5825}
5826
5827/* ei. */
5828void
267b3b8e 5829OP_5_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5830{
5831 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5832 SET_PSR_I (1);
267b3b8e 5833 trace_output_void (sd);
fee8ec00
SR		 5834}
5835
5836/* wait. */
5837void
267b3b8e 5838OP_6_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5839{
5840 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5841 trace_output_void (sd);
0ef7f981 5842 EXCEPTION (SIM_SIGTRAP);
fee8ec00
SR		 5843}
5844
5845/* ewait. */
5846void
267b3b8e 5847OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5848{
5849 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5850 SET_PSR_I (1);
267b3b8e 5851 trace_output_void (sd);
fee8ec00
SR		 5852}
5853
5854/* xorb. */
5855void
267b3b8e 5856OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5857{
32267d59 5858 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 5859 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5860 tmp = a ^ b;
5861 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5862 trace_output_16 (sd, tmp);
fee8ec00
SR		 5863}
5864
5865/* xorb. */
5866void
267b3b8e 5867OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5868{
32267d59 5869 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 5870 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5871 tmp = a ^ b;
5872 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5873 trace_output_16 (sd, tmp);
fee8ec00
SR		 5874}
5875
5876/* xorb. */
5877void
267b3b8e 5878OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5879{
32267d59 5880 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
fee8ec00
SR		 5881 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5882 tmp = a ^ b;
5883 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5884 trace_output_16 (sd, tmp);
fee8ec00
SR		 5885}
5886
5887/* xorw. */
5888void
267b3b8e 5889OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5890{
32267d59 5891 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
fee8ec00
SR		 5892 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5893 tmp = a ^ b;
5894 SET_GPR (OP[1], tmp);
267b3b8e 5895 trace_output_16 (sd, tmp);
fee8ec00
SR		 5896}
5897
5898/* xorw. */
5899void
267b3b8e 5900OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5901{
32267d59 5902 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
fee8ec00
SR		 5903 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5904 tmp = a ^ b;
5905 SET_GPR (OP[1], tmp);
267b3b8e 5906 trace_output_16 (sd, tmp);
fee8ec00
SR		 5907}
5908
5909/* xorw. */
5910void
267b3b8e 5911OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5912{
32267d59 5913 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 5914 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5915 tmp = a ^ b;
5916 SET_GPR (OP[1], tmp);
267b3b8e 5917 trace_output_16 (sd, tmp);
fee8ec00
SR		 5918}
5919
5920/*REVISIT FOR LPR/SPR . */
5921
5922/* lpr. */
5923void
267b3b8e 5924OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5925{
32267d59 5926 uint16_t a = GPR (OP[0]);
fee8ec00
SR		 5927 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5928 SET_CREG (OP[1], a);
267b3b8e 5929 trace_output_16 (sd, a);
fee8ec00
SR		 5930}
5931
5932/* lprd. */
5933void
267b3b8e 5934OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5935{
32267d59 5936 uint32_t a = GPR32 (OP[0]);
fee8ec00
SR		 5937 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5938 SET_CREG (OP[1], a);
267b3b8e 5939 trace_output_flag (sd);
fee8ec00
SR		 5940}
5941
5942/* spr. */
5943void
267b3b8e 5944OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5945{
32267d59 5946 uint16_t a = CREG (OP[0]);
fee8ec00
SR		 5947 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5948 SET_GPR (OP[1], a);
267b3b8e 5949 trace_output_16 (sd, a);
fee8ec00
SR		 5950}
5951
5952/* sprd. */
5953void
267b3b8e 5954OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5955{
32267d59 5956 uint32_t a = CREG (OP[0]);
fee8ec00
SR		 5957 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
5958 SET_GPR32 (OP[1], a);
267b3b8e 5959 trace_output_32 (sd, a);
fee8ec00
SR		 5960}
5961
5962/* null. */
5963void
267b3b8e 5964OP_0_20 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5965{
5966 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
0ef7f981 5967 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
fee8ec00 5968}
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