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sim: clean up C11 header includes
[thirdparty/binutils-gdb.git] / sim / cr16 / simops.c
CommitLineData
fee8ec00 1/* Simulation code for the CR16 processor.
3666a048 2 Copyright (C) 2008-2021 Free Software Foundation, Inc.
fee8ec00
SR		 3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
dc3cf14f 9 the Free Software Foundation; either version 3, or (at your option)
fee8ec00
SR		 10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
537e4bb9
SR		 17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
fee8ec00
SR		 19
20
21#include "config.h"
22
23#include <signal.h>
24#include <errno.h>
25#include <sys/types.h>
26#include <sys/stat.h>
27#ifdef HAVE_UNISTD_H
28#include <unistd.h>
29#endif
fee8ec00 30#include <string.h>
5aedb83b 31#include <time.h>
5aedb83b
MF		 32#ifdef HAVE_SYS_TIME_H
33#include <sys/time.h>
34#endif
fee8ec00 35
247ac9ee 36#include "sim-main.h"
fee8ec00
SR		 37#include "simops.h"
38#include "targ-vals.h"
39
5aedb83b
MF		 40#ifdef TARGET_SYS_utime
41#include <utime.h>
42#endif
43#ifdef TARGET_SYS_wait
44#include <sys/wait.h>
45#endif
fee8ec00 46
0ef7f981
MF		 47#define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
48
fee8ec00
SR		 49enum op_types {
50 OP_VOID,
51 OP_CONSTANT3,
fee8ec00 52 OP_UCONSTANT3,
fee8ec00 53 OP_CONSTANT4,
fee8ec00 54 OP_CONSTANT4_1,
fee8ec00 55 OP_CONSTANT5,
fee8ec00 56 OP_CONSTANT6,
fee8ec00 57 OP_CONSTANT16,
fee8ec00 58 OP_UCONSTANT16,
fee8ec00 59 OP_CONSTANT20,
fee8ec00 60 OP_UCONSTANT20,
fee8ec00 61 OP_CONSTANT32,
fee8ec00 62 OP_UCONSTANT32,
fee8ec00
SR		 63 OP_MEMREF,
64 OP_MEMREF2,
65 OP_MEMREF3,
66
67 OP_DISP5,
fee8ec00 68 OP_DISP17,
fee8ec00 69 OP_DISP25,
fee8ec00 70 OP_DISPE9,
fee8ec00
SR		 71 //OP_ABS20,
72 OP_ABS20_OUTPUT,
73 //OP_ABS24,
74 OP_ABS24_OUTPUT,
75
76 OP_R_BASE_DISPS16,
fee8ec00 77 OP_R_BASE_DISP20,
fee8ec00 78 OP_R_BASE_DISPS20,
fee8ec00 79 OP_R_BASE_DISPE20,
fee8ec00
SR		 80
81 OP_RP_BASE_DISPE0,
fee8ec00 82 OP_RP_BASE_DISP4,
fee8ec00 83 OP_RP_BASE_DISPE4,
fee8ec00 84 OP_RP_BASE_DISP14,
fee8ec00 85 OP_RP_BASE_DISP16,
fee8ec00 86 OP_RP_BASE_DISP20,
fee8ec00 87 OP_RP_BASE_DISPS20,
fee8ec00 88 OP_RP_BASE_DISPE20,
fee8ec00
SR		 89
90 OP_R_INDEX7_ABS20,
fee8ec00 91 OP_R_INDEX8_ABS20,
fee8ec00
SR		 92
93 OP_RP_INDEX_DISP0,
fee8ec00 94 OP_RP_INDEX_DISP14,
fee8ec00 95 OP_RP_INDEX_DISP20,
fee8ec00 96 OP_RP_INDEX_DISPS20,
fee8ec00
SR		 97
98 OP_REG,
fee8ec00 99 OP_REGP,
fee8ec00 100 OP_PROC_REG,
fee8ec00 101 OP_PROC_REGP,
fee8ec00 102 OP_COND,
537e4bb9 103 OP_RA
fee8ec00
SR		 104};
105
106
107enum {
108 PSR_MASK = (PSR_I_BIT
109 | PSR_P_BIT
110 | PSR_E_BIT
111 | PSR_N_BIT
112 | PSR_Z_BIT
113 | PSR_F_BIT
114 | PSR_U_BIT
115 | PSR_L_BIT
116 | PSR_T_BIT
117 | PSR_C_BIT),
118 /* The following bits in the PSR _can't_ be set by instructions such
119 as mvtc. */
120 PSR_HW_MASK = (PSR_MASK)
121};
122
123/* cond Code Condition True State
124 * EQ Equal Z flag is 1
125 * NE Not Equal Z flag is 0
126 * CS Carry Set C flag is 1
127 * CC Carry Clear C flag is 0
128 * HI Higher L flag is 1
129 * LS Lower or Same L flag is 0
130 * GT Greater Than N flag is 1
131 * LE Less Than or Equal To N flag is 0
132 * FS Flag Set F flag is 1
133 * FC Flag Clear F flag is 0
134 * LO Lower Z and L flags are 0
135 * HS Higher or Same Z or L flag is 1
136 * LT Less Than Z and N flags are 0
137 * GE Greater Than or Equal To Z or N flag is 1. */
138
5aedb83b 139static int cond_stat(int cc)
fee8ec00
SR		 140{
141 switch (cc)
142 {
143 case 0: return PSR_Z; break;
144 case 1: return !PSR_Z; break;
145 case 2: return PSR_C; break;
146 case 3: return !PSR_C; break;
147 case 4: return PSR_L; break;
148 case 5: return !PSR_L; break;
149 case 6: return PSR_N; break;
150 case 7: return !PSR_N; break;
151 case 8: return PSR_F; break;
152 case 9: return !PSR_F; break;
153 case 10: return !PSR_Z && !PSR_L; break;
154 case 11: return PSR_Z || PSR_L; break;
155 case 12: return !PSR_Z && !PSR_N; break;
156 case 13: return PSR_Z || PSR_N; break;
157 case 14: return 1; break; /*ALWAYS. */
158 default:
159 // case NEVER: return false; break;
160 //case NO_COND_CODE:
161 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
162 return 0; break;
163 }
164 return 0;
165}
166
167
168creg_t
267b3b8e 169move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
fee8ec00
SR		 170{
171 /* A MASK bit is set when the corresponding bit in the CR should
172 be left alone. */
173 /* This assumes that (VAL & MASK) == 0. */
174 switch (cr)
175 {
176 case PSR_CR:
177 if (psw_hw_p)
178 val &= PSR_HW_MASK;
179#if 0
180 else
181 val &= PSR_MASK;
9db36cf8
MF		 182 sim_io_printf
183 (sd,
fee8ec00 184 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
0ef7f981 185 EXCEPTION (SIM_SIGILL);
fee8ec00
SR		 186#endif
187 /* keep an up-to-date psw around for tracing. */
188 State.trace.psw = (State.trace.psw & mask) | val;
189 break;
190 default:
191 break;
192 }
193 /* only issue an update if the register is being changed. */
194 if ((State.cregs[cr] & ~mask) != val)
195 SLOT_PEND_MASK (State.cregs[cr], mask, val);
537e4bb9 196
fee8ec00
SR		 197 return val;
198}
199
200#ifdef DEBUG
267b3b8e
MF		 201static void trace_input_func (SIM_DESC sd,
202 const char *name,
bdca5ee4
TT		 203 enum op_types in1,
204 enum op_types in2,
205 enum op_types in3);
fee8ec00 206
267b3b8e 207#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
fee8ec00
SR		 208
209#ifndef SIZE_INSTRUCTION
210#define SIZE_INSTRUCTION 8
211#endif
212
213#ifndef SIZE_OPERANDS
214#define SIZE_OPERANDS 18
215#endif
216
217#ifndef SIZE_VALUES
218#define SIZE_VALUES 13
219#endif
220
221#ifndef SIZE_LOCATION
222#define SIZE_LOCATION 20
223#endif
224
225#ifndef SIZE_PC
226#define SIZE_PC 4
227#endif
228
229#ifndef SIZE_LINE_NUMBER
230#define SIZE_LINE_NUMBER 2
231#endif
232
233static void
267b3b8e 234trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
fee8ec00
SR		 235{
236 char *comma;
237 enum op_types in[3];
238 int i;
239 char buf[1024];
240 char *p;
241 long tmp;
242 char *type;
243 const char *filename;
244 const char *functionname;
245 unsigned int linenumber;
246 bfd_vma byte_pc;
247
248 if ((cr16_debug & DEBUG_TRACE) == 0)
249 return;
250
251 switch (State.ins_type)
252 {
253 default:
254 case INS_UNKNOWN: type = " ?"; break;
255 }
256
257 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
9db36cf8 258 sim_io_printf (sd,
fee8ec00
SR		 259 "0x%.*x %s: %-*s ",
260 SIZE_PC, (unsigned)PC,
261 type,
262 SIZE_INSTRUCTION, name);
263
264 else
265 {
266 buf[0] = '\0';
247ac9ee 267 byte_pc = PC;
267b3b8e
MF		 268 if (STATE_TEXT_SECTION (sd)
269 && byte_pc >= STATE_TEXT_START (sd)
270 && byte_pc < STATE_TEXT_END (sd))
fee8ec00
SR		 271 {
272 filename = (const char *)0;
273 functionname = (const char *)0;
274 linenumber = 0;
267b3b8e
MF		 275 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
276 STATE_TEXT_SECTION (sd),
247ac9ee 277 (struct bfd_symbol **)0,
267b3b8e 278 byte_pc - STATE_TEXT_START (sd),
fee8ec00
SR		 279 &filename, &functionname, &linenumber))
280 {
281 p = buf;
282 if (linenumber)
283 {
284 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
285 p += strlen (p);
286 }
287 else
288 {
289 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
290 p += SIZE_LINE_NUMBER+2;
291 }
292
293 if (functionname)
294 {
295 sprintf (p, "%s ", functionname);
296 p += strlen (p);
297 }
298 else if (filename)
299 {
300 char *q = strrchr (filename, '/');
301 sprintf (p, "%s ", (q) ? q+1 : filename);
302 p += strlen (p);
303 }
304
305 if (*p == ' ')
306 *p = '\0';
307 }
308 }
309
9db36cf8 310 sim_io_printf (sd,
fee8ec00
SR		 311 "0x%.*x %s: %-*.*s %-*s ",
312 SIZE_PC, (unsigned)PC,
313 type,
314 SIZE_LOCATION, SIZE_LOCATION, buf,
315 SIZE_INSTRUCTION, name);
316 }
317
318 in[0] = in1;
319 in[1] = in2;
320 in[2] = in3;
321 comma = "";
322 p = buf;
323 for (i = 0; i < 3; i++)
324 {
325 switch (in[i])
326 {
327 case OP_VOID:
328 break;
329
330 case OP_REG:
fee8ec00 331 case OP_REGP:
fee8ec00
SR		 332 sprintf (p, "%sr%d", comma, OP[i]);
333 p += strlen (p);
334 comma = ",";
335 break;
336
337 case OP_PROC_REG:
fee8ec00
SR		 338 sprintf (p, "%scr%d", comma, OP[i]);
339 p += strlen (p);
340 comma = ",";
341 break;
342
343 case OP_CONSTANT16:
344 sprintf (p, "%s%d", comma, OP[i]);
345 p += strlen (p);
346 comma = ",";
347 break;
348
349 case OP_CONSTANT4:
350 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
351 p += strlen (p);
352 comma = ",";
353 break;
354
355 case OP_CONSTANT3:
356 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
357 p += strlen (p);
358 comma = ",";
359 break;
360
361 case OP_MEMREF:
362 sprintf (p, "%s@r%d", comma, OP[i]);
363 p += strlen (p);
364 comma = ",";
365 break;
366
367 case OP_MEMREF2:
368 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
369 p += strlen (p);
370 comma = ",";
371 break;
372
373 case OP_MEMREF3:
374 sprintf (p, "%s@%d", comma, OP[i]);
375 p += strlen (p);
376 comma = ",";
377 break;
378 }
379 }
380
381 if ((cr16_debug & DEBUG_VALUES) == 0)
382 {
383 *p++ = '\n';
384 *p = '\0';
9db36cf8 385 sim_io_printf (sd, "%s", buf);
fee8ec00
SR		 386 }
387 else
388 {
389 *p = '\0';
9db36cf8 390 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
fee8ec00
SR		 391
392 p = buf;
393 for (i = 0; i < 3; i++)
394 {
395 buf[0] = '\0';
396 switch (in[i])
397 {
398 case OP_VOID:
9db36cf8 399 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
fee8ec00
SR		 400 break;
401
fee8ec00 402 case OP_REG:
9db36cf8 403 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 404 (uint16) GPR (OP[i]));
405 break;
406
407 case OP_REGP:
408 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
9db36cf8 409 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
fee8ec00
SR		 410 break;
411
412 case OP_PROC_REG:
9db36cf8 413 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 414 (uint16) CREG (OP[i]));
415 break;
416
417 case OP_CONSTANT16:
9db36cf8 418 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 419 (uint16)OP[i]);
420 break;
421
422 case OP_CONSTANT4:
9db36cf8 423 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 424 (uint16)SEXT4(OP[i]));
425 break;
426
427 case OP_CONSTANT3:
9db36cf8 428 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 429 (uint16)SEXT3(OP[i]));
430 break;
431
432 case OP_MEMREF2:
9db36cf8 433 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00 434 (uint16)OP[i]);
9db36cf8 435 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 436 (uint16)GPR (OP[i + 1]));
437 i++;
438 break;
439 }
440 }
441 }
442
9db36cf8 443 sim_io_flush_stdout (sd);
fee8ec00
SR		 444}
445
446static void
267b3b8e 447do_trace_output_flush (SIM_DESC sd)
fee8ec00 448{
9db36cf8 449 sim_io_flush_stdout (sd);
fee8ec00
SR		 450}
451
452static void
267b3b8e 453do_trace_output_finish (SIM_DESC sd)
fee8ec00 454{
9db36cf8 455 sim_io_printf (sd,
fee8ec00
SR		 456 " F0=%d F1=%d C=%d\n",
457 (State.trace.psw & PSR_F_BIT) != 0,
458 (State.trace.psw & PSR_F_BIT) != 0,
459 (State.trace.psw & PSR_C_BIT) != 0);
9db36cf8 460 sim_io_flush_stdout (sd);
fee8ec00
SR		 461}
462
5aedb83b 463#if 0
fee8ec00 464static void
267b3b8e 465trace_output_40 (SIM_DESC sd, uint64 val)
fee8ec00
SR		 466{
467 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
468 {
9db36cf8 469 sim_io_printf (sd,
fee8ec00
SR		 470 " :: %*s0x%.2x%.8lx",
471 SIZE_VALUES - 12,
472 "",
473 ((int)(val >> 32) & 0xff),
474 ((unsigned long) val) & 0xffffffff);
475 do_trace_output_finish ();
476 }
477}
5aedb83b 478#endif
fee8ec00
SR		 479
480static void
267b3b8e 481trace_output_32 (SIM_DESC sd, uint32 val)
fee8ec00
SR		 482{
483 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
484 {
9db36cf8 485 sim_io_printf (sd,
fee8ec00
SR		 486 " :: %*s0x%.8x",
487 SIZE_VALUES - 10,
488 "",
489 (int) val);
267b3b8e 490 do_trace_output_finish (sd);
fee8ec00
SR		 491 }
492}
493
494static void
267b3b8e 495trace_output_16 (SIM_DESC sd, uint16 val)
fee8ec00
SR		 496{
497 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
498 {
9db36cf8 499 sim_io_printf (sd,
fee8ec00
SR		 500 " :: %*s0x%.4x",
501 SIZE_VALUES - 6,
502 "",
503 (int) val);
267b3b8e 504 do_trace_output_finish (sd);
fee8ec00
SR		 505 }
506}
507
508static void
267b3b8e 509trace_output_void (SIM_DESC sd)
fee8ec00
SR		 510{
511 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
512 {
9db36cf8 513 sim_io_printf (sd, "\n");
267b3b8e 514 do_trace_output_flush (sd);
fee8ec00
SR		 515 }
516}
517
518static void
267b3b8e 519trace_output_flag (SIM_DESC sd)
fee8ec00
SR		 520{
521 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
522 {
9db36cf8 523 sim_io_printf (sd,
fee8ec00
SR		 524 " :: %*s",
525 SIZE_VALUES,
526 "");
267b3b8e 527 do_trace_output_finish (sd);
fee8ec00
SR		 528 }
529}
530
531
532
533
534#else
535#define trace_input(NAME, IN1, IN2, IN3)
536#define trace_output(RESULT)
537#endif
538
539/* addub. */
540void
267b3b8e 541OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 542{
543 uint8 tmp;
544 uint8 a = OP[0] & 0xff;
545 uint16 b = (GPR (OP[1])) & 0xff;
546 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
547 tmp = (a + b) & 0xff;
548 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 549 trace_output_16 (sd, tmp);
fee8ec00
SR		 550}
551
552/* addub. */
553void
267b3b8e 554OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 555{
556 uint16 tmp;
557 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
558 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
559 tmp = (a + b) & 0xff;
560 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 561 trace_output_16 (sd, tmp);
fee8ec00
SR		 562}
563
564/* addub. */
565void
267b3b8e 566OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 567{
568 uint8 a = (GPR (OP[0])) & 0xff;
569 uint8 b = (GPR (OP[1])) & 0xff;
570 uint16 tmp = (a + b) & 0xff;
571 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
572 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 573 trace_output_16 (sd, tmp);
fee8ec00
SR		 574}
575
576/* adduw. */
577void
267b3b8e 578OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 579{
580 uint16 a = OP[0];
581 uint16 b = GPR (OP[1]);
582 uint16 tmp = (a + b);
583 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
584 SET_GPR (OP[1], tmp);
267b3b8e 585 trace_output_16 (sd, tmp);
fee8ec00
SR		 586}
587
588/* adduw. */
589void
267b3b8e 590OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 591{
592 uint16 a = OP[0];
593 uint16 b = GPR (OP[1]);
594 uint16 tmp = (a + b);
595 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
596 SET_GPR (OP[1], tmp);
267b3b8e 597 trace_output_16 (sd, tmp);
fee8ec00
SR		 598}
599
600/* adduw. */
601void
267b3b8e 602OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 603{
604 uint16 a = GPR (OP[0]);
605 uint16 b = GPR (OP[1]);
606 uint16 tmp = (a + b);
607 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
608 SET_GPR (OP[1], tmp);
267b3b8e 609 trace_output_16 (sd, tmp);
fee8ec00
SR		 610}
611
612/* addb. */
613void
267b3b8e 614OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 615{
616 uint8 a = OP[0];
617 uint8 b = (GPR (OP[1]) & 0xff);
fee8ec00 618 uint16 tmp = (a + b) & 0xff;
5aedb83b 619 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 620 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
621 SET_PSR_C (tmp > 0xFF);
622 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 623 trace_output_16 (sd, tmp);
fee8ec00
SR		 624}
625
626/* addb. */
627void
267b3b8e 628OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 629{
630 uint8 a = (OP[0]) & 0xff;
631 uint8 b = (GPR (OP[1]) & 0xff);
fee8ec00 632 uint16 tmp = (a + b) & 0xff;
5aedb83b 633 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 634 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
635 SET_PSR_C (tmp > 0xFF);
636 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 637 trace_output_16 (sd, tmp);
fee8ec00
SR		 638}
639
640/* addb. */
641void
267b3b8e 642OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 643{
644 uint8 a = (GPR (OP[0]) & 0xff);
645 uint8 b = (GPR (OP[1]) & 0xff);
fee8ec00 646 uint16 tmp = (a + b) & 0xff;
5aedb83b 647 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 648 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
649 SET_PSR_C (tmp > 0xFF);
650 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 651 trace_output_16 (sd, tmp);
fee8ec00
SR		 652}
653
654/* addw. */
655void
267b3b8e 656OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 657{
658 int16 a = OP[0];
659 uint16 tmp, b = GPR (OP[1]);
fee8ec00 660 tmp = (a + b);
5aedb83b 661 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 662 SET_GPR (OP[1], tmp);
663 SET_PSR_C (tmp > 0xFFFF);
664 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 665 trace_output_16 (sd, tmp);
fee8ec00
SR		 666}
667
668/* addw. */
669void
267b3b8e 670OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 671{
672 int16 a = OP[0];
673 uint16 tmp, b = GPR (OP[1]);
674 tmp = (a + b);
675 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
676 SET_GPR (OP[1], tmp);
677 SET_PSR_C (tmp > 0xFFFF);
678 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 679 trace_output_16 (sd, tmp);
fee8ec00
SR		 680}
681
682/* addw. */
683void
267b3b8e 684OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 685{
686 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
687 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
688 tmp = (a + b);
689 SET_GPR (OP[1], tmp);
690 SET_PSR_C (tmp > 0xFFFF);
691 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 692 trace_output_16 (sd, tmp);
fee8ec00
SR		 693}
694
695/* addcb. */
696void
267b3b8e 697OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 698{
699 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
700 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
701 tmp = (a + b + PSR_C) & 0xff;
702 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
703 SET_PSR_C (tmp > 0xFF);
704 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 705 trace_output_16 (sd, tmp);
fee8ec00
SR		 706}
707
708/* addcb. */
709void
267b3b8e 710OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 711{
712 int8 a = OP[0] & 0xff;
713 uint8 b = (GPR (OP[1])) & 0xff;
fee8ec00 714 uint8 tmp = (a + b + PSR_C) & 0xff;
5aedb83b 715 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 716 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
717 SET_PSR_C (tmp > 0xFF);
718 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 719 trace_output_16 (sd, tmp);
fee8ec00
SR		 720}
721
722/* addcb. */
723void
267b3b8e 724OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 725{
726 uint8 a = (GPR (OP[0])) & 0xff;
727 uint8 b = (GPR (OP[1])) & 0xff;
fee8ec00 728 uint8 tmp = (a + b + PSR_C) & 0xff;
5aedb83b 729 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 730 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
731 SET_PSR_C (tmp > 0xFF);
732 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 733 trace_output_16 (sd, tmp);
fee8ec00
SR		 734}
735
736/* addcw. */
737void
267b3b8e 738OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 739{
740 uint16 a = OP[0];
741 uint16 b = GPR (OP[1]);
fee8ec00 742 uint16 tmp = (a + b + PSR_C);
5aedb83b 743 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 744 SET_GPR (OP[1], tmp);
745 SET_PSR_C (tmp > 0xFFFF);
746 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 747 trace_output_16 (sd, tmp);
fee8ec00
SR		 748}
749
750/* addcw. */
751void
267b3b8e 752OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 753{
754 int16 a = OP[0];
755 uint16 b = GPR (OP[1]);
fee8ec00 756 uint16 tmp = (a + b + PSR_C);
5aedb83b 757 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 758 SET_GPR (OP[1], tmp);
759 SET_PSR_C (tmp > 0xFFFF);
760 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 761 trace_output_16 (sd, tmp);
fee8ec00
SR		 762}
763
764/* addcw. */
765void
267b3b8e 766OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 767{
768 uint16 a = GPR (OP[1]);
769 uint16 b = GPR (OP[1]);
fee8ec00 770 uint16 tmp = (a + b + PSR_C);
5aedb83b 771 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 772 SET_GPR (OP[1], tmp);
773 SET_PSR_C (tmp > 0xFFFF);
774 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 775 trace_output_16 (sd, tmp);
fee8ec00
SR		 776}
777
778/* addd. */
779void
267b3b8e 780OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 781{
782 int16 a = (OP[0]);
783 uint32 b = GPR32 (OP[1]);
fee8ec00 784 uint32 tmp = (a + b);
5aedb83b 785 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
fee8ec00
SR		 786 SET_GPR32 (OP[1], tmp);
787 SET_PSR_C (tmp > 0xFFFFFFFF);
788 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 789 trace_output_32 (sd, tmp);
fee8ec00
SR		 790}
791
792/* addd. */
793void
267b3b8e 794OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 795{
796 int32 a = (SEXT16(OP[0]));
797 uint32 b = GPR32 (OP[1]);
fee8ec00 798 uint32 tmp = (a + b);
5aedb83b 799 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
fee8ec00
SR		 800 SET_GPR32 (OP[1], tmp);
801 SET_PSR_C (tmp > 0xFFFFFFFF);
802 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 803 trace_output_32 (sd, tmp);
fee8ec00
SR		 804}
805
806/* addd. */
807void
267b3b8e 808OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 809{
810 uint32 a = GPR32 (OP[0]);
811 uint32 b = GPR32 (OP[1]);
fee8ec00 812 uint32 tmp = (a + b);
5aedb83b 813 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
fee8ec00 814 SET_GPR32 (OP[1], tmp);
267b3b8e 815 trace_output_32 (sd, tmp);
fee8ec00
SR		 816 SET_PSR_C (tmp > 0xFFFFFFFF);
817 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
818}
819
820/* addd. */
821void
267b3b8e 822OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 823{
824 uint32 a = OP[0];
825 uint32 b = GPR32 (OP[1]);
826 uint32 tmp;
827 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
828 tmp = (a + b);
829 SET_GPR32 (OP[1], tmp);
830 SET_PSR_C (tmp > 0xFFFFFFFF);
831 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 832 trace_output_32 (sd, tmp);
fee8ec00
SR		 833}
834
835/* addd. */
836void
267b3b8e 837OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 838{
839 int32 a = OP[0];
840 uint32 b = GPR32 (OP[1]);
841 uint32 tmp;
842 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
843 tmp = (a + b);
844 SET_GPR32 (OP[1], tmp);
845 SET_PSR_C (tmp > 0xFFFFFFFF);
846 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 847 trace_output_32 (sd, tmp);
fee8ec00
SR		 848}
849
850/* andb. */
851void
267b3b8e 852OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 853{
854 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
855 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
856 tmp = a & b;
857 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 858 trace_output_16 (sd, tmp);
fee8ec00
SR		 859}
860
861/* andb. */
862void
267b3b8e 863OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 864{
865 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
866 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
867 tmp = a & b;
868 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 869 trace_output_16 (sd, tmp);
fee8ec00
SR		 870}
871
872/* andb. */
873void
267b3b8e 874OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 875{
876 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
877 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
878 tmp = a & b;
879 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 880 trace_output_16 (sd, tmp);
fee8ec00
SR		 881}
882
883/* andw. */
884void
267b3b8e 885OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 886{
887 uint16 tmp, a = OP[0], b = GPR (OP[1]);
888 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
889 tmp = a & b;
890 SET_GPR (OP[1], tmp);
267b3b8e 891 trace_output_16 (sd, tmp);
fee8ec00
SR		 892}
893
894/* andw. */
895void
267b3b8e 896OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 897{
898 uint16 tmp, a = OP[0], b = GPR (OP[1]);
899 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
900 tmp = a & b;
901 SET_GPR (OP[1], tmp);
267b3b8e 902 trace_output_16 (sd, tmp);
fee8ec00
SR		 903}
904
905/* andw. */
906void
267b3b8e 907OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 908{
909 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
910 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
911 tmp = a & b;
912 SET_GPR (OP[1], tmp);
267b3b8e 913 trace_output_16 (sd, tmp);
fee8ec00
SR		 914}
915
916/* andd. */
917void
267b3b8e 918OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 919{
920 uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
921 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
922 tmp = a & b;
923 SET_GPR32 (OP[1], tmp);
267b3b8e 924 trace_output_32 (sd, tmp);
fee8ec00
SR		 925}
926
927/* andd. */
928void
267b3b8e 929OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 930{
931 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
932 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
933 tmp = a & b;
934 SET_GPR32 (OP[1], tmp);
267b3b8e 935 trace_output_32 (sd, tmp);
fee8ec00
SR		 936}
937
938/* ord. */
939void
267b3b8e 940OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 941{
942 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
943 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
944 tmp = a | b;
945 SET_GPR32 (OP[1], tmp);
267b3b8e 946 trace_output_32 (sd, tmp);
fee8ec00
SR		 947}
948
949/* ord. */
950void
267b3b8e 951OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 952{
953 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
954 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
955 tmp = a | b;
956 SET_GPR32 (OP[1], tmp);
267b3b8e 957 trace_output_32 (sd, tmp);
fee8ec00
SR		 958}
959
960/* xord. */
961void
267b3b8e 962OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 963{
964 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
965 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
966 tmp = a ^ b;
967 SET_GPR32 (OP[1], tmp);
267b3b8e 968 trace_output_32 (sd, tmp);
fee8ec00
SR		 969}
970
971/* xord. */
972void
267b3b8e 973OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 974{
975 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
976 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
977 tmp = a ^ b;
978 SET_GPR32 (OP[1], tmp);
267b3b8e 979 trace_output_32 (sd, tmp);
fee8ec00
SR		 980}
981
982
983/* b. */
984void
267b3b8e 985OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 986{
5aedb83b 987 uint32 tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 988 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
989 if (cc)
990 {
991 if (sign_flag)
992 tmp = (PC - (OP[1]));
993 else
994 tmp = (PC + (OP[1]));
995 /* If the resulting PC value is less than 0x00_0000 or greater
996 than 0xFF_FFFF, this instruction causes an IAD trap.*/
997
998 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
999 {
267b3b8e 1000 trace_output_void (sd);
0ef7f981 1001 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1002 }
1003 else
1004 JMP (tmp);
1005 }
1006 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1007 trace_output_32 (sd, tmp);
fee8ec00
SR		 1008}
1009
1010/* b. */
1011void
267b3b8e 1012OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1013{
5aedb83b 1014 uint32 tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 1015 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1016 if (cc)
1017 {
1018 if (sign_flag)
1019 tmp = (PC - OP[1]);
1020 else
1021 tmp = (PC + OP[1]);
1022 /* If the resulting PC value is less than 0x00_0000 or greater
1023 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1024
1025 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1026 {
267b3b8e 1027 trace_output_void (sd);
0ef7f981 1028 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1029 }
1030 else
1031 JMP (tmp);
1032 }
1033 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1034 trace_output_32 (sd, tmp);
fee8ec00
SR		 1035}
1036
1037/* b. */
1038void
267b3b8e 1039OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1040{
5aedb83b 1041 uint32 tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 1042 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1043 if (cc)
1044 {
1045 if (sign_flag)
1046 tmp = (PC - (OP[1]));
1047 else
1048 tmp = (PC + (OP[1]));
1049 /* If the resulting PC value is less than 0x00_0000 or greater
1050 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1051
1052 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1053 {
267b3b8e 1054 trace_output_void (sd);
0ef7f981 1055 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1056 }
1057 else
1058 JMP (tmp);
1059 }
1060 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1061 trace_output_32 (sd, tmp);
fee8ec00
SR		 1062}
1063
1064/* bal. */
1065void
267b3b8e 1066OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1067{
1068 uint32 tmp;
1069 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1070 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1071 SET_GPR32 (14, tmp);
1072 if (sign_flag)
1073 tmp = (PC - (OP[1]));
1074 else
1075 tmp = (PC + (OP[1]));
1076
1077 /* If the resulting PC value is less than 0x00_0000 or greater
1078 than 0xFF_FFFF, this instruction causes an IAD trap. */
1079
1080 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1081 {
267b3b8e 1082 trace_output_void (sd);
0ef7f981 1083 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1084 }
1085 else
1086 JMP (tmp);
1087 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1088 trace_output_32 (sd, tmp);
fee8ec00
SR		 1089}
1090
1091
1092/* bal. */
1093void
267b3b8e 1094OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1095{
1096 uint32 tmp;
1097 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1098 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1099 SET_GPR32 (OP[0], tmp);
1100 if (sign_flag)
1101 tmp = ((PC) - (OP[1]));
1102 else
1103 tmp = ((PC) + (OP[1]));
1104 /* If the resulting PC value is less than 0x00_0000 or greater
1105 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1106
1107 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1108 {
267b3b8e 1109 trace_output_void (sd);
0ef7f981 1110 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1111 }
1112 else
1113 JMP (tmp);
1114 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1115 trace_output_32 (sd, tmp);
fee8ec00
SR		 1116}
1117
1118/* jal. */
1119void
267b3b8e 1120OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1121{
1122 uint32 tmp;
1123 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1124 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1125 tmp = GPR32 (OP[1]);
1126 tmp = SEXT24(tmp << 1);
1127 /* If the resulting PC value is less than 0x00_0000 or greater
1128 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1129
1130 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1131 {
267b3b8e 1132 trace_output_void (sd);
0ef7f981 1133 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1134 }
1135 else
1136 JMP (tmp);
1137
267b3b8e 1138 trace_output_32 (sd, tmp);
fee8ec00
SR		 1139}
1140
1141
1142/* jal. */
1143void
267b3b8e 1144OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1145{
1146 uint32 tmp;
1147 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1148 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1149 tmp = GPR32 (OP[0]);
1150 tmp = SEXT24(tmp << 1);
1151 /* If the resulting PC value is less than 0x00_0000 or greater
1152 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1153
1154 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1155 {
267b3b8e 1156 trace_output_void (sd);
0ef7f981 1157 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1158 }
1159 else
1160 JMP (tmp);
1161
267b3b8e 1162 trace_output_32 (sd, tmp);
fee8ec00
SR		 1163}
1164
1165
1166/* beq0b. */
1167void
267b3b8e 1168OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1169{
1170 uint32 addr;
1171 uint8 a = (GPR (OP[0]) & 0xFF);
1172 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1173 addr = OP[1];
1174 if (a == 0)
1175 {
1176 if (sign_flag)
1177 addr = (PC - OP[1]);
1178 else
1179 addr = (PC + OP[1]);
1180
1181 JMP (addr);
1182 }
1183 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1184 trace_output_void (sd);
fee8ec00
SR		 1185}
1186
1187/* bne0b. */
1188void
267b3b8e 1189OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1190{
1191 uint32 addr;
1192 uint8 a = (GPR (OP[0]) & 0xFF);
1193 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1194 addr = OP[1];
1195 if (a != 0)
1196 {
1197 if (sign_flag)
1198 addr = (PC - OP[1]);
1199 else
1200 addr = (PC + OP[1]);
1201
1202 JMP (addr);
1203 }
1204 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1205 trace_output_void (sd);
fee8ec00
SR		 1206}
1207
1208/* beq0w. */
1209void
267b3b8e 1210OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1211{
1212 uint32 addr;
1213 uint16 a = GPR (OP[0]);
1214 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1215 addr = OP[1];
1216 if (a == 0)
1217 {
1218 if (sign_flag)
1219 addr = (PC - OP[1]);
1220 else
1221 addr = (PC + OP[1]);
1222
1223 JMP (addr);
1224 }
1225 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1226 trace_output_void (sd);
fee8ec00
SR		 1227}
1228
1229/* bne0w. */
1230void
267b3b8e 1231OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1232{
1233 uint32 addr;
1234 uint16 a = GPR (OP[0]);
1235 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1236 addr = OP[1];
1237 if (a != 0)
1238 {
1239 if (sign_flag)
1240 addr = (PC - OP[1]);
1241 else
1242 addr = (PC + OP[1]);
1243
1244 JMP (addr);
1245 }
1246 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1247 trace_output_void (sd);
fee8ec00
SR		 1248}
1249
1250
1251/* jeq. */
1252void
267b3b8e 1253OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1254{
5aedb83b 1255 uint32 tmp = 0;
fee8ec00
SR		 1256 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1257 if ((PSR_Z) == 1)
1258 {
1259 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1260 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1261 }
267b3b8e 1262 trace_output_32 (sd, tmp);
fee8ec00
SR		 1263}
1264
1265/* jne. */
1266void
267b3b8e 1267OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1268{
5aedb83b 1269 uint32 tmp = 0;
fee8ec00
SR		 1270 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1271 if ((PSR_Z) == 0)
1272 {
1273 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1274 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1275 }
267b3b8e 1276 trace_output_32 (sd, tmp);
fee8ec00
SR		 1277}
1278
1279/* jcs. */
1280void
267b3b8e 1281OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1282{
5aedb83b 1283 uint32 tmp = 0;
fee8ec00
SR		 1284 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1285 if ((PSR_C) == 1)
1286 {
1287 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1288 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1289 }
267b3b8e 1290 trace_output_32 (sd, tmp);
fee8ec00
SR		 1291}
1292
1293/* jcc. */
1294void
267b3b8e 1295OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1296{
5aedb83b 1297 uint32 tmp = 0;
fee8ec00
SR		 1298 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1299 if ((PSR_C) == 0)
1300 {
1301 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1302 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1303 }
267b3b8e 1304 trace_output_32 (sd, tmp);
fee8ec00
SR		 1305}
1306
1307/* jhi. */
1308void
267b3b8e 1309OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1310{
5aedb83b 1311 uint32 tmp = 0;
fee8ec00
SR		 1312 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1313 if ((PSR_L) == 1)
1314 {
1315 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1316 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1317 }
267b3b8e 1318 trace_output_32 (sd, tmp);
fee8ec00
SR		 1319}
1320
1321/* jls. */
1322void
267b3b8e 1323OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1324{
5aedb83b 1325 uint32 tmp = 0;
fee8ec00
SR		 1326 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1327 if ((PSR_L) == 0)
1328 {
1329 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1330 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1331 }
267b3b8e 1332 trace_output_32 (sd, tmp);
fee8ec00
SR		 1333}
1334
1335/* jgt. */
1336void
267b3b8e 1337OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1338{
5aedb83b 1339 uint32 tmp = 0;
fee8ec00
SR		 1340 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1341 if ((PSR_N) == 1)
1342 {
1343 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1344 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1345 }
267b3b8e 1346 trace_output_32 (sd, tmp);
fee8ec00
SR		 1347}
1348
1349/* jle. */
1350void
267b3b8e 1351OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1352{
5aedb83b 1353 uint32 tmp = 0;
fee8ec00
SR		 1354 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1355 if ((PSR_N) == 0)
1356 {
1357 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1358 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1359 }
267b3b8e 1360 trace_output_32 (sd, tmp);
fee8ec00
SR		 1361}
1362
1363
1364/* jfs. */
1365void
267b3b8e 1366OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1367{
5aedb83b 1368 uint32 tmp = 0;
fee8ec00
SR		 1369 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1370 if ((PSR_F) == 1)
1371 {
1372 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1373 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1374 }
267b3b8e 1375 trace_output_32 (sd, tmp);
fee8ec00
SR		 1376}
1377
1378/* jfc. */
1379void
267b3b8e 1380OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1381{
5aedb83b 1382 uint32 tmp = 0;
fee8ec00
SR		 1383 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1384 if ((PSR_F) == 0)
1385 {
1386 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1387 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1388 }
267b3b8e 1389 trace_output_32 (sd, tmp);
fee8ec00
SR		 1390}
1391
1392/* jlo. */
1393void
267b3b8e 1394OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1395{
5aedb83b 1396 uint32 tmp = 0;
fee8ec00
SR		 1397 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1398 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1399 {
1400 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1401 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1402 }
267b3b8e 1403 trace_output_32 (sd, tmp);
fee8ec00
SR		 1404}
1405
1406/* jhs. */
1407void
267b3b8e 1408OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1409{
5aedb83b 1410 uint32 tmp = 0;
fee8ec00
SR		 1411 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1412 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1413 {
1414 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1415 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1416 }
267b3b8e 1417 trace_output_32 (sd, tmp);
fee8ec00
SR		 1418}
1419
1420/* jlt. */
1421void
267b3b8e 1422OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1423{
5aedb83b 1424 uint32 tmp = 0;
fee8ec00
SR		 1425 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1426 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1427 {
1428 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1429 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1430 }
267b3b8e 1431 trace_output_32 (sd, tmp);
fee8ec00
SR		 1432}
1433
1434/* jge. */
1435void
267b3b8e 1436OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1437{
5aedb83b 1438 uint32 tmp = 0;
fee8ec00
SR		 1439 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1440 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1441 {
1442 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1443 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1444 }
267b3b8e 1445 trace_output_32 (sd, tmp);
fee8ec00
SR		 1446}
1447
1448/* jump. */
1449void
267b3b8e 1450OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1451{
1452 uint32 tmp;
1453 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1454 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1455 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
267b3b8e 1456 trace_output_32 (sd, tmp);
fee8ec00
SR		 1457}
1458
1459/* jusr. */
1460void
267b3b8e 1461OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1462{
1463 uint32 tmp;
1464 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1465 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1466 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1467 SET_PSR_U(1);
267b3b8e 1468 trace_output_32 (sd, tmp);
fee8ec00
SR		 1469}
1470
1471/* seq. */
1472void
267b3b8e 1473OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1474{
1475 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1476 if ((PSR_Z) == 1)
1477 SET_GPR (OP[0], 1);
1478 else
1479 SET_GPR (OP[0], 0);
267b3b8e 1480 trace_output_void (sd);
fee8ec00
SR		 1481}
1482/* sne. */
1483void
267b3b8e 1484OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1485{
1486 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1487 if ((PSR_Z) == 0)
1488 SET_GPR (OP[0], 1);
1489 else
1490 SET_GPR (OP[0], 0);
267b3b8e 1491 trace_output_void (sd);
fee8ec00
SR		 1492}
1493
1494/* scs. */
1495void
267b3b8e 1496OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1497{
1498 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1499 if ((PSR_C) == 1)
1500 SET_GPR (OP[0], 1);
1501 else
1502 SET_GPR (OP[0], 0);
267b3b8e 1503 trace_output_void (sd);
fee8ec00
SR		 1504}
1505
1506/* scc. */
1507void
267b3b8e 1508OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1509{
1510 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1511 if ((PSR_C) == 0)
1512 SET_GPR (OP[0], 1);
1513 else
1514 SET_GPR (OP[0], 0);
267b3b8e 1515 trace_output_void (sd);
fee8ec00
SR		 1516}
1517
1518/* shi. */
1519void
267b3b8e 1520OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1521{
1522 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1523 if ((PSR_L) == 1)
1524 SET_GPR (OP[0], 1);
1525 else
1526 SET_GPR (OP[0], 0);
267b3b8e 1527 trace_output_void (sd);
fee8ec00
SR		 1528}
1529
1530/* sls. */
1531void
267b3b8e 1532OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1533{
1534 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1535 if ((PSR_L) == 0)
1536 SET_GPR (OP[0], 1);
1537 else
1538 SET_GPR (OP[0], 0);
267b3b8e 1539 trace_output_void (sd);
fee8ec00
SR		 1540}
1541
1542/* sgt. */
1543void
267b3b8e 1544OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1545{
1546 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1547 if ((PSR_N) == 1)
1548 SET_GPR (OP[0], 1);
1549 else
1550 SET_GPR (OP[0], 0);
267b3b8e 1551 trace_output_void (sd);
fee8ec00
SR		 1552}
1553
1554/* sle. */
1555void
267b3b8e 1556OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1557{
1558 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1559 if ((PSR_N) == 0)
1560 SET_GPR (OP[0], 1);
1561 else
1562 SET_GPR (OP[0], 0);
267b3b8e 1563 trace_output_void (sd);
fee8ec00
SR		 1564}
1565
1566/* sfs. */
1567void
267b3b8e 1568OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1569{
1570 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1571 if ((PSR_F) == 1)
1572 SET_GPR (OP[0], 1);
1573 else
1574 SET_GPR (OP[0], 0);
267b3b8e 1575 trace_output_void (sd);
fee8ec00
SR		 1576}
1577
1578/* sfc. */
1579void
267b3b8e 1580OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1581{
1582 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1583 if ((PSR_F) == 0)
1584 SET_GPR (OP[0], 1);
1585 else
1586 SET_GPR (OP[0], 0);
267b3b8e 1587 trace_output_void (sd);
fee8ec00
SR		 1588}
1589
1590
1591/* slo. */
1592void
267b3b8e 1593OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1594{
1595 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1596 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1597 SET_GPR (OP[0], 1);
1598 else
1599 SET_GPR (OP[0], 0);
267b3b8e 1600 trace_output_void (sd);
fee8ec00
SR		 1601}
1602
1603/* shs. */
1604void
267b3b8e 1605OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1606{
1607 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1608 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1609 SET_GPR (OP[0], 1);
1610 else
1611 SET_GPR (OP[0], 0);
267b3b8e 1612 trace_output_void (sd);
fee8ec00
SR		 1613}
1614
1615/* slt. */
1616void
267b3b8e 1617OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1618{
1619 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1620 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1621 SET_GPR (OP[0], 1);
1622 else
1623 SET_GPR (OP[0], 0);
267b3b8e 1624 trace_output_void (sd);
fee8ec00
SR		 1625}
1626
1627/* sge. */
1628void
267b3b8e 1629OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1630{
1631 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1632 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1633 SET_GPR (OP[0], 1);
1634 else
1635 SET_GPR (OP[0], 0);
267b3b8e 1636 trace_output_void (sd);
fee8ec00
SR		 1637}
1638
1639/* cbitb. */
1640void
267b3b8e 1641OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1642{
1643 uint8 a = OP[0] & 0xff;
1644 uint32 addr = OP[1], tmp;
1645 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1646 tmp = RB (addr);
1647 SET_PSR_F (tmp & (1 << a));
1648 tmp = tmp & ~(1 << a);
1649 SB (addr, tmp);
267b3b8e 1650 trace_output_32 (sd, tmp);
fee8ec00
SR		 1651}
1652
1653/* cbitb. */
1654void
267b3b8e 1655OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1656{
1657 uint8 a = OP[0] & 0xff;
1658 uint32 addr = OP[1], tmp;
1659 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1660 tmp = RB (addr);
1661 SET_PSR_F (tmp & (1 << a));
1662 tmp = tmp & ~(1 << a);
1663 SB (addr, tmp);
267b3b8e 1664 trace_output_32 (sd, tmp);
fee8ec00
SR		 1665}
1666
1667/* cbitb. */
1668void
267b3b8e 1669OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1670{
1671 uint8 a = (OP[0]) & 0xff;
1672 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1673 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1674 tmp = RB (addr);
1675 SET_PSR_F (tmp & (1 << a));
1676 tmp = tmp & ~(1 << a);
1677 SB (addr, tmp);
267b3b8e 1678 trace_output_32 (sd, addr);
fee8ec00
SR		 1679}
1680
1681/* cbitb. */
1682void
267b3b8e 1683OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1684{
1685 uint8 a = (OP[0]) & 0xff;
1686 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1687 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1688 tmp = RB (addr);
1689 SET_PSR_F (tmp & (1 << a));
1690 tmp = tmp & ~(1 << a);
1691 SB (addr, tmp);
267b3b8e 1692 trace_output_32 (sd, addr);
fee8ec00
SR		 1693}
1694
1695/* cbitb. */
1696void
267b3b8e 1697OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1698{
1699 uint8 a = (OP[0]) & 0xff;
1700 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1701 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1702 tmp = RB (addr);
1703 SET_PSR_F (tmp & (1 << a));
1704 tmp = tmp & ~(1 << a);
1705 SB (addr, tmp);
267b3b8e 1706 trace_output_32 (sd, addr);
fee8ec00
SR		 1707}
1708
1709/* cbitb. */
1710void
267b3b8e 1711OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1712{
1713 uint8 a = (OP[0]) & 0xff;
1714 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1715 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1716 tmp = RB (addr);
1717 SET_PSR_F (tmp & (1 << a));
1718 tmp = tmp & ~(1 << a);
1719 SB (addr, tmp);
267b3b8e 1720 trace_output_32 (sd, addr);
fee8ec00
SR		 1721}
1722
1723/* cbitb. */
1724void
267b3b8e 1725OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1726{
1727 uint8 a = (OP[0]) & 0xff;
1728 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1729 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1730 tmp = RB (addr);
1731 SET_PSR_F (tmp & (1 << a));
1732 tmp = tmp & ~(1 << a);
1733 SB (addr, tmp);
267b3b8e 1734 trace_output_32 (sd, addr);
fee8ec00
SR		 1735
1736}
1737
1738/* cbitb. */
1739void
267b3b8e 1740OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1741{
1742 uint8 a = (OP[0]) & 0xff;
1743 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1744 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1745 tmp = RB (addr);
1746 SET_PSR_F (tmp & (1 << a));
1747 tmp = tmp & ~(1 << a);
1748 SB (addr, tmp);
267b3b8e 1749 trace_output_32 (sd, addr);
fee8ec00
SR		 1750}
1751
1752/* cbitb. */
1753void
267b3b8e 1754OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1755{
1756 uint8 a = (OP[0]) & 0xff;
1757 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1758 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1759 tmp = RB (addr);
1760 SET_PSR_F (tmp & (1 << a));
1761 tmp = tmp & ~(1 << a);
1762 SB (addr, tmp);
267b3b8e 1763 trace_output_32 (sd, addr);
fee8ec00
SR		 1764}
1765
1766
1767/* cbitw. */
1768void
267b3b8e 1769OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1770{
1771 uint16 a = OP[0];
1772 uint32 addr = OP[1], tmp;
1773 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1774 tmp = RW (addr);
1775 SET_PSR_F (tmp & (1 << a));
1776 tmp = tmp & ~(1 << a);
1777 SW (addr, tmp);
267b3b8e 1778 trace_output_32 (sd, tmp);
fee8ec00
SR		 1779}
1780
1781/* cbitw. */
1782void
267b3b8e 1783OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1784{
1785 uint16 a = OP[0];
1786 uint32 addr = OP[1], tmp;
1787 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1788 tmp = RW (addr);
1789 SET_PSR_F (tmp & (1 << a));
1790 tmp = tmp & ~(1 << a);
1791 SW (addr, tmp);
267b3b8e 1792 trace_output_32 (sd, tmp);
fee8ec00
SR		 1793}
1794
1795/* cbitw. */
1796void
267b3b8e 1797OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1798{
1799 uint32 addr;
1800 uint16 a = (OP[0]), tmp;
1801 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1802
1803 if (OP[1] == 0)
1804 addr = (GPR32 (12)) + OP[2];
1805 else
1806 addr = (GPR32 (13)) + OP[2];
1807
1808 tmp = RW (addr);
1809 SET_PSR_F (tmp & (1 << a));
1810 tmp = tmp & ~(1 << a);
1811 SW (addr, tmp);
267b3b8e 1812 trace_output_32 (sd, addr);
fee8ec00
SR		 1813
1814}
1815
1816/* cbitw. */
1817void
267b3b8e 1818OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1819{
1820 uint16 a = (OP[0]);
1821 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1822 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1823 tmp = RW (addr);
1824 SET_PSR_F (tmp & (1 << a));
1825 tmp = tmp & ~(1 << a);
1826 SW (addr, tmp);
267b3b8e 1827 trace_output_32 (sd, addr);
fee8ec00
SR		 1828}
1829
1830/* cbitw. */
1831void
267b3b8e 1832OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1833{
1834 uint16 a = (OP[0]);
1835 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1836 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1837 tmp = RW (addr);
1838 SET_PSR_F (tmp & (1 << a));
1839 tmp = tmp & ~(1 << a);
1840 SW (addr, tmp);
267b3b8e 1841 trace_output_32 (sd, addr);
fee8ec00
SR		 1842}
1843
1844
1845/* cbitw. */
1846void
267b3b8e 1847OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1848{
1849 uint16 a = (OP[0]);
1850 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1851 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1852 tmp = RW (addr);
1853 SET_PSR_F (tmp & (1 << a));
1854 tmp = tmp & ~(1 << a);
1855 SW (addr, tmp);
267b3b8e 1856 trace_output_32 (sd, addr);
fee8ec00
SR		 1857}
1858
1859/* cbitw. */
1860void
267b3b8e 1861OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1862{
1863 uint16 a = (OP[0]);
1864 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1865 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1866 tmp = RW (addr);
1867 SET_PSR_F (tmp & (1 << a));
1868 tmp = tmp & ~(1 << a);
1869 SW (addr, tmp);
267b3b8e 1870 trace_output_32 (sd, addr);
fee8ec00
SR		 1871}
1872
1873
1874/* cbitw. */
1875void
267b3b8e 1876OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1877{
1878 uint16 a = (OP[0]);
1879 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1880 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1881 tmp = RW (addr);
1882 SET_PSR_F (tmp & (1 << a));
1883 tmp = tmp & ~(1 << a);
1884 SW (addr, tmp);
267b3b8e 1885 trace_output_32 (sd, addr);
fee8ec00
SR		 1886}
1887
1888/* cbitw. */
1889void
267b3b8e 1890OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1891{
1892 uint16 a = (OP[0]);
1893 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1894 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1895 tmp = RW (addr);
1896 SET_PSR_F (tmp & (1 << a));
1897 tmp = tmp & ~(1 << a);
1898 SW (addr, tmp);
267b3b8e 1899 trace_output_32 (sd, addr);
fee8ec00
SR		 1900}
1901
1902/* sbitb. */
1903void
267b3b8e 1904OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1905{
1906 uint8 a = OP[0] & 0xff;
1907 uint32 addr = OP[1], tmp;
1908 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1909 tmp = RB (addr);
1910 SET_PSR_F (tmp & (1 << a));
1911 tmp = tmp | (1 << a);
1912 SB (addr, tmp);
267b3b8e 1913 trace_output_32 (sd, tmp);
fee8ec00
SR		 1914}
1915
1916/* sbitb. */
1917void
267b3b8e 1918OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1919{
1920 uint8 a = OP[0] & 0xff;
1921 uint32 addr = OP[1], tmp;
1922 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1923 tmp = RB (addr);
1924 SET_PSR_F (tmp & (1 << a));
1925 tmp = tmp | (1 << a);
1926 SB (addr, tmp);
267b3b8e 1927 trace_output_32 (sd, tmp);
fee8ec00
SR		 1928}
1929
1930/* sbitb. */
1931void
267b3b8e 1932OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1933{
1934 uint8 a = OP[0] & 0xff;
1935 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1936 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1937 tmp = RB (addr);
1938 SET_PSR_F (tmp & (1 << a));
1939 tmp = tmp | (1 << a);
1940 SB (addr, tmp);
267b3b8e 1941 trace_output_32 (sd, tmp);
fee8ec00
SR		 1942}
1943
1944/* sbitb. */
1945void
267b3b8e 1946OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1947{
1948 uint8 a = OP[0] & 0xff;
1949 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1950 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1951 tmp = RB (addr);
1952 SET_PSR_F (tmp & (1 << a));
1953 tmp = tmp | (1 << a);
1954 SB (addr, tmp);
267b3b8e 1955 trace_output_32 (sd, tmp);
fee8ec00
SR		 1956}
1957
1958/* sbitb. */
1959void
267b3b8e 1960OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1961{
1962 uint8 a = OP[0] & 0xff;
1963 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1964 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1965 tmp = RB (addr);
1966 SET_PSR_F (tmp & (1 << a));
1967 tmp = tmp | (1 << a);
1968 SB (addr, tmp);
267b3b8e 1969 trace_output_32 (sd, tmp);
fee8ec00
SR		 1970}
1971
1972
1973/* sbitb. */
1974void
267b3b8e 1975OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1976{
1977 uint8 a = OP[0] & 0xff;
1978 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1979 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1980 tmp = RB (addr);
1981 SET_PSR_F (tmp & (1 << a));
1982 tmp = tmp | (1 << a);
1983 SB (addr, tmp);
267b3b8e 1984 trace_output_32 (sd, tmp);
fee8ec00
SR		 1985}
1986
1987/* sbitb. */
1988void
267b3b8e 1989OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1990{
1991 uint8 a = OP[0] & 0xff;
1992 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1993 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1994 tmp = RB (addr);
1995 SET_PSR_F (tmp & (1 << a));
1996 tmp = tmp | (1 << a);
1997 SB (addr, tmp);
267b3b8e 1998 trace_output_32 (sd, tmp);
fee8ec00
SR		 1999}
2000
2001
2002/* sbitb. */
2003void
267b3b8e 2004OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2005{
2006 uint8 a = OP[0] & 0xff;
2007 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2008 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2009 tmp = RB (addr);
2010 SET_PSR_F (tmp & (1 << a));
2011 tmp = tmp | (1 << a);
2012 SB (addr, tmp);
267b3b8e 2013 trace_output_32 (sd, tmp);
fee8ec00
SR		 2014}
2015
2016
2017/* sbitb. */
2018void
267b3b8e 2019OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2020{
2021 uint8 a = OP[0] & 0xff;
2022 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2023 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2024 tmp = RB (addr);
2025 SET_PSR_F (tmp & (1 << a));
2026 tmp = tmp | (1 << a);
2027 SB (addr, tmp);
267b3b8e 2028 trace_output_32 (sd, tmp);
fee8ec00
SR		 2029}
2030
2031
2032/* sbitw. */
2033void
267b3b8e 2034OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2035{
2036 uint16 a = OP[0];
2037 uint32 addr = OP[1], tmp;
2038 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2039 tmp = RW (addr);
2040 SET_PSR_F (tmp & (1 << a));
2041 tmp = tmp | (1 << a);
2042 SW (addr, tmp);
267b3b8e 2043 trace_output_32 (sd, tmp);
fee8ec00
SR		 2044}
2045
2046/* sbitw. */
2047void
267b3b8e 2048OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2049{
2050 uint16 a = OP[0];
2051 uint32 addr = OP[1], tmp;
2052 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2053 tmp = RW (addr);
2054 SET_PSR_F (tmp & (1 << a));
2055 tmp = tmp | (1 << a);
2056 SW (addr, tmp);
267b3b8e 2057 trace_output_32 (sd, tmp);
fee8ec00
SR		 2058}
2059
2060/* sbitw. */
2061void
267b3b8e 2062OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2063{
2064 uint32 addr;
2065 uint16 a = (OP[0]), tmp;
2066 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2067
2068 if (OP[1] == 0)
2069 addr = (GPR32 (12)) + OP[2];
2070 else
2071 addr = (GPR32 (13)) + OP[2];
2072
2073 tmp = RW (addr);
2074 SET_PSR_F (tmp & (1 << a));
2075 tmp = tmp | (1 << a);
2076 SW (addr, tmp);
267b3b8e 2077 trace_output_32 (sd, addr);
fee8ec00
SR		 2078}
2079
2080/* sbitw. */
2081void
267b3b8e 2082OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2083{
2084 uint16 a = (OP[0]);
2085 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2086 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2087 tmp = RW (addr);
2088 SET_PSR_F (tmp & (1 << a));
2089 tmp = tmp | (1 << a);
2090 SW (addr, tmp);
267b3b8e 2091 trace_output_32 (sd, addr);
fee8ec00
SR		 2092}
2093
2094/* sbitw. */
2095void
267b3b8e 2096OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2097{
2098 uint16 a = (OP[0]);
2099 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2100 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2101 tmp = RW (addr);
2102 SET_PSR_F (tmp & (1 << a));
2103 tmp = tmp | (1 << a);
2104 SW (addr, tmp);
267b3b8e 2105 trace_output_32 (sd, addr);
fee8ec00
SR		 2106}
2107
2108/* sbitw. */
2109void
267b3b8e 2110OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2111{
2112 uint16 a = (OP[0]);
2113 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2114 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2115 tmp = RW (addr);
2116 SET_PSR_F (tmp & (1 << a));
2117 tmp = tmp | (1 << a);
2118 SW (addr, tmp);
267b3b8e 2119 trace_output_32 (sd, addr);
fee8ec00
SR		 2120}
2121
2122/* sbitw. */
2123void
267b3b8e 2124OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2125{
2126 uint16 a = (OP[0]);
2127 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2128 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2129 tmp = RW (addr);
2130 SET_PSR_F (tmp & (1 << a));
2131 tmp = tmp | (1 << a);
2132 SW (addr, tmp);
267b3b8e 2133 trace_output_32 (sd, addr);
fee8ec00
SR		 2134}
2135
2136/* sbitw. */
2137void
267b3b8e 2138OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2139{
2140 uint16 a = (OP[0]);
2141 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2142 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2143 tmp = RW (addr);
2144 SET_PSR_F (tmp & (1 << a));
2145 tmp = tmp | (1 << a);
2146 SW (addr, tmp);
267b3b8e 2147 trace_output_32 (sd, addr);
fee8ec00
SR		 2148}
2149
2150/* sbitw. */
2151void
267b3b8e 2152OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2153{
2154 uint16 a = (OP[0]);
2155 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2156 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2157 tmp = RW (addr);
2158 SET_PSR_F (tmp & (1 << a));
2159 tmp = tmp | (1 << a);
2160 SW (addr, tmp);
267b3b8e 2161 trace_output_32 (sd, addr);
fee8ec00
SR		 2162}
2163
2164
2165/* tbitb. */
2166void
267b3b8e 2167OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2168{
2169 uint8 a = OP[0] & 0xff;
2170 uint32 addr = OP[1], tmp;
2171 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2172 tmp = RB (addr);
2173 SET_PSR_F (tmp & (1 << a));
267b3b8e 2174 trace_output_32 (sd, tmp);
fee8ec00
SR		 2175}
2176
2177/* tbitb. */
2178void
267b3b8e 2179OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2180{
2181 uint8 a = OP[0] & 0xff;
2182 uint32 addr = OP[1], tmp;
2183 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2184 tmp = RB (addr);
2185 SET_PSR_F (tmp & (1 << a));
267b3b8e 2186 trace_output_32 (sd, tmp);
fee8ec00
SR		 2187}
2188
2189/* tbitb. */
2190void
267b3b8e 2191OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2192{
2193 uint8 a = (OP[0]) & 0xff;
2194 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2195 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2196 tmp = RB (addr);
2197 SET_PSR_F (tmp & (1 << a));
267b3b8e 2198 trace_output_32 (sd, addr);
fee8ec00
SR		 2199}
2200
2201/* tbitb. */
2202void
267b3b8e 2203OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2204{
2205 uint8 a = (OP[0]) & 0xff;
2206 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2207 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2208 tmp = RB (addr);
2209 SET_PSR_F (tmp & (1 << a));
267b3b8e 2210 trace_output_32 (sd, addr);
fee8ec00
SR		 2211}
2212
2213/* tbitb. */
2214void
267b3b8e 2215OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2216{
2217 uint8 a = (OP[0]) & 0xff;
2218 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2219 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2220 tmp = RB (addr);
2221 SET_PSR_F (tmp & (1 << a));
267b3b8e 2222 trace_output_32 (sd, addr);
fee8ec00
SR		 2223}
2224
2225/* tbitb. */
2226void
267b3b8e 2227OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2228{
2229 uint8 a = (OP[0]) & 0xff;
2230 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2231 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2232 tmp = RB (addr);
2233 SET_PSR_F (tmp & (1 << a));
267b3b8e 2234 trace_output_32 (sd, addr);
fee8ec00
SR		 2235}
2236
2237/* tbitb. */
2238void
267b3b8e 2239OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2240{
2241 uint8 a = (OP[0]) & 0xff;
2242 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2243 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2244 tmp = RB (addr);
2245 SET_PSR_F (tmp & (1 << a));
267b3b8e 2246 trace_output_32 (sd, addr);
fee8ec00
SR		 2247}
2248
2249/* tbitb. */
2250void
267b3b8e 2251OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2252{
2253 uint8 a = (OP[0]) & 0xff;
2254 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2255 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2256 tmp = RB (addr);
2257 SET_PSR_F (tmp & (1 << a));
267b3b8e 2258 trace_output_32 (sd, addr);
fee8ec00
SR		 2259}
2260
2261/* tbitb. */
2262void
267b3b8e 2263OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2264{
2265 uint8 a = (OP[0]) & 0xff;
2266 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2267 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2268 tmp = RB (addr);
2269 SET_PSR_F (tmp & (1 << a));
267b3b8e 2270 trace_output_32 (sd, addr);
fee8ec00
SR		 2271}
2272
2273
2274/* tbitw. */
2275void
267b3b8e 2276OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2277{
2278 uint16 a = OP[0];
2279 uint32 addr = OP[1], tmp;
2280 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2281 tmp = RW (addr);
2282 SET_PSR_F (tmp & (1 << a));
267b3b8e 2283 trace_output_32 (sd, tmp);
fee8ec00
SR		 2284}
2285
2286/* tbitw. */
2287void
267b3b8e 2288OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2289{
2290 uint16 a = OP[0];
2291 uint32 addr = OP[1], tmp;
2292 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2293 tmp = RW (addr);
2294 SET_PSR_F (tmp & (1 << a));
267b3b8e 2295 trace_output_32 (sd, tmp);
fee8ec00
SR		 2296}
2297
2298
2299/* tbitw. */
2300void
267b3b8e 2301OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2302{
2303 uint32 addr;
2304 uint16 a = (OP[0]), tmp;
2305 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2306
2307 if (OP[1] == 0)
2308 addr = (GPR32 (12)) + OP[2];
2309 else
2310 addr = (GPR32 (13)) + OP[2];
2311
2312 tmp = RW (addr);
2313 SET_PSR_F (tmp & (1 << a));
267b3b8e 2314 trace_output_32 (sd, addr);
fee8ec00
SR		 2315}
2316
2317/* tbitw. */
2318void
267b3b8e 2319OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2320{
2321 uint16 a = (OP[0]);
2322 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2323 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2324 tmp = RW (addr);
2325 SET_PSR_F (tmp & (1 << a));
267b3b8e 2326 trace_output_32 (sd, addr);
fee8ec00
SR		 2327}
2328
2329/* tbitw. */
2330void
267b3b8e 2331OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2332{
2333 uint16 a = (OP[0]);
2334 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2335 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2336 tmp = RW (addr);
2337 SET_PSR_F (tmp & (1 << a));
267b3b8e 2338 trace_output_32 (sd, addr);
fee8ec00
SR		 2339}
2340
2341/* tbitw. */
2342void
267b3b8e 2343OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2344{
2345 uint16 a = (OP[0]);
2346 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2347 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2348 tmp = RW (addr);
2349 SET_PSR_F (tmp & (1 << a));
267b3b8e 2350 trace_output_32 (sd, addr);
fee8ec00
SR		 2351}
2352
2353/* tbitw. */
2354void
267b3b8e 2355OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2356{
2357 uint16 a = (OP[0]);
2358 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2359 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2360 tmp = RW (addr);
2361 SET_PSR_F (tmp & (1 << a));
267b3b8e 2362 trace_output_32 (sd, addr);
fee8ec00
SR		 2363}
2364
2365/* tbitw. */
2366void
267b3b8e 2367OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2368{
2369 uint16 a = (OP[0]);
2370 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2371 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2372 tmp = RW (addr);
2373 SET_PSR_F (tmp & (1 << a));
267b3b8e 2374 trace_output_32 (sd, addr);
fee8ec00
SR		 2375}
2376
2377
2378/* tbitw. */
2379void
267b3b8e 2380OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2381{
2382 uint16 a = (OP[0]);
2383 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2384 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2385 tmp = RW (addr);
2386 SET_PSR_F (tmp & (1 << a));
267b3b8e 2387 trace_output_32 (sd, addr);
fee8ec00
SR		 2388}
2389
2390
2391/* tbit. */
2392void
267b3b8e 2393OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2394{
2395 uint16 a = OP[0];
537e4bb9 2396 uint16 b = (GPR (OP[1]));
fee8ec00 2397 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
537e4bb9 2398 SET_PSR_F (b & (1 << a));
267b3b8e 2399 trace_output_16 (sd, b);
fee8ec00
SR		 2400}
2401
2402/* tbit. */
2403void
267b3b8e 2404OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2405{
2406 uint16 a = GPR (OP[0]);
537e4bb9 2407 uint16 b = (GPR (OP[1]));
fee8ec00 2408 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
537e4bb9 2409 SET_PSR_F (b & (1 << a));
267b3b8e 2410 trace_output_16 (sd, b);
fee8ec00
SR		 2411}
2412
2413
2414/* cmpb. */
2415void
267b3b8e 2416OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2417{
2418 uint8 a = (OP[0]) & 0xFF;
2419 uint8 b = (GPR (OP[1])) & 0xFF;
2420 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2421 SET_PSR_Z (a == b);
2422 SET_PSR_N ((int8)a > (int8)b);
2423 SET_PSR_L (a > b);
267b3b8e 2424 trace_output_flag (sd);
fee8ec00
SR		 2425}
2426
2427/* cmpb. */
2428void
267b3b8e 2429OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2430{
2431 uint8 a = (OP[0]) & 0xFF;
2432 uint8 b = (GPR (OP[1])) & 0xFF;
2433 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2434 SET_PSR_Z (a == b);
2435 SET_PSR_N ((int8)a > (int8)b);
2436 SET_PSR_L (a > b);
267b3b8e 2437 trace_output_flag (sd);
fee8ec00
SR		 2438}
2439
2440/* cmpb. */
2441void
267b3b8e 2442OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2443{
2444 uint8 a = (GPR (OP[0])) & 0xFF;
2445 uint8 b = (GPR (OP[1])) & 0xFF;
2446 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2447 SET_PSR_Z (a == b);
2448 SET_PSR_N ((int8)a > (int8)b);
2449 SET_PSR_L (a > b);
267b3b8e 2450 trace_output_flag (sd);
fee8ec00
SR		 2451}
2452
2453/* cmpw. */
2454void
267b3b8e 2455OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2456{
2457 uint16 a = (OP[0]);
2458 uint16 b = GPR (OP[1]);
2459 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2460 SET_PSR_Z (a == b);
2461 SET_PSR_N ((int16)a > (int16)b);
2462 SET_PSR_L (a > b);
267b3b8e 2463 trace_output_flag (sd);
fee8ec00
SR		 2464}
2465
2466/* cmpw. */
2467void
267b3b8e 2468OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2469{
2470 uint16 a = (OP[0]);
2471 uint16 b = GPR (OP[1]);
2472 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2473 SET_PSR_Z (a == b);
2474 SET_PSR_N ((int16)a > (int16)b);
2475 SET_PSR_L (a > b);
267b3b8e 2476 trace_output_flag (sd);
fee8ec00
SR		 2477}
2478
2479/* cmpw. */
2480void
267b3b8e 2481OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2482{
2483 uint16 a = GPR (OP[0]) ;
2484 uint16 b = GPR (OP[1]) ;
2485 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2486 SET_PSR_Z (a == b);
2487 SET_PSR_N ((int16)a > (int16)b);
2488 SET_PSR_L (a > b);
267b3b8e 2489 trace_output_flag (sd);
fee8ec00
SR		 2490}
2491
2492/* cmpd. */
2493void
267b3b8e 2494OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2495{
2496 uint32 a = (OP[0]);
2497 uint32 b = GPR32 (OP[1]);
2498 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2499 SET_PSR_Z (a == b);
2500 SET_PSR_N ((int32)a > (int32)b);
2501 SET_PSR_L (a > b);
267b3b8e 2502 trace_output_flag (sd);
fee8ec00
SR		 2503}
2504
2505/* cmpd. */
2506void
267b3b8e 2507OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2508{
2509 uint32 a = (SEXT16(OP[0]));
2510 uint32 b = GPR32 (OP[1]);
2511 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2512 SET_PSR_Z (a == b);
2513 SET_PSR_N ((int32)a > (int32)b);
2514 SET_PSR_L (a > b);
267b3b8e 2515 trace_output_flag (sd);
fee8ec00
SR		 2516}
2517
2518/* cmpd. */
2519void
267b3b8e 2520OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2521{
2522 uint32 a = GPR32 (OP[0]) ;
2523 uint32 b = GPR32 (OP[1]) ;
2524 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2525 SET_PSR_Z (a == b);
2526 SET_PSR_N ((int32)a > (int32)b);
2527 SET_PSR_L (a > b);
267b3b8e 2528 trace_output_flag (sd);
fee8ec00
SR		 2529}
2530
2531/* cmpd. */
2532void
267b3b8e 2533OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2534{
2535 uint32 a = (OP[0]);
2536 uint32 b = GPR32 (OP[1]);
2537 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2538 SET_PSR_Z (a == b);
2539 SET_PSR_N ((int32)a > (int32)b);
2540 SET_PSR_L (a > b);
267b3b8e 2541 trace_output_flag (sd);
fee8ec00
SR		 2542}
2543
2544
2545/* movb. */
2546void
267b3b8e 2547OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2548{
2549 uint8 tmp = OP[0] & 0xFF;
fee8ec00 2550 uint16 a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2551 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
fee8ec00 2552 SET_GPR (OP[1], (a | tmp));
267b3b8e 2553 trace_output_16 (sd, tmp);
fee8ec00
SR		 2554}
2555
2556/* movb. */
2557void
267b3b8e 2558OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2559{
2560 uint8 tmp = OP[0] & 0xFF;
fee8ec00 2561 uint16 a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2562 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00 2563 SET_GPR (OP[1], (a | tmp));
267b3b8e 2564 trace_output_16 (sd, tmp);
fee8ec00
SR		 2565}
2566
2567/* movb. */
2568void
267b3b8e 2569OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2570{
2571 uint8 tmp = (GPR (OP[0])) & 0xFF;
fee8ec00 2572 uint16 a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2573 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
fee8ec00 2574 SET_GPR (OP[1], (a | tmp));
267b3b8e 2575 trace_output_16 (sd, tmp);
fee8ec00
SR		 2576}
2577
2578/* movw. */
2579void
267b3b8e 2580OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2581{
2582 uint16 tmp = OP[0];
2583 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2584 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 2585 trace_output_16 (sd, tmp);
fee8ec00
SR		 2586}
2587
2588/* movw. */
2589void
267b3b8e 2590OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2591{
2592 int16 tmp = OP[0];
2593 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2594 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 2595 trace_output_16 (sd, tmp);
fee8ec00
SR		 2596}
2597
2598/* movw. */
2599void
267b3b8e 2600OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2601{
2602 uint16 tmp = GPR (OP[0]);
fee8ec00 2603 uint32 a = GPR32 (OP[1]);
5aedb83b 2604 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
fee8ec00
SR		 2605 a = (a & 0xffff0000) | tmp;
2606 SET_GPR32 (OP[1], a);
267b3b8e 2607 trace_output_16 (sd, tmp);
fee8ec00
SR		 2608}
2609
2610/* movxb. */
2611void
267b3b8e 2612OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2613{
2614 uint8 tmp = (GPR (OP[0])) & 0xFF;
2615 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2616 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
267b3b8e 2617 trace_output_16 (sd, tmp);
fee8ec00
SR		 2618}
2619
2620/* movzb. */
2621void
267b3b8e 2622OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2623{
2624 uint8 tmp = (GPR (OP[0])) & 0xFF;
2625 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2626 SET_GPR (OP[1], tmp);
267b3b8e 2627 trace_output_16 (sd, tmp);
fee8ec00
SR		 2628}
2629
2630/* movxw. */
2631void
267b3b8e 2632OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2633{
2634 uint16 tmp = GPR (OP[0]);
2635 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2636 SET_GPR32 (OP[1], SEXT16(tmp));
267b3b8e 2637 trace_output_16 (sd, tmp);
fee8ec00
SR		 2638}
2639
2640/* movzw. */
2641void
267b3b8e 2642OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2643{
2644 uint16 tmp = GPR (OP[0]);
2645 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2646 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
267b3b8e 2647 trace_output_16 (sd, tmp);
fee8ec00
SR		 2648}
2649
2650/* movd. */
2651void
267b3b8e 2652OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2653{
2654 int32 tmp = OP[0];
2655 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2656 SET_GPR32 (OP[1], tmp);
267b3b8e 2657 trace_output_32 (sd, tmp);
fee8ec00
SR		 2658}
2659
2660/* movd. */
2661void
267b3b8e 2662OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2663{
2664 int32 tmp = SEXT16(OP[0]);
2665 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2666 SET_GPR32 (OP[1], tmp);
267b3b8e 2667 trace_output_32 (sd, tmp);
fee8ec00
SR		 2668}
2669
2670/* movd. */
2671void
267b3b8e 2672OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2673{
2674 uint32 tmp = GPR32 (OP[0]);
2675 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2676 SET_GPR32 (OP[1], tmp);
267b3b8e 2677 trace_output_32 (sd, tmp);
fee8ec00
SR		 2678}
2679
2680/* movd. */
2681void
267b3b8e 2682OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2683{
2684 uint32 tmp = OP[0];
2685 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2686 SET_GPR32 (OP[1], tmp);
267b3b8e 2687 trace_output_32 (sd, tmp);
fee8ec00
SR		 2688}
2689
2690/* movd. */
2691void
267b3b8e 2692OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2693{
2694 int32 tmp = OP[0];
2695 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2696 SET_GPR32 (OP[1], tmp);
267b3b8e 2697 trace_output_32 (sd, tmp);
fee8ec00
SR		 2698}
2699
2700/* loadm. */
2701void
267b3b8e 2702OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2703{
2704 uint32 addr = GPR (0);
2705 uint16 count = OP[0], reg = 2, tmp;
2706 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2707 if ((addr & 1))
2708 {
267b3b8e 2709 trace_output_void (sd);
0ef7f981 2710 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 2711 }
2712
2713 while (count)
2714 {
2715 tmp = RW (addr);
2716 SET_GPR (reg, tmp);
2717 addr +=2;
2718 --count;
2719 reg++;
2720 if (reg == 6) reg = 8;
2721 };
2722
2723 SET_GPR (0, addr);
267b3b8e 2724 trace_output_void (sd);
fee8ec00
SR		 2725}
2726
2727
2728/* loadmp. */
2729void
267b3b8e 2730OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2731{
2732 uint32 addr = GPR32 (0);
2733 uint16 count = OP[0], reg = 2, tmp;
2734 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2735 if ((addr & 1))
2736 {
267b3b8e 2737 trace_output_void (sd);
0ef7f981 2738 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 2739 }
2740
2741 while (count)
2742 {
2743 tmp = RW (addr);
2744 SET_GPR (reg, tmp);
2745 addr +=2;
2746 --count;
2747 reg++;
2748 if (reg == 6) reg = 8;
2749 };
2750
2751 SET_GPR32 (0, addr);
267b3b8e 2752 trace_output_void (sd);
fee8ec00
SR		 2753}
2754
2755
2756/* loadb. */
2757void
267b3b8e 2758OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2759{
2760 /* loadb ABS20, REG
2761 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2762 * REG = [ADDR]
2763 * NOTE: remap is
2764 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2765 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2766 * by the core to 16M-64k to 16M. */
2767
2768 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2769 uint32 addr = OP[0];
2770 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2771 if (addr > 0xEFFFF) addr |= 0xF00000;
2772 tmp = (RB (addr));
2773 SET_GPR (OP[1], (a | tmp));
267b3b8e 2774 trace_output_16 (sd, tmp);
fee8ec00
SR		 2775}
2776
2777/* loadb. */
2778void
267b3b8e 2779OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2780{
2781 /* loadb ABS24, REG
2782 * ADDR = abs24
2783 * REGR = [ADDR]. */
2784
2785 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2786 uint32 addr = OP[0];
2787 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2788 tmp = (RB (addr));
2789 SET_GPR (OP[1], (a | tmp));
267b3b8e 2790 trace_output_16 (sd, tmp);
fee8ec00
SR		 2791}
2792
2793/* loadb. */
2794void
267b3b8e 2795OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2796{
2797 /* loadb [Rindex]ABS20 REG
2798 * ADDR = Rindex + zext24(disp20)
2799 * REGR = [ADDR]. */
2800
2801 uint32 addr;
2802 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2803 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2804
2805 if (OP[0] == 0)
2806 addr = (GPR32 (12)) + OP[1];
2807 else
2808 addr = (GPR32 (13)) + OP[1];
2809
2810 tmp = (RB (addr));
2811 SET_GPR (OP[2], (a | tmp));
267b3b8e 2812 trace_output_16 (sd, tmp);
fee8ec00
SR		 2813}
2814
2815
2816/* loadb. */
2817void
267b3b8e 2818OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2819{
2820 /* loadb DIPS4(REGP) REG
2821 * ADDR = RPBASE + zext24(DISP4)
2822 * REG = [ADDR]. */
2823 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2824 uint32 addr = (GPR32 (OP[1])) + OP[0];
2825 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2826 tmp = (RB (addr));
2827 SET_GPR (OP[2], (a | tmp));
267b3b8e 2828 trace_output_16 (sd, tmp);
fee8ec00
SR		 2829}
2830
2831/* loadb. */
2832void
267b3b8e 2833OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2834{
2835 /* loadb [Rindex]disp0(RPbasex) REG
2836 * ADDR = Rpbasex + Rindex
2837 * REGR = [ADDR] */
2838
2839 uint32 addr;
2840 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2841 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2842
2843 addr = (GPR32 (OP[2])) + OP[1];
2844
2845 if (OP[0] == 0)
2846 addr = (GPR32 (12)) + addr;
2847 else
2848 addr = (GPR32 (13)) + addr;
2849
2850 tmp = (RB (addr));
2851 SET_GPR (OP[3], (a | tmp));
267b3b8e 2852 trace_output_16 (sd, tmp);
fee8ec00
SR		 2853}
2854
2855/* loadb. */
2856void
267b3b8e 2857OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2858{
2859 /* loadb [Rindex]disp14(RPbasex) REG
2860 * ADDR = Rpbasex + Rindex + zext24(disp14)
2861 * REGR = [ADDR] */
2862
2863 uint32 addr;
2864 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2865
2866 addr = (GPR32 (OP[2])) + OP[1];
2867
2868 if (OP[0] == 0)
2869 addr = (GPR32 (12)) + addr;
2870 else
2871 addr = (GPR32 (13)) + addr;
2872
2873 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2874 tmp = (RB (addr));
2875 SET_GPR (OP[3], (a | tmp));
267b3b8e 2876 trace_output_16 (sd, tmp);
fee8ec00
SR		 2877}
2878
2879
2880/* loadb. */
2881void
267b3b8e 2882OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2883{
2884 /* loadb DISPE20(REG) REG
2885 * zext24(Rbase) + zext24(dispe20)
2886 * REG = [ADDR] */
2887
2888 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2889 uint32 addr = OP[0] + (GPR (OP[1]));
2890 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2891 tmp = (RB (addr));
2892 SET_GPR (OP[2], (a | tmp));
267b3b8e 2893 trace_output_16 (sd, tmp);
fee8ec00
SR		 2894}
2895
2896/* loadb. */
2897void
267b3b8e 2898OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2899{
2900 /* loadb DISP20(REG) REG
2901 * ADDR = zext24(Rbase) + zext24(disp20)
2902 * REG = [ADDR] */
2903
2904 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2905 uint32 addr = OP[0] + (GPR (OP[1]));
2906 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2907 tmp = (RB (addr));
2908 SET_GPR (OP[2], (a | tmp));
267b3b8e 2909 trace_output_16 (sd, tmp);
fee8ec00
SR		 2910}
2911
2912/* loadb. */
2913void
267b3b8e 2914OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2915{
2916 /* loadb disp16(REGP) REG
2917 * ADDR = RPbase + zext24(disp16)
2918 * REGR = [ADDR] */
2919
2920 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2921 uint32 addr = (GPR32 (OP[1])) + OP[0];
2922 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2923 tmp = (RB (addr));
2924 SET_GPR (OP[2], (a | tmp));
267b3b8e 2925 trace_output_16 (sd, tmp);
fee8ec00
SR		 2926}
2927
2928/* loadb. */
2929void
267b3b8e 2930OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2931{
2932 /* loadb disp20(REGP) REG
2933 * ADDR = RPbase + zext24(disp20)
2934 * REGR = [ADDR] */
2935 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2936 uint32 addr = (GPR32 (OP[1])) + OP[0];
2937 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2938 tmp = (RB (addr));
2939 SET_GPR (OP[2], (a | tmp));
267b3b8e 2940 trace_output_16 (sd, tmp);
fee8ec00
SR		 2941}
2942
2943
2944/* loadb. */
2945void
267b3b8e 2946OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2947{
2948 /* loadb -disp20(REGP) REG
2949 * ADDR = RPbase + zext24(-disp20)
2950 * REGR = [ADDR] */
2951 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2952 uint32 addr = (GPR32 (OP[1])) + OP[1];
2953 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2954 tmp = (RB (addr));
2955 SET_GPR (OP[2], (a | tmp));
267b3b8e 2956 trace_output_16 (sd, tmp);
fee8ec00
SR		 2957}
2958
2959/* loadb. */
2960void
267b3b8e 2961OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2962{
2963 /* loadb [Rindex]disp20(RPbasexb) REG
2964 * ADDR = RPbasex + Rindex + zext24(disp20)
2965 * REGR = [ADDR] */
2966
2967 uint32 addr;
2968 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2969 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2970
2971 addr = (GPR32 (OP[2])) + OP[1];
2972
2973 if (OP[0] == 0)
2974 addr = (GPR32 (12)) + addr;
2975 else
2976 addr = (GPR32 (13)) + addr;
2977
2978 tmp = (RB (addr));
2979 SET_GPR (OP[3], (a | tmp));
267b3b8e 2980 trace_output_16 (sd, tmp);
fee8ec00
SR		 2981}
2982
2983
2984/* loadw. */
2985void
267b3b8e 2986OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2987{
2988 /* loadw ABS20, REG
2989 * ADDR = zext24(abs20) | remap
2990 * REGR = [ADDR]
2991 * NOTE: remap is
2992 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2993 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2994 * by the core to 16M-64k to 16M. */
2995
2996 uint16 tmp;
2997 uint32 addr = OP[0];
2998 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
2999 if (addr > 0xEFFFF) addr |= 0xF00000;
3000 tmp = (RW (addr));
3001 SET_GPR (OP[1], tmp);
267b3b8e 3002 trace_output_16 (sd, tmp);
fee8ec00
SR		 3003}
3004
3005
3006/* loadw. */
3007void
267b3b8e 3008OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3009{
3010 /* loadw ABS24, REG
3011 * ADDR = abs24
3012 * REGR = [ADDR] */
3013 uint16 tmp;
3014 uint32 addr = OP[0];
3015 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3016 tmp = (RW (addr));
3017 SET_GPR (OP[1], tmp);
267b3b8e 3018 trace_output_16 (sd, tmp);
fee8ec00
SR		 3019}
3020
3021/* loadw. */
3022void
267b3b8e 3023OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3024{
3025 /* loadw [Rindex]ABS20 REG
3026 * ADDR = Rindex + zext24(disp20)
3027 * REGR = [ADDR] */
3028
3029 uint32 addr;
3030 uint16 tmp;
3031 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3032
3033 if (OP[0] == 0)
3034 addr = (GPR32 (12)) + OP[1];
3035 else
3036 addr = (GPR32 (13)) + OP[1];
3037
3038 tmp = (RW (addr));
3039 SET_GPR (OP[2], tmp);
267b3b8e 3040 trace_output_16 (sd, tmp);
fee8ec00
SR		 3041}
3042
3043
3044/* loadw. */
3045void
267b3b8e 3046OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3047{
3048 /* loadw DIPS4(REGP) REGP
3049 * ADDR = RPBASE + zext24(DISP4)
3050 * REGP = [ADDR]. */
3051 uint16 tmp;
3052 uint32 addr, a;
3053 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3054 addr = (GPR32 (OP[1])) + OP[0];
3055 tmp = (RW (addr));
3056 if (OP[2] > 11)
3057 {
3058 a = (GPR32 (OP[2])) & 0xffff0000;
3059 SET_GPR32 (OP[2], (a | tmp));
3060 }
3061 else
3062 SET_GPR (OP[2], tmp);
3063
267b3b8e 3064 trace_output_16 (sd, tmp);
fee8ec00
SR		 3065}
3066
3067
3068/* loadw. */
3069void
267b3b8e 3070OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3071{
3072 /* loadw [Rindex]disp0(RPbasex) REG
3073 * ADDR = Rpbasex + Rindex
3074 * REGR = [ADDR] */
3075
3076 uint32 addr;
3077 uint16 tmp;
3078 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3079
3080 addr = (GPR32 (OP[2])) + OP[1];
3081
3082 if (OP[0] == 0)
3083 addr = (GPR32 (12)) + addr;
3084 else
3085 addr = (GPR32 (13)) + addr;
3086
3087 tmp = RW (addr);
3088 SET_GPR (OP[3], tmp);
267b3b8e 3089 trace_output_16 (sd, tmp);
fee8ec00
SR		 3090}
3091
3092
3093/* loadw. */
3094void
267b3b8e 3095OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3096{
3097 /* loadw [Rindex]disp14(RPbasex) REG
3098 * ADDR = Rpbasex + Rindex + zext24(disp14)
3099 * REGR = [ADDR] */
3100
3101 uint32 addr;
3102 uint16 tmp;
3103 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3104 addr = (GPR32 (OP[2])) + OP[1];
3105
3106 if (OP[0] == 0)
3107 addr = (GPR32 (12)) + addr;
3108 else
3109 addr = (GPR32 (13)) + addr;
3110
3111 tmp = (RW (addr));
3112 SET_GPR (OP[3], tmp);
267b3b8e 3113 trace_output_16 (sd, tmp);
fee8ec00
SR		 3114}
3115
3116/* loadw. */
3117void
267b3b8e 3118OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3119{
3120 /* loadw dispe20(REG) REGP
3121 * REGP = [DISPE20+[REG]] */
3122
3123 uint16 tmp;
3124 uint32 addr, a;
3125 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3126 addr = OP[0] + (GPR (OP[1]));
3127 tmp = (RW (addr));
3128 if (OP[2] > 11)
3129 {
3130 a = (GPR32 (OP[2])) & 0xffff0000;
3131 SET_GPR32 (OP[2], (a | tmp));
3132 }
3133 else
3134 SET_GPR (OP[2], tmp);
3135
267b3b8e 3136 trace_output_16 (sd, tmp);
fee8ec00
SR		 3137}
3138
3139
3140/* loadw. */
3141void
267b3b8e 3142OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3143{
3144 /* loadw DISP20(REG) REGP
3145 * ADDR = zext24(Rbase) + zext24(disp20)
3146 * REGP = [ADDR] */
3147
3148 uint16 tmp;
3149 uint32 addr, a;
3150 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3151 addr = OP[0] + (GPR (OP[1]));
3152 tmp = (RW (addr));
3153 if (OP[2] > 11)
3154 {
3155 a = (GPR32 (OP[2])) & 0xffff0000;
3156 SET_GPR32 (OP[2], (a | tmp));
3157 }
3158 else
3159 SET_GPR (OP[2], tmp);
3160
267b3b8e 3161 trace_output_16 (sd, tmp);
fee8ec00
SR		 3162}
3163
3164/* loadw. */
3165void
267b3b8e 3166OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3167{
3168 /* loadw disp16(REGP) REGP
3169 * ADDR = RPbase + zext24(disp16)
3170 * REGP = [ADDR] */
3171 uint16 tmp;
3172 uint32 addr, a;
3173 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3174 addr = (GPR32 (OP[1])) + OP[0];
3175 tmp = (RW (addr));
3176 if (OP[2] > 11)
3177 {
3178 a = (GPR32 (OP[2])) & 0xffff0000;
3179 SET_GPR32 (OP[2], (a | tmp));
3180 }
3181 else
3182 SET_GPR (OP[2], tmp);
3183
267b3b8e 3184 trace_output_16 (sd, tmp);
fee8ec00
SR		 3185}
3186
3187/* loadw. */
3188void
267b3b8e 3189OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3190{
3191 /* loadw disp20(REGP) REGP
3192 * ADDR = RPbase + zext24(disp20)
3193 * REGP = [ADDR] */
3194 uint16 tmp;
3195 uint32 addr, a;
3196 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3197 addr = (GPR32 (OP[1])) + OP[0];
3198 tmp = (RW (addr));
3199 if (OP[2] > 11)
3200 {
3201 a = (GPR32 (OP[2])) & 0xffff0000;
3202 SET_GPR32 (OP[2], (a | tmp));
3203 }
3204 else
3205 SET_GPR (OP[2], tmp);
3206
267b3b8e 3207 trace_output_16 (sd, tmp);
fee8ec00
SR		 3208}
3209
3210/* loadw. */
3211void
267b3b8e 3212OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3213{
3214 /* loadw -disp20(REGP) REG
3215 * ADDR = RPbase + zext24(-disp20)
3216 * REGR = [ADDR] */
3217
3218 uint16 tmp;
3219 uint32 addr, a;
3220 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3221 addr = (GPR32 (OP[1])) + OP[0];
3222 tmp = (RB (addr));
3223 if (OP[2] > 11)
3224 {
3225 a = (GPR32 (OP[2])) & 0xffff0000;
3226 SET_GPR32 (OP[2], (a | tmp));
3227 }
3228 else
3229 SET_GPR (OP[2], tmp);
3230
267b3b8e 3231 trace_output_16 (sd, tmp);
fee8ec00
SR		 3232}
3233
3234
3235/* loadw. */
3236void
267b3b8e 3237OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3238{
3239 /* loadw [Rindex]disp20(RPbasexb) REG
3240 * ADDR = RPbasex + Rindex + zext24(disp20)
3241 * REGR = [ADDR] */
3242
3243 uint32 addr;
3244 uint16 tmp;
3245 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3246
3247 if (OP[0] == 0)
3248 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3249 else
3250 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3251
3252 tmp = (RW (addr));
3253 SET_GPR (OP[3], tmp);
267b3b8e 3254 trace_output_16 (sd, tmp);
fee8ec00
SR		 3255}
3256
3257
3258/* loadd. */
3259void
267b3b8e 3260OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3261{
3262 /* loadd ABS20, REGP
3263 * ADDR = zext24(abs20) | remap
3264 * REGP = [ADDR]
3265 * NOTE: remap is
3266 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3267 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3268 * by the core to 16M-64k to 16M. */
3269
3270 uint32 addr, tmp;
3271 addr = OP[0];
3272 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3273 if (addr > 0xEFFFF) addr |= 0xF00000;
3274 tmp = RLW (addr);
3275 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3276 SET_GPR32 (OP[1], tmp);
267b3b8e 3277 trace_output_32 (sd, tmp);
fee8ec00
SR		 3278}
3279
3280/* loadd. */
3281void
267b3b8e 3282OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3283{
3284 /* loadd ABS24, REGP
3285 * ADDR = abs24
3286 * REGP = [ADDR] */
3287
3288 uint32 addr = OP[0];
3289 uint32 tmp;
3290 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3291 tmp = RLW (addr);
3292 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3293 SET_GPR32 (OP[1],tmp);
267b3b8e 3294 trace_output_32 (sd, tmp);
fee8ec00
SR		 3295}
3296
3297
3298/* loadd. */
3299void
267b3b8e 3300OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3301{
3302 /* loadd [Rindex]ABS20 REGP
3303 * ADDR = Rindex + zext24(disp20)
3304 * REGP = [ADDR] */
3305
3306 uint32 addr, tmp;
3307 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3308
3309 if (OP[0] == 0)
3310 addr = (GPR32 (12)) + OP[1];
3311 else
3312 addr = (GPR32 (13)) + OP[1];
3313
3314 tmp = RLW (addr);
3315 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3316 SET_GPR32 (OP[2], tmp);
267b3b8e 3317 trace_output_32 (sd, tmp);
fee8ec00
SR		 3318}
3319
3320
3321/* loadd. */
3322void
267b3b8e 3323OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3324{
3325 /* loadd dips4(regp) REGP
3326 * ADDR = Rpbase + zext24(disp4)
3327 * REGP = [ADDR] */
3328
3329 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
3330 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3331 tmp = RLW (addr);
3332 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3333 SET_GPR32 (OP[2], tmp);
267b3b8e 3334 trace_output_32 (sd, tmp);
fee8ec00
SR		 3335}
3336
3337
3338/* loadd. */
3339void
267b3b8e 3340OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3341{
3342 /* loadd [Rindex]disp0(RPbasex) REGP
3343 * ADDR = Rpbasex + Rindex
3344 * REGP = [ADDR] */
3345
3346 uint32 addr, tmp;
3347 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3348
3349 if (OP[0] == 0)
3350 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3351 else
3352 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3353
3354 tmp = RLW (addr);
3355 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3356 SET_GPR32 (OP[3], tmp);
267b3b8e 3357 trace_output_32 (sd, tmp);
fee8ec00
SR		 3358}
3359
3360
3361/* loadd. */
3362void
267b3b8e 3363OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3364{
3365 /* loadd [Rindex]disp14(RPbasex) REGP
3366 * ADDR = Rpbasex + Rindex + zext24(disp14)
3367 * REGR = [ADDR] */
3368
3369 uint32 addr, tmp;
3370 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3371
3372 if (OP[0] == 0)
3373 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3374 else
3375 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3376
3377 tmp = RLW (addr);
3378 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3379 SET_GPR (OP[3],tmp);
267b3b8e 3380 trace_output_32 (sd, tmp);
fee8ec00
SR		 3381}
3382
3383
3384/* loadd. */
3385void
267b3b8e 3386OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3387{
3388 /* loadd dispe20(REG) REG
3389 * zext24(Rbase) + zext24(dispe20)
3390 * REG = [ADDR] */
3391
3392 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3393 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3394 tmp = RLW (addr);
3395 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3396 SET_GPR32 (OP[2], tmp);
267b3b8e 3397 trace_output_32 (sd, tmp);
fee8ec00
SR		 3398}
3399
3400
3401/* loadd. */
3402void
267b3b8e 3403OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3404{
3405 /* loadd DISP20(REG) REG
3406 * ADDR = zext24(Rbase) + zext24(disp20)
3407 * REG = [ADDR] */
3408
3409 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3410 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3411 tmp = RLW (addr);
3412 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3413 SET_GPR32 (OP[2], tmp);
267b3b8e 3414 trace_output_32 (sd, tmp);
fee8ec00
SR		 3415}
3416
3417/* loadd. */
3418void
267b3b8e 3419OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3420{
3421 /* loadd disp16(REGP) REGP
3422 * ADDR = RPbase + zext24(disp16)
3423 * REGR = [ADDR] */
3424 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3425 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3426 tmp = RLW (addr);
3427 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3428 SET_GPR32 (OP[2], tmp);
267b3b8e 3429 trace_output_32 (sd, tmp);
fee8ec00
SR		 3430}
3431
3432
3433/* loadd. */
3434void
267b3b8e 3435OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3436{
3437 /* loadd disp20(REGP) REGP
3438 * ADDR = RPbase + zext24(disp20)
3439 * REGP = [ADDR] */
3440 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3441 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3442 tmp = RLW (addr);
3443 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3444 SET_GPR32 (OP[2], tmp);
267b3b8e 3445 trace_output_32 (sd, tmp);
fee8ec00
SR		 3446}
3447
3448/* loadd. */
3449void
267b3b8e 3450OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3451{
3452 /* loadd -disp20(REGP) REGP
3453 * ADDR = RPbase + zext24(-disp20)
3454 * REGP = [ADDR] */
3455
3456 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3457 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3458 tmp = RLW (addr);
3459 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3460 SET_GPR32 (OP[2], tmp);
267b3b8e 3461 trace_output_32 (sd, tmp);
fee8ec00
SR		 3462}
3463
3464/* loadd. */
3465void
267b3b8e 3466OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3467{
3468 /* loadd [Rindex]disp20(RPbasexb) REGP
3469 * ADDR = RPbasex + Rindex + zext24(disp20)
3470 * REGP = [ADDR] */
3471
3472 uint32 addr, tmp;
3473 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3474
3475 if (OP[0] == 0)
3476 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3477 else
3478 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3479
3480 tmp = RLW (addr);
3481 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3482 SET_GPR32 (OP[3], tmp);
267b3b8e 3483 trace_output_32 (sd, tmp);
fee8ec00
SR		 3484}
3485
3486
3487/* storb. */
3488void
267b3b8e 3489OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3490{
3491 /* storb REG, ABS20
3492 * ADDR = zext24(abs20) | remap
3493 * [ADDR] = REGR
3494 * NOTE: remap is
3495 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3496 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3497 * by the core to 16M-64k to 16M. */
3498
3499 uint8 a = ((GPR (OP[0])) & 0xff);
3500 uint32 addr = OP[1];
3501 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3502 SB (addr, a);
267b3b8e 3503 trace_output_32 (sd, addr);
fee8ec00
SR		 3504}
3505
3506/* storb. */
3507void
267b3b8e 3508OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3509{
3510 /* storb REG, ABS24
3511 * ADDR = abs24
3512 * [ADDR] = REGR. */
3513
3514 uint8 a = ((GPR (OP[0])) & 0xff);
3515 uint32 addr = OP[1];
3516 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3517 SB (addr, a);
267b3b8e 3518 trace_output_32 (sd, addr);
fee8ec00
SR		 3519}
3520
3521/* storb. */
3522void
267b3b8e 3523OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3524{
3525 /* storb REG, [Rindex]ABS20
3526 * ADDR = Rindex + zext24(disp20)
3527 * [ADDR] = REGR */
3528
3529 uint32 addr;
3530 uint8 a = ((GPR (OP[0])) & 0xff);
3531 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3532
3533 if (OP[1] == 0)
3534 addr = (GPR32 (12)) + OP[2];
3535 else
3536 addr = (GPR32 (13)) + OP[2];
3537
3538 SB (addr, a);
267b3b8e 3539 trace_output_32 (sd, addr);
fee8ec00
SR		 3540}
3541
3542/* storb. */
3543void
267b3b8e 3544OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3545{
3546 /* storb REG, DIPS4(REGP)
3547 * ADDR = RPBASE + zext24(DISP4)
3548 * [ADDR] = REG. */
3549
3550 uint16 a = ((GPR (OP[0])) & 0xff);
5aedb83b 3551 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3552 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 3553 SB (addr, a);
267b3b8e 3554 trace_output_32 (sd, addr);
fee8ec00
SR		 3555}
3556
3557/* storb. */
3558void
267b3b8e 3559OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3560{
3561 /* storb [Rindex]disp0(RPbasex) REG
3562 * ADDR = Rpbasex + Rindex
3563 * [ADDR] = REGR */
3564
3565 uint32 addr;
3566 uint8 a = ((GPR (OP[0])) & 0xff);
3567 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3568
3569 if (OP[1] == 0)
3570 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3571 else
3572 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3573
3574 SB (addr, a);
267b3b8e 3575 trace_output_32 (sd, addr);
fee8ec00
SR		 3576}
3577
3578/* storb. */
3579void
267b3b8e 3580OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3581{
3582 /* storb REG, [Rindex]disp14(RPbasex)
3583 * ADDR = Rpbasex + Rindex + zext24(disp14)
3584 * [ADDR] = REGR */
3585
3586 uint8 a = ((GPR (OP[0])) & 0xff);
fee8ec00 3587 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3588 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 3589 SB (addr, a);
267b3b8e 3590 trace_output_32 (sd, addr);
fee8ec00
SR		 3591}
3592
3593/* storb. */
3594void
267b3b8e 3595OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3596{
3597 /* storb REG, DISPE20(REG)
3598 * zext24(Rbase) + zext24(dispe20)
3599 * [ADDR] = REG */
3600
3601 uint8 a = ((GPR (OP[0])) & 0xff);
fee8ec00 3602 uint32 addr = OP[1] + (GPR (OP[2]));
5aedb83b 3603 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
fee8ec00 3604 SB (addr, a);
267b3b8e 3605 trace_output_32 (sd, addr);
fee8ec00
SR		 3606}
3607
3608/* storb. */
3609void
267b3b8e 3610OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3611{
3612 /* storb REG, DISP20(REG)
3613 * ADDR = zext24(Rbase) + zext24(disp20)
3614 * [ADDR] = REG */
3615
3616 uint8 a = (GPR (OP[0]) & 0xff);
5aedb83b 3617 uint32 addr = OP[1] + (GPR (OP[2]));
fee8ec00 3618 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3619 SB (addr, a);
267b3b8e 3620 trace_output_32 (sd, addr);
fee8ec00
SR		 3621}
3622
3623/* storb. */
3624void
267b3b8e 3625OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3626{
3627 /* storb REG, disp16(REGP)
3628 * ADDR = RPbase + zext24(disp16)
3629 * [ADDR] = REGP */
3630
3631 uint8 a = ((GPR (OP[0])) & 0xff);
fee8ec00 3632 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3633 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3634 SB (addr, a);
267b3b8e 3635 trace_output_32 (sd, addr);
fee8ec00
SR		 3636}
3637
3638/* storb. */
3639void
267b3b8e 3640OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3641{
3642 /* storb REG, disp20(REGP)
3643 * ADDR = RPbase + zext24(disp20)
3644 * [ADDR] = REGP */
3645
3646 uint8 a = ((GPR (OP[0])) & 0xff);
fee8ec00 3647 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3648 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3649 SB (addr, a);
267b3b8e 3650 trace_output_32 (sd, addr);
fee8ec00
SR		 3651}
3652
3653/* storb. */
3654void
267b3b8e 3655OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3656{
3657 /* storb REG, -disp20(REGP)
3658 * ADDR = RPbase + zext24(-disp20)
3659 * [ADDR] = REGP */
3660
3661 uint8 a = (GPR (OP[0]) & 0xff);
fee8ec00 3662 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3663 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3664 SB (addr, a);
267b3b8e 3665 trace_output_32 (sd, addr);
fee8ec00
SR		 3666}
3667
3668/* storb. */
3669void
267b3b8e 3670OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3671{
3672 /* storb REG, [Rindex]disp20(RPbase)
3673 * ADDR = RPbasex + Rindex + zext24(disp20)
3674 * [ADDR] = REGP */
3675
3676 uint8 a = (GPR (OP[0])) & 0xff;
fee8ec00 3677 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3678 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3679 SB (addr, a);
267b3b8e 3680 trace_output_32 (sd, addr);
fee8ec00
SR		 3681}
3682
3683/* STR_IMM instructions. */
3684/* storb . */
3685void
267b3b8e 3686OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3687{
3688 uint8 a = (OP[0]) & 0xff;
fee8ec00 3689 uint32 addr = OP[1];
5aedb83b 3690 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3691 SB (addr, a);
267b3b8e 3692 trace_output_32 (sd, addr);
fee8ec00
SR		 3693}
3694
3695/* storb. */
3696void
267b3b8e 3697OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3698{
3699 uint8 a = (OP[0]) & 0xff;
fee8ec00 3700 uint32 addr = OP[1];
5aedb83b 3701 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3702 SB (addr, a);
267b3b8e 3703 trace_output_32 (sd, addr);
fee8ec00
SR		 3704}
3705
3706/* storb. */
3707void
267b3b8e 3708OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3709{
3710 uint32 addr;
3711 uint8 a = (OP[0]) & 0xff;
3712 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3713
3714 if (OP[1] == 0)
3715 addr = (GPR32 (12)) + OP[2];
3716 else
3717 addr = (GPR32 (13)) + OP[2];
3718
3719 SB (addr, a);
267b3b8e 3720 trace_output_32 (sd, addr);
fee8ec00
SR		 3721}
3722
3723/* storb. */
3724void
267b3b8e 3725OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3726{
3727 uint8 a = (OP[0]) & 0xff;
fee8ec00 3728 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3729 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
fee8ec00 3730 SB (addr, a);
267b3b8e 3731 trace_output_32 (sd, addr);
fee8ec00
SR		 3732}
3733
3734/* storb. */
3735void
267b3b8e 3736OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3737{
3738 uint8 a = (OP[0]) & 0xff;
fee8ec00 3739 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3740 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3741 SB (addr, a);
267b3b8e 3742 trace_output_32 (sd, addr);
fee8ec00
SR		 3743}
3744
3745/* storb. */
3746void
267b3b8e 3747OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3748{
3749 uint8 a = (OP[0]) & 0xff;
fee8ec00 3750 uint32 addr = (GPR (OP[2])) + OP[1];
5aedb83b 3751 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3752 SB (addr, a);
267b3b8e 3753 trace_output_32 (sd, addr);
fee8ec00
SR		 3754}
3755
3756/* storb. */
3757void
267b3b8e 3758OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3759{
3760 uint8 a = (OP[0]) & 0xff;
fee8ec00 3761 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3762 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3763 SB (addr, a);
267b3b8e 3764 trace_output_32 (sd, addr);
fee8ec00
SR		 3765}
3766
3767/* storb. */
3768void
267b3b8e 3769OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3770{
3771 uint8 a = (OP[0]) & 0xff;
fee8ec00 3772 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3773 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3774 SB (addr, a);
267b3b8e 3775 trace_output_32 (sd, addr);
fee8ec00
SR		 3776}
3777
3778/* storb. */
3779void
267b3b8e 3780OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3781{
3782 uint8 a = (OP[0]) & 0xff;
fee8ec00 3783 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3784 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3785 SB (addr, a);
267b3b8e 3786 trace_output_32 (sd, addr);
fee8ec00
SR		 3787}
3788/* endif for STR_IMM. */
3789
3790/* storw . */
3791void
267b3b8e 3792OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3793{
3794 uint16 a = GPR (OP[0]);
fee8ec00 3795 uint32 addr = OP[1];
5aedb83b 3796 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3797 SW (addr, a);
267b3b8e 3798 trace_output_32 (sd, addr);
fee8ec00
SR		 3799}
3800
3801/* storw. */
3802void
267b3b8e 3803OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3804{
3805 uint16 a = GPR (OP[0]);
fee8ec00 3806 uint32 addr = OP[1];
5aedb83b 3807 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3808 SW (addr, a);
267b3b8e 3809 trace_output_32 (sd, addr);
fee8ec00
SR		 3810}
3811
3812/* storw. */
3813void
267b3b8e 3814OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3815{
3816 uint32 addr;
3817 uint16 a = GPR (OP[0]);
3818 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3819
3820 if (OP[1] == 0)
3821 addr = (GPR32 (12)) + OP[2];
3822 else
3823 addr = (GPR32 (13)) + OP[2];
3824
3825 SW (addr, a);
267b3b8e 3826 trace_output_32 (sd, addr);
fee8ec00
SR		 3827}
3828
3829
3830/* storw. */
3831void
267b3b8e 3832OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3833{
3834 uint16 a = (GPR (OP[0]));
5aedb83b 3835 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3836 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 3837 SW (addr, a);
267b3b8e 3838 trace_output_32 (sd, addr);
fee8ec00
SR		 3839}
3840
3841/* storw. */
3842void
267b3b8e 3843OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3844{
3845 uint16 a = GPR (OP[0]);
fee8ec00 3846 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3847 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3848 SW (addr, a);
267b3b8e 3849 trace_output_32 (sd, addr);
fee8ec00
SR		 3850}
3851
3852/* storw. */
3853void
267b3b8e 3854OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3855{
3856 uint16 a = GPR (OP[0]);
fee8ec00 3857 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3858 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 3859 SW (addr, a);
267b3b8e 3860 trace_output_32 (sd, addr);
fee8ec00
SR		 3861}
3862
3863/* storw. */
3864void
267b3b8e 3865OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3866{
3867 uint16 a = (GPR (OP[0]));
5aedb83b 3868 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3869 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3870 SW (addr, a);
267b3b8e 3871 trace_output_32 (sd, addr);
fee8ec00
SR		 3872}
3873
3874/* storw. */
3875void
267b3b8e 3876OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3877{
3878 uint16 a = (GPR (OP[0]));
5aedb83b 3879 uint32 addr = (GPR (OP[2])) + OP[1];
fee8ec00 3880 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3881 SW (addr, a);
267b3b8e 3882 trace_output_32 (sd, addr);
fee8ec00
SR		 3883}
3884
3885/* storw. */
3886void
267b3b8e 3887OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3888{
3889 uint16 a = (GPR (OP[0]));
5aedb83b 3890 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3891 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3892 SW (addr, a);
267b3b8e 3893 trace_output_32 (sd, addr);
fee8ec00
SR		 3894}
3895
3896/* storw. */
3897void
267b3b8e 3898OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3899{
3900 uint16 a = (GPR (OP[0]));
5aedb83b 3901 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3902 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3903 SW (addr, a);
267b3b8e 3904 trace_output_32 (sd, addr);
fee8ec00
SR		 3905}
3906
3907/* storw. */
3908void
267b3b8e 3909OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3910{
3911 uint16 a = (GPR (OP[0]));
5aedb83b 3912 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3913 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3914 SW (addr, a);
267b3b8e 3915 trace_output_32 (sd, addr);
fee8ec00
SR		 3916}
3917
3918/* storw. */
3919void
267b3b8e 3920OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3921{
3922 uint16 a = (GPR (OP[0]));
5aedb83b 3923 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3924 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3925 SW (addr, a);
267b3b8e 3926 trace_output_32 (sd, addr);
fee8ec00
SR		 3927}
3928
3929/* STORE-w IMM instruction *****/
3930/* storw . */
3931void
267b3b8e 3932OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3933{
3934 uint16 a = OP[0];
5aedb83b 3935 uint32 addr = OP[1];
fee8ec00 3936 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3937 SW (addr, a);
267b3b8e 3938 trace_output_32 (sd, addr);
fee8ec00
SR		 3939}
3940
3941/* storw. */
3942void
267b3b8e 3943OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3944{
3945 uint16 a = OP[0];
5aedb83b 3946 uint32 addr = OP[1];
fee8ec00 3947 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3948 SW (addr, a);
267b3b8e 3949 trace_output_32 (sd, addr);
fee8ec00
SR		 3950}
3951
3952/* storw. */
3953void
267b3b8e 3954OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3955{
3956 uint32 addr;
3957 uint16 a = OP[0];
3958 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3959
3960 if (OP[1] == 0)
3961 addr = (GPR32 (12)) + OP[2];
3962 else
3963 addr = (GPR32 (13)) + OP[2];
3964
3965 SW (addr, a);
267b3b8e 3966 trace_output_32 (sd, addr);
fee8ec00
SR		 3967}
3968
3969/* storw. */
3970void
267b3b8e 3971OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3972{
3973 uint16 a = OP[0];
5aedb83b 3974 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3975 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
fee8ec00 3976 SW (addr, a);
267b3b8e 3977 trace_output_32 (sd, addr);
fee8ec00
SR		 3978}
3979
3980/* storw. */
3981void
267b3b8e 3982OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3983{
3984 uint16 a = OP[0];
5aedb83b 3985 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3986 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3987 SW (addr, a);
267b3b8e 3988 trace_output_32 (sd, addr);
fee8ec00
SR		 3989}
3990
3991/* storw. */
3992void
267b3b8e 3993OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3994{
3995 uint16 a = OP[0];
5aedb83b 3996 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3997 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3998 SW (addr, a);
267b3b8e 3999 trace_output_32 (sd, addr);
fee8ec00
SR		 4000}
4001
4002/* storw. */
4003void
267b3b8e 4004OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4005{
4006 uint16 a = OP[0];
5aedb83b 4007 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4008 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 4009 SW (addr, a);
267b3b8e 4010 trace_output_32 (sd, addr);
fee8ec00
SR		 4011}
4012
4013
4014/* storw. */
4015void
267b3b8e 4016OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4017{
4018 uint16 a = OP[0];
5aedb83b 4019 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4020 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 4021 SW (addr, a);
267b3b8e 4022 trace_output_32 (sd, addr);
fee8ec00
SR		 4023}
4024
4025/* storw. */
4026void
267b3b8e 4027OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4028{
4029 uint16 a = OP[0];
5aedb83b 4030 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4031 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 4032 SW (addr, a);
267b3b8e 4033 trace_output_32 (sd, addr);
fee8ec00
SR		 4034}
4035
4036
4037/* stord. */
4038void
267b3b8e 4039OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4040{
4041 uint32 a = GPR32 (OP[0]);
5aedb83b 4042 uint32 addr = OP[1];
fee8ec00 4043 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 4044 SLW (addr, a);
267b3b8e 4045 trace_output_32 (sd, addr);
fee8ec00
SR		 4046}
4047
4048/* stord. */
4049void
267b3b8e 4050OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4051{
4052 uint32 a = GPR32 (OP[0]);
5aedb83b 4053 uint32 addr = OP[1];
fee8ec00 4054 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 4055 SLW (addr, a);
267b3b8e 4056 trace_output_32 (sd, addr);
fee8ec00
SR		 4057}
4058
4059/* stord. */
4060void
267b3b8e 4061OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4062{
4063 uint32 addr, a = GPR32 (OP[0]);
4064 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4065
4066 if (OP[1] == 0)
4067 addr = (GPR32 (12)) + OP[2];
4068 else
4069 addr = (GPR32 (13)) + OP[2];
4070
4071 SLW (addr, a);
267b3b8e 4072 trace_output_32 (sd, addr);
fee8ec00
SR		 4073}
4074
4075/* stord. */
4076void
267b3b8e 4077OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4078{
4079 uint32 a = GPR32 (OP[0]);
5aedb83b 4080 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4081 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 4082 SLW (addr, a);
267b3b8e 4083 trace_output_32 (sd, addr);
fee8ec00
SR		 4084}
4085
4086/* stord. */
4087void
267b3b8e 4088OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4089{
4090 uint32 a = GPR32 (OP[0]);
5aedb83b 4091 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4092 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 4093 SLW (addr, a);
267b3b8e 4094 trace_output_32 (sd, addr);
fee8ec00
SR		 4095}
4096
4097/* stord. */
4098void
267b3b8e 4099OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4100{
4101 uint32 a = GPR32 (OP[0]);
5aedb83b 4102 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4103 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 4104 SLW (addr, a);
267b3b8e 4105 trace_output_32 (sd, addr);
fee8ec00
SR		 4106}
4107
4108/* stord. */
4109void
267b3b8e 4110OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4111{
4112 uint32 a = GPR32 (OP[0]);
5aedb83b 4113 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4114 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
fee8ec00 4115 SLW (addr, a);
267b3b8e 4116 trace_output_32 (sd, addr);
fee8ec00
SR		 4117}
4118
4119/* stord. */
4120void
267b3b8e 4121OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4122{
4123 uint32 a = GPR32 (OP[0]);
5aedb83b 4124 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4125 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 4126 SLW (addr, a);
267b3b8e 4127 trace_output_32 (sd, addr);
fee8ec00
SR		 4128}
4129
4130/* stord. */
4131void
267b3b8e 4132OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4133{
4134 uint32 a = GPR32 (OP[0]);
5aedb83b 4135 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4136 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 4137 SLW (addr, a);
267b3b8e 4138 trace_output_32 (sd, addr);
fee8ec00
SR		 4139}
4140
4141/* stord. */
4142void
267b3b8e 4143OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4144{
4145 uint32 a = GPR32 (OP[0]);
5aedb83b 4146 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4147 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 4148 SLW (addr, a);
267b3b8e 4149 trace_output_32 (sd, addr);
fee8ec00
SR		 4150}
4151
4152/* stord. */
4153void
267b3b8e 4154OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4155{
4156 uint32 a = GPR32 (OP[0]);
5aedb83b 4157 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4158 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 4159 SLW (addr, a);
267b3b8e 4160 trace_output_32 (sd, addr);
fee8ec00
SR		 4161}
4162
4163/* stord. */
4164void
267b3b8e 4165OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4166{
4167 uint32 a = GPR32 (OP[0]);
5aedb83b 4168 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4169 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 4170 SLW (addr, a);
267b3b8e 4171 trace_output_32 (sd, addr);
fee8ec00
SR		 4172}
4173
4174/* macqu. */
4175void
267b3b8e 4176OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4177{
4178 int32 tmp;
4179 int16 src1, src2;
4180 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4181 src1 = GPR (OP[0]);
4182 src2 = GPR (OP[1]);
4183 tmp = src1 * src2;
4184 /*REVISIT FOR SATURATION and Q FORMAT. */
4185 SET_GPR32 (OP[2], tmp);
267b3b8e 4186 trace_output_32 (sd, tmp);
fee8ec00
SR		 4187}
4188
4189/* macuw. */
4190void
267b3b8e 4191OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4192{
4193 uint32 tmp;
4194 uint16 src1, src2;
4195 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4196 src1 = GPR (OP[0]);
4197 src2 = GPR (OP[1]);
4198 tmp = src1 * src2;
4199 /*REVISIT FOR SATURATION. */
4200 SET_GPR32 (OP[2], tmp);
267b3b8e 4201 trace_output_32 (sd, tmp);
fee8ec00
SR		 4202}
4203
4204/* macsw. */
4205void
267b3b8e 4206OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4207{
4208 int32 tmp;
4209 int16 src1, src2;
4210 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4211 src1 = GPR (OP[0]);
4212 src2 = GPR (OP[1]);
4213 tmp = src1 * src2;
4214 /*REVISIT FOR SATURATION. */
4215 SET_GPR32 (OP[2], tmp);
267b3b8e 4216 trace_output_32 (sd, tmp);
fee8ec00
SR		 4217}
4218
4219
4220/* mulb. */
4221void
267b3b8e 4222OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4223{
4224 int16 tmp;
4225 int8 a = (OP[0]) & 0xff;
4226 int8 b = (GPR (OP[1])) & 0xff;
4227 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4228 tmp = (a * b) & 0xff;
4229 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4230 trace_output_16 (sd, tmp);
fee8ec00
SR		 4231}
4232
4233/* mulb. */
4234void
267b3b8e 4235OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4236{
4237 int16 tmp;
4238 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4239 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4240 tmp = (a * b) & 0xff;
4241 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4242 trace_output_16 (sd, tmp);
fee8ec00
SR		 4243}
4244
4245
4246/* mulb. */
4247void
267b3b8e 4248OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4249{
4250 int16 tmp;
4251 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4252 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4253 tmp = (a * b) & 0xff;
4254 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4255 trace_output_16 (sd, tmp);
fee8ec00
SR		 4256}
4257
4258
4259/* mulw. */
4260void
267b3b8e 4261OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4262{
4263 int32 tmp;
4264 uint16 a = OP[0];
4265 int16 b = (GPR (OP[1]));
4266 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4267 tmp = (a * b) & 0xffff;
4268 SET_GPR (OP[1], tmp);
267b3b8e 4269 trace_output_32 (sd, tmp);
fee8ec00
SR		 4270}
4271
4272/* mulw. */
4273void
267b3b8e 4274OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4275{
4276 int32 tmp;
4277 int16 a = OP[0], b = (GPR (OP[1]));
4278 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4279 tmp = (a * b) & 0xffff;
4280 SET_GPR (OP[1], tmp);
267b3b8e 4281 trace_output_32 (sd, tmp);
fee8ec00
SR		 4282}
4283
4284
4285/* mulw. */
4286void
267b3b8e 4287OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4288{
4289 int32 tmp;
4290 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4291 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4292 tmp = (a * b) & 0xffff;
4293 SET_GPR (OP[1], tmp);
267b3b8e 4294 trace_output_32 (sd, tmp);
fee8ec00
SR		 4295}
4296
4297
4298/* mulsb. */
4299void
267b3b8e 4300OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4301{
4302 int16 tmp;
4303 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4304 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4305 tmp = a * b;
4306 SET_GPR (OP[1], tmp);
267b3b8e 4307 trace_output_32 (sd, tmp);
fee8ec00
SR		 4308}
4309
4310/* mulsw. */
4311void
267b3b8e 4312OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4313{
537e4bb9
SR		 4314 int32 tmp;
4315 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 4316 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4317 tmp = a * b;
4318 SET_GPR32 (OP[1], tmp);
267b3b8e 4319 trace_output_32 (sd, tmp);
fee8ec00
SR		 4320}
4321
4322/* muluw. */
4323void
267b3b8e 4324OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4325{
537e4bb9
SR		 4326 uint32 tmp;
4327 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 4328 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4329 tmp = a * b;
4330 SET_GPR32 (OP[1], tmp);
267b3b8e 4331 trace_output_32 (sd, tmp);
fee8ec00
SR		 4332}
4333
4334
4335/* nop. */
4336void
267b3b8e 4337OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4338{
4339 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4340
4341#if 0
fee8ec00
SR		 4342 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4343 switch (State.ins_type)
4344 {
4345 default:
4346 ins_type_counters[ (int)INS_UNKNOWN ]++;
4347 break;
4348
4349 }
0ef7f981 4350 EXCEPTION (SIM_SIGTRAP);
fee8ec00 4351#endif
267b3b8e 4352 trace_output_void (sd);
fee8ec00
SR		 4353}
4354
4355
4356/* orb. */
4357void
267b3b8e 4358OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4359{
4360 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4361 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4362 tmp = a | b;
4363 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4364 trace_output_16 (sd, tmp);
fee8ec00
SR		 4365}
4366
4367/* orb. */
4368void
267b3b8e 4369OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4370{
4371 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4372 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4373 tmp = a | b;
4374 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4375 trace_output_16 (sd, tmp);
fee8ec00
SR		 4376}
4377
4378/* orb. */
4379void
267b3b8e 4380OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4381{
4382 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4383 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4384 tmp = a | b;
4385 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4386 trace_output_16 (sd, tmp);
fee8ec00
SR		 4387}
4388
4389/* orw. */
4390void
267b3b8e 4391OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4392{
4393 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4394 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4395 tmp = a | b;
4396 SET_GPR (OP[1], tmp);
267b3b8e 4397 trace_output_16 (sd, tmp);
fee8ec00
SR		 4398}
4399
4400
4401/* orw. */
4402void
267b3b8e 4403OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4404{
4405 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4406 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4407 tmp = a | b;
4408 SET_GPR (OP[1], tmp);
267b3b8e 4409 trace_output_16 (sd, tmp);
fee8ec00
SR		 4410}
4411
4412/* orw. */
4413void
267b3b8e 4414OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4415{
4416 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4417 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4418 tmp = a | b;
4419 SET_GPR (OP[1], tmp);
267b3b8e 4420 trace_output_16 (sd, tmp);
fee8ec00
SR		 4421}
4422
4423
4424/* lshb. */
4425void
267b3b8e 4426OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4427{
4428 uint16 a = OP[0];
4429 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4430 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4431 /* A positive count specifies a shift to the left;
4432 * A negative count specifies a shift to the right. */
4433 if (sign_flag)
4434 tmp = b >> a;
4435 else
4436 tmp = b << a;
4437
4438 sign_flag = 0; /* Reset sign_flag. */
4439
4440 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4441 trace_output_16 (sd, tmp);
fee8ec00
SR		 4442}
4443
4444/* lshb. */
4445void
267b3b8e 4446OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4447{
4448 uint16 a = (GPR (OP[0])) & 0xff;
4449 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4450 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4451 if (a & ((long)1 << 3))
4452 {
4453 sign_flag = 1;
4454 a = ~(a) + 1;
4455 }
4456 a = (unsigned int) (a & 0x7);
4457
4458 /* A positive count specifies a shift to the left;
4459 * A negative count specifies a shift to the right. */
4460 if (sign_flag)
4461 tmp = b >> a;
4462 else
4463 tmp = b << a;
4464
4465 sign_flag = 0; /* Reset sign_flag. */
4466 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4467 trace_output_16 (sd, tmp);
fee8ec00
SR		 4468}
4469
4470/* lshw. */
4471void
267b3b8e 4472OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4473{
4474 uint16 tmp, b = GPR (OP[1]);
4475 int16 a = GPR (OP[0]);
4476 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4477 if (a & ((long)1 << 4))
4478 {
4479 sign_flag = 1;
4480 a = ~(a) + 1;
4481 }
4482 a = (unsigned int) (a & 0xf);
4483
4484 /* A positive count specifies a shift to the left;
4485 * A negative count specifies a shift to the right. */
4486 if (sign_flag)
4487 tmp = b >> a;
4488 else
4489 tmp = b << a;
4490
4491 sign_flag = 0; /* Reset sign_flag. */
4492 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4493 trace_output_16 (sd, tmp);
fee8ec00
SR		 4494}
4495
4496/* lshw. */
4497void
267b3b8e 4498OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4499{
4500 uint16 tmp, b = GPR (OP[1]);
4501 uint16 a = OP[0];
4502 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4503 /* A positive count specifies a shift to the left;
4504 * A negative count specifies a shift to the right. */
4505 if (sign_flag)
4506 tmp = b >> a;
4507 else
4508 tmp = b << a;
4509
4510 sign_flag = 0; /* Reset sign_flag. */
4511 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4512 trace_output_16 (sd, tmp);
fee8ec00
SR		 4513}
4514
4515/* lshd. */
4516void
267b3b8e 4517OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4518{
4519 uint32 tmp, b = GPR32 (OP[1]);
4520 uint16 a = OP[0];
4521 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4522 /* A positive count specifies a shift to the left;
4523 * A negative count specifies a shift to the right. */
4524 if (sign_flag)
4525 tmp = b >> a;
4526 else
4527 tmp = b << a;
4528
4529 sign_flag = 0; /* Reset sign flag. */
4530
4531 SET_GPR32 (OP[1], tmp);
267b3b8e 4532 trace_output_32 (sd, tmp);
fee8ec00
SR		 4533}
4534
4535/* lshd. */
4536void
267b3b8e 4537OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4538{
4539 uint32 tmp, b = GPR32 (OP[1]);
4540 uint16 a = GPR (OP[0]);
4541 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4542 if (a & ((long)1 << 5))
4543 {
4544 sign_flag = 1;
4545 a = ~(a) + 1;
4546 }
4547 a = (unsigned int) (a & 0x1f);
4548 /* A positive count specifies a shift to the left;
4549 * A negative count specifies a shift to the right. */
4550 if (sign_flag)
4551 tmp = b >> a;
4552 else
4553 tmp = b << a;
4554
4555 sign_flag = 0; /* Reset sign flag. */
4556
4557 SET_GPR32 (OP[1], tmp);
267b3b8e 4558 trace_output_32 (sd, tmp);
fee8ec00
SR		 4559}
4560
4561/* ashub. */
4562void
267b3b8e 4563OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4564{
4565 uint16 a = OP[0];
4566 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4567 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4568 /* A positive count specifies a shift to the left;
4569 * A negative count specifies a shift to the right. */
4570 if (sign_flag)
4571 tmp = b >> a;
4572 else
4573 tmp = b << a;
4574
4575 sign_flag = 0; /* Reset sign flag. */
4576
4577 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4578 trace_output_16 (sd, tmp);
fee8ec00
SR		 4579}
4580
4581/* ashub. */
4582void
267b3b8e 4583OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4584{
4585 uint16 a = OP[0];
4586 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4587 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4588 /* A positive count specifies a shift to the left;
4589 * A negative count specifies a shift to the right. */
4590 if (sign_flag)
4591 tmp = b >> a;
4592 else
4593 tmp = b << a;
4594
4595 sign_flag = 0; /* Reset sign flag. */
4596
4597 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4598 trace_output_16 (sd, tmp);
fee8ec00
SR		 4599}
4600
4601
4602/* ashub. */
4603void
267b3b8e 4604OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4605{
4606 int16 a = (GPR (OP[0]));
4607 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4608 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4609
4610 if (a & ((long)1 << 3))
4611 {
4612 sign_flag = 1;
4613 a = ~(a) + 1;
4614 }
4615 a = (unsigned int) (a & 0x7);
4616
4617 /* A positive count specifies a shift to the left;
4618 * A negative count specifies a shift to the right. */
4619 if (sign_flag)
4620 tmp = b >> a;
4621 else
4622 tmp = b << a;
4623
4624 sign_flag = 0; /* Reset sign flag. */
4625
4626 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4627 trace_output_16 (sd, tmp);
fee8ec00
SR		 4628}
4629
4630
4631/* ashuw. */
4632void
267b3b8e 4633OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4634{
4635 int16 tmp, b = GPR (OP[1]);
4636 uint16 a = OP[0];
4637 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4638 /* A positive count specifies a shift to the left;
4639 * A negative count specifies a shift to the right. */
4640 if (sign_flag)
4641 tmp = b >> a;
4642 else
4643 tmp = b << a;
4644
4645 sign_flag = 0; /* Reset sign flag. */
4646
4647 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4648 trace_output_16 (sd, tmp);
fee8ec00
SR		 4649}
4650
4651/* ashuw. */
4652void
267b3b8e 4653OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4654{
4655 int16 tmp, b = GPR (OP[1]);
4656 uint16 a = OP[0];
4657 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4658 /* A positive count specifies a shift to the left;
4659 * A negative count specifies a shift to the right. */
4660 if (sign_flag)
4661 tmp = b >> a;
4662 else
4663 tmp = b << a;
4664
4665 sign_flag = 0; /* Reset sign flag. */
4666 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4667 trace_output_16 (sd, tmp);
fee8ec00
SR		 4668}
4669
4670/* ashuw. */
4671void
267b3b8e 4672OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4673{
4674 int16 tmp;
4675 int16 a = GPR (OP[0]), b = GPR (OP[1]);
4676 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4677
4678 if (a & ((long)1 << 4))
4679 {
4680 sign_flag = 1;
4681 a = ~(a) + 1;
4682 }
4683 a = (unsigned int) (a & 0xf);
4684 /* A positive count specifies a shift to the left;
4685 * A negative count specifies a shift to the right. */
4686
4687 if (sign_flag)
4688 tmp = b >> a;
4689 else
4690 tmp = b << a;
4691
4692 sign_flag = 0; /* Reset sign flag. */
4693 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4694 trace_output_16 (sd, tmp);
fee8ec00
SR		 4695}
4696
4697/* ashud. */
4698void
267b3b8e 4699OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4700{
4701 int32 tmp,b = GPR32 (OP[1]);
4702 uint32 a = OP[0];
4703 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4704 /* A positive count specifies a shift to the left;
4705 * A negative count specifies a shift to the right. */
4706 if (sign_flag)
4707 tmp = b >> a;
4708 else
4709 tmp = b << a;
4710
4711 sign_flag = 0; /* Reset sign flag. */
4712 SET_GPR32 (OP[1], tmp);
267b3b8e 4713 trace_output_32 (sd, tmp);
fee8ec00
SR		 4714}
4715
4716/* ashud. */
4717void
267b3b8e 4718OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4719{
4720 int32 tmp;
4721 int32 a = OP[0], b = GPR32 (OP[1]);
4722 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4723 /* A positive count specifies a shift to the left;
4724 * A negative count specifies a shift to the right. */
4725 if (sign_flag)
4726 tmp = b >> a;
4727 else
4728 tmp = b << a;
4729
4730 sign_flag = 0; /* Reset sign flag. */
4731 SET_GPR32 (OP[1], tmp);
267b3b8e 4732 trace_output_32 (sd, tmp);
fee8ec00
SR		 4733}
4734
4735/* ashud. */
4736void
267b3b8e 4737OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4738{
4739 int32 tmp;
4740 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4741 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4742
4743 if (a & ((long)1 << 5))
4744 {
4745 sign_flag = 1;
4746 a = ~(a) + 1;
4747 }
4748 a = (unsigned int) (a & 0x1f);
4749 /* A positive count specifies a shift to the left;
4750 * A negative count specifies a shift to the right. */
4751 if (sign_flag)
4752 tmp = b >> a;
4753 else
4754 tmp = b << a;
4755
4756 sign_flag = 0; /* Reset sign flag. */
4757 SET_GPR32 (OP[1], tmp);
267b3b8e 4758 trace_output_32 (sd, tmp);
fee8ec00
SR		 4759}
4760
4761
4762/* storm. */
4763void
267b3b8e 4764OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4765{
4766 uint32 addr = GPR (1);
4767 uint16 count = OP[0], reg = 2;
4768 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4769 if ((addr & 1))
4770 {
267b3b8e 4771 trace_output_void (sd);
0ef7f981 4772 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 4773 }
4774
4775 while (count)
4776 {
4777 SW (addr, (GPR (reg)));
4778 addr +=2;
4779 --count;
4780 reg++;
4781 if (reg == 6) reg = 8;
4782 };
4783
4784 SET_GPR (1, addr);
4785
267b3b8e 4786 trace_output_void (sd);
fee8ec00
SR		 4787}
4788
4789
4790/* stormp. */
4791void
267b3b8e 4792OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4793{
4794 uint32 addr = GPR32 (6);
4795 uint16 count = OP[0], reg = 2;
4796 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4797 if ((addr & 1))
4798 {
267b3b8e 4799 trace_output_void (sd);
0ef7f981 4800 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 4801 }
4802
4803 while (count)
4804 {
4805 SW (addr, (GPR (reg)));
4806 addr +=2;
4807 --count;
4808 reg++;
4809 if (reg == 6) reg = 8;
4810 };
4811
4812 SET_GPR32 (6, addr);
267b3b8e 4813 trace_output_void (sd);
fee8ec00
SR		 4814}
4815
4816/* subb. */
4817void
267b3b8e 4818OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4819{
4820 uint8 a = OP[0];
4821 uint8 b = (GPR (OP[1])) & 0xff;
4822 uint16 tmp = (~a + 1 + b) & 0xff;
4823 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4824 /* see ../common/sim-alu.h for a more extensive discussion on how to
4825 compute the carry/overflow bits. */
4826 SET_PSR_C (tmp > 0xff);
4827 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4828 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4829 trace_output_16 (sd, tmp);
fee8ec00
SR		 4830}
4831
4832/* subb. */
4833void
267b3b8e 4834OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4835{
4836 uint8 a = OP[0] & 0xFF;
4837 uint8 b = (GPR (OP[1])) & 0xFF;
4838 uint16 tmp = (~a + 1 + b) & 0xFF;
4839 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4840 /* see ../common/sim-alu.h for a more extensive discussion on how to
4841 compute the carry/overflow bits. */
4842 SET_PSR_C (tmp > 0xff);
4843 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4844 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4845 trace_output_16 (sd, tmp);
fee8ec00
SR		 4846}
4847
4848/* subb. */
4849void
267b3b8e 4850OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4851{
4852 uint8 a = (GPR (OP[0])) & 0xFF;
4853 uint8 b = (GPR (OP[1])) & 0xFF;
4854 uint16 tmp = (~a + 1 + b) & 0xff;
4855 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4856 /* see ../common/sim-alu.h for a more extensive discussion on how to
4857 compute the carry/overflow bits. */
4858 SET_PSR_C (tmp > 0xff);
4859 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4860 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4861 trace_output_16 (sd, tmp);
fee8ec00
SR		 4862}
4863
4864/* subw. */
4865void
267b3b8e 4866OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4867{
4868 uint16 a = OP[0];
4869 uint16 b = GPR (OP[1]);
4870 uint16 tmp = (~a + 1 + b);
4871 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4872 /* see ../common/sim-alu.h for a more extensive discussion on how to
4873 compute the carry/overflow bits. */
4874 SET_PSR_C (tmp > 0xffff);
4875 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4876 SET_GPR (OP[1], tmp);
267b3b8e 4877 trace_output_16 (sd, tmp);
fee8ec00
SR		 4878}
4879
4880/* subw. */
4881void
267b3b8e 4882OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4883{
4884 uint16 a = OP[0];
4885 uint16 b = GPR (OP[1]);
4886 uint32 tmp = (~a + 1 + b);
4887 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4888 /* see ../common/sim-alu.h for a more extensive discussion on how to
4889 compute the carry/overflow bits. */
4890 SET_PSR_C (tmp > 0xffff);
4891 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4892 SET_GPR (OP[1], tmp & 0xffff);
267b3b8e 4893 trace_output_16 (sd, tmp);
fee8ec00
SR		 4894}
4895
4896/* subw. */
4897void
267b3b8e 4898OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4899{
4900 uint16 a = GPR (OP[0]);
4901 uint16 b = GPR (OP[1]);
4902 uint32 tmp = (~a + 1 + b);
4903 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4904 /* see ../common/sim-alu.h for a more extensive discussion on how to
4905 compute the carry/overflow bits. */
4906 SET_PSR_C (tmp > 0xffff);
4907 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4908 SET_GPR (OP[1], tmp & 0xffff);
267b3b8e 4909 trace_output_16 (sd, tmp);
fee8ec00
SR		 4910}
4911
4912/* subcb. */
4913void
267b3b8e 4914OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4915{
4916 uint8 a = OP[0];
4917 uint8 b = (GPR (OP[1])) & 0xff;
4918 //uint16 tmp1 = a + 1;
4919 uint16 tmp1 = a + (PSR_C);
4920 uint16 tmp = (~tmp1 + 1 + b);
4921 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4922 /* see ../common/sim-alu.h for a more extensive discussion on how to
4923 compute the carry/overflow bits. */
4924 SET_PSR_C (tmp > 0xff);
4925 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4926 SET_GPR (OP[1], tmp);
267b3b8e 4927 trace_output_16 (sd, tmp);
fee8ec00
SR		 4928}
4929
4930/* subcb. */
4931void
267b3b8e 4932OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4933{
4934 uint16 a = OP[0];
4935 uint16 b = (GPR (OP[1])) & 0xff;
4936 //uint16 tmp1 = a + 1;
4937 uint16 tmp1 = a + (PSR_C);
4938 uint16 tmp = (~tmp1 + 1 + b);
4939 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4940 /* see ../common/sim-alu.h for a more extensive discussion on how to
4941 compute the carry/overflow bits. */
4942 SET_PSR_C (tmp > 0xff);
4943 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4944 SET_GPR (OP[1], tmp);
267b3b8e 4945 trace_output_16 (sd, tmp);
fee8ec00
SR		 4946}
4947
4948/* subcb. */
4949void
267b3b8e 4950OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4951{
4952 uint16 a = (GPR (OP[0])) & 0xff;
4953 uint16 b = (GPR (OP[1])) & 0xff;
4954 uint16 tmp1 = a + (PSR_C);
4955 uint16 tmp = (~tmp1 + 1 + b);
4956 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4957 /* see ../common/sim-alu.h for a more extensive discussion on how to
4958 compute the carry/overflow bits. */
4959 SET_PSR_C (tmp > 0xff);
4960 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4961 SET_GPR (OP[1], tmp);
267b3b8e 4962 trace_output_16 (sd, tmp);
fee8ec00
SR		 4963}
4964
4965/* subcw. */
4966void
267b3b8e 4967OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4968{
4969 uint16 a = OP[0], b = (GPR (OP[1]));
4970 uint16 tmp1 = a + (PSR_C);
4971 uint16 tmp = (~tmp1 + 1 + b);
4972 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4973 /* see ../common/sim-alu.h for a more extensive discussion on how to
4974 compute the carry/overflow bits. */
4975 SET_PSR_C (tmp > 0xffff);
4976 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4977 SET_GPR (OP[1], tmp);
267b3b8e 4978 trace_output_16 (sd, tmp);
fee8ec00
SR		 4979}
4980
4981/* subcw. */
4982void
267b3b8e 4983OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4984{
4985 int16 a = OP[0];
4986 uint16 b = GPR (OP[1]);
4987 uint16 tmp1 = a + (PSR_C);
4988 uint16 tmp = (~tmp1 + 1 + b);
4989 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
4990 /* see ../common/sim-alu.h for a more extensive discussion on how to
4991 compute the carry/overflow bits. */
4992 SET_PSR_C (tmp > 0xffff);
4993 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4994 SET_GPR (OP[1], tmp);
267b3b8e 4995 trace_output_16 (sd, tmp);
fee8ec00
SR		 4996}
4997
4998/* subcw. */
4999void
267b3b8e 5000OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5001{
5002 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
5003 uint16 tmp1 = a + (PSR_C);
5004 uint16 tmp = (~tmp1 + 1 + b);
5005 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5006 /* see ../common/sim-alu.h for a more extensive discussion on how to
5007 compute the carry/overflow bits. */
5008 SET_PSR_C (tmp > 0xffff);
5009 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5010 SET_GPR (OP[1], tmp);
267b3b8e 5011 trace_output_16 (sd, tmp);
fee8ec00
SR		 5012}
5013
5014/* subd. */
5015void
267b3b8e 5016OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5017{
5018 int32 a = OP[0];
5019 uint32 b = GPR32 (OP[1]);
5020 uint32 tmp = (~a + 1 + b);
5021 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5022 /* see ../common/sim-alu.h for a more extensive discussion on how to
5023 compute the carry/overflow bits. */
5024 SET_PSR_C (tmp > 0xffffffff);
5025 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5026 ((b & 0x80000000) != (tmp & 0x80000000)));
5027 SET_GPR32 (OP[1], tmp);
267b3b8e 5028 trace_output_32 (sd, tmp);
fee8ec00
SR		 5029}
5030
5031/* subd. */
5032void
267b3b8e 5033OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5034{
5035 uint32 a = GPR32 (OP[0]);
5036 uint32 b = GPR32 (OP[1]);
5037 uint32 tmp = (~a + 1 + b);
5038 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5039 /* see ../common/sim-alu.h for a more extensive discussion on how to
5040 compute the carry/overflow bits. */
5041 SET_PSR_C (tmp > 0xffffffff);
5042 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5043 ((b & 0x80000000) != (tmp & 0x80000000)));
5044 SET_GPR32 (OP[1], tmp);
267b3b8e 5045 trace_output_32 (sd, tmp);
fee8ec00
SR		 5046}
5047
5048/* excp. */
5049void
267b3b8e 5050OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5051{
9db36cf8 5052 host_callback *cb = STATE_CALLBACK (sd);
5a06d7c4
MF		 5053 uint32 tmp;
5054 uint16 a;
fee8ec00
SR		 5055 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5056 switch (OP[0])
5057 {
5058 default:
5059#if (DEBUG & DEBUG_TRAP) == 0
5060 {
5061#if 0
5062 uint16 vec = OP[0] + TRAP_VECTOR_START;
5063 SET_BPC (PC + 1);
5064 SET_BPSR (PSR);
5065 SET_PSR (PSR & PSR_SM_BIT);
5066 JMP (vec);
5067 break;
5068#endif
5069 }
5070#else /* if debugging use trap to print registers */
5071 {
5072 int i;
5073 static int first_time = 1;
5074
5075 if (first_time)
5076 {
5077 first_time = 0;
9db36cf8 5078 sim_io_printf (sd, "Trap # PC ");
fee8ec00 5079 for (i = 0; i < 16; i++)
9db36cf8
MF		 5080 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
5081 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
fee8ec00
SR		 5082 }
5083
9db36cf8 5084 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
fee8ec00
SR		 5085
5086 for (i = 0; i < 16; i++)
9db36cf8 5087 sim_io_printf (sd, " %.4x", (int) GPR (i));
fee8ec00
SR		 5088
5089 for (i = 0; i < 2; i++)
9db36cf8 5090 sim_io_printf (sd, " %.2x%.8lx",
fee8ec00
SR		 5091 ((int)(ACC (i) >> 32) & 0xff),
5092 ((unsigned long) ACC (i)) & 0xffffffff);
5093
9db36cf8 5094 sim_io_printf (sd, " %d %d %d\n",
fee8ec00 5095 PSR_F != 0, PSR_F != 0, PSR_C != 0);
9db36cf8 5096 sim_io_flush_stdout (sd);
fee8ec00
SR		 5097 break;
5098 }
5099#endif
5100 case 8: /* new system call trap */
5101 /* Trap 8 is used for simulating low-level I/O */
5102 {
5103 unsigned32 result = 0;
5104 errno = 0;
5105
5106/* Registers passed to trap 0. */
5107
5108#define FUNC GPR (0) /* function number. */
5109#define PARM1 GPR (2) /* optional parm 1. */
5110#define PARM2 GPR (3) /* optional parm 2. */
5111#define PARM3 GPR (4) /* optional parm 3. */
5112#define PARM4 GPR (5) /* optional parm 4. */
5113
5114/* Registers set by trap 0 */
5115
5116#define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5117#define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5118#define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5119
5120/* Turn a pointer in a register into a pointer into real memory. */
5121
761e171a 5122#define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
fee8ec00
SR		 5123
5124 switch (FUNC)
5125 {
5126#if !defined(__GO32__) && !defined(_WIN32)
9220438c 5127#ifdef TARGET_SYS_fork
fee8ec00
SR		 5128 case TARGET_SYS_fork:
5129 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5130 RETVAL (fork ());
267b3b8e 5131 trace_output_16 (sd, result);
fee8ec00 5132 break;
9220438c 5133#endif
fee8ec00
SR		 5134
5135#define getpid() 47
5136 case TARGET_SYS_getpid:
5137 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5138 RETVAL (getpid ());
267b3b8e 5139 trace_output_16 (sd, result);
fee8ec00
SR		 5140 break;
5141
5142 case TARGET_SYS_kill:
5143 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5144 if (PARM1 == getpid ())
5145 {
267b3b8e 5146 trace_output_void (sd);
0ef7f981 5147 EXCEPTION (PARM2);
fee8ec00
SR		 5148 }
5149 else
5150 {
5151 int os_sig = -1;
5152 switch (PARM2)
5153 {
5154#ifdef SIGHUP
5155 case 1: os_sig = SIGHUP; break;
5156#endif
5157#ifdef SIGINT
5158 case 2: os_sig = SIGINT; break;
5159#endif
5160#ifdef SIGQUIT
5161 case 3: os_sig = SIGQUIT; break;
5162#endif
5163#ifdef SIGILL
5164 case 4: os_sig = SIGILL; break;
5165#endif
5166#ifdef SIGTRAP
5167 case 5: os_sig = SIGTRAP; break;
5168#endif
5169#ifdef SIGABRT
5170 case 6: os_sig = SIGABRT; break;
5171#elif defined(SIGIOT)
5172 case 6: os_sig = SIGIOT; break;
5173#endif
5174#ifdef SIGEMT
5175 case 7: os_sig = SIGEMT; break;
5176#endif
5177#ifdef SIGFPE
5178 case 8: os_sig = SIGFPE; break;
5179#endif
5180#ifdef SIGKILL
5181 case 9: os_sig = SIGKILL; break;
5182#endif
5183#ifdef SIGBUS
5184 case 10: os_sig = SIGBUS; break;
5185#endif
5186#ifdef SIGSEGV
5187 case 11: os_sig = SIGSEGV; break;
5188#endif
5189#ifdef SIGSYS
5190 case 12: os_sig = SIGSYS; break;
5191#endif
5192#ifdef SIGPIPE
5193 case 13: os_sig = SIGPIPE; break;
5194#endif
5195#ifdef SIGALRM
5196 case 14: os_sig = SIGALRM; break;
5197#endif
5198#ifdef SIGTERM
5199 case 15: os_sig = SIGTERM; break;
5200#endif
5201#ifdef SIGURG
5202 case 16: os_sig = SIGURG; break;
5203#endif
5204#ifdef SIGSTOP
5205 case 17: os_sig = SIGSTOP; break;
5206#endif
5207#ifdef SIGTSTP
5208 case 18: os_sig = SIGTSTP; break;
5209#endif
5210#ifdef SIGCONT
5211 case 19: os_sig = SIGCONT; break;
5212#endif
5213#ifdef SIGCHLD
5214 case 20: os_sig = SIGCHLD; break;
5215#elif defined(SIGCLD)
5216 case 20: os_sig = SIGCLD; break;
5217#endif
5218#ifdef SIGTTIN
5219 case 21: os_sig = SIGTTIN; break;
5220#endif
5221#ifdef SIGTTOU
5222 case 22: os_sig = SIGTTOU; break;
5223#endif
5224#ifdef SIGIO
5225 case 23: os_sig = SIGIO; break;
5226#elif defined (SIGPOLL)
5227 case 23: os_sig = SIGPOLL; break;
5228#endif
5229#ifdef SIGXCPU
5230 case 24: os_sig = SIGXCPU; break;
5231#endif
5232#ifdef SIGXFSZ
5233 case 25: os_sig = SIGXFSZ; break;
5234#endif
5235#ifdef SIGVTALRM
5236 case 26: os_sig = SIGVTALRM; break;
5237#endif
5238#ifdef SIGPROF
5239 case 27: os_sig = SIGPROF; break;
5240#endif
5241#ifdef SIGWINCH
5242 case 28: os_sig = SIGWINCH; break;
5243#endif
5244#ifdef SIGLOST
5245 case 29: os_sig = SIGLOST; break;
5246#endif
5247#ifdef SIGUSR1
5248 case 30: os_sig = SIGUSR1; break;
5249#endif
5250#ifdef SIGUSR2
5251 case 31: os_sig = SIGUSR2; break;
5252#endif
5253 }
5254
5255 if (os_sig == -1)
5256 {
267b3b8e 5257 trace_output_void (sd);
9db36cf8
MF		 5258 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
5259 sim_io_flush_stdout (sd);
0ef7f981 5260 EXCEPTION (SIM_SIGILL);
fee8ec00
SR		 5261 }
5262 else
5263 {
5264 RETVAL (kill (PARM1, PARM2));
267b3b8e 5265 trace_output_16 (sd, result);
fee8ec00
SR		 5266 }
5267 }
5268 break;
5269
9220438c 5270#ifdef TARGET_SYS_execve
fee8ec00
SR		 5271 case TARGET_SYS_execve:
5272 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5273 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5274 (char **)MEMPTR (PARM4)));
267b3b8e 5275 trace_output_16 (sd, result);
fee8ec00 5276 break;
9220438c 5277#endif
fee8ec00
SR		 5278
5279#ifdef TARGET_SYS_execv
5280 case TARGET_SYS_execv:
5281 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5282 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
267b3b8e 5283 trace_output_16 (sd, result);
fee8ec00
SR		 5284 break;
5285#endif
5286
9220438c 5287#ifdef TARGET_SYS_pipe
fee8ec00
SR		 5288 case TARGET_SYS_pipe:
5289 {
5290 reg_t buf;
5291 int host_fd[2];
5292
5293 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5294 buf = PARM1;
5295 RETVAL (pipe (host_fd));
5296 SW (buf, host_fd[0]);
5297 buf += sizeof(uint16);
5298 SW (buf, host_fd[1]);
267b3b8e 5299 trace_output_16 (sd, result);
fee8ec00
SR		 5300 }
5301 break;
9220438c 5302#endif
fee8ec00
SR		 5303
5304#ifdef TARGET_SYS_wait
5305 case TARGET_SYS_wait:
5306 {
5307 int status;
5308 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5309 RETVAL (wait (&status));
5310 if (PARM1)
5311 SW (PARM1, status);
267b3b8e 5312 trace_output_16 (sd, result);
fee8ec00
SR		 5313 }
5314 break;
5315#endif
5316#else
5317 case TARGET_SYS_getpid:
5318 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5319 RETVAL (1);
267b3b8e 5320 trace_output_16 (sd, result);
fee8ec00
SR		 5321 break;
5322
5323 case TARGET_SYS_kill:
5324 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
267b3b8e 5325 trace_output_void (sd);
0ef7f981 5326 EXCEPTION (PARM2);
fee8ec00
SR		 5327 break;
5328#endif
5329
5330 case TARGET_SYS_read:
5331 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
9db36cf8
MF		 5332 RETVAL (cb->read (cb, PARM1,
5333 MEMPTR (((unsigned long)PARM3 << 16)
5334 | ((unsigned long)PARM2)), PARM4));
267b3b8e 5335 trace_output_16 (sd, result);
fee8ec00
SR		 5336 break;
5337
5338 case TARGET_SYS_write:
5339 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
9db36cf8
MF		 5340 RETVAL ((int)cb->write (cb, PARM1,
5341 MEMPTR (((unsigned long)PARM3 << 16)
5342 | PARM2), PARM4));
267b3b8e 5343 trace_output_16 (sd, result);
fee8ec00
SR		 5344 break;
5345
5346 case TARGET_SYS_lseek:
5347 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
9db36cf8
MF		 5348 RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2),
5349 PARM4));
267b3b8e 5350 trace_output_32 (sd, result);
fee8ec00
SR		 5351 break;
5352
5353 case TARGET_SYS_close:
5354 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
9db36cf8 5355 RETVAL (cb->close (cb, PARM1));
267b3b8e 5356 trace_output_16 (sd, result);
fee8ec00
SR		 5357 break;
5358
5359 case TARGET_SYS_open:
5360 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
9db36cf8
MF		 5361 RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16)
5362 | PARM1), PARM3));
267b3b8e 5363 trace_output_32 (sd, result);
fee8ec00
SR		 5364 break;
5365
9220438c 5366#ifdef TARGET_SYS_rename
fee8ec00
SR		 5367 case TARGET_SYS_rename:
5368 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
9db36cf8
MF		 5369 RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1),
5370 MEMPTR ((((unsigned long)PARM4) << 16) | PARM3)));
267b3b8e 5371 trace_output_16 (sd, result);
fee8ec00 5372 break;
9220438c 5373#endif
fee8ec00
SR		 5374
5375 case 0x408: /* REVISIT: Added a dummy getenv call. */
5376 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5aedb83b 5377 RETVAL32 (0);
267b3b8e 5378 trace_output_32 (sd, result);
fee8ec00
SR		 5379 break;
5380
5381 case TARGET_SYS_exit:
5382 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5383 trace_output_void (sd);
0ef7f981 5384 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
fee8ec00
SR		 5385 break;
5386
5387 case TARGET_SYS_unlink:
5388 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
9db36cf8 5389 RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1)));
267b3b8e 5390 trace_output_16 (sd, result);
fee8ec00
SR		 5391 break;
5392
5393
5394#ifdef TARGET_SYS_stat
5395 case TARGET_SYS_stat:
5396 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5397 /* stat system call. */
5398 {
5399 struct stat host_stat;
5400 reg_t buf;
5401
5402 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5403
5404 buf = PARM2;
5405
5406 /* The hard-coded offsets and sizes were determined by using
5407 * the CR16 compiler on a test program that used struct stat.
5408 */
5409 SW (buf, host_stat.st_dev);
5410 SW (buf+2, host_stat.st_ino);
5411 SW (buf+4, host_stat.st_mode);
5412 SW (buf+6, host_stat.st_nlink);
5413 SW (buf+8, host_stat.st_uid);
5414 SW (buf+10, host_stat.st_gid);
5415 SW (buf+12, host_stat.st_rdev);
5416 SLW (buf+16, host_stat.st_size);
5417 SLW (buf+20, host_stat.st_atime);
5418 SLW (buf+28, host_stat.st_mtime);
5419 SLW (buf+36, host_stat.st_ctime);
5420 }
267b3b8e 5421 trace_output_16 (sd, result);
fee8ec00
SR		 5422 break;
5423#endif
5424
9220438c 5425#ifdef TARGET_SYS_chown
fee8ec00
SR		 5426 case TARGET_SYS_chown:
5427 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5428 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
267b3b8e 5429 trace_output_16 (sd, result);
fee8ec00 5430 break;
9220438c 5431#endif
fee8ec00
SR		 5432
5433 case TARGET_SYS_chmod:
5434 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5435 RETVAL (chmod (MEMPTR (PARM1), PARM2));
267b3b8e 5436 trace_output_16 (sd, result);
fee8ec00
SR		 5437 break;
5438
5439#ifdef TARGET_SYS_utime
5440 case TARGET_SYS_utime:
5441 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5442 /* Cast the second argument to void *, to avoid type mismatch
5443 if a prototype is present. */
5444 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
267b3b8e 5445 trace_output_16 (sd, result);
fee8ec00
SR		 5446 break;
5447#endif
5448
5449#ifdef TARGET_SYS_time
5450 case TARGET_SYS_time:
5451 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5452 RETVAL32 (time (NULL));
267b3b8e 5453 trace_output_32 (sd, result);
fee8ec00
SR		 5454 break;
5455#endif
5456
5457 default:
5a06d7c4
MF		 5458 a = OP[0];
5459 switch (a)
5460 {
5461 case TRAP_BREAKPOINT:
5a06d7c4
MF		 5462 tmp = (PC);
5463 JMP(tmp);
267b3b8e 5464 trace_output_void (sd);
0ef7f981 5465 EXCEPTION (SIM_SIGTRAP);
5a06d7c4
MF		 5466 break;
5467 case SIGTRAP: /* supervisor call ? */
267b3b8e 5468 trace_output_void (sd);
0ef7f981 5469 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5a06d7c4
MF		 5470 break;
5471 default:
9db36cf8 5472 cb->error (cb, "Unknown syscall %d", FUNC);
5a06d7c4
MF		 5473 break;
5474 }
fee8ec00 5475 }
fee8ec00 5476 if ((uint16) result == (uint16) -1)
9db36cf8 5477 RETERR (cb->get_errno (cb));
fee8ec00
SR		 5478 else
5479 RETERR (0);
5480 break;
5481 }
5482 }
5483}
5484
5485
5486/* push. */
5487void
267b3b8e 5488OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5489{
5490 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5491 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5492 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5493
5494 for (; i < a; ++i)
5495 {
5496 if ((b+i) <= 11)
5497 {
5498 SW (sp_addr, (GPR (b+i)));
5499 sp_addr +=2;
5500 }
5501 else
5502 {
5503 if (is_regp == 0)
5504 tmp = (GPR32 (b+i));
5505 else
5506 tmp = (GPR32 (b+i-1));
5507
5508 if ((a-i) > 1)
5509 {
5510 SLW (sp_addr, tmp);
5511 sp_addr +=4;
5512 }
5513 else
5514 {
5515 SW (sp_addr, tmp);
5516 sp_addr +=2;
5517 }
5518 ++i;
5519 is_regp = 1;
5520 }
5521 }
5522
5523 sp_addr +=4;
5524
5525 /* Store RA address. */
5526 tmp = (GPR32 (14));
5527 SLW(sp_addr,tmp);
5528
5529 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5530 SET_GPR32 (15, sp_addr); /* Update SP address. */
5531
267b3b8e 5532 trace_output_void (sd);
fee8ec00
SR		 5533}
5534
5535/* push. */
5536void
267b3b8e 5537OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5538{
5539 uint32 sp_addr, tmp, is_regp = 0;
5540 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5541 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5542
5543 if (c == 1)
5544 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5545 else
5546 sp_addr = (GPR32 (15)) - (a * 2);
5547
5548 for (; i < a; ++i)
5549 {
5550 if ((b+i) <= 11)
5551 {
5552 SW (sp_addr, (GPR (b+i)));
5553 sp_addr +=2;
5554 }
5555 else
5556 {
5557 if (is_regp == 0)
5558 tmp = (GPR32 (b+i));
5559 else
5560 tmp = (GPR32 (b+i-1));
5561
5562 if ((a-i) > 1)
5563 {
5564 SLW (sp_addr, tmp);
5565 sp_addr +=4;
5566 }
5567 else
5568 {
5569 SW (sp_addr, tmp);
5570 sp_addr +=2;
5571 }
5572 ++i;
5573 is_regp = 1;
5574 }
5575 }
5576
5577 if (c == 1)
5578 {
5579 /* Store RA address. */
5580 tmp = (GPR32 (14));
5581 SLW(sp_addr,tmp);
5582 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5583 }
5584 else
5585 sp_addr = (GPR32 (15)) - (a * 2);
5586
5587 SET_GPR32 (15, sp_addr); /* Update SP address. */
5588
267b3b8e 5589 trace_output_void (sd);
fee8ec00
SR		 5590}
5591
5592
5593/* push. */
5594void
267b3b8e 5595OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5596{
5597 uint32 sp_addr = (GPR32 (15)), tmp;
5598 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5599 tmp = (GPR32 (14));
5600 SLW(sp_addr-4,tmp); /* Store RA address. */
5601 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
267b3b8e 5602 trace_output_void (sd);
fee8ec00
SR		 5603}
5604
5605
5606/* pop. */
5607void
267b3b8e 5608OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5609{
5610 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5611 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5612 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5613
5614 for (; i < a; ++i)
5615 {
5616 if ((b+i) <= 11)
5617 {
5618 SET_GPR ((b+i), RW(sp_addr));
5619 sp_addr +=2;
5620 }
5621 else
5622 {
5623 if ((a-i) > 1)
5624 {
5625 tmp = RLW(sp_addr);
5626 sp_addr +=4;
5627 }
5628 else
5629 {
5630 tmp = RW(sp_addr);
5631 sp_addr +=2;
5632
5633 if (is_regp == 0)
5634 tmp = (tmp << 16) | (GPR32 (b+i));
5635 else
5636 tmp = (tmp << 16) | (GPR32 (b+i-1));
5637 }
5638
5639 if (is_regp == 0)
5640 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5641 | ((tmp >> 16) & 0xffff)));
5642 else
5643 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5644 | ((tmp >> 16) & 0xffff)));
5645
5646 ++i;
5647 is_regp = 1;
5648 }
5649 }
5650
5651 tmp = RLW(sp_addr); /* store RA also. */
5652 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5653
5654 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5655
267b3b8e 5656 trace_output_void (sd);
fee8ec00
SR		 5657}
5658
5659/* pop. */
5660void
267b3b8e 5661OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5662{
5663 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5664 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5665 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5666
5667 for (; i < a; ++i)
5668 {
5669 if ((b+i) <= 11)
5670 {
5671 SET_GPR ((b+i), RW(sp_addr));
5672 sp_addr +=2;
5673 }
5674 else
5675 {
5676 if ((a-i) > 1)
5677 {
5678 tmp = RLW(sp_addr);
5679 sp_addr +=4;
5680 }
5681 else
5682 {
5683 tmp = RW(sp_addr);
5684 sp_addr +=2;
5685
5686 if (is_regp == 0)
5687 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5688 else
5689 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5690 }
5691
5692 if (is_regp == 0)
5693 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5694 else
5695 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5696 ++i;
5697 is_regp = 1;
5698 }
5699 }
5700
5701 if (c == 1)
5702 {
5703 tmp = RLW(sp_addr); /* Store RA Reg. */
5704 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5705 sp_addr +=4;
5706 }
5707
5708 SET_GPR32 (15, sp_addr); /* Update SP address. */
5709
267b3b8e 5710 trace_output_void (sd);
fee8ec00
SR		 5711}
5712
5713/* pop. */
5714void
267b3b8e 5715OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5716{
5717 uint32 sp_addr = GPR32 (15);
5718 uint32 tmp;
5719 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5720
5721 tmp = RLW(sp_addr);
5722 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5723 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5724
267b3b8e 5725 trace_output_void (sd);
fee8ec00
SR		 5726}
5727
5728/* popret. */
5729void
267b3b8e 5730OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5731{
5732 uint16 a = OP[0], b = OP[1];
5733 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
267b3b8e 5734 OP_5_9 (sd, cpu);
fee8ec00
SR		 5735 JMP(((GPR32(14)) << 1) & 0xffffff);
5736
267b3b8e 5737 trace_output_void (sd);
fee8ec00
SR		 5738}
5739
5740/* popret. */
5741void
267b3b8e 5742OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5743{
5744 uint16 a = OP[0], b = OP[1];
5745 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
267b3b8e 5746 OP_2_8 (sd, cpu);
fee8ec00
SR		 5747 JMP(((GPR32(14)) << 1) & 0xffffff);
5748
267b3b8e 5749 trace_output_void (sd);
fee8ec00
SR		 5750}
5751
5752/* popret. */
5753void
267b3b8e 5754OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5755{
5756 uint32 tmp;
5757 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5758 OP_21E_10 (sd, cpu);
fee8ec00
SR		 5759 tmp = (((GPR32(14)) << 1) & 0xffffff);
5760 /* If the resulting PC value is less than 0x00_0000 or greater
5761 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5762
5763 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5764 {
267b3b8e 5765 trace_output_void (sd);
0ef7f981 5766 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 5767 }
5768 else
5769 JMP (tmp);
5770
267b3b8e 5771 trace_output_32 (sd, tmp);
fee8ec00
SR		 5772}
5773
5774
5775/* cinv[i]. */
5776void
267b3b8e 5777OP_A_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5778{
5779 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5780 SET_PSR_I (1);
267b3b8e 5781 trace_output_void (sd);
fee8ec00
SR		 5782}
5783
5784/* cinv[i,u]. */
5785void
267b3b8e 5786OP_B_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5787{
5788 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5789 SET_PSR_I (1);
267b3b8e 5790 trace_output_void (sd);
fee8ec00
SR		 5791}
5792
5793/* cinv[d]. */
5794void
267b3b8e 5795OP_C_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5796{
5797 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5798 SET_PSR_I (1);
267b3b8e 5799 trace_output_void (sd);
fee8ec00
SR		 5800}
5801
5802/* cinv[d,u]. */
5803void
267b3b8e 5804OP_D_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5805{
5806 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5807 SET_PSR_I (1);
267b3b8e 5808 trace_output_void (sd);
fee8ec00
SR		 5809}
5810
5811/* cinv[d,i]. */
5812void
267b3b8e 5813OP_E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5814{
5815 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5816 SET_PSR_I (1);
267b3b8e 5817 trace_output_void (sd);
fee8ec00
SR		 5818}
5819
5820/* cinv[d,i,u]. */
5821void
267b3b8e 5822OP_F_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5823{
5824 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5825 SET_PSR_I (1);
267b3b8e 5826 trace_output_void (sd);
fee8ec00
SR		 5827}
5828
5829/* retx. */
5830void
267b3b8e 5831OP_3_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5832{
5833 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5834 SET_PSR_I (1);
267b3b8e 5835 trace_output_void (sd);
fee8ec00
SR		 5836}
5837
5838/* di. */
5839void
267b3b8e 5840OP_4_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5841{
5842 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5843 SET_PSR_I (1);
267b3b8e 5844 trace_output_void (sd);
fee8ec00
SR		 5845}
5846
5847/* ei. */
5848void
267b3b8e 5849OP_5_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5850{
5851 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5852 SET_PSR_I (1);
267b3b8e 5853 trace_output_void (sd);
fee8ec00
SR		 5854}
5855
5856/* wait. */
5857void
267b3b8e 5858OP_6_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5859{
5860 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5861 trace_output_void (sd);
0ef7f981 5862 EXCEPTION (SIM_SIGTRAP);
fee8ec00
SR		 5863}
5864
5865/* ewait. */
5866void
267b3b8e 5867OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5868{
5869 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5870 SET_PSR_I (1);
267b3b8e 5871 trace_output_void (sd);
fee8ec00
SR		 5872}
5873
5874/* xorb. */
5875void
267b3b8e 5876OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5877{
5878 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5879 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5880 tmp = a ^ b;
5881 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5882 trace_output_16 (sd, tmp);
fee8ec00
SR		 5883}
5884
5885/* xorb. */
5886void
267b3b8e 5887OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5888{
5889 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5890 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5891 tmp = a ^ b;
5892 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5893 trace_output_16 (sd, tmp);
fee8ec00
SR		 5894}
5895
5896/* xorb. */
5897void
267b3b8e 5898OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5899{
5900 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5901 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5902 tmp = a ^ b;
5903 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5904 trace_output_16 (sd, tmp);
fee8ec00
SR		 5905}
5906
5907/* xorw. */
5908void
267b3b8e 5909OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5910{
5911 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5912 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5913 tmp = a ^ b;
5914 SET_GPR (OP[1], tmp);
267b3b8e 5915 trace_output_16 (sd, tmp);
fee8ec00
SR		 5916}
5917
5918/* xorw. */
5919void
267b3b8e 5920OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5921{
5922 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5923 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5924 tmp = a ^ b;
5925 SET_GPR (OP[1], tmp);
267b3b8e 5926 trace_output_16 (sd, tmp);
fee8ec00
SR		 5927}
5928
5929/* xorw. */
5930void
267b3b8e 5931OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5932{
5933 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5934 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5935 tmp = a ^ b;
5936 SET_GPR (OP[1], tmp);
267b3b8e 5937 trace_output_16 (sd, tmp);
fee8ec00
SR		 5938}
5939
5940/*REVISIT FOR LPR/SPR . */
5941
5942/* lpr. */
5943void
267b3b8e 5944OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5945{
5946 uint16 a = GPR (OP[0]);
5947 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5948 SET_CREG (OP[1], a);
267b3b8e 5949 trace_output_16 (sd, a);
fee8ec00
SR		 5950}
5951
5952/* lprd. */
5953void
267b3b8e 5954OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5955{
5956 uint32 a = GPR32 (OP[0]);
5957 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5958 SET_CREG (OP[1], a);
267b3b8e 5959 trace_output_flag (sd);
fee8ec00
SR		 5960}
5961
5962/* spr. */
5963void
267b3b8e 5964OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5965{
5966 uint16 a = CREG (OP[0]);
5967 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5968 SET_GPR (OP[1], a);
267b3b8e 5969 trace_output_16 (sd, a);
fee8ec00
SR		 5970}
5971
5972/* sprd. */
5973void
267b3b8e 5974OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5975{
5976 uint32 a = CREG (OP[0]);
5977 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
5978 SET_GPR32 (OP[1], a);
267b3b8e 5979 trace_output_32 (sd, a);
fee8ec00
SR		 5980}
5981
5982/* null. */
5983void
267b3b8e 5984OP_0_20 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5985{
5986 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
0ef7f981 5987 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
fee8ec00 5988}
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