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[thirdparty/binutils-gdb.git] / sim / cris / cpuv10.h
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f6bcefef
HPN		 1/* CPU family header for crisv10f.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
c9b3544a 5Copyright 1996-2007 Free Software Foundation, Inc.
f6bcefef
HPN		 6
7This file is part of the GNU simulators.
8
c9b3544a
HPN		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
f6bcefef 13
c9b3544a
HPN		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
f6bcefef 18
c9b3544a
HPN		 19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
f6bcefef
HPN		 22
23*/
24
25#ifndef CPU_CRISV10F_H
26#define CPU_CRISV10F_H
27
28/* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30#define MAX_LIW_INSNS 1
31
32/* Maximum number of instructions that can be executed in parallel. */
33#define MAX_PARALLEL_INSNS 1
34
35/* CPU state information. */
36typedef struct {
37 /* Hardware elements. */
38 struct {
39 /* program counter */
40 USI h_pc;
41#define GET_H_PC() CPU (h_pc)
42#define SET_H_PC(x) \
43do { \
44CPU (h_pc) = ANDSI ((x), (~ (1)));\
45;} while (0)
46 /* General purpose registers */
47 SI h_gr_real_pc[16];
48#define GET_H_GR_REAL_PC(a1) CPU (h_gr_real_pc)[a1]
49#define SET_H_GR_REAL_PC(a1, x) (CPU (h_gr_real_pc)[a1] = (x))
50 /* Special registers for v10 */
51 SI h_sr_v10[16];
52#define GET_H_SR_V10(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (10) : (ORIF (((index) == (((UINT) 5))), ((index) == (((UINT) 13))))) ? (ORSI (ANDSI (CPU (h_sr_v10[((UINT) 5)]), 0xffffff00), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), 0)))))))))) : (CPU (h_sr_v10[index]))
53#define SET_H_SR_V10(index, x) \
54do { \
55if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
56((void) 0); /*nop*/\
57}\
58 else if (ORIF ((((index)) == (((UINT) 5))), (((index)) == (((UINT) 13))))) {\
59{\
60CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
61CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
62CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
63CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
64CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
65SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
66SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
67CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
68CPU (h_sr_v10[((UINT) 5)]) = (x);\
69CPU (h_sr_v10[((UINT) 13)]) = (x);\
70}\
71}\
72 else {\
73CPU (h_sr_v10[(index)]) = (x);\
74}\
75;} while (0)
76 /* carry bit */
77 BI h_cbit;
78#define GET_H_CBIT() CPU (h_cbit)
79#define SET_H_CBIT(x) (CPU (h_cbit) = (x))
80 /* overflow bit */
81 BI h_vbit;
82#define GET_H_VBIT() CPU (h_vbit)
83#define SET_H_VBIT(x) (CPU (h_vbit) = (x))
84 /* zero bit */
85 BI h_zbit;
86#define GET_H_ZBIT() CPU (h_zbit)
87#define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
88 /* sign bit */
89 BI h_nbit;
90#define GET_H_NBIT() CPU (h_nbit)
91#define SET_H_NBIT(x) (CPU (h_nbit) = (x))
92 /* extended-arithmetic bit */
93 BI h_xbit;
94#define GET_H_XBIT() CPU (h_xbit)
95#define SET_H_XBIT(x) (CPU (h_xbit) = (x))
96 /* interrupt-enable bit */
97 BI h_ibit_pre_v32;
98#define GET_H_IBIT_PRE_V32() CPU (h_ibit_pre_v32)
99#define SET_H_IBIT_PRE_V32(x) (CPU (h_ibit_pre_v32) = (x))
100 /* sequence-broken bit */
101 BI h_pbit;
102#define GET_H_PBIT() CPU (h_pbit)
103#define SET_H_PBIT(x) (CPU (h_pbit) = (x))
104 /* user mode bit */
105 BI h_ubit_pre_v32;
106#define GET_H_UBIT_PRE_V32() CPU (h_ubit_pre_v32)
107#define SET_H_UBIT_PRE_V32(x) (CPU (h_ubit_pre_v32) = (x))
108 /* instruction-is-prefixed bit */
109 BI h_insn_prefixed_p_pre_v32;
110#define GET_H_INSN_PREFIXED_P_PRE_V32() CPU (h_insn_prefixed_p_pre_v32)
111#define SET_H_INSN_PREFIXED_P_PRE_V32(x) (CPU (h_insn_prefixed_p_pre_v32) = (x))
112 /* Prefix-address register */
113 SI h_prefixreg_pre_v32;
114#define GET_H_PREFIXREG_PRE_V32() CPU (h_prefixreg_pre_v32)
115#define SET_H_PREFIXREG_PRE_V32(x) (CPU (h_prefixreg_pre_v32) = (x))
116 } hardware;
117#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
118} CRISV10F_CPU_DATA;
119
120/* Virtual regs. */
121
122#define GET_H_V32_NON_V32() 0
123#define SET_H_V32_NON_V32(x) \
124do { \
125cgen_rtx_error (current_cpu, "Can't set h-v32");\
126;} while (0)
127#define GET_H_GR(index) GET_H_GR_PC (index)
128#define SET_H_GR(index, x) \
129do { \
130SET_H_GR_PC ((index), (x));\
131;} while (0)
132#define GET_H_GR_PC(index) ((((index) == (15))) ? ((cgen_rtx_error (current_cpu, "General register read of PC is not implemented."), 0)) : (CPU (h_gr_real_pc[index])))
133#define SET_H_GR_PC(index, x) \
134do { \
135{\
136if ((((index)) == (15))) {\
137cgen_rtx_error (current_cpu, "General register write to PC is not implemented.");\
138}\
139CPU (h_gr_real_pc[(index)]) = (x);\
140}\
141;} while (0)
142#define GET_H_RAW_GR_PC(index) CPU (h_gr_real_pc[index])
143#define SET_H_RAW_GR_PC(index, x) \
144do { \
145CPU (h_gr_real_pc[(index)]) = (x);\
146;} while (0)
147#define GET_H_SR(index) GET_H_SR_V10 (index)
148#define SET_H_SR(index, x) \
149do { \
150SET_H_SR_V10 ((index), (x));\
151;} while (0)
152#define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_PRE_V32 ()
153#define SET_H_CBIT_MOVE(x) \
154do { \
155SET_H_CBIT_MOVE_PRE_V32 ((x));\
156;} while (0)
157#define GET_H_CBIT_MOVE_PRE_V32() CPU (h_cbit)
158#define SET_H_CBIT_MOVE_PRE_V32(x) \
159do { \
160CPU (h_cbit) = (x);\
161;} while (0)
162#define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_PRE_V32 ()
163#define SET_H_VBIT_MOVE(x) \
164do { \
165SET_H_VBIT_MOVE_PRE_V32 ((x));\
166;} while (0)
167#define GET_H_VBIT_MOVE_PRE_V32() CPU (h_vbit)
168#define SET_H_VBIT_MOVE_PRE_V32(x) \
169do { \
170CPU (h_vbit) = (x);\
171;} while (0)
172#define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_PRE_V32 ()
173#define SET_H_ZBIT_MOVE(x) \
174do { \
175SET_H_ZBIT_MOVE_PRE_V32 ((x));\
176;} while (0)
177#define GET_H_ZBIT_MOVE_PRE_V32() CPU (h_zbit)
178#define SET_H_ZBIT_MOVE_PRE_V32(x) \
179do { \
180CPU (h_zbit) = (x);\
181;} while (0)
182#define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_PRE_V32 ()
183#define SET_H_NBIT_MOVE(x) \
184do { \
185SET_H_NBIT_MOVE_PRE_V32 ((x));\
186;} while (0)
187#define GET_H_NBIT_MOVE_PRE_V32() CPU (h_nbit)
188#define SET_H_NBIT_MOVE_PRE_V32(x) \
189do { \
190CPU (h_nbit) = (x);\
191;} while (0)
192#define GET_H_IBIT() CPU (h_ibit_pre_v32)
193#define SET_H_IBIT(x) \
194do { \
195CPU (h_ibit_pre_v32) = (x);\
196;} while (0)
197#define GET_H_UBIT() CPU (h_ubit_pre_v32)
198#define SET_H_UBIT(x) \
199do { \
200CPU (h_ubit_pre_v32) = (x);\
201;} while (0)
202#define GET_H_INSN_PREFIXED_P() CPU (h_insn_prefixed_p_pre_v32)
203#define SET_H_INSN_PREFIXED_P(x) \
204do { \
205CPU (h_insn_prefixed_p_pre_v32) = (x);\
206;} while (0)
207
208/* Cover fns for register access. */
209BI crisv10f_h_v32_non_v32_get (SIM_CPU *);
210void crisv10f_h_v32_non_v32_set (SIM_CPU *, BI);
211USI crisv10f_h_pc_get (SIM_CPU *);
212void crisv10f_h_pc_set (SIM_CPU *, USI);
213SI crisv10f_h_gr_get (SIM_CPU *, UINT);
214void crisv10f_h_gr_set (SIM_CPU *, UINT, SI);
215SI crisv10f_h_gr_pc_get (SIM_CPU *, UINT);
216void crisv10f_h_gr_pc_set (SIM_CPU *, UINT, SI);
217SI crisv10f_h_gr_real_pc_get (SIM_CPU *, UINT);
218void crisv10f_h_gr_real_pc_set (SIM_CPU *, UINT, SI);
219SI crisv10f_h_raw_gr_pc_get (SIM_CPU *, UINT);
220void crisv10f_h_raw_gr_pc_set (SIM_CPU *, UINT, SI);
221SI crisv10f_h_sr_get (SIM_CPU *, UINT);
222void crisv10f_h_sr_set (SIM_CPU *, UINT, SI);
223SI crisv10f_h_sr_v10_get (SIM_CPU *, UINT);
224void crisv10f_h_sr_v10_set (SIM_CPU *, UINT, SI);
225BI crisv10f_h_cbit_get (SIM_CPU *);
226void crisv10f_h_cbit_set (SIM_CPU *, BI);
227BI crisv10f_h_cbit_move_get (SIM_CPU *);
228void crisv10f_h_cbit_move_set (SIM_CPU *, BI);
229BI crisv10f_h_cbit_move_pre_v32_get (SIM_CPU *);
230void crisv10f_h_cbit_move_pre_v32_set (SIM_CPU *, BI);
231BI crisv10f_h_vbit_get (SIM_CPU *);
232void crisv10f_h_vbit_set (SIM_CPU *, BI);
233BI crisv10f_h_vbit_move_get (SIM_CPU *);
234void crisv10f_h_vbit_move_set (SIM_CPU *, BI);
235BI crisv10f_h_vbit_move_pre_v32_get (SIM_CPU *);
236void crisv10f_h_vbit_move_pre_v32_set (SIM_CPU *, BI);
237BI crisv10f_h_zbit_get (SIM_CPU *);
238void crisv10f_h_zbit_set (SIM_CPU *, BI);
239BI crisv10f_h_zbit_move_get (SIM_CPU *);
240void crisv10f_h_zbit_move_set (SIM_CPU *, BI);
241BI crisv10f_h_zbit_move_pre_v32_get (SIM_CPU *);
242void crisv10f_h_zbit_move_pre_v32_set (SIM_CPU *, BI);
243BI crisv10f_h_nbit_get (SIM_CPU *);
244void crisv10f_h_nbit_set (SIM_CPU *, BI);
245BI crisv10f_h_nbit_move_get (SIM_CPU *);
246void crisv10f_h_nbit_move_set (SIM_CPU *, BI);
247BI crisv10f_h_nbit_move_pre_v32_get (SIM_CPU *);
248void crisv10f_h_nbit_move_pre_v32_set (SIM_CPU *, BI);
249BI crisv10f_h_xbit_get (SIM_CPU *);
250void crisv10f_h_xbit_set (SIM_CPU *, BI);
251BI crisv10f_h_ibit_get (SIM_CPU *);
252void crisv10f_h_ibit_set (SIM_CPU *, BI);
253BI crisv10f_h_ibit_pre_v32_get (SIM_CPU *);
254void crisv10f_h_ibit_pre_v32_set (SIM_CPU *, BI);
255BI crisv10f_h_pbit_get (SIM_CPU *);
256void crisv10f_h_pbit_set (SIM_CPU *, BI);
257BI crisv10f_h_ubit_get (SIM_CPU *);
258void crisv10f_h_ubit_set (SIM_CPU *, BI);
259BI crisv10f_h_ubit_pre_v32_get (SIM_CPU *);
260void crisv10f_h_ubit_pre_v32_set (SIM_CPU *, BI);
261BI crisv10f_h_insn_prefixed_p_get (SIM_CPU *);
262void crisv10f_h_insn_prefixed_p_set (SIM_CPU *, BI);
263BI crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU *);
264void crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU *, BI);
265SI crisv10f_h_prefixreg_pre_v32_get (SIM_CPU *);
266void crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *, SI);
267
268/* These must be hand-written. */
269extern CPUREG_FETCH_FN crisv10f_fetch_register;
270extern CPUREG_STORE_FN crisv10f_store_register;
271
272typedef struct {
273 int empty;
274} MODEL_CRISV10_DATA;
275
276/* Instruction argument buffer. */
277
278union sem_fields {
279 struct { /* no operands */
280 int empty;
281 } fmt_empty;
282 struct { /* */
283 UINT f_u4;
284 } sfmt_break;
285 struct { /* */
286 UINT f_dstsrc;
287 } sfmt_setf;
288 struct { /* */
289 IADDR i_o_word_pcrel;
290 UINT f_operand2;
291 } sfmt_bcc_w;
292 struct { /* */
293 IADDR i_o_pcrel;
294 UINT f_operand2;
295 } sfmt_bcc_b;
392753ae
HPN		 296 struct { /* */
297 UINT f_memmode;
298 unsigned char in_h_gr_SI_14;
299 unsigned char out_h_gr_SI_14;
300 } sfmt_move_m_spplus_p8;
f6bcefef
HPN		 301 struct { /* */
302 INT f_s8;
303 UINT f_operand2;
304 unsigned char in_Rd;
305 } sfmt_addoq;
306 struct { /* */
307 INT f_indir_pc__dword;
308 UINT f_operand2;
309 unsigned char out_Pd;
392753ae 310 } sfmt_move_c_sprv10_p9;
f6bcefef
HPN		 311 struct { /* */
312 INT f_indir_pc__word;
313 UINT f_operand2;
314 unsigned char out_Pd;
392753ae 315 } sfmt_move_c_sprv10_p5;
f6bcefef
HPN		 316 struct { /* */
317 INT f_s6;
318 UINT f_operand2;
319 unsigned char out_Rd;
320 } sfmt_moveq;
321 struct { /* */
322 INT f_indir_pc__dword;
323 UINT f_operand2;
324 unsigned char in_Rd;
325 unsigned char out_Rd;
326 } sfmt_bound_cd;
327 struct { /* */
328 INT f_indir_pc__word;
329 UINT f_operand2;
330 unsigned char in_Rd;
331 unsigned char out_Rd;
332 } sfmt_bound_cw;
333 struct { /* */
334 INT f_indir_pc__byte;
335 UINT f_operand2;
336 unsigned char in_Rd;
337 unsigned char out_Rd;
338 } sfmt_bound_cb;
339 struct { /* */
340 UINT f_operand2;
341 UINT f_u5;
342 unsigned char in_Rd;
343 unsigned char out_Rd;
344 } sfmt_asrq;
345 struct { /* */
346 INT f_s6;
347 UINT f_operand2;
348 unsigned char in_Rd;
349 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
350 } sfmt_andq;
351 struct { /* */
352 INT f_indir_pc__dword;
353 UINT f_operand2;
354 unsigned char in_Rd;
355 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
356 } sfmt_addcdr;
357 struct { /* */
358 INT f_indir_pc__word;
359 UINT f_operand2;
360 unsigned char in_Rd;
361 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
362 } sfmt_addcwr;
363 struct { /* */
364 INT f_indir_pc__byte;
365 UINT f_operand2;
366 unsigned char in_Rd;
367 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
368 } sfmt_addcbr;
369 struct { /* */
370 UINT f_operand1;
371 UINT f_operand2;
372 unsigned char in_Ps;
373 unsigned char out_h_gr_SI_index_of__DFLT_Rs;
374 } sfmt_move_spr_rv10;
375 struct { /* */
376 UINT f_operand2;
377 UINT f_u6;
378 unsigned char in_Rd;
379 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
380 } sfmt_addq;
381 struct { /* */
382 UINT f_operand1;
383 UINT f_operand2;
384 unsigned char in_Rd;
385 unsigned char in_Rs;
386 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
387 } sfmt_add_b_r;
388 struct { /* */
389 UINT f_operand1;
390 UINT f_operand2;
391 unsigned char in_Rd;
392 unsigned char in_Rs;
393 unsigned char out_Rd;
394 unsigned char out_h_sr_SI_7;
395 } sfmt_muls_b;
396 struct { /* */
397 UINT f_memmode;
398 UINT f_operand1;
399 UINT f_operand2;
400 unsigned char in_Ps;
401 unsigned char in_Rs;
402 unsigned char out_Rs;
403 } sfmt_move_spr_mv10;
404 struct { /* */
405 UINT f_memmode;
406 UINT f_operand1;
407 UINT f_operand2;
408 unsigned char in_Rs;
409 unsigned char out_Pd;
410 unsigned char out_Rs;
411 } sfmt_move_m_sprv10;
412 struct { /* */
413 UINT f_memmode;
414 UINT f_operand1;
415 UINT f_operand2;
416 unsigned char in_Rd;
417 unsigned char in_Rs;
418 unsigned char out_Rd;
419 unsigned char out_Rs;
420 } sfmt_bound_m_b_m;
421 struct { /* */
422 UINT f_memmode;
423 UINT f_operand1;
424 UINT f_operand2;
425 unsigned char in_Rd;
426 unsigned char in_Rs;
427 unsigned char out_Rs;
428 unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
429 } sfmt_add_m_b_m;
430 struct { /* */
431 UINT f_memmode;
432 UINT f_operand1;
433 UINT f_operand2;
434 unsigned char in_Rd;
435 unsigned char in_Rs;
436 unsigned char out_Rs;
437 unsigned char out_h_gr_SI_0;
438 unsigned char out_h_gr_SI_1;
439 unsigned char out_h_gr_SI_10;
440 unsigned char out_h_gr_SI_11;
441 unsigned char out_h_gr_SI_12;
442 unsigned char out_h_gr_SI_13;
443 unsigned char out_h_gr_SI_14;
444 unsigned char out_h_gr_SI_2;
445 unsigned char out_h_gr_SI_3;
446 unsigned char out_h_gr_SI_4;
447 unsigned char out_h_gr_SI_5;
448 unsigned char out_h_gr_SI_6;
449 unsigned char out_h_gr_SI_7;
450 unsigned char out_h_gr_SI_8;
451 unsigned char out_h_gr_SI_9;
452 } sfmt_movem_m_r;
453 struct { /* */
454 UINT f_memmode;
455 UINT f_operand1;
456 UINT f_operand2;
457 unsigned char in_Rd;
458 unsigned char in_Rs;
459 unsigned char in_h_gr_SI_0;
460 unsigned char in_h_gr_SI_1;
461 unsigned char in_h_gr_SI_10;
462 unsigned char in_h_gr_SI_11;
463 unsigned char in_h_gr_SI_12;
464 unsigned char in_h_gr_SI_13;
465 unsigned char in_h_gr_SI_14;
466 unsigned char in_h_gr_SI_15;
467 unsigned char in_h_gr_SI_2;
468 unsigned char in_h_gr_SI_3;
469 unsigned char in_h_gr_SI_4;
470 unsigned char in_h_gr_SI_5;
471 unsigned char in_h_gr_SI_6;
472 unsigned char in_h_gr_SI_7;
473 unsigned char in_h_gr_SI_8;
474 unsigned char in_h_gr_SI_9;
475 unsigned char out_Rs;
476 } sfmt_movem_r_m;
477#if WITH_SCACHE_PBB
478 /* Writeback handler. */
479 struct {
480 /* Pointer to argbuf entry for insn whose results need writing back. */
481 const struct argbuf *abuf;
482 } write;
483 /* x-before handler */
484 struct {
485 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
486 int first_p;
487 } before;
488 /* x-after handler */
489 struct {
490 int empty;
491 } after;
492 /* This entry is used to terminate each pbb. */
493 struct {
494 /* Number of insns in pbb. */
495 int insn_count;
496 /* Next pbb to execute. */
497 SCACHE *next;
498 SCACHE *branch_target;
499 } chain;
500#endif
501};
502
503/* The ARGBUF struct. */
504struct argbuf {
505 /* These are the baseclass definitions. */
506 IADDR addr;
507 const IDESC *idesc;
508 char trace_p;
509 char profile_p;
510 /* ??? Temporary hack for skip insns. */
511 char skip_count;
512 char unused;
513 /* cpu specific data follows */
514 union sem semantic;
515 int written;
516 union sem_fields fields;
517};
518
519/* A cached insn.
520
521 ??? SCACHE used to contain more than just argbuf. We could delete the
522 type entirely and always just use ARGBUF, but for future concerns and as
523 a level of abstraction it is left in. */
524
525struct scache {
526 struct argbuf argbuf;
527};
528
529/* Macros to simplify extraction, reading and semantic code.
530 These define and assign the local vars that contain the insn's fields. */
531
532#define EXTRACT_IFMT_EMPTY_VARS \
533 unsigned int length;
534#define EXTRACT_IFMT_EMPTY_CODE \
535 length = 0; \
536
537#define EXTRACT_IFMT_NOP_VARS \
538 UINT f_operand2; \
539 UINT f_mode; \
540 UINT f_opcode; \
541 UINT f_size; \
542 UINT f_operand1; \
543 unsigned int length;
544#define EXTRACT_IFMT_NOP_CODE \
545 length = 2; \
546 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
547 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
548 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
549 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
550 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
551
552#define EXTRACT_IFMT_MOVE_B_R_VARS \
553 UINT f_operand2; \
554 UINT f_mode; \
555 UINT f_opcode; \
556 UINT f_size; \
557 UINT f_operand1; \
558 unsigned int length;
559#define EXTRACT_IFMT_MOVE_B_R_CODE \
560 length = 2; \
561 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
562 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
563 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
564 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
565 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
566
567#define EXTRACT_IFMT_MOVEPCR_VARS \
568 UINT f_operand2; \
569 UINT f_mode; \
570 UINT f_opcode; \
571 UINT f_size; \
572 UINT f_operand1; \
573 unsigned int length;
574#define EXTRACT_IFMT_MOVEPCR_CODE \
575 length = 2; \
576 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
577 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
578 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
579 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
580 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
581
582#define EXTRACT_IFMT_MOVEQ_VARS \
583 UINT f_operand2; \
584 UINT f_mode; \
585 UINT f_opcode; \
586 INT f_s6; \
587 unsigned int length;
588#define EXTRACT_IFMT_MOVEQ_CODE \
589 length = 2; \
590 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
591 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
592 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
593 f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
594
595#define EXTRACT_IFMT_MOVECBR_VARS \
596 UINT f_operand2; \
597 INT f_indir_pc__byte; \
598 UINT f_mode; \
599 UINT f_opcode; \
600 UINT f_size; \
601 UINT f_operand1; \
602 /* Contents of trailing part of insn. */ \
603 UINT word_1; \
604 unsigned int length;
605#define EXTRACT_IFMT_MOVECBR_CODE \
606 length = 4; \
cf2bf87e 607 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
f6bcefef 608 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
cf2bf87e 609 f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
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HPN		 610 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
611 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
612 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
613 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
614
615#define EXTRACT_IFMT_MOVECWR_VARS \
616 UINT f_operand2; \
617 INT f_indir_pc__word; \
618 UINT f_mode; \
619 UINT f_opcode; \
620 UINT f_size; \
621 UINT f_operand1; \
622 /* Contents of trailing part of insn. */ \
623 UINT word_1; \
624 unsigned int length;
625#define EXTRACT_IFMT_MOVECWR_CODE \
626 length = 4; \
cf2bf87e 627 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
f6bcefef 628 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
cf2bf87e 629 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
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HPN		 630 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
631 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
632 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
633 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
634
635#define EXTRACT_IFMT_MOVECDR_VARS \
636 INT f_indir_pc__dword; \
637 UINT f_operand2; \
638 UINT f_mode; \
639 UINT f_opcode; \
640 UINT f_size; \
641 UINT f_operand1; \
642 /* Contents of trailing part of insn. */ \
643 UINT word_1; \
644 unsigned int length;
645#define EXTRACT_IFMT_MOVECDR_CODE \
646 length = 6; \
647 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
648 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
649 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
650 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
651 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
652 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
653 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
654
655#define EXTRACT_IFMT_MOVUCBR_VARS \
656 UINT f_operand2; \
657 INT f_indir_pc__byte; \
658 UINT f_mode; \
659 UINT f_opcode; \
660 UINT f_size; \
661 UINT f_operand1; \
662 /* Contents of trailing part of insn. */ \
663 UINT word_1; \
664 unsigned int length;
665#define EXTRACT_IFMT_MOVUCBR_CODE \
666 length = 4; \
cf2bf87e 667 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
f6bcefef 668 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
cf2bf87e 669 f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
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HPN		 670 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
671 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
672 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
673 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
674
675#define EXTRACT_IFMT_MOVUCWR_VARS \
676 UINT f_operand2; \
677 INT f_indir_pc__word; \
678 UINT f_mode; \
679 UINT f_opcode; \
680 UINT f_size; \
681 UINT f_operand1; \
682 /* Contents of trailing part of insn. */ \
683 UINT word_1; \
684 unsigned int length;
685#define EXTRACT_IFMT_MOVUCWR_CODE \
686 length = 4; \
cf2bf87e 687 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
f6bcefef 688 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
cf2bf87e 689 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
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HPN		 690 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
691 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
692 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
693 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
694
695#define EXTRACT_IFMT_ADDQ_VARS \
696 UINT f_operand2; \
697 UINT f_mode; \
698 UINT f_opcode; \
699 UINT f_u6; \
700 unsigned int length;
701#define EXTRACT_IFMT_ADDQ_CODE \
702 length = 2; \
703 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
704 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
705 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
706 f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
707
708#define EXTRACT_IFMT_CMP_M_B_M_VARS \
709 UINT f_operand2; \
710 UINT f_membit; \
711 UINT f_memmode; \
712 UINT f_opcode; \
713 UINT f_size; \
714 UINT f_operand1; \
715 unsigned int length;
716#define EXTRACT_IFMT_CMP_M_B_M_CODE \
717 length = 2; \
718 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
719 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
720 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
721 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
722 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
723 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
724
725#define EXTRACT_IFMT_MOVE_R_SPRV10_VARS \
726 UINT f_operand2; \
727 UINT f_mode; \
728 UINT f_opcode; \
729 UINT f_size; \
730 UINT f_operand1; \
731 unsigned int length;
732#define EXTRACT_IFMT_MOVE_R_SPRV10_CODE \
733 length = 2; \
734 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
735 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
736 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
737 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
738 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
739
740#define EXTRACT_IFMT_MOVE_SPR_RV10_VARS \
741 UINT f_operand2; \
742 UINT f_mode; \
743 UINT f_opcode; \
744 UINT f_size; \
745 UINT f_operand1; \
746 unsigned int length;
747#define EXTRACT_IFMT_MOVE_SPR_RV10_CODE \
748 length = 2; \
749 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
750 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
751 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
752 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
753 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
754
755#define EXTRACT_IFMT_RET_TYPE_VARS \
756 UINT f_operand2; \
757 UINT f_mode; \
758 UINT f_opcode; \
759 UINT f_size; \
760 UINT f_operand1; \
761 unsigned int length;
762#define EXTRACT_IFMT_RET_TYPE_CODE \
763 length = 2; \
764 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
765 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
766 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
767 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
768 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
769
770#define EXTRACT_IFMT_MOVE_M_SPRV10_VARS \
771 UINT f_operand2; \
772 UINT f_membit; \
773 UINT f_memmode; \
774 UINT f_opcode; \
775 UINT f_size; \
776 UINT f_operand1; \
777 unsigned int length;
778#define EXTRACT_IFMT_MOVE_M_SPRV10_CODE \
779 length = 2; \
780 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
781 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
782 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
783 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
784 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
785 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
786
392753ae 787#define EXTRACT_IFMT_MOVE_C_SPRV10_P5_VARS \
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HPN		 788 UINT f_operand2; \
789 INT f_indir_pc__word; \
790 UINT f_mode; \
791 UINT f_opcode; \
792 UINT f_size; \
793 UINT f_operand1; \
794 /* Contents of trailing part of insn. */ \
795 UINT word_1; \
796 unsigned int length;
392753ae 797#define EXTRACT_IFMT_MOVE_C_SPRV10_P5_CODE \
f6bcefef 798 length = 4; \
cf2bf87e 799 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
f6bcefef 800 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
cf2bf87e 801 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
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HPN		 802 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
803 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
804 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
805 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
806
392753ae 807#define EXTRACT_IFMT_MOVE_C_SPRV10_P9_VARS \
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HPN		 808 INT f_indir_pc__dword; \
809 UINT f_operand2; \
810 UINT f_mode; \
811 UINT f_opcode; \
812 UINT f_size; \
813 UINT f_operand1; \
814 /* Contents of trailing part of insn. */ \
815 UINT word_1; \
816 unsigned int length;
392753ae 817#define EXTRACT_IFMT_MOVE_C_SPRV10_P9_CODE \
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HPN		 818 length = 6; \
819 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
820 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
821 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
822 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
823 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
824 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
825 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
826
827#define EXTRACT_IFMT_MOVE_SPR_MV10_VARS \
828 UINT f_operand2; \
829 UINT f_membit; \
830 UINT f_memmode; \
831 UINT f_opcode; \
832 UINT f_size; \
833 UINT f_operand1; \
834 unsigned int length;
835#define EXTRACT_IFMT_MOVE_SPR_MV10_CODE \
836 length = 2; \
837 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
838 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
839 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
840 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
841 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
842 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
843
844#define EXTRACT_IFMT_SBFS_VARS \
845 UINT f_operand2; \
846 UINT f_membit; \
847 UINT f_memmode; \
848 UINT f_opcode; \
849 UINT f_size; \
850 UINT f_operand1; \
851 unsigned int length;
852#define EXTRACT_IFMT_SBFS_CODE \
853 length = 2; \
854 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
855 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
856 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
857 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
858 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
859 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
860
861#define EXTRACT_IFMT_SWAP_VARS \
862 UINT f_operand2; \
863 UINT f_mode; \
864 UINT f_opcode; \
865 UINT f_size; \
866 UINT f_operand1; \
867 unsigned int length;
868#define EXTRACT_IFMT_SWAP_CODE \
869 length = 2; \
870 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
871 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
872 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
873 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
874 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
875
876#define EXTRACT_IFMT_ASRQ_VARS \
877 UINT f_operand2; \
878 UINT f_mode; \
879 UINT f_opcode; \
880 UINT f_b5; \
881 UINT f_u5; \
882 unsigned int length;
883#define EXTRACT_IFMT_ASRQ_CODE \
884 length = 2; \
885 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
886 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
887 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
888 f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
889 f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
890
891#define EXTRACT_IFMT_SETF_VARS \
892 UINT f_mode; \
893 UINT f_opcode; \
894 UINT f_size; \
895 UINT f_operand2; \
896 UINT f_operand1; \
897 UINT f_dstsrc; \
898 unsigned int length;
899#define EXTRACT_IFMT_SETF_CODE \
900 length = 2; \
901 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
902 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
903 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
904 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
905 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
906 f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
907
908#define EXTRACT_IFMT_BCC_B_VARS \
909 UINT f_operand2; \
910 UINT f_mode; \
911 UINT f_opcode_hi; \
912 INT f_disp9_hi; \
913 UINT f_disp9_lo; \
914 INT f_disp9; \
915 unsigned int length;
916#define EXTRACT_IFMT_BCC_B_CODE \
917 length = 2; \
918 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
919 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
920 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
921 f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
922 f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
923{\
924 SI tmp_abslo;\
925 SI tmp_absval;\
926 tmp_abslo = ((f_disp9_lo) << (1));\
927 tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
928 f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
929}\
930
931#define EXTRACT_IFMT_BA_B_VARS \
932 UINT f_operand2; \
933 UINT f_mode; \
934 UINT f_opcode_hi; \
935 INT f_disp9_hi; \
936 UINT f_disp9_lo; \
937 INT f_disp9; \
938 unsigned int length;
939#define EXTRACT_IFMT_BA_B_CODE \
940 length = 2; \
941 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
942 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
943 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
944 f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
945 f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
946{\
947 SI tmp_abslo;\
948 SI tmp_absval;\
949 tmp_abslo = ((f_disp9_lo) << (1));\
950 tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
951 f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
952}\
953
954#define EXTRACT_IFMT_BCC_W_VARS \
955 UINT f_operand2; \
956 SI f_indir_pc__word_pcrel; \
957 UINT f_mode; \
958 UINT f_opcode; \
959 UINT f_size; \
960 UINT f_operand1; \
961 /* Contents of trailing part of insn. */ \
962 UINT word_1; \
963 unsigned int length;
964#define EXTRACT_IFMT_BCC_W_CODE \
965 length = 4; \
cf2bf87e 966 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
f6bcefef 967 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
cf2bf87e 968 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
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HPN		 969 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
970 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
971 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
972 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
973
974#define EXTRACT_IFMT_BA_W_VARS \
975 UINT f_operand2; \
976 SI f_indir_pc__word_pcrel; \
977 UINT f_mode; \
978 UINT f_opcode; \
979 UINT f_size; \
980 UINT f_operand1; \
981 /* Contents of trailing part of insn. */ \
982 UINT word_1; \
983 unsigned int length;
984#define EXTRACT_IFMT_BA_W_CODE \
985 length = 4; \
cf2bf87e 986 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
f6bcefef 987 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
cf2bf87e 988 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
f6bcefef
HPN		 989 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
990 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
991 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
992 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
993
994#define EXTRACT_IFMT_JUMP_C_VARS \
995 INT f_indir_pc__dword; \
996 UINT f_operand2; \
997 UINT f_mode; \
998 UINT f_opcode; \
999 UINT f_size; \
1000 UINT f_operand1; \
1001 /* Contents of trailing part of insn. */ \
1002 UINT word_1; \
1003 unsigned int length;
1004#define EXTRACT_IFMT_JUMP_C_CODE \
1005 length = 6; \
1006 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1007 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
1008 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1009 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1010 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1011 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1012 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1013
1014#define EXTRACT_IFMT_BREAK_VARS \
1015 UINT f_operand2; \
1016 UINT f_mode; \
1017 UINT f_opcode; \
1018 UINT f_size; \
1019 UINT f_u4; \
1020 unsigned int length;
1021#define EXTRACT_IFMT_BREAK_CODE \
1022 length = 2; \
1023 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1024 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1025 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1026 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1027 f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1028
1029#define EXTRACT_IFMT_SCC_VARS \
1030 UINT f_operand2; \
1031 UINT f_mode; \
1032 UINT f_opcode; \
1033 UINT f_size; \
1034 UINT f_operand1; \
1035 unsigned int length;
1036#define EXTRACT_IFMT_SCC_CODE \
1037 length = 2; \
1038 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1039 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1040 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1041 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1042 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1043
1044#define EXTRACT_IFMT_ADDOQ_VARS \
1045 UINT f_operand2; \
1046 UINT f_mode; \
1047 UINT f_opcode_hi; \
1048 INT f_s8; \
1049 unsigned int length;
1050#define EXTRACT_IFMT_ADDOQ_CODE \
1051 length = 2; \
1052 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1053 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1054 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1055 f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1056
1057#define EXTRACT_IFMT_BDAPQPC_VARS \
1058 UINT f_operand2; \
1059 UINT f_mode; \
1060 UINT f_opcode_hi; \
1061 INT f_s8; \
1062 unsigned int length;
1063#define EXTRACT_IFMT_BDAPQPC_CODE \
1064 length = 2; \
1065 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1066 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1067 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1068 f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1069
1070/* Collection of various things for the trace handler to use. */
1071
1072typedef struct trace_record {
1073 IADDR pc;
1074 /* FIXME:wip */
1075} TRACE_RECORD;
1076
1077#endif /* CPU_CRISV10F_H */
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