[thirdparty/binutils-gdb.git] / sim / cris / cris-sim.h

/* Collection of junk for CRIS.
   Copyright (C) 2004-2022 Free Software Foundation, Inc.
   Contributed by Axis Communications.

This file is part of the GNU simulators.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* For other arch:s, this file is described as a "collection of junk", so
   let's collect some nice junk of our own.  Keep it; it might be useful
   some day!  */

#ifndef CRIS_SIM_H
#define CRIS_SIM_H

typedef struct {
  /* Whether the branch for the current insn was taken.  Placed first
     here, in hope it'll get closer to the main simulator data.  */
  USI branch_taken;

  /* PC of the insn of the branch.  */
  USI old_pc;

  /* Static cycle count for all insns executed so far, including
     non-context-specific stall cycles, for example when adding to PC.  */
  uint64_t basic_cycle_count;

  /* Stall cycles for unaligned access of memory operands.  FIXME:
     Should or should not include unaligned [PC+] operands?  */
  uint64_t unaligned_mem_dword_count;

  /* Context-specific stall cycles.  */
  uint64_t memsrc_stall_count;
  uint64_t memraw_stall_count;
  uint64_t movemsrc_stall_count;
  uint64_t movemaddr_stall_count;
  uint64_t movemdst_stall_count;
  uint64_t mulsrc_stall_count;
  uint64_t jumpsrc_stall_count;
  uint64_t branch_stall_count;
  uint64_t jumptarget_stall_count;

  /* What kind of target-specific trace to perform.  */
  int flags;

  /* Just the basic cycle count.  */
#define FLAG_CRIS_MISC_PROFILE_SIMPLE 1

  /* Show unaligned accesses.  */
#define FLAG_CRIS_MISC_PROFILE_UNALIGNED 2

  /* Show schedulable entities.  */
#define FLAG_CRIS_MISC_PROFILE_SCHEDULABLE 4

  /* Show everything.  */
#define FLAG_CRIS_MISC_PROFILE_ALL		\
 (FLAG_CRIS_MISC_PROFILE_SIMPLE			\
  | FLAG_CRIS_MISC_PROFILE_UNALIGNED		\
  | FLAG_CRIS_MISC_PROFILE_SCHEDULABLE)

  /* Emit trace of each insn, xsim style.  */
#define FLAG_CRIS_MISC_PROFILE_XSIM_TRACE 8

#define N_CRISV32_BRANCH_PREDICTORS 256
  unsigned char branch_predictors[N_CRISV32_BRANCH_PREDICTORS];

} CRIS_MISC_PROFILE;

/* Handler prototypes for functions called from the CGEN description.  */

extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI);
extern USI crisv10f_break_handler (SIM_CPU *, USI, USI);
extern USI crisv32f_break_handler (SIM_CPU *, USI, USI);
extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI,
				  USI, USI);
extern char cris_have_900000xxif;
enum cris_unknown_syscall_action_type
  { CRIS_USYSC_MSG_STOP, CRIS_USYSC_MSG_ENOSYS, CRIS_USYSC_QUIET_ENOSYS };
extern enum cris_unknown_syscall_action_type cris_unknown_syscall_action;
enum cris_interrupt_type { CRIS_INT_NMI, CRIS_INT_RESET, CRIS_INT_INT };
extern int crisv10deliver_interrupt (SIM_CPU *,
				     enum cris_interrupt_type,
				       unsigned int);
extern int crisv32deliver_interrupt (SIM_CPU *,
				     enum cris_interrupt_type,
				     unsigned int);

/* Using GNU syntax (not C99) so we can compile this on RH 6.2
   (egcs-1.1.2/gcc-2.91.66).  */
#define cris_trace_printf(SD, CPU, FMT...)			\
  do								\
    {								\
      if (TRACE_FILE (STATE_TRACE_DATA (SD)) != NULL)		\
	fprintf (TRACE_FILE (CPU_TRACE_DATA (CPU)), FMT);	\
      else							\
	sim_io_printf (SD, FMT);				\
    }								\
  while (0)

#if WITH_PROFILE_MODEL_P
#define crisv32f_branch_taken(cpu, oldpc, newpc, taken)	\
  do								\
    {								\
      CPU_CRIS_MISC_PROFILE (cpu)->old_pc = oldpc;		\
      CPU_CRIS_MISC_PROFILE (cpu)->branch_taken = taken;	\
    }								\
  while (0)
#else
#define crisv32f_branch_taken(cpu, oldpc, newpc, taken)
#endif

#define crisv10f_branch_taken(cpu, oldpc, newpc, taken)

#define crisv32f_read_supr(cpu, index)				\
 (cgen_rtx_error (current_cpu,					\
		  "Read of support register is unimplemented"),	\
  0)

#define crisv32f_write_supr(cpu, index, val)			\
 cgen_rtx_error (current_cpu,					\
		 "Write to support register is unimplemented")	\

#define crisv32f_rfg_handler(cpu, pc)				\
 cgen_rtx_error (current_cpu, "RFG isn't implemented")

#define crisv32f_halt_handler(cpu, pc)				\
 (cgen_rtx_error (current_cpu, "HALT isn't implemented"), 0)

#define crisv32f_fidxi_handler(cpu, pc, indx)			\
 (cgen_rtx_error (current_cpu, "FIDXI isn't implemented"), 0)

#define crisv32f_ftagi_handler(cpu, pc, indx)			\
 (cgen_rtx_error (current_cpu, "FTAGI isn't implemented"), 0)

#define crisv32f_fidxd_handler(cpu, pc, indx)			\
 (cgen_rtx_error (current_cpu, "FIDXD isn't implemented"), 0)

#define crisv32f_ftagd_handler(cpu, pc, indx)			\
 (cgen_rtx_error (current_cpu, "FTAGD isn't implemented"), 0)

/* We have nothing special to do when interrupts or NMI are enabled
   after having been disabled, so empty macros are enough for these
   hooks.  */
#define crisv32f_interrupts_enabled(cpu)
#define crisv32f_nmi_enabled(cpu)

/* Better warn for this case here, because everything needed is
   somewhere within the CPU.  Compare to trying to use interrupts and
   NMI, which would fail earlier, when trying to make nonexistent
   external components generate those exceptions.  */
#define crisv32f_single_step_enabled(cpu)			\
 ((crisv32f_h_qbit_get (cpu) != 0				\
   || (crisv32f_h_sr_get (cpu, H_SR_SPC) & ~1) != 0)		\
  ? (cgen_rtx_error (cpu,					\
		     "single-stepping isn't implemented"), 0)	\
  : 0)

/* We don't need to track the value of the PID register here.  */
#define crisv32f_write_pid_handler(cpu, val)

/* Neither do we need to know of transitions to user mode.  */
#define crisv32f_usermode_enabled(cpu)

/* House-keeping exported from traps.c  */
extern void cris_set_callbacks (host_callback *);

/* FIXME: Add more junk.  */
#endif
Commit	Line	Data
f6bcefef	1	/* Collection of junk for CRIS.
4a94e368	2	Copyright (C) 2004-2022 Free Software Foundation, Inc.
f6bcefef HPN	3	Contributed by Axis Communications.
	4
	5	This file is part of the GNU simulators.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
f6bcefef HPN	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
f6bcefef HPN	19
	20	/* For other arch:s, this file is described as a "collection of junk", so
	21	let's collect some nice junk of our own. Keep it; it might be useful
	22	some day! */
	23
	24	#ifndef CRIS_SIM_H
	25	#define CRIS_SIM_H
	26
	27	typedef struct {
	28	/* Whether the branch for the current insn was taken. Placed first
	29	here, in hope it'll get closer to the main simulator data. */
	30	USI branch_taken;
	31
	32	/* PC of the insn of the branch. */
	33	USI old_pc;
	34
	35	/* Static cycle count for all insns executed so far, including
	36	non-context-specific stall cycles, for example when adding to PC. */
2875d098	37	uint64_t basic_cycle_count;
f6bcefef HPN	38
	39	/* Stall cycles for unaligned access of memory operands. FIXME:
	40	Should or should not include unaligned [PC+] operands? */
2875d098	41	uint64_t unaligned_mem_dword_count;
f6bcefef HPN	42
f6bcefef HPN	43	/* Context-specific stall cycles. */
2875d098 MF	44	uint64_t memsrc_stall_count;
	45	uint64_t memraw_stall_count;
	46	uint64_t movemsrc_stall_count;
	47	uint64_t movemaddr_stall_count;
	48	uint64_t movemdst_stall_count;
	49	uint64_t mulsrc_stall_count;
	50	uint64_t jumpsrc_stall_count;
	51	uint64_t branch_stall_count;
	52	uint64_t jumptarget_stall_count;
f6bcefef HPN	53
	54	/* What kind of target-specific trace to perform. */
	55	int flags;
	56
	57	/* Just the basic cycle count. */
	58	#define FLAG_CRIS_MISC_PROFILE_SIMPLE 1
	59
	60	/* Show unaligned accesses. */
	61	#define FLAG_CRIS_MISC_PROFILE_UNALIGNED 2
	62
	63	/* Show schedulable entities. */
	64	#define FLAG_CRIS_MISC_PROFILE_SCHEDULABLE 4
	65
	66	/* Show everything. */
	67	#define FLAG_CRIS_MISC_PROFILE_ALL \
	68	(FLAG_CRIS_MISC_PROFILE_SIMPLE \
	69	\| FLAG_CRIS_MISC_PROFILE_UNALIGNED \
	70	\| FLAG_CRIS_MISC_PROFILE_SCHEDULABLE)
	71
	72	/* Emit trace of each insn, xsim style. */
	73	#define FLAG_CRIS_MISC_PROFILE_XSIM_TRACE 8
	74
	75	#define N_CRISV32_BRANCH_PREDICTORS 256
	76	unsigned char branch_predictors[N_CRISV32_BRANCH_PREDICTORS];
	77
	78	} CRIS_MISC_PROFILE;
	79
	80	/* Handler prototypes for functions called from the CGEN description. */
	81
f6bcefef HPN	82	extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI);
	83	extern USI crisv10f_break_handler (SIM_CPU *, USI, USI);
	84	extern USI crisv32f_break_handler (SIM_CPU *, USI, USI);
	85	extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI,
	86	USI, USI);
aad3b3cb	87	extern char cris_have_900000xxif;
466b1d33 HPN	88	enum cris_unknown_syscall_action_type
	89	{ CRIS_USYSC_MSG_STOP, CRIS_USYSC_MSG_ENOSYS, CRIS_USYSC_QUIET_ENOSYS };
	90	extern enum cris_unknown_syscall_action_type cris_unknown_syscall_action;
aad3b3cb HPN	91	enum cris_interrupt_type { CRIS_INT_NMI, CRIS_INT_RESET, CRIS_INT_INT };
	92	extern int crisv10deliver_interrupt (SIM_CPU *,
	93	enum cris_interrupt_type,
	94	unsigned int);
	95	extern int crisv32deliver_interrupt (SIM_CPU *,
	96	enum cris_interrupt_type,
	97	unsigned int);
f6bcefef HPN	98
	99	/* Using GNU syntax (not C99) so we can compile this on RH 6.2
	100	(egcs-1.1.2/gcc-2.91.66). */
	101	#define cris_trace_printf(SD, CPU, FMT...) \
	102	do \
	103	{ \
	104	if (TRACE_FILE (STATE_TRACE_DATA (SD)) != NULL) \
	105	fprintf (TRACE_FILE (CPU_TRACE_DATA (CPU)), FMT); \
	106	else \
	107	sim_io_printf (SD, FMT); \
	108	} \
	109	while (0)
	110
	111	#if WITH_PROFILE_MODEL_P
	112	#define crisv32f_branch_taken(cpu, oldpc, newpc, taken) \
	113	do \
	114	{ \
	115	CPU_CRIS_MISC_PROFILE (cpu)->old_pc = oldpc; \
	116	CPU_CRIS_MISC_PROFILE (cpu)->branch_taken = taken; \
	117	} \
	118	while (0)
	119	#else
	120	#define crisv32f_branch_taken(cpu, oldpc, newpc, taken)
	121	#endif
	122
	123	#define crisv10f_branch_taken(cpu, oldpc, newpc, taken)
	124
	125	#define crisv32f_read_supr(cpu, index) \
	126	(cgen_rtx_error (current_cpu, \
	127	"Read of support register is unimplemented"), \
	128	0)
	129
	130	#define crisv32f_write_supr(cpu, index, val) \
	131	cgen_rtx_error (current_cpu, \
	132	"Write to support register is unimplemented") \
	133
	134	#define crisv32f_rfg_handler(cpu, pc) \
	135	cgen_rtx_error (current_cpu, "RFG isn't implemented")
	136
	137	#define crisv32f_halt_handler(cpu, pc) \
	138	(cgen_rtx_error (current_cpu, "HALT isn't implemented"), 0)
	139
	140	#define crisv32f_fidxi_handler(cpu, pc, indx) \
	141	(cgen_rtx_error (current_cpu, "FIDXI isn't implemented"), 0)
	142
	143	#define crisv32f_ftagi_handler(cpu, pc, indx) \
	144	(cgen_rtx_error (current_cpu, "FTAGI isn't implemented"), 0)
	145
	146	#define crisv32f_fidxd_handler(cpu, pc, indx) \
	147	(cgen_rtx_error (current_cpu, "FIDXD isn't implemented"), 0)
	148
	149	#define crisv32f_ftagd_handler(cpu, pc, indx) \
	150	(cgen_rtx_error (current_cpu, "FTAGD isn't implemented"), 0)
	151
	152	/* We have nothing special to do when interrupts or NMI are enabled
	153	after having been disabled, so empty macros are enough for these
	154	hooks. */
	155	#define crisv32f_interrupts_enabled(cpu)
	156	#define crisv32f_nmi_enabled(cpu)
	157
	158	/* Better warn for this case here, because everything needed is
	159	somewhere within the CPU. Compare to trying to use interrupts and
	160	NMI, which would fail earlier, when trying to make nonexistent
	161	external components generate those exceptions. */
162	#define crisv32f_single_step_enabled(cpu) \
163	((crisv32f_h_qbit_get (cpu) != 0 \
164	\|\| (crisv32f_h_sr_get (cpu, H_SR_SPC) & ~1) != 0) \
165	? (cgen_rtx_error (cpu, \
166	"single-stepping isn't implemented"), 0) \
167	: 0)
168
169	/* We don't need to track the value of the PID register here. */
170	#define crisv32f_write_pid_handler(cpu, val)
171
172	/* Neither do we need to know of transitions to user mode. */
173	#define crisv32f_usermode_enabled(cpu)
174
175	/* House-keeping exported from traps.c */
176	extern void cris_set_callbacks (host_callback *);
177
178	/* FIXME: Add more junk. */
179	#endif