[thirdparty/binutils-gdb.git] / sim / cris / cris-tmpl.c

/* CRIS base simulator support code
   Copyright (C) 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
   Contributed by Axis Communications.

This file is part of the GNU simulators.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

/* The infrastructure is based on that of i960.c.  */

#define WANT_CPU

#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"

#define MY(f) XCONCAT3(crisv,BASENUM,f)

/* Dispatcher for break insn.  */

USI
MY (f_break_handler) (SIM_CPU *cpu, USI breaknum, USI pc)
{
  SIM_DESC sd = CPU_STATE (cpu);
  USI ret = pc + 2;

  MY (f_h_pc_set) (cpu, ret);

  /* FIXME: Error out if IBR or ERP set.  */
  switch (breaknum)
    {
    case 13:
      MY (f_h_gr_set (cpu, 10,
		      cris_break_13_handler (cpu,
					     MY (f_h_gr_get (cpu, 9)),
					     MY (f_h_gr_get (cpu, 10)),
					     MY (f_h_gr_get (cpu, 11)),
					     MY (f_h_gr_get (cpu, 12)),
					     MY (f_h_gr_get (cpu, 13)),
					     MY (f_h_sr_get (cpu, 7)),
					     MY (f_h_sr_get (cpu, 11)),
					     pc)));
      break;

    case 14:
      sim_io_printf (sd, "%x\n", MY (f_h_gr_get (cpu, 3)));
      break;

    case 15:
      /* Re-use the Linux exit call.  */
      cris_break_13_handler (cpu, /* TARGET_SYS_exit */ 1, 0,
			     0, 0, 0, 0, 0, pc);

    default:
      abort ();
    }

  return MY (f_h_pc_get) (cpu);
}

/* Accessor function for simulator internal use.
   Note the contents of BUF are in target byte order.  */

int
MY (f_fetch_register) (SIM_CPU *current_cpu, int rn,
		      unsigned char *buf, int len ATTRIBUTE_UNUSED)
{
  SETTSI (buf, XCONCAT3(crisv,BASENUM,f_h_gr_get) (current_cpu, rn));
  return -1;
}

/* Accessor function for simulator internal use.
   Note the contents of BUF are in target byte order.  */

int
MY (f_store_register) (SIM_CPU *current_cpu, int rn,
		      unsigned char *buf, int len ATTRIBUTE_UNUSED)
{
  XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf));
  return -1;
}
\f
#if WITH_PROFILE_MODEL_P

/* FIXME: Some of these should be inline or macros.  Later.  */

/* Initialize cycle counting for an insn.
   FIRST_P is non-zero if this is the first insn in a set of parallel
   insns.  */

void
MY (f_model_insn_before) (SIM_CPU *current_cpu, int first_p ATTRIBUTE_UNUSED)
{
  /* To give the impression that we actually know what PC is, we have to
     dump register contents *before* the *next* insn, not after the
     *previous* insn.  Uhh...  */

  /* FIXME: Move this to separate, overridable function.  */
  if ((CPU_CRIS_MISC_PROFILE (current_cpu)->flags
       & FLAG_CRIS_MISC_PROFILE_XSIM_TRACE)
#ifdef GET_H_INSN_PREFIXED_P
      /* For versions with prefixed insns, trace the combination as
	 one insn.  */
      && !GET_H_INSN_PREFIXED_P ()
#endif
      && 1)
  {
    int i;
    char flags[7];
    unsigned64 cycle_count;

    SIM_DESC sd = CPU_STATE (current_cpu);

    cris_trace_printf (sd, current_cpu, "%lx ",
		       0xffffffffUL & (unsigned long) (CPU (h_pc)));

    for (i = 0; i < 15; i++)
      cris_trace_printf (sd, current_cpu, "%lx ",
			 0xffffffffUL
			 & (unsigned long) (XCONCAT3(crisv,BASENUM,
						     f_h_gr_get) (current_cpu,
								  i)));
    flags[0] = GET_H_IBIT () != 0 ? 'I' : 'i';
    flags[1] = GET_H_XBIT () != 0 ? 'X' : 'x';
    flags[2] = GET_H_NBIT () != 0 ? 'N' : 'n';
    flags[3] = GET_H_ZBIT () != 0 ? 'Z' : 'z';
    flags[4] = GET_H_VBIT () != 0 ? 'V' : 'v';
    flags[5] = GET_H_CBIT () != 0 ? 'C' : 'c';
    flags[6] = 0;

    /* For anything else than basic tracing we'd add stall cycles for
       e.g. unaligned accesses.  FIXME: add --cris-trace=x options to
       match --cris-cycles=x.  */
    cycle_count
      = (CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count
	 - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)->basic_cycle_count);

    /* Emit ACR after flags and cycle count for this insn.  */
    if (BASENUM == 32)
      cris_trace_printf (sd, current_cpu, "%s %d %lx\n", flags,
			 (int) cycle_count,
			 0xffffffffUL
			 & (unsigned long) (XCONCAT3(crisv,BASENUM,
						     f_h_gr_get) (current_cpu,
								  15)));
    else
      cris_trace_printf (sd, current_cpu, "%s %d\n", flags,
			 (int) cycle_count);

    CPU_CRIS_PREV_MISC_PROFILE (current_cpu)[0]
      = CPU_CRIS_MISC_PROFILE (current_cpu)[0];
  }
}

/* Record the cycles computed for an insn.
   LAST_P is non-zero if this is the last insn in a set of parallel insns,
   and we update the total cycle count.
   CYCLES is the cycle count of the insn.  */

void
MY (f_model_insn_after) (SIM_CPU *current_cpu, int last_p ATTRIBUTE_UNUSED,
			 int cycles)
{
  PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu);

  PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
  CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count += cycles;
  PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;

#if WITH_HW
  /* For some reason, we don't get to the sim_events_tick call in
     cgen-run.c:engine_run_1.  Besides, more than one cycle has
     passed, so we want sim_events_tickn anyway.  The "events we want
     to process" is usually to initiate an interrupt, but might also
     be other events.  We can't do the former until the main loop is
     at point where it accepts changing the PC without internal
     inconsistency, so just set a flag and wait.  */
  if (sim_events_tickn (CPU_STATE (current_cpu), cycles))
    STATE_EVENTS (CPU_STATE (current_cpu))->work_pending = 1;
#endif
}

/* Initialize cycle counting for an insn.
   FIRST_P is non-zero if this is the first insn in a set of parallel
   insns.  */

void
MY (f_model_init_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
			       int first_p ATTRIBUTE_UNUSED)
{
  abort ();
}

/* Record the cycles computed for an insn.
   LAST_P is non-zero if this is the last insn in a set of parallel insns,
   and we update the total cycle count.  */

void
MY (f_model_update_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
				 int last_p ATTRIBUTE_UNUSED)
{
  abort ();
}

#if 0
void
MY (f_model_record_cycles) (SIM_CPU *current_cpu, unsigned long cycles)
{
  abort ();
}

void
MY (f_model_mark_get_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
{
  abort ();
}

void
MY (f_model_mark_set_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
{
  abort ();
}
#endif
\f
/* Create the context for a thread.  */

void *
MY (make_thread_cpu_data) (SIM_CPU *current_cpu, void *context)
{
  void *info = xmalloc (current_cpu->thread_cpu_data_size);

  if (context != NULL)
    memcpy (info,
	    context,
	    current_cpu->thread_cpu_data_size);
  else
    memset (info, 0, current_cpu->thread_cpu_data_size),abort();
  return info;
}

/* Hook function for per-cpu simulator initialization.  */

void
MY (f_specific_init) (SIM_CPU *current_cpu)
{
  current_cpu->make_thread_cpu_data = MY (make_thread_cpu_data);
  current_cpu->thread_cpu_data_size = sizeof (current_cpu->cpu_data);
#if WITH_HW
  current_cpu->deliver_interrupt = MY (deliver_interrupt);
#endif
}
\f
/* Model function for arbitrary single stall cycles.  */

int
MY (XCONCAT3 (f_model_crisv,BASENUM,
	      _u_stall)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
			  const IDESC *idesc,
			  int unit_num,
			  int referenced ATTRIBUTE_UNUSED)
{
  return idesc->timing->units[unit_num].done;
}

#ifndef SPECIFIC_U_SKIP4_FN

/* Model function for u-skip4 unit.  */

int
MY (XCONCAT3 (f_model_crisv,BASENUM,
	      _u_skip4)) (SIM_CPU *current_cpu,
			  const IDESC *idesc,
			  int unit_num,
			  int referenced ATTRIBUTE_UNUSED)
{
  /* Handle PC not being updated with pbb.  FIXME: What if not pbb?  */
  CPU (h_pc) += 4;
  return idesc->timing->units[unit_num].done;
}

#endif

#ifndef SPECIFIC_U_EXEC_FN

/* Model function for u-exec unit.  */

int
MY (XCONCAT3 (f_model_crisv,BASENUM,
	      _u_exec)) (SIM_CPU *current_cpu,
			 const IDESC *idesc,
			 int unit_num, int referenced ATTRIBUTE_UNUSED)
{
  /* Handle PC not being updated with pbb.  FIXME: What if not pbb?  */
  CPU (h_pc) += 2;
  return idesc->timing->units[unit_num].done;
}
#endif

#ifndef SPECIFIC_U_MEM_FN

/* Model function for u-mem unit.  */

int
MY (XCONCAT3 (f_model_crisv,BASENUM,
	      _u_mem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
			const IDESC *idesc,
			int unit_num,
			int referenced ATTRIBUTE_UNUSED)
{
  return idesc->timing->units[unit_num].done;
}
#endif

#ifndef SPECIFIC_U_CONST16_FN

/* Model function for u-const16 unit.  */

int
MY (XCONCAT3 (f_model_crisv,BASENUM,
	      _u_const16)) (SIM_CPU *current_cpu,
			    const IDESC *idesc,
			    int unit_num,
			    int referenced ATTRIBUTE_UNUSED)
{
  CPU (h_pc) += 2;
  return idesc->timing->units[unit_num].done;
}
#endif /* SPECIFIC_U_CONST16_FN */

#ifndef SPECIFIC_U_CONST32_FN

/* This will be incorrect for early models, where a dword always take
   two cycles.  */
#define CRIS_MODEL_MASK_PC_STALL 2

/* Model function for u-const32 unit.  */

int
MY (XCONCAT3 (f_model_crisv,BASENUM,
	      _u_const32)) (SIM_CPU *current_cpu,
			    const IDESC *idesc,
			    int unit_num,
			    int referenced ATTRIBUTE_UNUSED)
{
  int unaligned_extra
    = (((CPU (h_pc) + 2) & CRIS_MODEL_MASK_PC_STALL)
       == CRIS_MODEL_MASK_PC_STALL);

  /* Handle PC not being updated with pbb.  FIXME: What if not pbb?  */
  CPU_CRIS_MISC_PROFILE (current_cpu)->unaligned_mem_dword_count
    += unaligned_extra;

  CPU (h_pc) += 4;
  return idesc->timing->units[unit_num].done;
}
#endif /* SPECIFIC_U_CONST32_FN */

#ifndef SPECIFIC_U_MOVEM_FN

/* Model function for u-movem unit.  */

int
MY (XCONCAT3 (f_model_crisv,BASENUM,
	      _u_movem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
			  const IDESC *idesc ATTRIBUTE_UNUSED,
			  int unit_num ATTRIBUTE_UNUSED,
			  int referenced ATTRIBUTE_UNUSED,
			  INT limreg)
{
  /* FIXME: Add cycles for misalignment.  */

  if (limreg == -1)
    abort ();

  /* We don't record movem move cycles in movemsrc_stall_count since
     those cycles have historically been handled as ordinary cycles.  */
  return limreg + 1;
}
#endif /* SPECIFIC_U_MOVEM_FN */

#endif /* WITH_PROFILE_MODEL_P */
Commit	Line	Data
f6bcefef	1	/* CRIS base simulator support code
6aba47ca	2	Copyright (C) 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
f6bcefef HPN	3	Contributed by Axis Communications.
	4
	5	This file is part of the GNU simulators.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	/* The infrastructure is based on that of i960.c. */
	22
	23	#define WANT_CPU
	24
	25	#include "sim-main.h"
	26	#include "cgen-mem.h"
	27	#include "cgen-ops.h"
	28
	29	#define MY(f) XCONCAT3(crisv,BASENUM,f)
	30
	31	/* Dispatcher for break insn. */
	32
	33	USI
	34	MY (f_break_handler) (SIM_CPU *cpu, USI breaknum, USI pc)
	35	{
	36	SIM_DESC sd = CPU_STATE (cpu);
	37	USI ret = pc + 2;
	38
	39	MY (f_h_pc_set) (cpu, ret);
	40
	41	/* FIXME: Error out if IBR or ERP set. */
	42	switch (breaknum)
	43	{
	44	case 13:
	45	MY (f_h_gr_set (cpu, 10,
	46	cris_break_13_handler (cpu,
	47	MY (f_h_gr_get (cpu, 9)),
	48	MY (f_h_gr_get (cpu, 10)),
	49	MY (f_h_gr_get (cpu, 11)),
	50	MY (f_h_gr_get (cpu, 12)),
	51	MY (f_h_gr_get (cpu, 13)),
	52	MY (f_h_sr_get (cpu, 7)),
	53	MY (f_h_sr_get (cpu, 11)),
	54	pc)));
	55	break;
	56
	57	case 14:
	58	sim_io_printf (sd, "%x\n", MY (f_h_gr_get (cpu, 3)));
	59	break;
	60
	61	case 15:
	62	/* Re-use the Linux exit call. */
	63	cris_break_13_handler (cpu, /* TARGET_SYS_exit */ 1, 0,
	64	0, 0, 0, 0, 0, pc);
	65
	66	default:
67	abort ();
68	}
69
70	return MY (f_h_pc_get) (cpu);
71	}
72
73	/* Accessor function for simulator internal use.
74	Note the contents of BUF are in target byte order. */
75
76	int
77	MY (f_fetch_register) (SIM_CPU *current_cpu, int rn,
78	unsigned char *buf, int len ATTRIBUTE_UNUSED)
79	{
80	SETTSI (buf, XCONCAT3(crisv,BASENUM,f_h_gr_get) (current_cpu, rn));
81	return -1;
82	}
83
84	/* Accessor function for simulator internal use.
85	Note the contents of BUF are in target byte order. */
86
87	int
88	MY (f_store_register) (SIM_CPU *current_cpu, int rn,
89	unsigned char *buf, int len ATTRIBUTE_UNUSED)
90	{
91	XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf));
92	return -1;
93	}
94	\f
95	#if WITH_PROFILE_MODEL_P
96
97	/* FIXME: Some of these should be inline or macros. Later. */
98
99	/* Initialize cycle counting for an insn.
100	FIRST_P is non-zero if this is the first insn in a set of parallel
101	insns. */
102
103	void
104	MY (f_model_insn_before) (SIM_CPU *current_cpu, int first_p ATTRIBUTE_UNUSED)
105	{
106	/* To give the impression that we actually know what PC is, we have to
107	dump register contents before the next insn, not after the
108	previous insn. Uhh... */
109
110	/* FIXME: Move this to separate, overridable function. */
111	if ((CPU_CRIS_MISC_PROFILE (current_cpu)->flags
112	& FLAG_CRIS_MISC_PROFILE_XSIM_TRACE)
113	#ifdef GET_H_INSN_PREFIXED_P
114	/* For versions with prefixed insns, trace the combination as
115	one insn. */
116	&& !GET_H_INSN_PREFIXED_P ()
117	#endif
118	&& 1)
119	{
120	int i;
121	char flags[7];
4fc9958a HPN	122	unsigned64 cycle_count;
4fc9958a HPN	123
f6bcefef HPN	124	SIM_DESC sd = CPU_STATE (current_cpu);
f6bcefef HPN	125
ae81c235 HPN	126	cris_trace_printf (sd, current_cpu, "%lx ",
ae81c235 HPN	127	0xffffffffUL & (unsigned long) (CPU (h_pc)));
f6bcefef HPN	128
	129	for (i = 0; i < 15; i++)
	130	cris_trace_printf (sd, current_cpu, "%lx ",
ae81c235 HPN	131	0xffffffffUL
	132	& (unsigned long) (XCONCAT3(crisv,BASENUM,
	133	f_h_gr_get) (current_cpu,
	134	i)));
f6bcefef HPN	135	flags[0] = GET_H_IBIT () != 0 ? 'I' : 'i';
	136	flags[1] = GET_H_XBIT () != 0 ? 'X' : 'x';
	137	flags[2] = GET_H_NBIT () != 0 ? 'N' : 'n';
	138	flags[3] = GET_H_ZBIT () != 0 ? 'Z' : 'z';
	139	flags[4] = GET_H_VBIT () != 0 ? 'V' : 'v';
	140	flags[5] = GET_H_CBIT () != 0 ? 'C' : 'c';
	141	flags[6] = 0;
	142
4fc9958a HPN	143	/* For anything else than basic tracing we'd add stall cycles for
	144	e.g. unaligned accesses. FIXME: add --cris-trace=x options to
	145	match --cris-cycles=x. */
	146	cycle_count
	147	= (CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count
	148	- CPU_CRIS_PREV_MISC_PROFILE (current_cpu)->basic_cycle_count);
	149
f6bcefef HPN	150	/* Emit ACR after flags and cycle count for this insn. */
	151	if (BASENUM == 32)
	152	cris_trace_printf (sd, current_cpu, "%s %d %lx\n", flags,
4fc9958a	153	(int) cycle_count,
ae81c235 HPN	154	0xffffffffUL
	155	& (unsigned long) (XCONCAT3(crisv,BASENUM,
	156	f_h_gr_get) (current_cpu,
	157	15)));
f6bcefef HPN	158	else
f6bcefef HPN	159	cris_trace_printf (sd, current_cpu, "%s %d\n", flags,
4fc9958a	160	(int) cycle_count);
f6bcefef HPN	161
	162	CPU_CRIS_PREV_MISC_PROFILE (current_cpu)[0]
	163	= CPU_CRIS_MISC_PROFILE (current_cpu)[0];
	164	}
	165	}
	166
	167	/* Record the cycles computed for an insn.
	168	LAST_P is non-zero if this is the last insn in a set of parallel insns,
	169	and we update the total cycle count.
	170	CYCLES is the cycle count of the insn. */
	171
	172	void
	173	MY (f_model_insn_after) (SIM_CPU *current_cpu, int last_p ATTRIBUTE_UNUSED,
	174	int cycles)
	175	{
	176	PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu);
	177
	178	PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
	179	CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count += cycles;
	180	PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
aad3b3cb HPN	181
	182	#if WITH_HW
	183	/* For some reason, we don't get to the sim_events_tick call in
	184	cgen-run.c:engine_run_1. Besides, more than one cycle has
	185	passed, so we want sim_events_tickn anyway. The "events we want
	186	to process" is usually to initiate an interrupt, but might also
	187	be other events. We can't do the former until the main loop is
	188	at point where it accepts changing the PC without internal
	189	inconsistency, so just set a flag and wait. */
	190	if (sim_events_tickn (CPU_STATE (current_cpu), cycles))
	191	STATE_EVENTS (CPU_STATE (current_cpu))->work_pending = 1;
	192	#endif
f6bcefef HPN	193	}
	194
	195	/* Initialize cycle counting for an insn.
	196	FIRST_P is non-zero if this is the first insn in a set of parallel
	197	insns. */
	198
	199	void
	200	MY (f_model_init_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
	201	int first_p ATTRIBUTE_UNUSED)
	202	{
	203	abort ();
	204	}
	205
	206	/* Record the cycles computed for an insn.
	207	LAST_P is non-zero if this is the last insn in a set of parallel insns,
	208	and we update the total cycle count. */
	209
	210	void
	211	MY (f_model_update_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
	212	int last_p ATTRIBUTE_UNUSED)
	213	{
	214	abort ();
	215	}
	216
	217	#if 0
	218	void
	219	MY (f_model_record_cycles) (SIM_CPU *current_cpu, unsigned long cycles)
	220	{
	221	abort ();
	222	}
	223
	224	void
	225	MY (f_model_mark_get_h_gr) (SIM_CPU current_cpu, ARGBUF abuf)
	226	{
	227	abort ();
	228	}
	229
	230	void
	231	MY (f_model_mark_set_h_gr) (SIM_CPU current_cpu, ARGBUF abuf)
	232	{
	233	abort ();
	234	}
	235	#endif
	236	\f
	237	/* Create the context for a thread. */
	238
	239	void *
	240	MY (make_thread_cpu_data) (SIM_CPU current_cpu, void context)
	241	{
	242	void *info = xmalloc (current_cpu->thread_cpu_data_size);
	243
	244	if (context != NULL)
	245	memcpy (info,
	246	context,
	247	current_cpu->thread_cpu_data_size);
	248	else
	249	memset (info, 0, current_cpu->thread_cpu_data_size),abort();
	250	return info;
	251	}
	252
	253	/* Hook function for per-cpu simulator initialization. */
	254
	255	void
	256	MY (f_specific_init) (SIM_CPU *current_cpu)
257	{
258	current_cpu->make_thread_cpu_data = MY (make_thread_cpu_data);
259	current_cpu->thread_cpu_data_size = sizeof (current_cpu->cpu_data);
aad3b3cb HPN	260	#if WITH_HW
	261	current_cpu->deliver_interrupt = MY (deliver_interrupt);
	262	#endif
f6bcefef HPN	263	}
	264	\f
	265	/* Model function for arbitrary single stall cycles. */
	266
	267	int
	268	MY (XCONCAT3 (f_model_crisv,BASENUM,
	269	_u_stall)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
	270	const IDESC *idesc,
	271	int unit_num,
	272	int referenced ATTRIBUTE_UNUSED)
	273	{
	274	return idesc->timing->units[unit_num].done;
	275	}
	276
	277	#ifndef SPECIFIC_U_SKIP4_FN
	278
	279	/* Model function for u-skip4 unit. */
	280
	281	int
	282	MY (XCONCAT3 (f_model_crisv,BASENUM,
	283	_u_skip4)) (SIM_CPU *current_cpu,
	284	const IDESC *idesc,
	285	int unit_num,
	286	int referenced ATTRIBUTE_UNUSED)
	287	{
	288	/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
	289	CPU (h_pc) += 4;
	290	return idesc->timing->units[unit_num].done;
	291	}
	292
	293	#endif
	294
	295	#ifndef SPECIFIC_U_EXEC_FN
	296
	297	/* Model function for u-exec unit. */
	298
	299	int
	300	MY (XCONCAT3 (f_model_crisv,BASENUM,
	301	_u_exec)) (SIM_CPU *current_cpu,
	302	const IDESC *idesc,
	303	int unit_num, int referenced ATTRIBUTE_UNUSED)
	304	{
	305	/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
	306	CPU (h_pc) += 2;
	307	return idesc->timing->units[unit_num].done;
	308	}
	309	#endif
	310
	311	#ifndef SPECIFIC_U_MEM_FN
	312
	313	/* Model function for u-mem unit. */
	314
	315	int
	316	MY (XCONCAT3 (f_model_crisv,BASENUM,
	317	_u_mem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
	318	const IDESC *idesc,
	319	int unit_num,
	320	int referenced ATTRIBUTE_UNUSED)
	321	{
	322	return idesc->timing->units[unit_num].done;
	323	}
	324	#endif
	325
	326	#ifndef SPECIFIC_U_CONST16_FN
327
328	/* Model function for u-const16 unit. */
329
330	int
331	MY (XCONCAT3 (f_model_crisv,BASENUM,
332	_u_const16)) (SIM_CPU *current_cpu,
333	const IDESC *idesc,
334	int unit_num,
335	int referenced ATTRIBUTE_UNUSED)
336	{
337	CPU (h_pc) += 2;
338	return idesc->timing->units[unit_num].done;
339	}
340	#endif /* SPECIFIC_U_CONST16_FN */
341
342	#ifndef SPECIFIC_U_CONST32_FN
343
344	/* This will be incorrect for early models, where a dword always take
345	two cycles. */
346	#define CRIS_MODEL_MASK_PC_STALL 2
347
348	/* Model function for u-const32 unit. */
349
350	int
351	MY (XCONCAT3 (f_model_crisv,BASENUM,
352	_u_const32)) (SIM_CPU *current_cpu,
353	const IDESC *idesc,
354	int unit_num,
355	int referenced ATTRIBUTE_UNUSED)
356	{
357	int unaligned_extra
358	= (((CPU (h_pc) + 2) & CRIS_MODEL_MASK_PC_STALL)
359	== CRIS_MODEL_MASK_PC_STALL);
360
361	/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
362	CPU_CRIS_MISC_PROFILE (current_cpu)->unaligned_mem_dword_count
363	+= unaligned_extra;
364
365	CPU (h_pc) += 4;
366	return idesc->timing->units[unit_num].done;
367	}
368	#endif /* SPECIFIC_U_CONST32_FN */
369
370	#ifndef SPECIFIC_U_MOVEM_FN
371
372	/* Model function for u-movem unit. */
373
374	int
375	MY (XCONCAT3 (f_model_crisv,BASENUM,
376	_u_movem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
377	const IDESC *idesc ATTRIBUTE_UNUSED,
378	int unit_num ATTRIBUTE_UNUSED,
379	int referenced ATTRIBUTE_UNUSED,
380	INT limreg)
381	{
382	/* FIXME: Add cycles for misalignment. */
383
384	if (limreg == -1)
385	abort ();
386
387	/* We don't record movem move cycles in movemsrc_stall_count since
388	those cycles have historically been handled as ordinary cycles. */
389	return limreg + 1;
390	}
391	#endif /* SPECIFIC_U_MOVEM_FN */
392
393	#endif /* WITH_PROFILE_MODEL_P */