[thirdparty/binutils-gdb.git] / sim / d10v / d10v_sim.h

#include <stdio.h>
#include <ctype.h>
#include <limits.h>
#include "ansidecl.h"
#include "sim/callback.h"
#include "opcode/d10v.h"
#include "bfd.h"

#define DEBUG_TRACE		0x00000001
#define DEBUG_VALUES		0x00000002
#define DEBUG_LINE_NUMBER	0x00000004
#define DEBUG_MEMSIZE		0x00000008
#define DEBUG_INSTRUCTION	0x00000010
#define DEBUG_TRAP		0x00000020
#define DEBUG_MEMORY		0x00000040

#ifndef	DEBUG
#define	DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
#endif

extern int d10v_debug;

#include "sim/sim.h"
#include "sim-config.h"
#include "sim-types.h"

/* FIXME: D10V defines */
typedef uint16_t reg_t;

struct simops 
{
  long opcode;
  int  is_long;
  long mask;
  int format;
  int cycles;
  int unit;
  int exec_type;
  void (*func)(SIM_DESC, SIM_CPU *);
  int numops;
  int operands[9];
};

enum _ins_type
{
  INS_UNKNOWN,			/* unknown instruction */
  INS_COND_TRUE,		/* # times EXExxx executed other instruction */
  INS_COND_FALSE,		/* # times EXExxx did not execute other instruction */
  INS_COND_JUMP,		/* # times JUMP skipped other instruction */
  INS_CYCLES,			/* # cycles */
  INS_LONG,			/* long instruction (both containers, ie FM == 11) */
  INS_LEFTRIGHT,		/* # times instruction encoded as L -> R (ie, FM == 01) */
  INS_RIGHTLEFT,		/* # times instruction encoded as L <- R (ie, FM == 10) */
  INS_PARALLEL,			/* # times instruction encoded as L || R (ie, RM == 00) */

  INS_LEFT,			/* normal left instructions */
  INS_LEFT_PARALLEL,		/* left side of || */
  INS_LEFT_COND_TEST,		/* EXExx test on left side */
  INS_LEFT_COND_EXE,		/* execution after EXExxx test on right side succeeded */
  INS_LEFT_NOPS,		/* NOP on left side */

  INS_RIGHT,			/* normal right instructions */
  INS_RIGHT_PARALLEL,		/* right side of || */
  INS_RIGHT_COND_TEST,		/* EXExx test on right side */
  INS_RIGHT_COND_EXE,		/* execution after EXExxx test on left side succeeded */
  INS_RIGHT_NOPS,		/* NOP on right side */

  INS_MAX
};

extern unsigned long ins_type_counters[ (int)INS_MAX ];

enum {
  SP_IDX = 15,
};

/* Write-back slots */
union slot_data {
  unsigned_1 _1;
  unsigned_2 _2;
  unsigned_4 _4;
  unsigned_8 _8;
};
struct slot {
  void *dest;
  int size;
  union slot_data data;
  union slot_data mask;
};
enum {
 NR_SLOTS = 16,
};
#define SLOT (State.slot)
#define SLOT_NR (State.slot_nr)
#define SLOT_PEND_MASK(DEST, MSK, VAL) \
  do \
    { \
      SLOT[SLOT_NR].dest = &(DEST); \
      SLOT[SLOT_NR].size = sizeof (DEST); \
      switch (sizeof (DEST)) \
        { \
        case 1: \
          SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
          SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
          break; \
        case 2: \
          SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
          SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
          break; \
        case 4: \
          SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
          SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
          break; \
        case 8: \
          SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \
          SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \
          break; \
        } \
      SLOT_NR = (SLOT_NR + 1); \
    } \
  while (0)
#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
#define SLOT_DISCARD() (SLOT_NR = 0)
#define SLOT_FLUSH() \
  do \
    { \
      int i; \
      for (i = 0; i < SLOT_NR; i++) \
	{ \
	  switch (SLOT[i].size) \
	    { \
	    case 1: \
	      *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
	      *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
	      break; \
	    case 2: \
	      *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
	      *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
	      break; \
	    case 4: \
	      *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
	      *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
	      break; \
	    case 8: \
	      *(unsigned_8*) SLOT[i].dest &= SLOT[i].mask._8; \
	      *(unsigned_8*) SLOT[i].dest |= SLOT[i].data._8; \
	      break; \
	    } \
        } \
      SLOT_NR = 0; \
    } \
  while (0)
#define SLOT_DUMP() \
  do \
    { \
      int i; \
      for (i = 0; i < SLOT_NR; i++) \
	{ \
	  switch (SLOT[i].size) \
	    { \
	    case 1: \
              printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._1, \
                      (unsigned) SLOT[i].data._1); \
	      break; \
	    case 2: \
              printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._2, \
                      (unsigned) SLOT[i].data._2); \
	      break; \
	    case 4: \
              printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._4, \
                      (unsigned) SLOT[i].data._4); \
	      break; \
	    case 8: \
              printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) (SLOT[i].mask._8 >> 32),  \
                      (unsigned) SLOT[i].mask._8, \
                      (unsigned) (SLOT[i].data._8 >> 32),  \
                      (unsigned) SLOT[i].data._8); \
	      break; \
	    } \
        } \
    } \
  while (0)

/* d10v memory: There are three separate d10v memory regions IMEM,
   UMEM and DMEM.  The IMEM and DMEM are further broken down into
   blocks (very like VM pages). */

enum
{
  IMAP_BLOCK_SIZE = 0x20000,
  DMAP_BLOCK_SIZE = 0x4000,
};

/* Implement the three memory regions using sparse arrays.  Allocate
   memory using ``segments''.  A segment must be at least as large as
   a BLOCK - ensures that an access that doesn't cross a block
   boundary can't cross a segment boundary */

enum
{
  SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
  IMEM_SEGMENTS = 8, /* 1MB */
  DMEM_SEGMENTS = 8, /* 1MB */
  UMEM_SEGMENTS = 128 /* 16MB */
};

struct d10v_memory
{
  uint8_t *insn[IMEM_SEGMENTS];
  uint8_t *data[DMEM_SEGMENTS];
  uint8_t *unif[UMEM_SEGMENTS];
};

struct _state
{
  reg_t regs[16];		/* general-purpose registers */
#define GPR(N) (State.regs[(N)] + 0)
#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))

#define GPR32(N) ((((uint32_t) State.regs[(N) + 0]) << 16) \
		  | (uint16_t) State.regs[(N) + 1])
#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)

  reg_t cregs[16];		/* control registers */
#define CREG(N) (State.cregs[(N)] + 0)
#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)

  reg_t sp[2];                  /* holding area for SPI(0)/SPU(1) */
#define HELD_SP(N) (State.sp[(N)] + 0)
#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))

  int64_t a[2];			/* accumulators */
#define ACC(N) (State.a[(N)] + 0)
#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)

  /* writeback info */
  struct slot slot[NR_SLOTS];
  int slot_nr;

  /* trace data */
  struct {
    uint16_t psw;
  } trace;

  uint8_t exe;
  int	pc_changed;

  /* NOTE: everything below this line is not reset by
     sim_create_inferior() */

  struct d10v_memory mem;

  enum _ins_type ins_type;

};

extern struct _state State;


extern uint16_t OP[4];
extern struct simops Simops[];

enum
{
  PSW_CR = 0,
  BPSW_CR = 1,
  PC_CR = 2,
  BPC_CR = 3,
  DPSW_CR = 4,
  DPC_CR = 5,
  RPT_C_CR = 7,
  RPT_S_CR = 8,
  RPT_E_CR = 9,
  MOD_S_CR = 10,
  MOD_E_CR = 11,
  IBA_CR = 14,
};

enum
{
  PSW_SM_BIT = 0x8000,
  PSW_EA_BIT = 0x2000,
  PSW_DB_BIT = 0x1000,
  PSW_DM_BIT = 0x0800,
  PSW_IE_BIT = 0x0400,
  PSW_RP_BIT = 0x0200,
  PSW_MD_BIT = 0x0100,
  PSW_FX_BIT = 0x0080,
  PSW_ST_BIT = 0x0040,
  PSW_F0_BIT = 0x0008,
  PSW_F1_BIT = 0x0004,
  PSW_C_BIT =  0x0001,
};

#define PSW CREG (PSW_CR)
#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
#define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)

#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))

#define PSW_EA ((PSW & PSW_EA_BIT) != 0)
#define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL))

#define PSW_DB ((PSW & PSW_DB_BIT) != 0)
#define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL))

#define PSW_DM ((PSW & PSW_DM_BIT) != 0)
#define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL))

#define PSW_IE ((PSW & PSW_IE_BIT) != 0)
#define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL))

#define PSW_RP ((PSW & PSW_RP_BIT) != 0)
#define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL))

#define PSW_MD ((PSW & PSW_MD_BIT) != 0)
#define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL))

#define PSW_FX ((PSW & PSW_FX_BIT) != 0)
#define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL))

#define PSW_ST ((PSW & PSW_ST_BIT) != 0)
#define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL))

#define PSW_F0 ((PSW & PSW_F0_BIT) != 0)
#define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL))

#define PSW_F1 ((PSW & PSW_F1_BIT) != 0)
#define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL))

#define PSW_C ((PSW & PSW_C_BIT) != 0)
#define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL))

/* See simopsc.:move_to_cr() for registers that can not be read-from
   or assigned-to directly */

#define PC	CREG (PC_CR)
#define SET_PC(VAL) SET_CREG (PC_CR, (VAL))

#define BPSW	CREG (BPSW_CR)
#define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL))

#define BPC	CREG (BPC_CR)
#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))

#define DPSW	CREG (DPSW_CR)
#define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL))

#define DPC	CREG (DPC_CR)
#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))

#define RPT_C	CREG (RPT_C_CR)
#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))

#define RPT_S	CREG (RPT_S_CR)
#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))

#define RPT_E	CREG (RPT_E_CR)
#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))

#define MOD_S	CREG (MOD_S_CR)
#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))

#define MOD_E	CREG (MOD_E_CR)
#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))

#define IBA	CREG (IBA_CR)
#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))


#define SIG_D10V_STOP	-1
#define SIG_D10V_EXIT	-2
#define SIG_D10V_BUS    -3

/* TODO: Resolve conflicts with common headers.  */
#undef SEXT8
#undef SEXT16
#undef SEXT32
#undef MASK32

#define SEXT3(x)	((((x)&0x7)^(~3))+4)	

/* sign-extend a 4-bit number */
#define SEXT4(x)	((((x)&0xf)^(~7))+8)	

/* sign-extend an 8-bit number */
#define SEXT8(x)	((((x)&0xff)^(~0x7f))+0x80)

/* sign-extend a 16-bit number */
#define SEXT16(x)	((((x)&0xffff)^(~0x7fff))+0x8000)

/* sign-extend a 32-bit number */
#define SEXT32(x)	((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))

/* sign extend a 40 bit number */
#define SEXT40(x)	((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))

/* sign extend a 44 bit number */
#define SEXT44(x)	((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))

/* sign extend a 56 bit number */
#define SEXT56(x)	((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))

/* sign extend a 60 bit number */
#define SEXT60(x)	((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))

#define MAX32	SIGNED64(0x7fffffff)
#define MIN32	SIGNED64(0xff80000000)
#define MASK32	SIGNED64(0xffffffff)
#define MASK40	SIGNED64(0xffffffffff)

/* The alignment of MOD_E in the following macro depends upon "i"
   always being a power of 2. */
#define INC_ADDR(x,i) \
do \
  { \
    int test_i = i < 0 ? i : ~((i) - 1); \
    if (PSW_MD && GPR (x) == (MOD_E & test_i)) \
      SET_GPR (x, MOD_S & test_i); \
    else \
      SET_GPR (x, GPR (x) + (i)); \
  } \
while (0)

extern uint8_t *dmem_addr (SIM_DESC, SIM_CPU *, uint16_t offset);
extern uint8_t *imem_addr (SIM_DESC, SIM_CPU *, uint32_t);

#define	RB(x)	(*(dmem_addr (sd, cpu, x)))
#define SB(addr,data)	( RB(addr) = (data & 0xff))

#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
#define ENDIAN_INLINE static __inline__
#include "endian.c"
#undef ENDIAN_INLINE

#else
extern uint32_t get_longword (uint8_t *);
extern uint16_t get_word (uint8_t *);
extern int64_t get_longlong (uint8_t *);
extern void write_word (uint8_t *addr, uint16_t data);
extern void write_longword (uint8_t *addr, uint32_t data);
extern void write_longlong (uint8_t *addr, int64_t data);
#endif

#define SW(addr,data)		write_word (dmem_addr (sd, cpu, addr), data)
#define RW(x)			get_word (dmem_addr (sd, cpu, x))
#define SLW(addr,data)  	write_longword (dmem_addr (sd, cpu, addr), data)
#define RLW(x)			get_longword (dmem_addr (sd, cpu, x))
#define READ_16(x)		get_word(x)
#define WRITE_16(addr,data)	write_word(addr,data)
#define READ_64(x)		get_longlong(x)
#define WRITE_64(addr,data)	write_longlong(addr,data)

#define JMP(x)			do { SET_PC (x); State.pc_changed = 1; } while (0)

#define RIE_VECTOR_START 0xffc2
#define AE_VECTOR_START 0xffc3
#define TRAP_VECTOR_START 0xffc4	/* vector for trap 0 */
#define DBT_VECTOR_START 0xffd4
#define SDBT_VECTOR_START 0xffd5

/* Scedule a store of VAL into cr[CR].  MASK indicates the bits in
   cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
   (VAL & ~MASK)).  In addition, unless PSW_HW_P, a VAL intended for
   PSW is masked for zero bits. */

extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);
Commit	Line	Data
c906108c SS	1	#include <stdio.h>
	2	#include <ctype.h>
	3	#include <limits.h>
	4	#include "ansidecl.h"
df68e12b	5	#include "sim/callback.h"
c906108c SS	6	#include "opcode/d10v.h"
	7	#include "bfd.h"
	8
	9	#define DEBUG_TRACE 0x00000001
	10	#define DEBUG_VALUES 0x00000002
	11	#define DEBUG_LINE_NUMBER 0x00000004
	12	#define DEBUG_MEMSIZE 0x00000008
	13	#define DEBUG_INSTRUCTION 0x00000010
	14	#define DEBUG_TRAP 0x00000020
4ce44c66	15	#define DEBUG_MEMORY 0x00000040
c906108c SS	16
	17	#ifndef DEBUG
	18	#define DEBUG (DEBUG_TRACE \| DEBUG_VALUES \| DEBUG_LINE_NUMBER)
	19	#endif
	20
	21	extern int d10v_debug;
	22
df68e12b	23	#include "sim/sim.h"
c906108c SS	24	#include "sim-config.h"
	25	#include "sim-types.h"
	26
c906108c	27	/* FIXME: D10V defines */
eae126cb	28	typedef uint16_t reg_t;
c906108c SS	29
	30	struct simops
	31	{
	32	long opcode;
	33	int is_long;
	34	long mask;
	35	int format;
	36	int cycles;
	37	int unit;
	38	int exec_type;
67954606	39	void (func)(SIM_DESC, SIM_CPU );
c906108c SS	40	int numops;
	41	int operands[9];
	42	};
	43
	44	enum _ins_type
	45	{
	46	INS_UNKNOWN, /* unknown instruction */
	47	INS_COND_TRUE, /* # times EXExxx executed other instruction */
	48	INS_COND_FALSE, /* # times EXExxx did not execute other instruction */
	49	INS_COND_JUMP, /* # times JUMP skipped other instruction */
	50	INS_CYCLES, /* # cycles */
	51	INS_LONG, /* long instruction (both containers, ie FM == 11) */
	52	INS_LEFTRIGHT, /* # times instruction encoded as L -> R (ie, FM == 01) */
	53	INS_RIGHTLEFT, /* # times instruction encoded as L <- R (ie, FM == 10) */
	54	INS_PARALLEL, /* # times instruction encoded as L \|\| R (ie, RM == 00) */
	55
	56	INS_LEFT, /* normal left instructions */
	57	INS_LEFT_PARALLEL, /* left side of \|\| */
	58	INS_LEFT_COND_TEST, /* EXExx test on left side */
	59	INS_LEFT_COND_EXE, /* execution after EXExxx test on right side succeeded */
	60	INS_LEFT_NOPS, /* NOP on left side */
	61
	62	INS_RIGHT, /* normal right instructions */
	63	INS_RIGHT_PARALLEL, /* right side of \|\| */
	64	INS_RIGHT_COND_TEST, /* EXExx test on right side */
	65	INS_RIGHT_COND_EXE, /* execution after EXExxx test on left side succeeded */
	66	INS_RIGHT_NOPS, /* NOP on right side */
	67
	68	INS_MAX
	69	};
	70
	71	extern unsigned long ins_type_counters[ (int)INS_MAX ];
	72
	73	enum {
	74	SP_IDX = 15,
	75	};
	76
	77	/* Write-back slots */
	78	union slot_data {
	79	unsigned_1 _1;
	80	unsigned_2 _2;
	81	unsigned_4 _4;
	82	unsigned_8 _8;
	83	};
	84	struct slot {
	85	void *dest;
	86	int size;
	87	union slot_data data;
	88	union slot_data mask;
	89	};
	90	enum {
	91	NR_SLOTS = 16,
	92	};
	93	#define SLOT (State.slot)
	94	#define SLOT_NR (State.slot_nr)
	95	#define SLOT_PEND_MASK(DEST, MSK, VAL) \
	96	do \
	97	{ \
	98	SLOT[SLOT_NR].dest = &(DEST); \
	99	SLOT[SLOT_NR].size = sizeof (DEST); \
	100	switch (sizeof (DEST)) \
	101	{ \
	102	case 1: \
	103	SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
104	SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
105	break; \
106	case 2: \
107	SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
108	SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
109	break; \
110	case 4: \
111	SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
112	SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
113	break; \
114	case 8: \
115	SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \
116	SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \
117	break; \
118	} \
119	SLOT_NR = (SLOT_NR + 1); \
120	} \
121	while (0)
122	#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
123	#define SLOT_DISCARD() (SLOT_NR = 0)
124	#define SLOT_FLUSH() \
125	do \
126	{ \
127	int i; \
128	for (i = 0; i < SLOT_NR; i++) \
129	{ \
130	switch (SLOT[i].size) \
131	{ \
132	case 1: \
133	(unsigned_1) SLOT[i].dest &= SLOT[i].mask._1; \
134	(unsigned_1) SLOT[i].dest \|= SLOT[i].data._1; \
135	break; \
136	case 2: \
137	(unsigned_2) SLOT[i].dest &= SLOT[i].mask._2; \
138	(unsigned_2) SLOT[i].dest \|= SLOT[i].data._2; \
139	break; \
140	case 4: \
141	(unsigned_4) SLOT[i].dest &= SLOT[i].mask._4; \
142	(unsigned_4) SLOT[i].dest \|= SLOT[i].data._4; \
143	break; \
144	case 8: \
145	(unsigned_8) SLOT[i].dest &= SLOT[i].mask._8; \
146	(unsigned_8) SLOT[i].dest \|= SLOT[i].data._8; \
147	break; \
148	} \
149	} \
150	SLOT_NR = 0; \
151	} \
152	while (0)
153	#define SLOT_DUMP() \
154	do \
155	{ \
156	int i; \
157	for (i = 0; i < SLOT_NR; i++) \
158	{ \
159	switch (SLOT[i].size) \
160	{ \
161	case 1: \
162	printf ("SLOT %d *0x%08lx & 0x%02x \| 0x%02x\n", i, \
163	(long) SLOT[i].dest, \
164	(unsigned) SLOT[i].mask._1, \
165	(unsigned) SLOT[i].data._1); \
166	break; \
167	case 2: \
168	printf ("SLOT %d *0x%08lx & 0x%04x \| 0x%04x\n", i, \
169	(long) SLOT[i].dest, \
170	(unsigned) SLOT[i].mask._2, \
171	(unsigned) SLOT[i].data._2); \
172	break; \
173	case 4: \
174	printf ("SLOT %d *0x%08lx & 0x%08x \| 0x%08x\n", i, \
175	(long) SLOT[i].dest, \
176	(unsigned) SLOT[i].mask._4, \
177	(unsigned) SLOT[i].data._4); \
178	break; \
179	case 8: \
180	printf ("SLOT %d *0x%08lx & 0x%08x%08x \| 0x%08x%08x\n", i, \
181	(long) SLOT[i].dest, \
182	(unsigned) (SLOT[i].mask._8 >> 32), \
183	(unsigned) SLOT[i].mask._8, \
184	(unsigned) (SLOT[i].data._8 >> 32), \
185	(unsigned) SLOT[i].data._8); \
186	break; \
187	} \
188	} \
189	} \
190	while (0)
191
4ce44c66 JM	192	/* d10v memory: There are three separate d10v memory regions IMEM,
	193	UMEM and DMEM. The IMEM and DMEM are further broken down into
	194	blocks (very like VM pages). */
	195
	196	enum
	197	{
	198	IMAP_BLOCK_SIZE = 0x20000,
	199	DMAP_BLOCK_SIZE = 0x4000,
	200	};
	201
	202	/* Implement the three memory regions using sparse arrays. Allocate
	203	memory using ``segments''. A segment must be at least as large as
	204	a BLOCK - ensures that an access that doesn't cross a block
	205	boundary can't cross a segment boundary */
	206
	207	enum
	208	{
	209	SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
	210	IMEM_SEGMENTS = 8, /* 1MB */
	211	DMEM_SEGMENTS = 8, /* 1MB */
	212	UMEM_SEGMENTS = 128 /* 16MB */
	213	};
	214
	215	struct d10v_memory
	216	{
eae126cb MF	217	uint8_t *insn[IMEM_SEGMENTS];
	218	uint8_t *data[DMEM_SEGMENTS];
	219	uint8_t *unif[UMEM_SEGMENTS];
4ce44c66 JM	220	};
4ce44c66 JM	221
c906108c SS	222	struct _state
	223	{
	224	reg_t regs[16]; /* general-purpose registers */
	225	#define GPR(N) (State.regs[(N)] + 0)
	226	#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
	227
eae126cb MF	228	#define GPR32(N) ((((uint32_t) State.regs[(N) + 0]) << 16) \
eae126cb MF	229	\| (uint16_t) State.regs[(N) + 1])
c906108c SS	230	#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
	231
	232	reg_t cregs[16]; /* control registers */
	233	#define CREG(N) (State.cregs[(N)] + 0)
67954606 MF	234	#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
67954606 MF	235	#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
c906108c SS	236
	237	reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
	238	#define HELD_SP(N) (State.sp[(N)] + 0)
	239	#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
	240
eae126cb	241	int64_t a[2]; /* accumulators */
c906108c SS	242	#define ACC(N) (State.a[(N)] + 0)
	243	#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
	244
	245	/* writeback info */
	246	struct slot slot[NR_SLOTS];
	247	int slot_nr;
	248
	249	/* trace data */
	250	struct {
eae126cb	251	uint16_t psw;
c906108c SS	252	} trace;
c906108c SS	253
eae126cb	254	uint8_t exe;
c906108c SS	255	int pc_changed;
c906108c SS	256
4ce44c66 JM	257	/* NOTE: everything below this line is not reset by
	258	sim_create_inferior() */
	259
	260	struct d10v_memory mem;
	261
c906108c SS	262	enum _ins_type ins_type;
c906108c SS	263
7eb99e5e MF	264	};
	265
	266	extern struct _state State;
c906108c SS	267
c906108c SS	268
eae126cb	269	extern uint16_t OP[4];
c906108c	270	extern struct simops Simops[];
c906108c SS	271
	272	enum
	273	{
	274	PSW_CR = 0,
	275	BPSW_CR = 1,
	276	PC_CR = 2,
	277	BPC_CR = 3,
	278	DPSW_CR = 4,
	279	DPC_CR = 5,
	280	RPT_C_CR = 7,
	281	RPT_S_CR = 8,
	282	RPT_E_CR = 9,
	283	MOD_S_CR = 10,
	284	MOD_E_CR = 11,
	285	IBA_CR = 14,
	286	};
	287
	288	enum
	289	{
	290	PSW_SM_BIT = 0x8000,
	291	PSW_EA_BIT = 0x2000,
	292	PSW_DB_BIT = 0x1000,
	293	PSW_DM_BIT = 0x0800,
	294	PSW_IE_BIT = 0x0400,
	295	PSW_RP_BIT = 0x0200,
	296	PSW_MD_BIT = 0x0100,
	297	PSW_FX_BIT = 0x0080,
	298	PSW_ST_BIT = 0x0040,
	299	PSW_F0_BIT = 0x0008,
	300	PSW_F1_BIT = 0x0004,
	301	PSW_C_BIT = 0x0001,
	302	};
	303
	304	#define PSW CREG (PSW_CR)
	305	#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
4ce44c66	306	#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
67954606	307	#define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
c906108c SS	308
	309	#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
	310	#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
	311
	312	#define PSW_EA ((PSW & PSW_EA_BIT) != 0)
	313	#define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL))
	314
	315	#define PSW_DB ((PSW & PSW_DB_BIT) != 0)
	316	#define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL))
	317
	318	#define PSW_DM ((PSW & PSW_DM_BIT) != 0)
	319	#define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL))
	320
	321	#define PSW_IE ((PSW & PSW_IE_BIT) != 0)
	322	#define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL))
	323
	324	#define PSW_RP ((PSW & PSW_RP_BIT) != 0)
	325	#define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL))
	326
	327	#define PSW_MD ((PSW & PSW_MD_BIT) != 0)
	328	#define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL))
	329
	330	#define PSW_FX ((PSW & PSW_FX_BIT) != 0)
	331	#define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL))
	332
	333	#define PSW_ST ((PSW & PSW_ST_BIT) != 0)
	334	#define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL))
	335
	336	#define PSW_F0 ((PSW & PSW_F0_BIT) != 0)
	337	#define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL))
	338
	339	#define PSW_F1 ((PSW & PSW_F1_BIT) != 0)
	340	#define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL))
	341
	342	#define PSW_C ((PSW & PSW_C_BIT) != 0)
	343	#define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL))
	344
	345	/* See simopsc.:move_to_cr() for registers that can not be read-from
	346	or assigned-to directly */
	347
	348	#define PC CREG (PC_CR)
	349	#define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
	350
	351	#define BPSW CREG (BPSW_CR)
	352	#define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL))
	353
	354	#define BPC CREG (BPC_CR)
	355	#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
	356
	357	#define DPSW CREG (DPSW_CR)
	358	#define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL))
	359
	360	#define DPC CREG (DPC_CR)
	361	#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
	362
	363	#define RPT_C CREG (RPT_C_CR)
	364	#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
	365
	366	#define RPT_S CREG (RPT_S_CR)
	367	#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
	368
	369	#define RPT_E CREG (RPT_E_CR)
	370	#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
	371
372	#define MOD_S CREG (MOD_S_CR)
373	#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
374
375	#define MOD_E CREG (MOD_E_CR)
376	#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
377
378	#define IBA CREG (IBA_CR)
379	#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
380
381
382	#define SIG_D10V_STOP -1
383	#define SIG_D10V_EXIT -2
7fc5b5ad	384	#define SIG_D10V_BUS -3
c906108c	385
541ebcee MF	386	/* TODO: Resolve conflicts with common headers. */
	387	#undef SEXT8
	388	#undef SEXT16
	389	#undef SEXT32
	390	#undef MASK32
	391
c906108c SS	392	#define SEXT3(x) ((((x)&0x7)^(~3))+4)
	393
	394	/* sign-extend a 4-bit number */
	395	#define SEXT4(x) ((((x)&0xf)^(~7))+8)
	396
	397	/* sign-extend an 8-bit number */
	398	#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
	399
	400	/* sign-extend a 16-bit number */
	401	#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
	402
	403	/* sign-extend a 32-bit number */
	404	#define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))
	405
	406	/* sign extend a 40 bit number */
	407	#define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))
	408
	409	/* sign extend a 44 bit number */
	410	#define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))
	411
	412	/* sign extend a 56 bit number */
	413	#define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))
	414
	415	/* sign extend a 60 bit number */
	416	#define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))
	417
	418	#define MAX32 SIGNED64(0x7fffffff)
	419	#define MIN32 SIGNED64(0xff80000000)
	420	#define MASK32 SIGNED64(0xffffffff)
	421	#define MASK40 SIGNED64(0xffffffffff)
	422
	423	/* The alignment of MOD_E in the following macro depends upon "i"
	424	always being a power of 2. */
	425	#define INC_ADDR(x,i) \
	426	do \
	427	{ \
c3f6f71d JM	428	int test_i = i < 0 ? i : ~((i) - 1); \
c3f6f71d JM	429	if (PSW_MD && GPR (x) == (MOD_E & test_i)) \
c7675842	430	SET_GPR (x, MOD_S & test_i); \
c906108c SS	431	else \
	432	SET_GPR (x, GPR (x) + (i)); \
	433	} \
	434	while (0)
	435
eae126cb MF	436	extern uint8_t dmem_addr (SIM_DESC, SIM_CPU , uint16_t offset);
eae126cb MF	437	extern uint8_t imem_addr (SIM_DESC, SIM_CPU , uint32_t);
c906108c	438
67954606	439	#define RB(x) (*(dmem_addr (sd, cpu, x)))
c906108c SS	440	#define SB(addr,data) ( RB(addr) = (data & 0xff))
	441
	442	#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
	443	#define ENDIAN_INLINE static __inline__
	444	#include "endian.c"
	445	#undef ENDIAN_INLINE
	446
	447	#else
eae126cb MF	448	extern uint32_t get_longword (uint8_t *);
	449	extern uint16_t get_word (uint8_t *);
	450	extern int64_t get_longlong (uint8_t *);
	451	extern void write_word (uint8_t *addr, uint16_t data);
	452	extern void write_longword (uint8_t *addr, uint32_t data);
	453	extern void write_longlong (uint8_t *addr, int64_t data);
c906108c SS	454	#endif
c906108c SS	455
67954606 MF	456	#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
	457	#define RW(x) get_word (dmem_addr (sd, cpu, x))
	458	#define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data)
	459	#define RLW(x) get_longword (dmem_addr (sd, cpu, x))
c906108c SS	460	#define READ_16(x) get_word(x)
	461	#define WRITE_16(addr,data) write_word(addr,data)
	462	#define READ_64(x) get_longlong(x)
	463	#define WRITE_64(addr,data) write_longlong(addr,data)
	464
c906108c SS	465	#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
	466
	467	#define RIE_VECTOR_START 0xffc2
	468	#define AE_VECTOR_START 0xffc3
	469	#define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
	470	#define DBT_VECTOR_START 0xffd4
	471	#define SDBT_VECTOR_START 0xffd5
	472
4ce44c66 JM	473	/* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
	474	cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) \|
	475	(VAL & ~MASK)). In addition, unless PSW_HW_P, a VAL intended for
	476	PSW is masked for zero bits. */
	477
67954606	478	extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);