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Fix HI16 and HI16_S relocations for PR14258
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
fd435e9f
MM		 1#include "config.h"
2
4f425a32 3#include <signal.h>
63a91cfb
MM		 4#include <errno.h>
5#include <sys/types.h>
6#include <sys/stat.h>
fd435e9f 7#ifdef HAVE_UNISTD_H
63a91cfb 8#include <unistd.h>
fd435e9f 9#endif
63a91cfb 10
2934d1c9
MH		 11#include "d10v_sim.h"
12#include "simops.h"
8719be26 13#include "sys/syscall.h"
2934d1c9 14
c422ecc7
MH		 15extern char *strrchr ();
16
87178dbd
MM		 17enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
60fc5b72 30 OP_FLAG_OUTPUT,
87178dbd 31 OP_CONSTANT16,
a18cb100 32 OP_CONSTANT8,
87178dbd
MM		 33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
a18cb100
MM		 39 OP_PREDEC,
40 OP_R2,
8918b3a7
MM		 41 OP_R3,
42 OP_R4,
43 OP_R2R3
87178dbd
MM		 44};
45
7eebfc62 46#ifdef DEBUG
a49a15ad
MM		 47static void trace_input_func PARAMS ((char *name,
48 enum op_types in1,
49 enum op_types in2,
50 enum op_types in3));
87178dbd 51
a49a15ad
MM		 52#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
53
54static void trace_output_func PARAMS ((enum op_types result));
55
56#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
57
87178dbd 58#ifndef SIZE_INSTRUCTION
a49a15ad 59#define SIZE_INSTRUCTION 8
87178dbd
MM		 60#endif
61
62#ifndef SIZE_OPERANDS
a49a15ad 63#define SIZE_OPERANDS 18
87178dbd
MM		 64#endif
65
66#ifndef SIZE_VALUES
67#define SIZE_VALUES 13
68#endif
69
a49a15ad
MM		 70#ifndef SIZE_LOCATION
71#define SIZE_LOCATION 20
72#endif
73
891513ee
MM		 74#ifndef SIZE_PC
75#define SIZE_PC 6
76#endif
77
78#ifndef SIZE_LINE_NUMBER
79#define SIZE_LINE_NUMBER 4
80#endif
81
87178dbd 82static void
a49a15ad 83trace_input_func (name, in1, in2, in3)
87178dbd
MM		 84 char *name;
85 enum op_types in1;
86 enum op_types in2;
87 enum op_types in3;
88{
89 char *comma;
90 enum op_types in[3];
91 int i;
a49a15ad 92 char buf[1024];
87178dbd
MM		 93 char *p;
94 long tmp;
95 char *type;
a49a15ad
MM		 96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
87178dbd 100
7eebfc62
MM		 101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
87178dbd
MM		 104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
c422ecc7
MH		 112 case INS_LEFT_COND_TEST: type = "?L"; break;
113 case INS_RIGHT_COND_TEST: type = "?R"; break;
114 case INS_LEFT_COND_EXE: type = "&L"; break;
115 case INS_RIGHT_COND_EXE: type = "&R"; break;
87178dbd
MM		 116 case INS_LONG: type = " B"; break;
117 }
118
a49a15ad
MM		 119 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
120 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 121 "0x%.*x %s: %-*s ",
891513ee
MM		 122 SIZE_PC, (unsigned)PC,
123 type,
a49a15ad
MM		 124 SIZE_INSTRUCTION, name);
125
126 else
127 {
891513ee 128 buf[0] = '\0';
b30cdd35 129 byte_pc = decode_pc ();
a49a15ad
MM		 130 if (text && byte_pc >= text_start && byte_pc < text_end)
131 {
132 filename = (const char *)0;
133 functionname = (const char *)0;
134 linenumber = 0;
b83093ff 135 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 136 &filename, &functionname, &linenumber))
137 {
138 p = buf;
139 if (linenumber)
140 {
891513ee 141 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 142 p += strlen (p);
143 }
891513ee
MM		 144 else
145 {
146 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
147 p += SIZE_LINE_NUMBER+2;
148 }
a49a15ad
MM		 149
150 if (functionname)
151 {
152 sprintf (p, "%s ", functionname);
153 p += strlen (p);
154 }
155 else if (filename)
156 {
c422ecc7 157 char *q = strrchr (filename, '/');
a49a15ad
MM		 158 sprintf (p, "%s ", (q) ? q+1 : filename);
159 p += strlen (p);
160 }
161
162 if (*p == ' ')
163 *p = '\0';
164 }
165 }
166
167 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 168 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 169 SIZE_PC, (unsigned)PC,
170 type,
a49a15ad
MM		 171 SIZE_LOCATION, SIZE_LOCATION, buf,
172 SIZE_INSTRUCTION, name);
173 }
87178dbd
MM		 174
175 in[0] = in1;
176 in[1] = in2;
177 in[2] = in3;
178 comma = "";
179 p = buf;
180 for (i = 0; i < 3; i++)
181 {
182 switch (in[i])
183 {
184 case OP_VOID:
a18cb100
MM		 185 case OP_R2:
186 case OP_R3:
8918b3a7 187 case OP_R4:
c422ecc7 188 case OP_R2R3:
87178dbd
MM		 189 break;
190
191 case OP_REG:
192 case OP_REG_OUTPUT:
193 case OP_DREG:
194 case OP_DREG_OUTPUT:
195 sprintf (p, "%sr%d", comma, OP[i]);
196 p += strlen (p);
197 comma = ",";
198 break;
199
200 case OP_CR:
201 case OP_CR_OUTPUT:
202 case OP_CR_REVERSE:
203 sprintf (p, "%scr%d", comma, OP[i]);
204 p += strlen (p);
205 comma = ",";
206 break;
207
208 case OP_ACCUM:
209 case OP_ACCUM_OUTPUT:
210 case OP_ACCUM_REVERSE:
211 sprintf (p, "%sa%d", comma, OP[i]);
212 p += strlen (p);
213 comma = ",";
214 break;
215
216 case OP_CONSTANT16:
217 sprintf (p, "%s%d", comma, OP[i]);
218 p += strlen (p);
219 comma = ",";
220 break;
221
a18cb100
MM		 222 case OP_CONSTANT8:
223 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
224 p += strlen (p);
225 comma = ",";
226 break;
227
87178dbd
MM		 228 case OP_CONSTANT4:
229 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
230 p += strlen (p);
231 comma = ",";
232 break;
233
234 case OP_CONSTANT3:
235 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
236 p += strlen (p);
237 comma = ",";
238 break;
239
240 case OP_MEMREF:
241 sprintf (p, "%s@r%d", comma, OP[i]);
242 p += strlen (p);
243 comma = ",";
244 break;
245
246 case OP_MEMREF2:
247 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
248 p += strlen (p);
249 comma = ",";
250 break;
251
252 case OP_POSTINC:
253 sprintf (p, "%s@r%d+", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_POSTDEC:
259 sprintf (p, "%s@r%d-", comma, OP[i]);
260 p += strlen (p);
261 comma = ",";
262 break;
263
264 case OP_PREDEC:
265 sprintf (p, "%s@-r%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_FLAG:
60fc5b72 271 case OP_FLAG_OUTPUT:
87178dbd
MM		 272 if (OP[i] == 0)
273 sprintf (p, "%sf0", comma);
274
275 else if (OP[i] == 1)
276 sprintf (p, "%sf1", comma);
277
278 else
60fc5b72 279 sprintf (p, "%sc", comma);
87178dbd
MM		 280
281 p += strlen (p);
282 comma = ",";
283 break;
284 }
285 }
286
7eebfc62
MM		 287 if ((d10v_debug & DEBUG_VALUES) == 0)
288 {
289 *p++ = '\n';
290 *p = '\0';
291 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
292 }
293 else
294 {
295 *p = '\0';
296 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 297
7eebfc62
MM		 298 p = buf;
299 for (i = 0; i < 3; i++)
300 {
301 buf[0] = '\0';
302 switch (in[i])
303 {
304 case OP_VOID:
305 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
306 break;
307
308 case OP_REG_OUTPUT:
309 case OP_DREG_OUTPUT:
310 case OP_CR_OUTPUT:
311 case OP_ACCUM_OUTPUT:
60fc5b72 312 case OP_FLAG_OUTPUT:
7eebfc62
MM		 313 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
314 break;
315
316 case OP_REG:
317 case OP_MEMREF:
318 case OP_POSTDEC:
319 case OP_POSTINC:
320 case OP_PREDEC:
321 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
322 (uint16)State.regs[OP[i]]);
323 break;
324
325 case OP_DREG:
326 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
327 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
328 break;
329
330 case OP_CR:
331 case OP_CR_REVERSE:
332 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
333 (uint16)State.cregs[OP[i]]);
334 break;
335
336 case OP_ACCUM:
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[i]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
341 break;
342
343 case OP_CONSTANT16:
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
345 (uint16)OP[i]);
346 break;
347
348 case OP_CONSTANT4:
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)SEXT4(OP[i]));
351 break;
352
a18cb100
MM		 353 case OP_CONSTANT8:
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)SEXT8(OP[i]));
356 break;
357
7eebfc62
MM		 358 case OP_CONSTANT3:
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT3(OP[i]));
361 break;
362
363 case OP_FLAG:
364 if (OP[i] == 0)
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
366 State.F0 != 0);
367
368 else if (OP[i] == 1)
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
370 State.F1 != 0);
371
372 else
373 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
374 State.C != 0);
375
376 break;
377
378 case OP_MEMREF2:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16)OP[i]);
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
382 (uint16)State.regs[OP[++i]]);
383 break;
a18cb100
MM		 384
385 case OP_R2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)State.regs[2]);
388 break;
389
390 case OP_R3:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[3]);
393 break;
8918b3a7
MM		 394
395 case OP_R4:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[4]);
398 break;
c422ecc7
MH		 399
400 case OP_R2R3:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[2]);
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[3]);
405 i++;
406 break;
7eebfc62
MM		 407 }
408 }
409 }
fd435e9f
MM		 410
411 (*d10v_callback->flush_stdout) (d10v_callback);
7eebfc62 412}
87178dbd 413
7eebfc62 414static void
a49a15ad 415trace_output_func (result)
7eebfc62
MM		 416 enum op_types result;
417{
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 419 {
7eebfc62 420 long tmp;
87178dbd 421
7eebfc62
MM		 422 switch (result)
423 {
424 default:
425 putchar ('\n');
87178dbd
MM		 426 break;
427
428 case OP_REG:
7eebfc62
MM		 429 case OP_REG_OUTPUT:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 433 break;
434
435 case OP_DREG:
7eebfc62
MM		 436 case OP_DREG_OUTPUT:
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 440 break;
441
442 case OP_CR:
7eebfc62
MM		 443 case OP_CR_OUTPUT:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 447 break;
448
7eebfc62
MM		 449 case OP_CR_REVERSE:
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 453 break;
454
7eebfc62
MM		 455 case OP_ACCUM:
456 case OP_ACCUM_OUTPUT:
069398aa 457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 461 break;
462
7eebfc62 463 case OP_ACCUM_REVERSE:
069398aa 464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 468 break;
469
470 case OP_FLAG:
60fc5b72 471 case OP_FLAG_OUTPUT:
7eebfc62
MM		 472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd 474 break;
8918b3a7
MM		 475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
481
482 case OP_R2R3:
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
486 break;
87178dbd
MM		 487 }
488 }
fd435e9f
MM		 489
490 (*d10v_callback->flush_stdout) (d10v_callback);
87178dbd
MM		 491}
492
493#else
494#define trace_input(NAME, IN1, IN2, IN3)
495#define trace_output(RESULT)
496#endif
2934d1c9
MH		 497
498/* abs */
499void
500OP_4607 ()
501{
87178dbd 502 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 503 State.F1 = State.F0;
504 if ((int16)(State.regs[OP[0]]) < 0)
505 {
506 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
507 State.F0 = 1;
508 }
509 else
510 State.F0 = 0;
87178dbd 511 trace_output (OP_REG);
2934d1c9
MH		 512}
513
514/* abs */
515void
516OP_5607 ()
517{
518 int64 tmp;
519
87178dbd 520 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 521 State.F1 = State.F0;
522 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
523
4c38885c 524 if (State.a[OP[0]] < 0 )
2934d1c9 525 {
4c38885c 526 tmp = -State.a[OP[0]];
2934d1c9
MH		 527 if (State.ST)
528 {
4c38885c 529 if (tmp > MAX32)
2934d1c9 530 State.a[OP[0]] = MAX32;
4c38885c 531 else if (tmp < MIN32)
2934d1c9
MH		 532 State.a[OP[0]] = MIN32;
533 else
4f425a32 534 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 535 }
536 else
4f425a32 537 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 538 State.F0 = 1;
539 }
540 else
541 State.F0 = 0;
87178dbd 542 trace_output (OP_ACCUM);
2934d1c9
MH		 543}
544
545/* add */
546void
547OP_200 ()
548{
549 uint16 tmp = State.regs[OP[0]];
87178dbd 550 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 551 State.regs[OP[0]] += State.regs[OP[1]];
552 if ( tmp > State.regs[OP[0]])
553 State.C = 1;
554 else
555 State.C = 0;
87178dbd 556 trace_output (OP_REG);
2934d1c9
MH		 557}
558
559/* add */
560void
561OP_1201 ()
562{
4c38885c 563 int64 tmp;
4f425a32 564 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 565
566 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 567 if (State.ST)
568 {
569 if ( tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
4f425a32 574 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 575 }
576 else
4f425a32 577 State.a[OP[0]] = tmp & MASK40;
87178dbd 578 trace_output (OP_ACCUM);
2934d1c9
MH		 579}
580
581/* add */
582void
583OP_1203 ()
584{
4c38885c 585 int64 tmp;
4f425a32 586 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 587
588 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 589 if (State.ST)
590 {
591 if (tmp > MAX32)
592 State.a[OP[0]] = MAX32;
593 else if ( tmp < MIN32)
594 State.a[OP[0]] = MIN32;
595 else
4f425a32 596 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 597 }
598 else
4f425a32 599 State.a[OP[0]] = tmp & MASK40;
87178dbd 600 trace_output (OP_ACCUM);
2934d1c9
MH		 601}
602
603/* add2w */
604void
605OP_1200 ()
606{
607 uint32 tmp;
f4b022d3
MM		 608 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
609 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 610
611 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 612 tmp = a + b;
613 State.C = (tmp < a);
2934d1c9
MH		 614 State.regs[OP[0]] = tmp >> 16;
615 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 616 trace_output (OP_DREG);
2934d1c9
MH		 617}
618
619/* add3 */
620void
621OP_1000000 ()
622{
f4b022d3
MM		 623 uint16 tmp = State.regs[OP[1]];
624 State.regs[OP[0]] = tmp + OP[2];
87178dbd
MM		 625
626 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
f4b022d3 627 State.C = (State.regs[OP[0]] < tmp);
87178dbd 628 trace_output (OP_REG);
2934d1c9
MH		 629}
630
631/* addac3 */
632void
633OP_17000200 ()
634{
4c38885c 635 int64 tmp;
4f425a32 636 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 637
638 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 639 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
640 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 641 trace_output (OP_DREG);
2934d1c9
MH		 642}
643
644/* addac3 */
645void
646OP_17000202 ()
647{
4c38885c 648 int64 tmp;
4f425a32 649 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 650
651 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 652 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
653 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 654 trace_output (OP_DREG);
2934d1c9
MH		 655}
656
657/* addac3s */
658void
659OP_17001200 ()
660{
4c38885c 661 int64 tmp;
4c38885c 662 State.F1 = State.F0;
87178dbd
MM		 663
664 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 665 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 666 if ( tmp > MAX32)
667 {
668 State.regs[OP[0]] = 0x7fff;
669 State.regs[OP[0]+1] = 0xffff;
670 State.F0 = 1;
671 }
672 else if (tmp < MIN32)
673 {
674 State.regs[OP[0]] = 0x8000;
675 State.regs[OP[0]+1] = 0;
676 State.F0 = 1;
677 }
678 else
679 {
680 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
681 State.regs[OP[0]+1] = tmp & 0xffff;
682 State.F0 = 0;
683 }
87178dbd 684 trace_output (OP_DREG);
2934d1c9
MH		 685}
686
687/* addac3s */
688void
689OP_17001202 ()
690{
4c38885c 691 int64 tmp;
4c38885c 692 State.F1 = State.F0;
87178dbd
MM		 693
694 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 695 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 696 if ( tmp > MAX32)
697 {
698 State.regs[OP[0]] = 0x7fff;
699 State.regs[OP[0]+1] = 0xffff;
700 State.F0 = 1;
701 }
702 else if (tmp < MIN32)
703 {
704 State.regs[OP[0]] = 0x8000;
705 State.regs[OP[0]+1] = 0;
706 State.F0 = 1;
707 }
708 else
709 {
710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
712 State.F0 = 0;
713 }
87178dbd 714 trace_output (OP_DREG);
2934d1c9
MH		 715}
716
717/* addi */
718void
719OP_201 ()
720{
2254cd90 721 uint tmp = State.regs[OP[0]];
4f425a32
MH		 722 if (OP[1] == 0)
723 OP[1] = 16;
f4b022d3 724
87178dbd 725 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 726 State.regs[OP[0]] += OP[1];
f4b022d3 727 State.C = (State.regs[OP[0]] < tmp);
87178dbd 728 trace_output (OP_REG);
2934d1c9
MH		 729}
730
731/* and */
732void
733OP_C00 ()
734{
87178dbd 735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 736 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 737 trace_output (OP_REG);
2934d1c9
MH		 738}
739
740/* and3 */
741void
742OP_6000000 ()
743{
87178dbd 744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 746 trace_output (OP_REG);
2934d1c9
MH		 747}
748
749/* bclri */
750void
751OP_C01 ()
752{
87178dbd 753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 755 trace_output (OP_REG);
2934d1c9
MH		 756}
757
758/* bl.s */
759void
760OP_4900 ()
761{
a18cb100 762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
2934d1c9 763 State.regs[13] = PC+1;
fd435e9f 764 JMP( PC + SEXT8 (OP[0]));
87178dbd 765 trace_output (OP_VOID);
2934d1c9
MH		 766}
767
768/* bl.l */
769void
770OP_24800000 ()
771{
a18cb100 772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
2934d1c9 773 State.regs[13] = PC+1;
fd435e9f 774 JMP (PC + OP[0]);
87178dbd 775 trace_output (OP_VOID);
2934d1c9
MH		 776}
777
778/* bnoti */
779void
780OP_A01 ()
781{
87178dbd 782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 784 trace_output (OP_REG);
2934d1c9
MH		 785}
786
787/* bra.s */
788void
789OP_4800 ()
790{
a18cb100 791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
fd435e9f 792 JMP (PC + SEXT8 (OP[0]));
87178dbd 793 trace_output (OP_VOID);
2934d1c9
MH		 794}
795
796/* bra.l */
797void
798OP_24000000 ()
799{
87178dbd 800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
fd435e9f 801 JMP (PC + OP[0]);
87178dbd 802 trace_output (OP_VOID);
2934d1c9
MH		 803}
804
805/* brf0f.s */
806void
807OP_4A00 ()
808{
a18cb100 809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 810 if (State.F0 == 0)
fd435e9f 811 JMP (PC + SEXT8 (OP[0]));
87178dbd 812 trace_output (OP_FLAG);
2934d1c9
MH		 813}
814
815/* brf0f.l */
816void
817OP_25000000 ()
818{
87178dbd 819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 820 if (State.F0 == 0)
fd435e9f 821 JMP (PC + OP[0]);
87178dbd 822 trace_output (OP_FLAG);
2934d1c9
MH		 823}
824
825/* brf0t.s */
826void
827OP_4B00 ()
828{
a18cb100 829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 830 if (State.F0)
fd435e9f 831 JMP (PC + SEXT8 (OP[0]));
87178dbd 832 trace_output (OP_FLAG);
2934d1c9
MH		 833}
834
835/* brf0t.l */
836void
837OP_25800000 ()
838{
87178dbd 839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 840 if (State.F0)
fd435e9f 841 JMP (PC + OP[0]);
87178dbd 842 trace_output (OP_FLAG);
2934d1c9
MH		 843}
844
845/* bseti */
846void
847OP_801 ()
848{
87178dbd 849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 850 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 851 trace_output (OP_REG);
2934d1c9
MH		 852}
853
854/* btsti */
855void
856OP_E01 ()
857{
87178dbd 858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 859 State.F1 = State.F0;
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 861 trace_output (OP_FLAG);
2934d1c9
MH		 862}
863
864/* clrac */
865void
866OP_5601 ()
867{
87178dbd 868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 869 State.a[OP[0]] = 0;
87178dbd 870 trace_output (OP_ACCUM);
2934d1c9
MH		 871}
872
873/* cmp */
874void
875OP_600 ()
876{
87178dbd 877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 878 State.F1 = State.F0;
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 880 trace_output (OP_FLAG);
2934d1c9
MH		 881}
882
883/* cmp */
884void
885OP_1603 ()
886{
87178dbd 887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 888 State.F1 = State.F0;
4f425a32 889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 890 trace_output (OP_FLAG);
2934d1c9
MH		 891}
892
893/* cmpeq */
894void
895OP_400 ()
896{
87178dbd 897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 898 State.F1 = State.F0;
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 900 trace_output (OP_FLAG);
2934d1c9
MH		 901}
902
903/* cmpeq */
904void
905OP_1403 ()
906{
87178dbd 907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 908 State.F1 = State.F0;
fd435e9f 909 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
87178dbd 910 trace_output (OP_FLAG);
2934d1c9
MH		 911}
912
913/* cmpeqi.s */
914void
915OP_401 ()
916{
c12f5c67 917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 918 State.F1 = State.F0;
c12f5c67 919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 920 trace_output (OP_FLAG);
2934d1c9
MH		 921}
922
923/* cmpeqi.l */
924void
925OP_2000000 ()
926{
87178dbd 927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 928 State.F1 = State.F0;
c12f5c67 929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 930 trace_output (OP_FLAG);
2934d1c9
MH		 931}
932
933/* cmpi.s */
934void
935OP_601 ()
936{
87178dbd 937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 938 State.F1 = State.F0;
c12f5c67 939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 940 trace_output (OP_FLAG);
2934d1c9
MH		 941}
942
943/* cmpi.l */
944void
945OP_3000000 ()
946{
87178dbd 947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 950 trace_output (OP_FLAG);
2934d1c9
MH		 951}
952
953/* cmpu */
954void
955OP_4600 ()
956{
87178dbd 957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 958 State.F1 = State.F0;
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 960 trace_output (OP_FLAG);
2934d1c9
MH		 961}
962
963/* cmpui */
964void
965OP_23000000 ()
966{
87178dbd 967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 968 State.F1 = State.F0;
c12f5c67 969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 970 trace_output (OP_FLAG);
2934d1c9
MH		 971}
972
973/* cpfg */
974void
975OP_4E09 ()
976{
977 uint8 *src, *dst;
2934d1c9 978
60fc5b72 979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 980 if (OP[0] == 0)
981 dst = &State.F0;
982 else
983 dst = &State.F1;
984
985 if (OP[1] == 0)
986 src = &State.F0;
987 else if (OP[1] == 1)
988 src = &State.F1;
989 else
990 src = &State.C;
991
992 *dst = *src;
87178dbd 993 trace_output (OP_FLAG);
2934d1c9
MH		 994}
995
996/* dbt */
997void
998OP_5F20 ()
999{
a49a15ad 1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 1001 State.exception = SIGTRAP;
2934d1c9
MH		 1002}
1003
1004/* divs */
1005void
1006OP_14002800 ()
1007{
1008 uint16 foo, tmp, tmpf;
87178dbd
MM		 1009
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1016 trace_output (OP_DREG);
2934d1c9
MH		 1017}
1018
1019/* exef0f */
1020void
1021OP_4E04 ()
1022{
87178dbd 1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1024 State.exe = (State.F0 == 0);
87178dbd 1025 trace_output (OP_FLAG);
2934d1c9
MH		 1026}
1027
1028/* exef0t */
1029void
1030OP_4E24 ()
1031{
87178dbd 1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1033 State.exe = (State.F0 != 0);
87178dbd 1034 trace_output (OP_FLAG);
2934d1c9
MH		 1035}
1036
1037/* exef1f */
1038void
1039OP_4E40 ()
1040{
87178dbd 1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1042 State.exe = (State.F1 == 0);
87178dbd 1043 trace_output (OP_FLAG);
2934d1c9
MH		 1044}
1045
1046/* exef1t */
1047void
1048OP_4E42 ()
1049{
87178dbd 1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1051 State.exe = (State.F1 != 0);
87178dbd 1052 trace_output (OP_FLAG);
2934d1c9
MH		 1053}
1054
1055/* exefaf */
1056void
1057OP_4E00 ()
1058{
87178dbd 1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1061 trace_output (OP_FLAG);
2934d1c9
MH		 1062}
1063
1064/* exefat */
1065void
1066OP_4E02 ()
1067{
87178dbd 1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1070 trace_output (OP_FLAG);
2934d1c9
MH		 1071}
1072
1073/* exetaf */
1074void
1075OP_4E20 ()
1076{
87178dbd 1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1079 trace_output (OP_FLAG);
2934d1c9
MH		 1080}
1081
1082/* exetat */
1083void
1084OP_4E22 ()
1085{
87178dbd 1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1088 trace_output (OP_FLAG);
2934d1c9
MH		 1089}
1090
1091/* exp */
1092void
1093OP_15002A00 ()
1094{
1095 uint32 tmp, foo;
1096 int i;
1097
87178dbd 1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1101 else
4c38885c 1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1103
1104 foo = 0x40000000;
4c38885c 1105 for (i=1;i<17;i++)
2934d1c9
MH		 1106 {
1107 if (tmp & foo)
1108 {
1109 State.regs[OP[0]] = i-1;
87178dbd 1110 trace_output (OP_REG);
2934d1c9
MH		 1111 return;
1112 }
4c38885c 1113 foo >>= 1;
2934d1c9
MH		 1114 }
1115 State.regs[OP[0]] = 16;
87178dbd 1116 trace_output (OP_REG);
2934d1c9
MH		 1117}
1118
1119/* exp */
1120void
1121OP_15002A02 ()
1122{
4c38885c
MH		 1123 int64 tmp, foo;
1124 int i;
87178dbd
MM		 1125
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
fd435e9f
MM		 1127 tmp = SEXT40(State.a[OP[1]]);
1128 if (tmp < 0)
1129 tmp = ~tmp & MASK40;
4c38885c
MH		 1130
1131 foo = 0x4000000000LL;
1132 for (i=1;i<25;i++)
1133 {
1134 if (tmp & foo)
1135 {
1136 State.regs[OP[0]] = i-9;
87178dbd 1137 trace_output (OP_REG);
4c38885c
MH		 1138 return;
1139 }
1140 foo >>= 1;
1141 }
1142 State.regs[OP[0]] = 16;
87178dbd 1143 trace_output (OP_REG);
2934d1c9
MH		 1144}
1145
1146/* jl */
1147void
1148OP_4D00 ()
1149{
a18cb100 1150 trace_input ("jl", OP_REG, OP_R2, OP_R3);
2934d1c9 1151 State.regs[13] = PC+1;
fd435e9f 1152 JMP (State.regs[OP[0]]);
87178dbd 1153 trace_output (OP_VOID);
2934d1c9
MH		 1154}
1155
1156/* jmp */
1157void
1158OP_4C00 ()
1159{
a18cb100
MM		 1160 trace_input ("jmp", OP_REG,
1161 (OP[0] == 13) ? OP_R2 : OP_VOID,
1162 (OP[0] == 13) ? OP_R3 : OP_VOID);
1163
fd435e9f 1164 JMP (State.regs[OP[0]]);
87178dbd 1165 trace_output (OP_VOID);
2934d1c9
MH		 1166}
1167
1168/* ld */
1169void
1170OP_30000000 ()
1171{
87178dbd 1172 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1173 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1174 trace_output (OP_REG);
2934d1c9
MH		 1175}
1176
1177/* ld */
1178void
1179OP_6401 ()
1180{
87178dbd 1181 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1182 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1183 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1184 trace_output (OP_REG);
2934d1c9
MH		 1185}
1186
1187/* ld */
1188void
1189OP_6001 ()
1190{
87178dbd 1191 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1192 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1193 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1194 trace_output (OP_REG);
2934d1c9
MH		 1195}
1196
1197/* ld */
1198void
1199OP_6000 ()
1200{
87178dbd 1201 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1202 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1203 trace_output (OP_REG);
2934d1c9
MH		 1204}
1205
1206/* ld2w */
1207void
1208OP_31000000 ()
1209{
8918b3a7 1210 uint16 addr = State.regs[OP[2]];
308f64d3 1211 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
8918b3a7
MM		 1212 State.regs[OP[0]] = RW (OP[1] + addr);
1213 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
87178dbd 1214 trace_output (OP_DREG);
2934d1c9
MH		 1215}
1216
1217/* ld2w */
1218void
1219OP_6601 ()
1220{
8918b3a7 1221 uint16 addr = State.regs[OP[1]];
87178dbd 1222 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
8918b3a7
MM		 1223 State.regs[OP[0]] = RW (addr);
1224 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1225 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1226 trace_output (OP_DREG);
2934d1c9
MH		 1227}
1228
1229/* ld2w */
1230void
1231OP_6201 ()
1232{
8918b3a7 1233 uint16 addr = State.regs[OP[1]];
87178dbd 1234 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
8918b3a7
MM		 1235 State.regs[OP[0]] = RW (addr);
1236 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1237 INC_ADDR(State.regs[OP[1]],4);
8918b3a7 1238 trace_output (OP_DREG);
2934d1c9
MH		 1239}
1240
1241/* ld2w */
1242void
1243OP_6200 ()
1244{
8918b3a7 1245 uint16 addr = State.regs[OP[1]];
addb61a5 1246 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
8918b3a7
MM		 1247 State.regs[OP[0]] = RW (addr);
1248 State.regs[OP[0]+1] = RW (addr+2);
1249 trace_output (OP_DREG);
2934d1c9
MH		 1250}
1251
1252/* ldb */
1253void
1254OP_38000000 ()
1255{
87178dbd 1256 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
c422ecc7 1257 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
87178dbd 1258 trace_output (OP_REG);
2934d1c9
MH		 1259}
1260
1261/* ldb */
1262void
1263OP_7000 ()
1264{
87178dbd 1265 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
c422ecc7 1266 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
87178dbd 1267 trace_output (OP_REG);
2934d1c9
MH		 1268}
1269
1270/* ldi.s */
1271void
1272OP_4001 ()
1273{
87178dbd 1274 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1275 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1276 trace_output (OP_REG);
2934d1c9
MH		 1277}
1278
1279/* ldi.l */
1280void
1281OP_20000000 ()
1282{
fd435e9f 1283 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1284 State.regs[OP[0]] = OP[1];
87178dbd 1285 trace_output (OP_REG);
2934d1c9
MH		 1286}
1287
1288/* ldub */
1289void
1290OP_39000000 ()
1291{
87178dbd 1292 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1293 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1294 trace_output (OP_REG);
2934d1c9
MH		 1295}
1296
1297/* ldub */
1298void
1299OP_7200 ()
1300{
87178dbd 1301 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1302 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1303 trace_output (OP_REG);
2934d1c9
MH		 1304}
1305
1306/* mac */
1307void
1308OP_2A00 ()
1309{
4c38885c 1310 int64 tmp;
87178dbd
MM		 1311
1312 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1313 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1314
1315 if (State.FX)
4f425a32 1316 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1317
1318 if (State.ST && tmp > MAX32)
1319 tmp = MAX32;
1320
4f425a32 1321 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1322 if (State.ST)
1323 {
1324 if (tmp > MAX32)
1325 State.a[OP[0]] = MAX32;
1326 else if (tmp < MIN32)
1327 State.a[OP[0]] = MIN32;
1328 else
4f425a32 1329 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1330 }
1331 else
4f425a32 1332 State.a[OP[0]] = tmp & MASK40;
87178dbd 1333 trace_output (OP_ACCUM);
2934d1c9
MH		 1334}
1335
1336/* macsu */
1337void
1338OP_1A00 ()
1339{
4f425a32 1340 int64 tmp;
87178dbd
MM		 1341
1342 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1343 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1344 if (State.FX)
1345 tmp = SEXT40( (tmp << 1) & MASK40);
1346
1347 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1348 trace_output (OP_ACCUM);
2934d1c9
MH		 1349}
1350
1351/* macu */
1352void
1353OP_3A00 ()
1354{
ae558075
AC		 1355 uint64 tmp;
1356 uint32 src1;
1357 uint32 src2;
87178dbd
MM		 1358
1359 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
ae558075
AC		 1360 src1 = (uint16) State.regs[OP[1]];
1361 src2 = (uint16) State.regs[OP[2]];
1362 tmp = src1 * src2;
4f425a32 1363 if (State.FX)
ae558075
AC		 1364 tmp = (tmp << 1);
1365 State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
87178dbd 1366 trace_output (OP_ACCUM);
2934d1c9
MH		 1367}
1368
1369/* max */
1370void
1371OP_2600 ()
1372{
87178dbd 1373 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1374 State.F1 = State.F0;
ea2155e8 1375 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1376 {
1377 State.regs[OP[0]] = State.regs[OP[1]];
1378 State.F0 = 1;
1379 }
1380 else
1381 State.F0 = 0;
87178dbd 1382 trace_output (OP_REG);
2934d1c9
MH		 1383}
1384
1385/* max */
1386void
1387OP_3600 ()
1388{
4f425a32 1389 int64 tmp;
87178dbd
MM		 1390
1391 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1392 State.F1 = State.F0;
1393 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1394 if (tmp > SEXT40(State.a[OP[0]]))
1395 {
1396 State.a[OP[0]] = tmp & MASK40;
1397 State.F0 = 1;
1398 }
1399 else
1400 State.F0 = 0;
87178dbd 1401 trace_output (OP_ACCUM);
2934d1c9
MH		 1402}
1403
1404/* max */
1405void
1406OP_3602 ()
1407{
87178dbd 1408 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1409 State.F1 = State.F0;
1410 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1411 {
1412 State.a[OP[0]] = State.a[OP[1]];
1413 State.F0 = 1;
1414 }
1415 else
1416 State.F0 = 0;
87178dbd 1417 trace_output (OP_ACCUM);
2934d1c9
MH		 1418}
1419
4f425a32 1420
2934d1c9
MH		 1421/* min */
1422void
1423OP_2601 ()
1424{
87178dbd 1425 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1426 State.F1 = State.F0;
ea2155e8 1427 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1428 {
1429 State.regs[OP[0]] = State.regs[OP[1]];
1430 State.F0 = 1;
1431 }
1432 else
1433 State.F0 = 0;
87178dbd 1434 trace_output (OP_REG);
2934d1c9
MH		 1435}
1436
1437/* min */
1438void
1439OP_3601 ()
1440{
4f425a32 1441 int64 tmp;
87178dbd
MM		 1442
1443 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1444 State.F1 = State.F0;
1445 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1446 if (tmp < SEXT40(State.a[OP[0]]))
1447 {
1448 State.a[OP[0]] = tmp & MASK40;
1449 State.F0 = 1;
1450 }
1451 else
1452 State.F0 = 0;
87178dbd 1453 trace_output (OP_ACCUM);
2934d1c9
MH		 1454}
1455
1456/* min */
1457void
1458OP_3603 ()
1459{
87178dbd 1460 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1461 State.F1 = State.F0;
1462 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1463 {
1464 State.a[OP[0]] = State.a[OP[1]];
1465 State.F0 = 1;
1466 }
1467 else
1468 State.F0 = 0;
87178dbd 1469 trace_output (OP_ACCUM);
2934d1c9
MH		 1470}
1471
1472/* msb */
1473void
1474OP_2800 ()
1475{
4f425a32 1476 int64 tmp;
87178dbd
MM		 1477
1478 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1479 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1480
1481 if (State.FX)
1482 tmp = SEXT40 ((tmp << 1) & MASK40);
1483
1484 if (State.ST && tmp > MAX32)
1485 tmp = MAX32;
1486
1487 tmp = SEXT40(State.a[OP[0]]) - tmp;
1488 if (State.ST)
1489 {
1490 if (tmp > MAX32)
1491 State.a[OP[0]] = MAX32;
1492 else if (tmp < MIN32)
1493 State.a[OP[0]] = MIN32;
1494 else
1495 State.a[OP[0]] = tmp & MASK40;
1496 }
1497 else
1498 State.a[OP[0]] = tmp & MASK40;
87178dbd 1499 trace_output (OP_ACCUM);
2934d1c9
MH		 1500}
1501
1502/* msbsu */
1503void
1504OP_1800 ()
1505{
4f425a32 1506 int64 tmp;
87178dbd
MM		 1507
1508 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1509 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1510 if (State.FX)
1511 tmp = SEXT40( (tmp << 1) & MASK40);
1512
1513 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1514 trace_output (OP_ACCUM);
2934d1c9
MH		 1515}
1516
1517/* msbu */
1518void
1519OP_3800 ()
1520{
d294a657
AC		 1521 uint64 tmp;
1522 uint32 src1;
1523 uint32 src2;
87178dbd
MM		 1524
1525 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
d294a657
AC		 1526 src1 = (uint16) State.regs[OP[1]];
1527 src2 = (uint16) State.regs[OP[2]];
1528 tmp = src1 * src2;
4f425a32 1529 if (State.FX)
d294a657 1530 tmp = (tmp << 1);
4f425a32 1531
d294a657 1532 State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40;
87178dbd 1533 trace_output (OP_ACCUM);
2934d1c9
MH		 1534}
1535
1536/* mul */
1537void
1538OP_2E00 ()
1539{
87178dbd 1540 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1541 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1542 trace_output (OP_REG);
2934d1c9
MH		 1543}
1544
1545/* mulx */
1546void
1547OP_2C00 ()
1548{
4f425a32 1549 int64 tmp;
87178dbd
MM		 1550
1551 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1552 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1553
1554 if (State.FX)
1555 tmp = SEXT40 ((tmp << 1) & MASK40);
1556
1557 if (State.ST && tmp > MAX32)
1558 State.a[OP[0]] = MAX32;
1559 else
1560 State.a[OP[0]] = tmp & MASK40;
87178dbd 1561 trace_output (OP_ACCUM);
2934d1c9
MH		 1562}
1563
1564/* mulxsu */
1565void
1566OP_1C00 ()
1567{
4f425a32 1568 int64 tmp;
87178dbd
MM		 1569
1570 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1571 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1572
1573 if (State.FX)
1574 tmp <<= 1;
1575
1576 State.a[OP[0]] = tmp & MASK40;
87178dbd 1577 trace_output (OP_ACCUM);
2934d1c9
MH		 1578}
1579
1580/* mulxu */
1581void
1582OP_3C00 ()
1583{
9420287e
AC		 1584 uint64 tmp;
1585 uint32 src1;
1586 uint32 src2;
87178dbd
MM		 1587
1588 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
9420287e
AC		 1589 src1 = (uint16) State.regs[OP[1]];
1590 src2 = (uint16) State.regs[OP[2]];
1591 tmp = src1 * src2;
4f425a32
MH		 1592 if (State.FX)
1593 tmp <<= 1;
1594
1595 State.a[OP[0]] = tmp & MASK40;
87178dbd 1596 trace_output (OP_ACCUM);
2934d1c9
MH		 1597}
1598
1599/* mv */
1600void
1601OP_4000 ()
1602{
87178dbd 1603 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1604 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1605 trace_output (OP_REG);
2934d1c9
MH		 1606}
1607
1608/* mv2w */
1609void
1610OP_5000 ()
1611{
87178dbd 1612 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1613 State.regs[OP[0]] = State.regs[OP[1]];
1614 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1615 trace_output (OP_DREG);
2934d1c9
MH		 1616}
1617
1618/* mv2wfac */
1619void
1620OP_3E00 ()
1621{
87178dbd 1622 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1623 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1624 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1625 trace_output (OP_DREG);
2934d1c9
MH		 1626}
1627
1628/* mv2wtac */
1629void
1630OP_3E01 ()
1631{
fd435e9f 1632 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
4f425a32 1633 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
fd435e9f 1634 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1635}
1636
1637/* mvac */
1638void
1639OP_3E03 ()
1640{
87178dbd 1641 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1642 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1643 trace_output (OP_ACCUM);
2934d1c9
MH		 1644}
1645
1646/* mvb */
1647void
1648OP_5400 ()
1649{
87178dbd 1650 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1651 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1652 trace_output (OP_REG);
2934d1c9
MH		 1653}
1654
1655/* mvf0f */
1656void
1657OP_4400 ()
1658{
87178dbd 1659 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1660 if (State.F0 == 0)
1661 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1662 trace_output (OP_REG);
2934d1c9
MH		 1663}
1664
1665/* mvf0t */
1666void
1667OP_4401 ()
1668{
87178dbd 1669 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1670 if (State.F0)
1671 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1672 trace_output (OP_REG);
2934d1c9
MH		 1673}
1674
1675/* mvfacg */
1676void
1677OP_1E04 ()
1678{
87178dbd 1679 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1680 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1681 trace_output (OP_ACCUM);
2934d1c9
MH		 1682}
1683
1684/* mvfachi */
1685void
1686OP_1E00 ()
1687{
87178dbd 1688 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1689 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1690 trace_output (OP_REG);
2934d1c9
MH		 1691}
1692
1693/* mvfaclo */
1694void
1695OP_1E02 ()
1696{
87178dbd 1697 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1698 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1699 trace_output (OP_REG);
2934d1c9
MH		 1700}
1701
1702/* mvfc */
1703void
1704OP_5200 ()
1705{
87178dbd 1706 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1707 if (OP[1] == 0)
1708 {
1709 /* PSW is treated specially */
1710 PSW = 0;
1711 if (State.SM) PSW |= 0x8000;
1712 if (State.EA) PSW |= 0x2000;
1713 if (State.DB) PSW |= 0x1000;
7f48c9fe 1714 if (State.DM) PSW |= 0x800;
2934d1c9
MH		 1715 if (State.IE) PSW |= 0x400;
1716 if (State.RP) PSW |= 0x200;
1717 if (State.MD) PSW |= 0x100;
1718 if (State.FX) PSW |= 0x80;
1719 if (State.ST) PSW |= 0x40;
1720 if (State.F0) PSW |= 8;
1721 if (State.F1) PSW |= 4;
1722 if (State.C) PSW |= 1;
1723 }
1724 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1725 trace_output (OP_REG);
2934d1c9
MH		 1726}
1727
1728/* mvtacg */
1729void
1730OP_1E41 ()
1731{
87178dbd 1732 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1733 State.a[OP[1]] &= MASK32;
1734 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1735 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1736}
1737
1738/* mvtachi */
1739void
1740OP_1E01 ()
1741{
1742 uint16 tmp;
87178dbd
MM		 1743
1744 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1745 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1746 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1747 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1748}
1749
1750/* mvtaclo */
1751void
1752OP_1E21 ()
1753{
87178dbd 1754 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1755 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1756 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1757}
1758
1759/* mvtc */
1760void
1761OP_5600 ()
1762{
87178dbd 1763 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1764 State.cregs[OP[1]] = State.regs[OP[0]];
1765 if (OP[1] == 0)
1766 {
1767 /* PSW is treated specially */
1768 State.SM = (PSW & 0x8000) ? 1 : 0;
1769 State.EA = (PSW & 0x2000) ? 1 : 0;
1770 State.DB = (PSW & 0x1000) ? 1 : 0;
7f48c9fe 1771 State.DM = (PSW & 0x800) ? 1 : 0;
2934d1c9
MH		 1772 State.IE = (PSW & 0x400) ? 1 : 0;
1773 State.RP = (PSW & 0x200) ? 1 : 0;
1774 State.MD = (PSW & 0x100) ? 1 : 0;
1775 State.FX = (PSW & 0x80) ? 1 : 0;
1776 State.ST = (PSW & 0x40) ? 1 : 0;
1777 State.F0 = (PSW & 8) ? 1 : 0;
1778 State.F1 = (PSW & 4) ? 1 : 0;
1779 State.C = PSW & 1;
1780 if (State.ST && !State.FX)
1781 {
7eebfc62
MM		 1782 (*d10v_callback->printf_filtered) (d10v_callback,
1783 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1784 PC<<2);
4f425a32 1785 State.exception = SIGILL;
2934d1c9
MH		 1786 }
1787 }
87178dbd 1788 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1789}
1790
1791/* mvub */
1792void
1793OP_5401 ()
1794{
87178dbd 1795 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1796 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1797 trace_output (OP_REG);
2934d1c9
MH		 1798}
1799
1800/* neg */
1801void
1802OP_4605 ()
1803{
87178dbd 1804 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1805 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1806 trace_output (OP_REG);
2934d1c9
MH		 1807}
1808
1809/* neg */
1810void
1811OP_5605 ()
1812{
1813 int64 tmp;
87178dbd
MM		 1814
1815 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1816 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1817 if (State.ST)
1818 {
4c38885c 1819 if ( tmp > MAX32)
2934d1c9 1820 State.a[OP[0]] = MAX32;
4c38885c 1821 else if (tmp < MIN32)
2934d1c9
MH		 1822 State.a[OP[0]] = MIN32;
1823 else
4f425a32 1824 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1825 }
1826 else
4f425a32 1827 State.a[OP[0]] = tmp & MASK40;
87178dbd 1828 trace_output (OP_ACCUM);
2934d1c9
MH		 1829}
1830
1831
1832/* nop */
1833void
1834OP_5E00 ()
1835{
87178dbd 1836 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
7eebfc62 1837
c422ecc7
MH		 1838 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1839 switch (State.ins_type)
1840 {
1841 default:
1842 ins_type_counters[ (int)INS_UNKNOWN ]++;
1843 break;
1844
1845 case INS_LEFT_PARALLEL:
1846 /* Don't count a parallel op that includes a NOP as a true parallel op */
1847 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1848 ins_type_counters[ (int)INS_RIGHT ]++;
1849 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1850 break;
1851
1852 case INS_LEFT:
1853 case INS_LEFT_COND_EXE:
1854 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1855 break;
1856
1857 case INS_RIGHT_PARALLEL:
1858 /* Don't count a parallel op that includes a NOP as a true parallel op */
1859 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1860 ins_type_counters[ (int)INS_LEFT ]++;
1861 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1862 break;
1863
1864 case INS_RIGHT:
1865 case INS_RIGHT_COND_EXE:
1866 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1867 break;
1868 }
1869
1870 trace_output (OP_VOID);
2934d1c9
MH		 1871}
1872
1873/* not */
1874void
1875OP_4603 ()
1876{
87178dbd 1877 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1878 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1879 trace_output (OP_REG);
2934d1c9
MH		 1880}
1881
1882/* or */
1883void
1884OP_800 ()
1885{
87178dbd 1886 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1887 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1888 trace_output (OP_REG);
2934d1c9
MH		 1889}
1890
1891/* or3 */
1892void
1893OP_4000000 ()
1894{
87178dbd 1895 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1896 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1897 trace_output (OP_REG);
2934d1c9
MH		 1898}
1899
1900/* rac */
1901void
1902OP_5201 ()
1903{
1904 int64 tmp;
1905 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1906
1907 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1908 if (OP[1] != 0)
1909 {
7eebfc62
MM		 1910 (*d10v_callback->printf_filtered) (d10v_callback,
1911 "ERROR at PC 0x%x: instruction only valid for A0\n",
1912 PC<<2);
166acb9f
MH		 1913 State.exception = SIGILL;
1914 }
1915
2934d1c9 1916 State.F1 = State.F0;
aa49c64f 1917 tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff));
2934d1c9 1918 if (shift >=0)
aa49c64f 1919 tmp <<= shift;
2934d1c9 1920 else
aa49c64f
AC		 1921 tmp >>= -shift;
1922 tmp += 0x8000;
1923 tmp >>= 16; /* look at bits 0:43 */
1924 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2934d1c9
MH		 1925 {
1926 State.regs[OP[0]] = 0x7fff;
1927 State.regs[OP[0]+1] = 0xffff;
1928 State.F0 = 1;
1929 }
aa49c64f 1930 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2934d1c9
MH		 1931 {
1932 State.regs[OP[0]] = 0x8000;
1933 State.regs[OP[0]+1] = 0;
1934 State.F0 = 1;
1935 }
1936 else
1937 {
1938 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1939 State.regs[OP[0]+1] = tmp & 0xffff;
1940 State.F0 = 0;
1941 }
87178dbd 1942 trace_output (OP_DREG);
2934d1c9
MH		 1943}
1944
1945/* rachi */
1946void
1947OP_4201 ()
1948{
70ee56c5 1949 signed64 tmp;
4c38885c 1950 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1951
1952 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1953 State.F1 = State.F0;
1954 if (shift >=0)
70ee56c5 1955 tmp = SEXT40 (State.a[OP[1]]) << shift;
4c38885c 1956 else
70ee56c5 1957 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
4c38885c 1958 tmp += 0x8000;
63a91cfb 1959
70ee56c5 1960 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
4c38885c
MH		 1961 {
1962 State.regs[OP[0]] = 0x7fff;
1963 State.F0 = 1;
1964 }
70ee56c5 1965 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
4c38885c
MH		 1966 {
1967 State.regs[OP[0]] = 0x8000;
1968 State.F0 = 1;
1969 }
1970 else
1971 {
1972 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1973 State.F0 = 0;
1974 }
87178dbd 1975 trace_output (OP_REG);
2934d1c9
MH		 1976}
1977
1978/* rep */
1979void
1980OP_27000000 ()
1981{
87178dbd 1982 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1983 RPT_S = PC + 1;
1984 RPT_E = PC + OP[1];
1985 RPT_C = State.regs[OP[0]];
1986 State.RP = 1;
1987 if (RPT_C == 0)
1988 {
7eebfc62 1989 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1990 State.exception = SIGILL;
2934d1c9 1991 }
4c38885c
MH		 1992 if (OP[1] < 4)
1993 {
7eebfc62 1994 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1995 State.exception = SIGILL;
4c38885c 1996 }
87178dbd 1997 trace_output (OP_VOID);
2934d1c9
MH		 1998}
1999
2000/* repi */
2001void
2002OP_2F000000 ()
2003{
87178dbd 2004 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 2005 RPT_S = PC + 1;
2006 RPT_E = PC + OP[1];
2007 RPT_C = OP[0];
2008 State.RP = 1;
2009 if (RPT_C == 0)
2010 {
7eebfc62 2011 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 2012 State.exception = SIGILL;
4c38885c
MH		 2013 }
2014 if (OP[1] < 4)
2015 {
7eebfc62 2016 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 2017 State.exception = SIGILL;
2934d1c9 2018 }
87178dbd 2019 trace_output (OP_VOID);
2934d1c9
MH		 2020}
2021
2022/* rtd */
2023void
2024OP_5F60 ()
2025{
7eebfc62 2026 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 2027 State.exception = SIGILL;
2934d1c9
MH		 2028}
2029
2030/* rte */
2031void
2032OP_5F40 ()
2033{
87178dbd 2034 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 2035 PC = BPC;
2036 PSW = BPSW;
87178dbd 2037 trace_output (OP_VOID);
2934d1c9
MH		 2038}
2039
2040/* sadd */
2041void
2042OP_1223 ()
2043{
4c38885c 2044 int64 tmp;
87178dbd
MM		 2045
2046 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 2047 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 2048 if (State.ST)
2049 {
2050 if (tmp > MAX32)
2051 State.a[OP[0]] = MAX32;
2052 else if (tmp < MIN32)
2053 State.a[OP[0]] = MIN32;
2054 else
4f425a32 2055 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 2056 }
2057 else
4f425a32 2058 State.a[OP[0]] = tmp & MASK40;
87178dbd 2059 trace_output (OP_ACCUM);
2934d1c9
MH		 2060}
2061
2062/* setf0f */
2063void
2064OP_4611 ()
2065{
87178dbd 2066 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2067 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2068 trace_output (OP_REG);
2934d1c9
MH		 2069}
2070
2071/* setf0t */
2072void
2073OP_4613 ()
2074{
87178dbd 2075 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2076 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2077 trace_output (OP_REG);
2934d1c9
MH		 2078}
2079
2080/* sleep */
2081void
2082OP_5FC0 ()
2083{
87178dbd 2084 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2085 State.IE = 1;
87178dbd 2086 trace_output (OP_VOID);
2934d1c9
MH		 2087}
2088
2089/* sll */
2090void
2091OP_2200 ()
2092{
87178dbd 2093 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2094 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2095 trace_output (OP_REG);
2934d1c9
MH		 2096}
2097
2098/* sll */
2099void
2100OP_3200 ()
2101{
4c38885c 2102 int64 tmp;
87178dbd 2103 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2104 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2105 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2106 else
2107 {
2108 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2109 State.exception = SIGILL;
2110 return;
2111 }
4c38885c
MH		 2112
2113 if (State.ST)
2114 {
2115 if (tmp > MAX32)
2116 State.a[OP[0]] = MAX32;
2117 else if (tmp < 0xffffff80000000LL)
2118 State.a[OP[0]] = MIN32;
2119 else
2120 State.a[OP[0]] = tmp & MASK40;
2121 }
2122 else
2123 State.a[OP[0]] = tmp & MASK40;
87178dbd 2124 trace_output (OP_ACCUM);
2934d1c9
MH		 2125}
2126
2127/* slli */
2128void
2129OP_2201 ()
2130{
87178dbd 2131 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2132 State.regs[OP[0]] <<= OP[1];
87178dbd 2133 trace_output (OP_REG);
2934d1c9
MH		 2134}
2135
2136/* slli */
2137void
2138OP_3201 ()
2139{
4c38885c 2140 int64 tmp;
4f425a32
MH		 2141
2142 if (OP[1] == 0)
2143 OP[1] = 16;
4f425a32 2144
87178dbd 2145 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2146 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2147
2148 if (State.ST)
2149 {
2150 if (tmp > MAX32)
2151 State.a[OP[0]] = MAX32;
2152 else if (tmp < 0xffffff80000000LL)
2153 State.a[OP[0]] = MIN32;
2154 else
2155 State.a[OP[0]] = tmp & MASK40;
2156 }
2157 else
2158 State.a[OP[0]] = tmp & MASK40;
87178dbd 2159 trace_output (OP_ACCUM);
2934d1c9
MH		 2160}
2161
2162/* slx */
2163void
2164OP_460B ()
2165{
87178dbd 2166 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2167 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2168 trace_output (OP_REG);
2934d1c9
MH		 2169}
2170
2171/* sra */
2172void
2173OP_2400 ()
2174{
87178dbd 2175 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2176 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2177 trace_output (OP_REG);
2934d1c9
MH		 2178}
2179
2180/* sra */
2181void
2182OP_3400 ()
2183{
87178dbd 2184 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2185 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2186 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
069398aa
MM		 2187 else
2188 {
2189 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2190 State.exception = SIGILL;
2191 return;
2192 }
2193
87178dbd 2194 trace_output (OP_ACCUM);
2934d1c9
MH		 2195}
2196
2197/* srai */
2198void
2199OP_2401 ()
2200{
87178dbd 2201 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2202 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2203 trace_output (OP_REG);
2934d1c9
MH		 2204}
2205
2206/* srai */
2207void
2208OP_3401 ()
2209{
4f425a32
MH		 2210 if (OP[1] == 0)
2211 OP[1] = 16;
87178dbd
MM		 2212
2213 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2214 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
87178dbd 2215 trace_output (OP_ACCUM);
2934d1c9
MH		 2216}
2217
2218/* srl */
2219void
2220OP_2000 ()
2221{
87178dbd 2222 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2223 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2224 trace_output (OP_REG);
2934d1c9
MH		 2225}
2226
2227/* srl */
2228void
2229OP_3000 ()
2230{
87178dbd 2231 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2232 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2233 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
069398aa
MM		 2234 else
2235 {
2236 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2237 State.exception = SIGILL;
2238 return;
2239 }
2240
87178dbd 2241 trace_output (OP_ACCUM);
2934d1c9
MH		 2242}
2243
2244/* srli */
2245void
2246OP_2001 ()
2247{
87178dbd 2248 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2249 State.regs[OP[0]] >>= OP[1];
87178dbd 2250 trace_output (OP_REG);
2934d1c9
MH		 2251}
2252
2253/* srli */
2254void
2255OP_3001 ()
2256{
4f425a32
MH		 2257 if (OP[1] == 0)
2258 OP[1] = 16;
87178dbd
MM		 2259
2260 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2261 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
87178dbd 2262 trace_output (OP_ACCUM);
2934d1c9
MH		 2263}
2264
2265/* srx */
2266void
2267OP_4609 ()
2268{
2269 uint16 tmp;
87178dbd
MM		 2270
2271 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2272 tmp = State.F0 << 15;
2273 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2274 trace_output (OP_REG);
2934d1c9
MH		 2275}
2276
2277/* st */
2278void
2279OP_34000000 ()
2280{
87178dbd 2281 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2282 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2283 trace_output (OP_VOID);
2934d1c9
MH		 2284}
2285
2286/* st */
2287void
2288OP_6800 ()
2289{
87178dbd 2290 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2291 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2292 trace_output (OP_VOID);
2934d1c9
MH		 2293}
2294
2295/* st */
2296void
2297OP_6C1F ()
2298{
87178dbd 2299 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2300 if ( OP[1] != 15 )
2301 {
7eebfc62 2302 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2303 State.exception = SIGILL;
2304 return;
4c38885c
MH		 2305 }
2306 State.regs[OP[1]] -= 2;
2307 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2308 trace_output (OP_VOID);
2934d1c9
MH		 2309}
2310
2311/* st */
2312void
2313OP_6801 ()
2314{
87178dbd 2315 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2316 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2317 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2318 trace_output (OP_VOID);
2934d1c9
MH		 2319}
2320
2321/* st */
2322void
2323OP_6C01 ()
2324{
87178dbd 2325 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
fd435e9f
MM		 2326 if ( OP[1] == 15 )
2327 {
2328 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2329 State.exception = SIGILL;
2330 return;
2331 }
4c38885c 2332 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2333 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2334 trace_output (OP_VOID);
2934d1c9
MH		 2335}
2336
2337/* st2w */
2338void
2339OP_35000000 ()
2340{
87178dbd 2341 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2342 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2343 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2344 trace_output (OP_VOID);
2934d1c9
MH		 2345}
2346
2347/* st2w */
2348void
2349OP_6A00 ()
2350{
a18cb100 2351 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2352 SW (State.regs[OP[1]], State.regs[OP[0]]);
2353 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2354 trace_output (OP_VOID);
2934d1c9
MH		 2355}
2356
2357/* st2w */
2358void
2359OP_6E1F ()
2360{
a18cb100 2361 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2362 if ( OP[1] != 15 )
2363 {
7eebfc62 2364 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2365 State.exception = SIGILL;
2366 return;
4c38885c
MH		 2367 }
2368 State.regs[OP[1]] -= 4;
2369 SW (State.regs[OP[1]], State.regs[OP[0]]);
2370 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2371 trace_output (OP_VOID);
2934d1c9
MH		 2372}
2373
2374/* st2w */
2375void
2376OP_6A01 ()
2377{
1155e06e 2378 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2379 SW (State.regs[OP[1]], State.regs[OP[0]]);
2380 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2381 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2382 trace_output (OP_VOID);
2934d1c9
MH		 2383}
2384
2385/* st2w */
2386void
2387OP_6E01 ()
2388{
1155e06e
FF		 2389 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2390 if ( OP[1] == 15 )
2391 {
2392 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2393 State.exception = SIGILL;
2394 return;
2395 }
4c38885c
MH		 2396 SW (State.regs[OP[1]], State.regs[OP[0]]);
2397 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2398 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2399 trace_output (OP_VOID);
2934d1c9
MH		 2400}
2401
2402/* stb */
2403void
2404OP_3C000000 ()
2405{
87178dbd 2406 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2407 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2408 trace_output (OP_VOID);
2934d1c9
MH		 2409}
2410
2411/* stb */
2412void
2413OP_7800 ()
2414{
87178dbd 2415 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2416 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2417 trace_output (OP_VOID);
2934d1c9
MH		 2418}
2419
2420/* stop */
2421void
2422OP_5FE0 ()
2423{
87178dbd 2424 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2425 State.exception = SIG_D10V_STOP;
87178dbd 2426 trace_output (OP_VOID);
2934d1c9
MH		 2427}
2428
2429/* sub */
2430void
2431OP_0 ()
4c38885c 2432{
f4b022d3 2433 uint16 tmp;
87178dbd
MM		 2434
2435 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
aa49c64f
AC		 2436 /* see ../common/sim-alu.h for a more extensive discussion on how to
2437 compute the carry/overflow bits. */
f4b022d3 2438 tmp = State.regs[OP[0]] - State.regs[OP[1]];
aa49c64f 2439 State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]);
f4b022d3 2440 State.regs[OP[0]] = tmp;
87178dbd 2441 trace_output (OP_REG);
4c38885c
MH		 2442}
2443
2444/* sub */
2445void
2446OP_1001 ()
2447{
4f425a32 2448 int64 tmp;
87178dbd
MM		 2449
2450 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2451 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2452 if (State.ST)
2453 {
2454 if ( tmp > MAX32)
2455 State.a[OP[0]] = MAX32;
2456 else if ( tmp < MIN32)
2457 State.a[OP[0]] = MIN32;
2458 else
2459 State.a[OP[0]] = tmp & MASK40;
2460 }
2461 else
2462 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2463
2464 trace_output (OP_ACCUM);
4c38885c
MH		 2465}
2466
2467/* sub */
2468
2469void
2470OP_1003 ()
2934d1c9 2471{
4f425a32 2472 int64 tmp;
87178dbd
MM		 2473
2474 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2475 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2476 if (State.ST)
2477 {
2478 if (tmp > MAX32)
2479 State.a[OP[0]] = MAX32;
2480 else if ( tmp < MIN32)
2481 State.a[OP[0]] = MIN32;
2482 else
2483 State.a[OP[0]] = tmp & MASK40;
2484 }
2485 else
2486 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2487
2488 trace_output (OP_ACCUM);
2934d1c9
MH		 2489}
2490
2491/* sub2w */
2492void
2493OP_1000 ()
2494{
f4b022d3 2495 uint32 tmp,a,b;
4c38885c 2496
87178dbd 2497 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 2498 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2499 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
70ee56c5
AC		 2500 /* see ../common/sim-alu.h for a more extensive discussion on how to
2501 compute the carry/overflow bits */
2502 tmp = a - b;
51b057f2 2503 State.C = (a >= b);
4c38885c
MH		 2504 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2505 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2506 trace_output (OP_DREG);
2934d1c9
MH		 2507}
2508
2509/* subac3 */
2510void
2511OP_17000000 ()
2512{
4f425a32 2513 int64 tmp;
87178dbd
MM		 2514
2515 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2516 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2517 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2518 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2519 trace_output (OP_DREG);
2934d1c9
MH		 2520}
2521
2522/* subac3 */
2523void
2524OP_17000002 ()
2525{
4f425a32 2526 int64 tmp;
87178dbd
MM		 2527
2528 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2529 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2530 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2531 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2532 trace_output (OP_DREG);
2934d1c9
MH		 2533}
2534
2535/* subac3s */
2536void
2537OP_17001000 ()
2538{
4f425a32 2539 int64 tmp;
87178dbd
MM		 2540
2541 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2542 State.F1 = State.F0;
2543 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2544 if ( tmp > MAX32)
2545 {
2546 State.regs[OP[0]] = 0x7fff;
2547 State.regs[OP[0]+1] = 0xffff;
2548 State.F0 = 1;
2549 }
2550 else if (tmp < MIN32)
2551 {
2552 State.regs[OP[0]] = 0x8000;
2553 State.regs[OP[0]+1] = 0;
2554 State.F0 = 1;
2555 }
2556 else
2557 {
2558 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2559 State.regs[OP[0]+1] = tmp & 0xffff;
2560 State.F0 = 0;
2561 }
87178dbd 2562 trace_output (OP_DREG);
2934d1c9
MH		 2563}
2564
2565/* subac3s */
2566void
2567OP_17001002 ()
2568{
4f425a32 2569 int64 tmp;
87178dbd
MM		 2570
2571 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2572 State.F1 = State.F0;
2573 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2574 if ( tmp > MAX32)
2575 {
2576 State.regs[OP[0]] = 0x7fff;
2577 State.regs[OP[0]+1] = 0xffff;
2578 State.F0 = 1;
2579 }
2580 else if (tmp < MIN32)
2581 {
2582 State.regs[OP[0]] = 0x8000;
2583 State.regs[OP[0]+1] = 0;
2584 State.F0 = 1;
2585 }
2586 else
2587 {
2588 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2589 State.regs[OP[0]+1] = tmp & 0xffff;
2590 State.F0 = 0;
2591 }
87178dbd 2592 trace_output (OP_DREG);
2934d1c9
MH		 2593}
2594
2595/* subi */
2596void
2597OP_1 ()
2598{
70ee56c5 2599 unsigned tmp;
4f425a32
MH		 2600 if (OP[1] == 0)
2601 OP[1] = 16;
87178dbd
MM		 2602
2603 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
70ee56c5 2604 /* see ../common/sim-alu.h for a more extensive discussion on how to
51b057f2
AC		 2605 compute the carry/overflow bits. */
2606 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
70ee56c5
AC		 2607 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2608 + (unsigned)(unsigned16) ( - OP[1]));
2609 State.C = (tmp >= (1 << 16));
2610 State.regs[OP[0]] = tmp;
87178dbd 2611 trace_output (OP_REG);
2934d1c9
MH		 2612}
2613
2614/* trap */
2615void
2616OP_5F00 ()
2617{
a5719092 2618 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2619 trace_output (OP_VOID);
8918b3a7 2620
63a91cfb 2621 switch (OP[0])
2934d1c9 2622 {
63a91cfb 2623 default:
19d44375 2624#if 0
7eebfc62 2625 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb 2626 State.exception = SIGILL;
19d44375
MM		 2627#else
2628 /* Use any other traps for batch debugging. */
2629 {
2630 int i;
2631 static int first_time = 1;
2632
2633 if (first_time)
2634 {
2635 first_time = 0;
2636 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2637 for (i = 0; i < 16; i++)
2638 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2639 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2640 }
2641
87e43259 2642 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
19d44375 2643
87e43259
AC		 2644 for (i = 0; i < 16; i++)
2645 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
19d44375 2646
87e43259
AC		 2647 for (i = 0; i < 2; i++)
2648 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2649 ((int)(State.a[i] >> 32) & 0xff),
2650 ((unsigned long)State.a[i]) & 0xffffffff);
19d44375 2651
87e43259
AC		 2652 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2653 State.F0 != 0, State.F1 != 0, State.C != 0);
2654 (*d10v_callback->flush_stdout) (d10v_callback);
2655 break;
2656 }
19d44375 2657#endif
63a91cfb 2658
87e43259
AC		 2659 case 0: /* old system call trap, to be deleted */
2660 case 15: /* new system call trap */
2661 /* Trap 15 is used for simulating low-level I/O */
63a91cfb 2662 {
63a91cfb
MM		 2663 errno = 0;
2664
2665/* Registers passed to trap 0 */
2666
65c0d7de
MA		 2667#define FUNC State.regs[6] /* function number */
2668#define PARM1 State.regs[2] /* optional parm 1 */
2669#define PARM2 State.regs[3] /* optional parm 2 */
2670#define PARM3 State.regs[4] /* optional parm 3 */
2671#define PARM4 State.regs[5] /* optional parm 3 */
63a91cfb
MM		 2672
2673/* Registers set by trap 0 */
2674
65c0d7de
MA		 2675#define RETVAL State.regs[2] /* return value */
2676#define RETVAL_HIGH State.regs[2] /* return value */
2677#define RETVAL_LOW State.regs[3] /* return value */
2678#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2679
2680/* Turn a pointer in a register into a pointer into real memory. */
2681
c422ecc7 2682#define MEMPTR(x) ((char *)(dmem_addr(x)))
63a91cfb
MM		 2683
2684 switch (FUNC)
2685 {
2686#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2687 case SYS_fork:
2688 RETVAL = fork ();
8918b3a7
MM		 2689 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2690 trace_output (OP_R2);
63a91cfb 2691 break;
8918b3a7 2692
57bc1a72
MM		 2693 case SYS_getpid:
2694 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2695 RETVAL = getpid ();
2696 trace_output (OP_R2);
2697 break;
2698
2699 case SYS_kill:
2700 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2701 if (PARM1 == getpid ())
2702 {
2703 trace_output (OP_VOID);
2704 State.exception = PARM2;
2705 }
2706 else
2707 {
2708 int os_sig = -1;
2709 switch (PARM2)
2710 {
2711#ifdef SIGHUP
2712 case 1: os_sig = SIGHUP; break;
2713#endif
2714#ifdef SIGINT
2715 case 2: os_sig = SIGINT; break;
2716#endif
2717#ifdef SIGQUIT
2718 case 3: os_sig = SIGQUIT; break;
2719#endif
2720#ifdef SIGILL
2721 case 4: os_sig = SIGILL; break;
2722#endif
2723#ifdef SIGTRAP
2724 case 5: os_sig = SIGTRAP; break;
2725#endif
2726#ifdef SIGABRT
2727 case 6: os_sig = SIGABRT; break;
2728#elif defined(SIGIOT)
2729 case 6: os_sig = SIGIOT; break;
2730#endif
2731#ifdef SIGEMT
2732 case 7: os_sig = SIGEMT; break;
2733#endif
2734#ifdef SIGFPE
2735 case 8: os_sig = SIGFPE; break;
2736#endif
2737#ifdef SIGKILL
2738 case 9: os_sig = SIGKILL; break;
2739#endif
2740#ifdef SIGBUS
2741 case 10: os_sig = SIGBUS; break;
2742#endif
2743#ifdef SIGSEGV
2744 case 11: os_sig = SIGSEGV; break;
2745#endif
2746#ifdef SIGSYS
2747 case 12: os_sig = SIGSYS; break;
2748#endif
2749#ifdef SIGPIPE
2750 case 13: os_sig = SIGPIPE; break;
2751#endif
2752#ifdef SIGALRM
2753 case 14: os_sig = SIGALRM; break;
2754#endif
2755#ifdef SIGTERM
2756 case 15: os_sig = SIGTERM; break;
2757#endif
2758#ifdef SIGURG
2759 case 16: os_sig = SIGURG; break;
2760#endif
2761#ifdef SIGSTOP
2762 case 17: os_sig = SIGSTOP; break;
2763#endif
2764#ifdef SIGTSTP
2765 case 18: os_sig = SIGTSTP; break;
2766#endif
2767#ifdef SIGCONT
2768 case 19: os_sig = SIGCONT; break;
2769#endif
2770#ifdef SIGCHLD
2771 case 20: os_sig = SIGCHLD; break;
2772#elif defined(SIGCLD)
2773 case 20: os_sig = SIGCLD; break;
2774#endif
2775#ifdef SIGTTIN
2776 case 21: os_sig = SIGTTIN; break;
2777#endif
2778#ifdef SIGTTOU
2779 case 22: os_sig = SIGTTOU; break;
2780#endif
2781#ifdef SIGIO
2782 case 23: os_sig = SIGIO; break;
2783#elif defined (SIGPOLL)
2784 case 23: os_sig = SIGPOLL; break;
2785#endif
2786#ifdef SIGXCPU
2787 case 24: os_sig = SIGXCPU; break;
2788#endif
2789#ifdef SIGXFSZ
2790 case 25: os_sig = SIGXFSZ; break;
2791#endif
2792#ifdef SIGVTALRM
2793 case 26: os_sig = SIGVTALRM; break;
2794#endif
2795#ifdef SIGPROF
2796 case 27: os_sig = SIGPROF; break;
2797#endif
2798#ifdef SIGWINCH
2799 case 28: os_sig = SIGWINCH; break;
2800#endif
2801#ifdef SIGLOST
2802 case 29: os_sig = SIGLOST; break;
2803#endif
2804#ifdef SIGUSR1
2805 case 30: os_sig = SIGUSR1; break;
2806#endif
2807#ifdef SIGUSR2
2808 case 31: os_sig = SIGUSR2; break;
2809#endif
2810 }
2811
2812 if (os_sig == -1)
2813 {
2814 trace_output (OP_VOID);
2815 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
fd435e9f 2816 (*d10v_callback->flush_stdout) (d10v_callback);
57bc1a72
MM		 2817 State.exception = SIGILL;
2818 }
2819 else
2820 {
2821 RETVAL = kill (PARM1, PARM2);
2822 trace_output (OP_R2);
2823 }
2824 }
2825 break;
2826
63a91cfb
MM		 2827 case SYS_execve:
2828 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2829 (char **)MEMPTR (PARM3));
8918b3a7
MM		 2830 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2831 trace_output (OP_R2);
63a91cfb 2832 break;
8918b3a7 2833
87e43259 2834#ifdef SYS_execv
63a91cfb
MM		 2835 case SYS_execv:
2836 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
8918b3a7
MM		 2837 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2838 trace_output (OP_R2);
63a91cfb 2839 break;
87e43259 2840#endif
8918b3a7 2841
63a91cfb
MM		 2842 case SYS_pipe:
2843 {
2844 reg_t buf;
2845 int host_fd[2];
2846
2847 buf = PARM1;
2848 RETVAL = pipe (host_fd);
2849 SW (buf, host_fd[0]);
2850 buf += sizeof(uint16);
2851 SW (buf, host_fd[1]);
8918b3a7
MM		 2852 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2853 trace_output (OP_R2);
63a91cfb
MM		 2854 }
2855 break;
8918b3a7 2856
87e43259 2857#ifdef SYS_wait
63a91cfb
MM		 2858 case SYS_wait:
2859 {
2860 int status;
2861
2862 RETVAL = wait (&status);
8918b3a7
MM		 2863 if (PARM1)
2864 SW (PARM1, status);
2865 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2866 trace_output (OP_R2);
63a91cfb
MM		 2867 }
2868 break;
87e43259 2869#endif
57bc1a72
MM		 2870#else
2871 case SYS_getpid:
2872 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2873 RETVAL = 1;
2874 trace_output (OP_R2);
2875 break;
2876
2877 case SYS_kill:
2878 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2879 trace_output (OP_VOID);
2880 State.exception = PARM2;
2881 break;
63a91cfb 2882#endif
8918b3a7 2883
63a91cfb
MM		 2884 case SYS_read:
2885 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2886 PARM3);
8918b3a7
MM		 2887 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2888 trace_output (OP_R2);
63a91cfb 2889 break;
8918b3a7 2890
63a91cfb
MM		 2891 case SYS_write:
2892 if (PARM1 == 1)
2893 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2894 MEMPTR (PARM2), PARM3);
2895 else
2896 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2897 MEMPTR (PARM2), PARM3);
8918b3a7
MM		 2898 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2899 trace_output (OP_R2);
63a91cfb 2900 break;
8918b3a7 2901
63a91cfb 2902 case SYS_lseek:
65c0d7de
MA		 2903 {
2904 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2905 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2906 PARM4);
2907 RETVAL_HIGH = ret >> 16;
2908 RETVAL_LOW = ret & 0xffff;
2909 }
8918b3a7
MM		 2910 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2911 trace_output (OP_R2R3);
63a91cfb 2912 break;
8918b3a7 2913
63a91cfb
MM		 2914 case SYS_close:
2915 RETVAL = d10v_callback->close (d10v_callback, PARM1);
8918b3a7
MM		 2916 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2917 trace_output (OP_R2);
63a91cfb 2918 break;
8918b3a7 2919
63a91cfb
MM		 2920 case SYS_open:
2921 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2922 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2923 trace_output (OP_R2);
2924 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2925 trace_output (OP_R2);
63a91cfb 2926 break;
8918b3a7 2927
63a91cfb 2928 case SYS_exit:
a49a15ad 2929 State.exception = SIG_D10V_EXIT;
8918b3a7
MM		 2930 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2931 trace_output (OP_VOID);
63a91cfb 2932 break;
63a91cfb 2933
8719be26 2934 case SYS_stat:
63a91cfb
MM		 2935 /* stat system call */
2936 {
2937 struct stat host_stat;
2938 reg_t buf;
2939
2940 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2941
2942 buf = PARM2;
2943
2944 /* The hard-coded offsets and sizes were determined by using
2945 * the D10V compiler on a test program that used struct stat.
2946 */
2947 SW (buf, host_stat.st_dev);
2948 SW (buf+2, host_stat.st_ino);
2949 SW (buf+4, host_stat.st_mode);
2950 SW (buf+6, host_stat.st_nlink);
2951 SW (buf+8, host_stat.st_uid);
2952 SW (buf+10, host_stat.st_gid);
2953 SW (buf+12, host_stat.st_rdev);
2954 SLW (buf+16, host_stat.st_size);
2955 SLW (buf+20, host_stat.st_atime);
2956 SLW (buf+28, host_stat.st_mtime);
2957 SLW (buf+36, host_stat.st_ctime);
2958 }
8918b3a7
MM		 2959 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2960 trace_output (OP_R2);
63a91cfb 2961 break;
63a91cfb 2962
63a91cfb
MM		 2963 case SYS_chown:
2964 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
8918b3a7
MM		 2965 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2966 trace_output (OP_R2);
63a91cfb 2967 break;
8918b3a7 2968
63a91cfb
MM		 2969 case SYS_chmod:
2970 RETVAL = chmod (MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2971 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2972 trace_output (OP_R2);
63a91cfb 2973 break;
8918b3a7 2974
87e43259 2975#ifdef SYS_utime
63a91cfb
MM		 2976 case SYS_utime:
2977 /* Cast the second argument to void *, to avoid type mismatch
2978 if a prototype is present. */
2979 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
8918b3a7
MM		 2980 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2981 trace_output (OP_R2);
2982 break;
87e43259 2983#endif
8918b3a7 2984
87e43259 2985#ifdef SYS_time
8918b3a7
MM		 2986 case SYS_time:
2987 {
2988 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2989 RETVAL_HIGH = ret >> 16;
2990 RETVAL_LOW = ret & 0xffff;
2991 }
2992 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2993 trace_output (OP_R2R3);
63a91cfb 2994 break;
87e43259 2995#endif
8918b3a7 2996
63a91cfb
MM		 2997 default:
2998 abort ();
2999 }
87e43259 3000 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
63a91cfb
MM		 3001 break;
3002 }
2934d1c9
MH		 3003 }
3004}
3005
3006/* tst0i */
3007void
3008OP_7000000 ()
3009{
87178dbd 3010 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3011 State.F1 = State.F0;
4f425a32 3012 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 3013 trace_output (OP_FLAG);
2934d1c9
MH		 3014}
3015
3016/* tst1i */
3017void
3018OP_F000000 ()
3019{
87178dbd 3020 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3021 State.F1 = State.F0;
4f425a32 3022 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 3023 trace_output (OP_FLAG);
2934d1c9
MH		 3024}
3025
3026/* wait */
3027void
3028OP_5F80 ()
3029{
87178dbd 3030 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 3031 State.IE = 1;
87178dbd 3032 trace_output (OP_VOID);
2934d1c9
MH		 3033}
3034
3035/* xor */
3036void
3037OP_A00 ()
3038{
87178dbd 3039 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 3040 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 3041 trace_output (OP_REG);
2934d1c9
MH		 3042}
3043
3044/* xor3 */
3045void
3046OP_5000000 ()
3047{
87178dbd 3048 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 3049 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 3050 trace_output (OP_REG);
2934d1c9
MH		 3051}
3052
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