]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/d10v/simops.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* config/tc-v850.h (tc_fix_adjustable): Don't adjust relocs
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
4f425a32 1#include <signal.h>
63a91cfb
MM		 2#include <errno.h>
3#include <sys/types.h>
4#include <sys/stat.h>
5#include <unistd.h>
6
2934d1c9
MH		 7#include "d10v_sim.h"
8#include "simops.h"
8719be26 9#include "sys/syscall.h"
a49a15ad 10#include "bfd.h"
2934d1c9 11
c422ecc7
MH		 12extern char *strrchr ();
13
87178dbd
MM		 14enum op_types {
15 OP_VOID,
16 OP_REG,
17 OP_REG_OUTPUT,
18 OP_DREG,
19 OP_DREG_OUTPUT,
20 OP_ACCUM,
21 OP_ACCUM_OUTPUT,
22 OP_ACCUM_REVERSE,
23 OP_CR,
24 OP_CR_OUTPUT,
25 OP_CR_REVERSE,
26 OP_FLAG,
60fc5b72 27 OP_FLAG_OUTPUT,
87178dbd 28 OP_CONSTANT16,
a18cb100 29 OP_CONSTANT8,
87178dbd
MM		 30 OP_CONSTANT3,
31 OP_CONSTANT4,
32 OP_MEMREF,
33 OP_MEMREF2,
34 OP_POSTDEC,
35 OP_POSTINC,
a18cb100
MM		 36 OP_PREDEC,
37 OP_R2,
8918b3a7
MM		 38 OP_R3,
39 OP_R4,
40 OP_R2R3
87178dbd
MM		 41};
42
7eebfc62 43#ifdef DEBUG
a49a15ad
MM		 44static void trace_input_func PARAMS ((char *name,
45 enum op_types in1,
46 enum op_types in2,
47 enum op_types in3));
87178dbd 48
a49a15ad
MM		 49#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
50
51static void trace_output_func PARAMS ((enum op_types result));
52
53#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
54
55static int init_text_p = 0;
56static asection *text;
57static bfd_vma text_start;
58static bfd_vma text_end;
0535fa1a 59extern bfd *exec_bfd;
87178dbd
MM		 60
61#ifndef SIZE_INSTRUCTION
a49a15ad 62#define SIZE_INSTRUCTION 8
87178dbd
MM		 63#endif
64
65#ifndef SIZE_OPERANDS
a49a15ad 66#define SIZE_OPERANDS 18
87178dbd
MM		 67#endif
68
69#ifndef SIZE_VALUES
70#define SIZE_VALUES 13
71#endif
72
a49a15ad
MM		 73#ifndef SIZE_LOCATION
74#define SIZE_LOCATION 20
75#endif
76
891513ee
MM		 77#ifndef SIZE_PC
78#define SIZE_PC 6
79#endif
80
81#ifndef SIZE_LINE_NUMBER
82#define SIZE_LINE_NUMBER 4
83#endif
84
87178dbd 85static void
a49a15ad 86trace_input_func (name, in1, in2, in3)
87178dbd
MM		 87 char *name;
88 enum op_types in1;
89 enum op_types in2;
90 enum op_types in3;
91{
92 char *comma;
93 enum op_types in[3];
94 int i;
a49a15ad 95 char buf[1024];
87178dbd
MM		 96 char *p;
97 long tmp;
98 char *type;
a49a15ad
MM		 99 asection *s;
100 const char *filename;
101 const char *functionname;
102 unsigned int linenumber;
103 bfd_vma byte_pc;
87178dbd 104
7eebfc62
MM		 105 if ((d10v_debug & DEBUG_TRACE) == 0)
106 return;
107
87178dbd
MM		 108 switch (State.ins_type)
109 {
110 default:
111 case INS_UNKNOWN: type = " ?"; break;
112 case INS_LEFT: type = " L"; break;
113 case INS_RIGHT: type = " R"; break;
114 case INS_LEFT_PARALLEL: type = "*L"; break;
115 case INS_RIGHT_PARALLEL: type = "*R"; break;
c422ecc7
MH		 116 case INS_LEFT_COND_TEST: type = "?L"; break;
117 case INS_RIGHT_COND_TEST: type = "?R"; break;
118 case INS_LEFT_COND_EXE: type = "&L"; break;
119 case INS_RIGHT_COND_EXE: type = "&R"; break;
87178dbd
MM		 120 case INS_LONG: type = " B"; break;
121 }
122
a49a15ad
MM		 123 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
124 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 125 "0x%.*x %s: %-*s ",
891513ee
MM		 126 SIZE_PC, (unsigned)PC,
127 type,
a49a15ad
MM		 128 SIZE_INSTRUCTION, name);
129
130 else
131 {
a49a15ad
MM		 132 if (!init_text_p)
133 {
134 init_text_p = 1;
0535fa1a
MM		 135 for (s = exec_bfd->sections; s; s = s->next)
136 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
a49a15ad
MM		 137 {
138 text = s;
0535fa1a
MM		 139 text_start = bfd_get_section_vma (exec_bfd, s);
140 text_end = text_start + bfd_section_size (exec_bfd, s);
a49a15ad
MM		 141 break;
142 }
143 }
144
891513ee 145 buf[0] = '\0';
a49a15ad
MM		 146 byte_pc = (bfd_vma)PC << 2;
147 if (text && byte_pc >= text_start && byte_pc < text_end)
148 {
149 filename = (const char *)0;
150 functionname = (const char *)0;
151 linenumber = 0;
0535fa1a 152 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 153 &filename, &functionname, &linenumber))
154 {
155 p = buf;
156 if (linenumber)
157 {
891513ee 158 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 159 p += strlen (p);
160 }
891513ee
MM		 161 else
162 {
163 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
164 p += SIZE_LINE_NUMBER+2;
165 }
a49a15ad
MM		 166
167 if (functionname)
168 {
169 sprintf (p, "%s ", functionname);
170 p += strlen (p);
171 }
172 else if (filename)
173 {
c422ecc7 174 char *q = strrchr (filename, '/');
a49a15ad
MM		 175 sprintf (p, "%s ", (q) ? q+1 : filename);
176 p += strlen (p);
177 }
178
179 if (*p == ' ')
180 *p = '\0';
181 }
182 }
183
184 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 185 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 186 SIZE_PC, (unsigned)PC,
187 type,
a49a15ad
MM		 188 SIZE_LOCATION, SIZE_LOCATION, buf,
189 SIZE_INSTRUCTION, name);
190 }
87178dbd
MM		 191
192 in[0] = in1;
193 in[1] = in2;
194 in[2] = in3;
195 comma = "";
196 p = buf;
197 for (i = 0; i < 3; i++)
198 {
199 switch (in[i])
200 {
201 case OP_VOID:
a18cb100
MM		 202 case OP_R2:
203 case OP_R3:
8918b3a7 204 case OP_R4:
c422ecc7 205 case OP_R2R3:
87178dbd
MM		 206 break;
207
208 case OP_REG:
209 case OP_REG_OUTPUT:
210 case OP_DREG:
211 case OP_DREG_OUTPUT:
212 sprintf (p, "%sr%d", comma, OP[i]);
213 p += strlen (p);
214 comma = ",";
215 break;
216
217 case OP_CR:
218 case OP_CR_OUTPUT:
219 case OP_CR_REVERSE:
220 sprintf (p, "%scr%d", comma, OP[i]);
221 p += strlen (p);
222 comma = ",";
223 break;
224
225 case OP_ACCUM:
226 case OP_ACCUM_OUTPUT:
227 case OP_ACCUM_REVERSE:
228 sprintf (p, "%sa%d", comma, OP[i]);
229 p += strlen (p);
230 comma = ",";
231 break;
232
233 case OP_CONSTANT16:
234 sprintf (p, "%s%d", comma, OP[i]);
235 p += strlen (p);
236 comma = ",";
237 break;
238
a18cb100
MM		 239 case OP_CONSTANT8:
240 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
241 p += strlen (p);
242 comma = ",";
243 break;
244
87178dbd
MM		 245 case OP_CONSTANT4:
246 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
247 p += strlen (p);
248 comma = ",";
249 break;
250
251 case OP_CONSTANT3:
252 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
253 p += strlen (p);
254 comma = ",";
255 break;
256
257 case OP_MEMREF:
258 sprintf (p, "%s@r%d", comma, OP[i]);
259 p += strlen (p);
260 comma = ",";
261 break;
262
263 case OP_MEMREF2:
264 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
265 p += strlen (p);
266 comma = ",";
267 break;
268
269 case OP_POSTINC:
270 sprintf (p, "%s@r%d+", comma, OP[i]);
271 p += strlen (p);
272 comma = ",";
273 break;
274
275 case OP_POSTDEC:
276 sprintf (p, "%s@r%d-", comma, OP[i]);
277 p += strlen (p);
278 comma = ",";
279 break;
280
281 case OP_PREDEC:
282 sprintf (p, "%s@-r%d", comma, OP[i]);
283 p += strlen (p);
284 comma = ",";
285 break;
286
287 case OP_FLAG:
60fc5b72 288 case OP_FLAG_OUTPUT:
87178dbd
MM		 289 if (OP[i] == 0)
290 sprintf (p, "%sf0", comma);
291
292 else if (OP[i] == 1)
293 sprintf (p, "%sf1", comma);
294
295 else
60fc5b72 296 sprintf (p, "%sc", comma);
87178dbd
MM		 297
298 p += strlen (p);
299 comma = ",";
300 break;
301 }
302 }
303
7eebfc62
MM		 304 if ((d10v_debug & DEBUG_VALUES) == 0)
305 {
306 *p++ = '\n';
307 *p = '\0';
308 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
309 }
310 else
311 {
312 *p = '\0';
313 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 314
7eebfc62
MM		 315 p = buf;
316 for (i = 0; i < 3; i++)
317 {
318 buf[0] = '\0';
319 switch (in[i])
320 {
321 case OP_VOID:
322 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
323 break;
324
325 case OP_REG_OUTPUT:
326 case OP_DREG_OUTPUT:
327 case OP_CR_OUTPUT:
328 case OP_ACCUM_OUTPUT:
60fc5b72 329 case OP_FLAG_OUTPUT:
7eebfc62
MM		 330 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
331 break;
332
333 case OP_REG:
334 case OP_MEMREF:
335 case OP_POSTDEC:
336 case OP_POSTINC:
337 case OP_PREDEC:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
339 (uint16)State.regs[OP[i]]);
340 break;
341
342 case OP_DREG:
343 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
345 break;
346
347 case OP_CR:
348 case OP_CR_REVERSE:
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)State.cregs[OP[i]]);
351 break;
352
353 case OP_ACCUM:
354 case OP_ACCUM_REVERSE:
355 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
356 ((int)(State.a[OP[i]] >> 32) & 0xff),
357 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
358 break;
359
360 case OP_CONSTANT16:
361 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
362 (uint16)OP[i]);
363 break;
364
365 case OP_CONSTANT4:
366 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
367 (uint16)SEXT4(OP[i]));
368 break;
369
a18cb100
MM		 370 case OP_CONSTANT8:
371 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
372 (uint16)SEXT8(OP[i]));
373 break;
374
7eebfc62
MM		 375 case OP_CONSTANT3:
376 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
377 (uint16)SEXT3(OP[i]));
378 break;
379
380 case OP_FLAG:
381 if (OP[i] == 0)
382 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
383 State.F0 != 0);
384
385 else if (OP[i] == 1)
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
387 State.F1 != 0);
388
389 else
390 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
391 State.C != 0);
392
393 break;
394
395 case OP_MEMREF2:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)OP[i]);
398 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
399 (uint16)State.regs[OP[++i]]);
400 break;
a18cb100
MM		 401
402 case OP_R2:
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[2]);
405 break;
406
407 case OP_R3:
408 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
409 (uint16)State.regs[3]);
410 break;
8918b3a7
MM		 411
412 case OP_R4:
413 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
414 (uint16)State.regs[4]);
415 break;
c422ecc7
MH		 416
417 case OP_R2R3:
418 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
419 (uint16)State.regs[2]);
420 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
421 (uint16)State.regs[3]);
422 i++;
423 break;
7eebfc62
MM		 424 }
425 }
426 }
427}
87178dbd 428
7eebfc62 429static void
a49a15ad 430trace_output_func (result)
7eebfc62
MM		 431 enum op_types result;
432{
433 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 434 {
7eebfc62 435 long tmp;
87178dbd 436
7eebfc62
MM		 437 switch (result)
438 {
439 default:
440 putchar ('\n');
87178dbd
MM		 441 break;
442
443 case OP_REG:
7eebfc62
MM		 444 case OP_REG_OUTPUT:
445 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
446 (uint16)State.regs[OP[0]],
447 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 448 break;
449
450 case OP_DREG:
7eebfc62
MM		 451 case OP_DREG_OUTPUT:
452 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
453 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
454 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 455 break;
456
457 case OP_CR:
7eebfc62
MM		 458 case OP_CR_OUTPUT:
459 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
460 (uint16)State.cregs[OP[0]],
461 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 462 break;
463
7eebfc62
MM		 464 case OP_CR_REVERSE:
465 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
466 (uint16)State.cregs[OP[1]],
467 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 468 break;
469
7eebfc62
MM		 470 case OP_ACCUM:
471 case OP_ACCUM_OUTPUT:
069398aa 472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 473 ((int)(State.a[OP[0]] >> 32) & 0xff),
474 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
475 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 476 break;
477
7eebfc62 478 case OP_ACCUM_REVERSE:
069398aa 479 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 480 ((int)(State.a[OP[1]] >> 32) & 0xff),
481 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
482 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 483 break;
484
485 case OP_FLAG:
60fc5b72 486 case OP_FLAG_OUTPUT:
7eebfc62
MM		 487 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
488 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd 489 break;
8918b3a7
MM		 490
491 case OP_R2:
492 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
493 (uint16)State.regs[2],
494 State.F0 != 0, State.F1 != 0, State.C != 0);
495 break;
496
497 case OP_R2R3:
498 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
499 (uint16)State.regs[2], (uint16)State.regs[3],
500 State.F0 != 0, State.F1 != 0, State.C != 0);
501 break;
87178dbd
MM		 502 }
503 }
87178dbd
MM		 504}
505
506#else
507#define trace_input(NAME, IN1, IN2, IN3)
508#define trace_output(RESULT)
509#endif
2934d1c9
MH		 510
511/* abs */
512void
513OP_4607 ()
514{
87178dbd 515 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 516 State.F1 = State.F0;
517 if ((int16)(State.regs[OP[0]]) < 0)
518 {
519 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
520 State.F0 = 1;
521 }
522 else
523 State.F0 = 0;
87178dbd 524 trace_output (OP_REG);
2934d1c9
MH		 525}
526
527/* abs */
528void
529OP_5607 ()
530{
531 int64 tmp;
532
87178dbd 533 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 534 State.F1 = State.F0;
535 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
536
4c38885c 537 if (State.a[OP[0]] < 0 )
2934d1c9 538 {
4c38885c 539 tmp = -State.a[OP[0]];
2934d1c9
MH		 540 if (State.ST)
541 {
4c38885c 542 if (tmp > MAX32)
2934d1c9 543 State.a[OP[0]] = MAX32;
4c38885c 544 else if (tmp < MIN32)
2934d1c9
MH		 545 State.a[OP[0]] = MIN32;
546 else
4f425a32 547 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 548 }
549 else
4f425a32 550 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 551 State.F0 = 1;
552 }
553 else
554 State.F0 = 0;
87178dbd 555 trace_output (OP_ACCUM);
2934d1c9
MH		 556}
557
558/* add */
559void
560OP_200 ()
561{
562 uint16 tmp = State.regs[OP[0]];
87178dbd 563 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 564 State.regs[OP[0]] += State.regs[OP[1]];
565 if ( tmp > State.regs[OP[0]])
566 State.C = 1;
567 else
568 State.C = 0;
87178dbd 569 trace_output (OP_REG);
2934d1c9
MH		 570}
571
572/* add */
573void
574OP_1201 ()
575{
4c38885c 576 int64 tmp;
4f425a32 577 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 578
579 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 580 if (State.ST)
581 {
582 if ( tmp > MAX32)
583 State.a[OP[0]] = MAX32;
584 else if ( tmp < MIN32)
585 State.a[OP[0]] = MIN32;
586 else
4f425a32 587 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 588 }
589 else
4f425a32 590 State.a[OP[0]] = tmp & MASK40;
87178dbd 591 trace_output (OP_ACCUM);
2934d1c9
MH		 592}
593
594/* add */
595void
596OP_1203 ()
597{
4c38885c 598 int64 tmp;
4f425a32 599 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 600
601 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 602 if (State.ST)
603 {
604 if (tmp > MAX32)
605 State.a[OP[0]] = MAX32;
606 else if ( tmp < MIN32)
607 State.a[OP[0]] = MIN32;
608 else
4f425a32 609 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 610 }
611 else
4f425a32 612 State.a[OP[0]] = tmp & MASK40;
87178dbd 613 trace_output (OP_ACCUM);
2934d1c9
MH		 614}
615
616/* add2w */
617void
618OP_1200 ()
619{
620 uint32 tmp;
621 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
622 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 623
624 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
2934d1c9
MH		 625 tmp = tmp1 + tmp2;
626 if ( (tmp < tmp1) || (tmp < tmp2) )
627 State.C = 1;
628 else
629 State.C = 0;
630 State.regs[OP[0]] = tmp >> 16;
631 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 632 trace_output (OP_DREG);
2934d1c9
MH		 633}
634
635/* add3 */
636void
637OP_1000000 ()
638{
639 uint16 tmp = State.regs[OP[0]];
2934d1c9 640 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
87178dbd
MM		 641
642 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9
MH		 643 if ( tmp > State.regs[OP[0]])
644 State.C = 1;
645 else
646 State.C = 0;
87178dbd 647 trace_output (OP_REG);
2934d1c9
MH		 648}
649
650/* addac3 */
651void
652OP_17000200 ()
653{
4c38885c 654 int64 tmp;
4f425a32 655 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 656
657 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 658 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
659 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 660 trace_output (OP_DREG);
2934d1c9
MH		 661}
662
663/* addac3 */
664void
665OP_17000202 ()
666{
4c38885c 667 int64 tmp;
4f425a32 668 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 669
670 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 671 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
672 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 673 trace_output (OP_DREG);
2934d1c9
MH		 674}
675
676/* addac3s */
677void
678OP_17001200 ()
679{
4c38885c 680 int64 tmp;
4c38885c 681 State.F1 = State.F0;
87178dbd
MM		 682
683 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 684 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 685 if ( tmp > MAX32)
686 {
687 State.regs[OP[0]] = 0x7fff;
688 State.regs[OP[0]+1] = 0xffff;
689 State.F0 = 1;
690 }
691 else if (tmp < MIN32)
692 {
693 State.regs[OP[0]] = 0x8000;
694 State.regs[OP[0]+1] = 0;
695 State.F0 = 1;
696 }
697 else
698 {
699 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
700 State.regs[OP[0]+1] = tmp & 0xffff;
701 State.F0 = 0;
702 }
87178dbd 703 trace_output (OP_DREG);
2934d1c9
MH		 704}
705
706/* addac3s */
707void
708OP_17001202 ()
709{
4c38885c 710 int64 tmp;
4c38885c 711 State.F1 = State.F0;
87178dbd
MM		 712
713 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 714 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 715 if ( tmp > MAX32)
716 {
717 State.regs[OP[0]] = 0x7fff;
718 State.regs[OP[0]+1] = 0xffff;
719 State.F0 = 1;
720 }
721 else if (tmp < MIN32)
722 {
723 State.regs[OP[0]] = 0x8000;
724 State.regs[OP[0]+1] = 0;
725 State.F0 = 1;
726 }
727 else
728 {
729 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
730 State.regs[OP[0]+1] = tmp & 0xffff;
731 State.F0 = 0;
732 }
87178dbd 733 trace_output (OP_DREG);
2934d1c9
MH		 734}
735
736/* addi */
737void
738OP_201 ()
739{
2254cd90 740 uint tmp = State.regs[OP[0]];
4f425a32
MH		 741 if (OP[1] == 0)
742 OP[1] = 16;
87178dbd 743 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 744 State.regs[OP[0]] += OP[1];
2254cd90
MM		 745 if (tmp > State.regs[OP[0]])
746 State.C = 1;
747 else
748 State.C = 0;
87178dbd 749 trace_output (OP_REG);
2934d1c9
MH		 750}
751
752/* and */
753void
754OP_C00 ()
755{
87178dbd 756 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 757 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 758 trace_output (OP_REG);
2934d1c9
MH		 759}
760
761/* and3 */
762void
763OP_6000000 ()
764{
87178dbd 765 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 766 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 767 trace_output (OP_REG);
2934d1c9
MH		 768}
769
770/* bclri */
771void
772OP_C01 ()
773{
87178dbd 774 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 775 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 776 trace_output (OP_REG);
2934d1c9
MH		 777}
778
779/* bl.s */
780void
781OP_4900 ()
782{
a18cb100 783 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
2934d1c9
MH		 784 State.regs[13] = PC+1;
785 PC += SEXT8 (OP[0]);
87178dbd 786 trace_output (OP_VOID);
2934d1c9
MH		 787}
788
789/* bl.l */
790void
791OP_24800000 ()
792{
a18cb100 793 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
2934d1c9
MH		 794 State.regs[13] = PC+1;
795 PC += OP[0];
87178dbd 796 trace_output (OP_VOID);
2934d1c9
MH		 797}
798
799/* bnoti */
800void
801OP_A01 ()
802{
87178dbd 803 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 804 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 805 trace_output (OP_REG);
2934d1c9
MH		 806}
807
808/* bra.s */
809void
810OP_4800 ()
811{
a18cb100 812 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 813 PC += SEXT8 (OP[0]);
87178dbd 814 trace_output (OP_VOID);
2934d1c9
MH		 815}
816
817/* bra.l */
818void
819OP_24000000 ()
820{
87178dbd 821 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 822 PC += OP[0];
87178dbd 823 trace_output (OP_VOID);
2934d1c9
MH		 824}
825
826/* brf0f.s */
827void
828OP_4A00 ()
829{
a18cb100 830 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9
MH		 831 if (State.F0 == 0)
832 PC += SEXT8 (OP[0]);
87178dbd 833 trace_output (OP_FLAG);
2934d1c9
MH		 834}
835
836/* brf0f.l */
837void
838OP_25000000 ()
839{
87178dbd 840 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 841 if (State.F0 == 0)
842 PC += OP[0];
87178dbd 843 trace_output (OP_FLAG);
2934d1c9
MH		 844}
845
846/* brf0t.s */
847void
848OP_4B00 ()
849{
a18cb100 850 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9
MH		 851 if (State.F0)
852 PC += SEXT8 (OP[0]);
87178dbd 853 trace_output (OP_FLAG);
2934d1c9
MH		 854}
855
856/* brf0t.l */
857void
858OP_25800000 ()
859{
87178dbd 860 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 861 if (State.F0)
862 PC += OP[0];
87178dbd 863 trace_output (OP_FLAG);
2934d1c9
MH		 864}
865
866/* bseti */
867void
868OP_801 ()
869{
87178dbd 870 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 871 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 872 trace_output (OP_REG);
2934d1c9
MH		 873}
874
875/* btsti */
876void
877OP_E01 ()
878{
87178dbd 879 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 880 State.F1 = State.F0;
881 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 882 trace_output (OP_FLAG);
2934d1c9
MH		 883}
884
885/* clrac */
886void
887OP_5601 ()
888{
87178dbd 889 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 890 State.a[OP[0]] = 0;
87178dbd 891 trace_output (OP_ACCUM);
2934d1c9
MH		 892}
893
894/* cmp */
895void
896OP_600 ()
897{
87178dbd 898 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 899 State.F1 = State.F0;
900 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 901 trace_output (OP_FLAG);
2934d1c9
MH		 902}
903
904/* cmp */
905void
906OP_1603 ()
907{
87178dbd 908 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 909 State.F1 = State.F0;
4f425a32 910 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 911 trace_output (OP_FLAG);
2934d1c9
MH		 912}
913
914/* cmpeq */
915void
916OP_400 ()
917{
87178dbd 918 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 919 State.F1 = State.F0;
920 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 921 trace_output (OP_FLAG);
2934d1c9
MH		 922}
923
924/* cmpeq */
925void
926OP_1403 ()
927{
87178dbd 928 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 929 State.F1 = State.F0;
930 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
87178dbd 931 trace_output (OP_FLAG);
2934d1c9
MH		 932}
933
934/* cmpeqi.s */
935void
936OP_401 ()
937{
c12f5c67 938 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 939 State.F1 = State.F0;
c12f5c67 940 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 941 trace_output (OP_FLAG);
2934d1c9
MH		 942}
943
944/* cmpeqi.l */
945void
946OP_2000000 ()
947{
87178dbd 948 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 949 State.F1 = State.F0;
c12f5c67 950 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 951 trace_output (OP_FLAG);
2934d1c9
MH		 952}
953
954/* cmpi.s */
955void
956OP_601 ()
957{
87178dbd 958 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 959 State.F1 = State.F0;
c12f5c67 960 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 961 trace_output (OP_FLAG);
2934d1c9
MH		 962}
963
964/* cmpi.l */
965void
966OP_3000000 ()
967{
87178dbd 968 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 969 State.F1 = State.F0;
970 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 971 trace_output (OP_FLAG);
2934d1c9
MH		 972}
973
974/* cmpu */
975void
976OP_4600 ()
977{
87178dbd 978 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 979 State.F1 = State.F0;
980 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 981 trace_output (OP_FLAG);
2934d1c9
MH		 982}
983
984/* cmpui */
985void
986OP_23000000 ()
987{
87178dbd 988 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 989 State.F1 = State.F0;
c12f5c67 990 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 991 trace_output (OP_FLAG);
2934d1c9
MH		 992}
993
994/* cpfg */
995void
996OP_4E09 ()
997{
998 uint8 *src, *dst;
2934d1c9 999
60fc5b72 1000 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 1001 if (OP[0] == 0)
1002 dst = &State.F0;
1003 else
1004 dst = &State.F1;
1005
1006 if (OP[1] == 0)
1007 src = &State.F0;
1008 else if (OP[1] == 1)
1009 src = &State.F1;
1010 else
1011 src = &State.C;
1012
1013 *dst = *src;
87178dbd 1014 trace_output (OP_FLAG);
2934d1c9
MH		 1015}
1016
1017/* dbt */
1018void
1019OP_5F20 ()
1020{
a49a15ad 1021 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 1022 State.exception = SIGTRAP;
2934d1c9
MH		 1023}
1024
1025/* divs */
1026void
1027OP_14002800 ()
1028{
1029 uint16 foo, tmp, tmpf;
87178dbd
MM		 1030
1031 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 1032 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1033 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1034 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1035 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1036 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1037 trace_output (OP_DREG);
2934d1c9
MH		 1038}
1039
1040/* exef0f */
1041void
1042OP_4E04 ()
1043{
87178dbd 1044 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1045 State.exe = (State.F0 == 0);
87178dbd 1046 trace_output (OP_FLAG);
2934d1c9
MH		 1047}
1048
1049/* exef0t */
1050void
1051OP_4E24 ()
1052{
87178dbd 1053 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1054 State.exe = (State.F0 != 0);
87178dbd 1055 trace_output (OP_FLAG);
2934d1c9
MH		 1056}
1057
1058/* exef1f */
1059void
1060OP_4E40 ()
1061{
87178dbd 1062 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1063 State.exe = (State.F1 == 0);
87178dbd 1064 trace_output (OP_FLAG);
2934d1c9
MH		 1065}
1066
1067/* exef1t */
1068void
1069OP_4E42 ()
1070{
87178dbd 1071 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1072 State.exe = (State.F1 != 0);
87178dbd 1073 trace_output (OP_FLAG);
2934d1c9
MH		 1074}
1075
1076/* exefaf */
1077void
1078OP_4E00 ()
1079{
87178dbd 1080 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1081 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1082 trace_output (OP_FLAG);
2934d1c9
MH		 1083}
1084
1085/* exefat */
1086void
1087OP_4E02 ()
1088{
87178dbd 1089 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1090 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1091 trace_output (OP_FLAG);
2934d1c9
MH		 1092}
1093
1094/* exetaf */
1095void
1096OP_4E20 ()
1097{
87178dbd 1098 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1099 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1100 trace_output (OP_FLAG);
2934d1c9
MH		 1101}
1102
1103/* exetat */
1104void
1105OP_4E22 ()
1106{
87178dbd 1107 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1108 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1109 trace_output (OP_FLAG);
2934d1c9
MH		 1110}
1111
1112/* exp */
1113void
1114OP_15002A00 ()
1115{
1116 uint32 tmp, foo;
1117 int i;
1118
87178dbd 1119 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1120 if (((int16)State.regs[OP[1]]) >= 0)
1121 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1122 else
4c38885c 1123 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1124
1125 foo = 0x40000000;
4c38885c 1126 for (i=1;i<17;i++)
2934d1c9
MH		 1127 {
1128 if (tmp & foo)
1129 {
1130 State.regs[OP[0]] = i-1;
87178dbd 1131 trace_output (OP_REG);
2934d1c9
MH		 1132 return;
1133 }
4c38885c 1134 foo >>= 1;
2934d1c9
MH		 1135 }
1136 State.regs[OP[0]] = 16;
87178dbd 1137 trace_output (OP_REG);
2934d1c9
MH		 1138}
1139
1140/* exp */
1141void
1142OP_15002A02 ()
1143{
4c38885c
MH		 1144 int64 tmp, foo;
1145 int i;
87178dbd
MM		 1146
1147 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
4f425a32 1148 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 1149 tmp = State.a[OP[1]];
1150 else
1151 tmp = ~(State.a[OP[1]]);
1152
1153 foo = 0x4000000000LL;
1154 for (i=1;i<25;i++)
1155 {
1156 if (tmp & foo)
1157 {
1158 State.regs[OP[0]] = i-9;
87178dbd 1159 trace_output (OP_REG);
4c38885c
MH		 1160 return;
1161 }
1162 foo >>= 1;
1163 }
1164 State.regs[OP[0]] = 16;
87178dbd 1165 trace_output (OP_REG);
2934d1c9
MH		 1166}
1167
1168/* jl */
1169void
1170OP_4D00 ()
1171{
a18cb100 1172 trace_input ("jl", OP_REG, OP_R2, OP_R3);
2934d1c9
MH		 1173 State.regs[13] = PC+1;
1174 PC = State.regs[OP[0]];
87178dbd 1175 trace_output (OP_VOID);
2934d1c9
MH		 1176}
1177
1178/* jmp */
1179void
1180OP_4C00 ()
1181{
a18cb100
MM		 1182 trace_input ("jmp", OP_REG,
1183 (OP[0] == 13) ? OP_R2 : OP_VOID,
1184 (OP[0] == 13) ? OP_R3 : OP_VOID);
1185
2934d1c9 1186 PC = State.regs[OP[0]];
87178dbd 1187 trace_output (OP_VOID);
2934d1c9
MH		 1188}
1189
1190/* ld */
1191void
1192OP_30000000 ()
1193{
87178dbd 1194 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1195 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1196 trace_output (OP_REG);
2934d1c9
MH		 1197}
1198
1199/* ld */
1200void
1201OP_6401 ()
1202{
87178dbd 1203 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1204 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1205 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1206 trace_output (OP_REG);
2934d1c9
MH		 1207}
1208
1209/* ld */
1210void
1211OP_6001 ()
1212{
87178dbd 1213 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1214 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1215 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1216 trace_output (OP_REG);
2934d1c9
MH		 1217}
1218
1219/* ld */
1220void
1221OP_6000 ()
1222{
87178dbd 1223 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1224 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1225 trace_output (OP_REG);
2934d1c9
MH		 1226}
1227
1228/* ld2w */
1229void
1230OP_31000000 ()
1231{
8918b3a7 1232 uint16 addr = State.regs[OP[2]];
308f64d3 1233 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
8918b3a7
MM		 1234 State.regs[OP[0]] = RW (OP[1] + addr);
1235 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
87178dbd 1236 trace_output (OP_DREG);
2934d1c9
MH		 1237}
1238
1239/* ld2w */
1240void
1241OP_6601 ()
1242{
8918b3a7 1243 uint16 addr = State.regs[OP[1]];
87178dbd 1244 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
8918b3a7
MM		 1245 State.regs[OP[0]] = RW (addr);
1246 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1247 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1248 trace_output (OP_DREG);
2934d1c9
MH		 1249}
1250
1251/* ld2w */
1252void
1253OP_6201 ()
1254{
8918b3a7 1255 uint16 addr = State.regs[OP[1]];
87178dbd 1256 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
8918b3a7
MM		 1257 State.regs[OP[0]] = RW (addr);
1258 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1259 INC_ADDR(State.regs[OP[1]],4);
8918b3a7 1260 trace_output (OP_DREG);
2934d1c9
MH		 1261}
1262
1263/* ld2w */
1264void
1265OP_6200 ()
1266{
8918b3a7 1267 uint16 addr = State.regs[OP[1]];
addb61a5 1268 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
8918b3a7
MM		 1269 State.regs[OP[0]] = RW (addr);
1270 State.regs[OP[0]+1] = RW (addr+2);
1271 trace_output (OP_DREG);
2934d1c9
MH		 1272}
1273
1274/* ldb */
1275void
1276OP_38000000 ()
1277{
87178dbd 1278 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
c422ecc7 1279 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
87178dbd 1280 trace_output (OP_REG);
2934d1c9
MH		 1281}
1282
1283/* ldb */
1284void
1285OP_7000 ()
1286{
87178dbd 1287 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
c422ecc7 1288 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
87178dbd 1289 trace_output (OP_REG);
2934d1c9
MH		 1290}
1291
1292/* ldi.s */
1293void
1294OP_4001 ()
1295{
87178dbd 1296 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1297 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1298 trace_output (OP_REG);
2934d1c9
MH		 1299}
1300
1301/* ldi.l */
1302void
1303OP_20000000 ()
1304{
87178dbd 1305 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1306 State.regs[OP[0]] = OP[1];
87178dbd 1307 trace_output (OP_REG);
2934d1c9
MH		 1308}
1309
1310/* ldub */
1311void
1312OP_39000000 ()
1313{
87178dbd 1314 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1315 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1316 trace_output (OP_REG);
2934d1c9
MH		 1317}
1318
1319/* ldub */
1320void
1321OP_7200 ()
1322{
87178dbd 1323 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1324 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1325 trace_output (OP_REG);
2934d1c9
MH		 1326}
1327
1328/* mac */
1329void
1330OP_2A00 ()
1331{
4c38885c 1332 int64 tmp;
87178dbd
MM		 1333
1334 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1335 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1336
1337 if (State.FX)
4f425a32 1338 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1339
1340 if (State.ST && tmp > MAX32)
1341 tmp = MAX32;
1342
4f425a32 1343 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1344 if (State.ST)
1345 {
1346 if (tmp > MAX32)
1347 State.a[OP[0]] = MAX32;
1348 else if (tmp < MIN32)
1349 State.a[OP[0]] = MIN32;
1350 else
4f425a32 1351 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1352 }
1353 else
4f425a32 1354 State.a[OP[0]] = tmp & MASK40;
87178dbd 1355 trace_output (OP_ACCUM);
2934d1c9
MH		 1356}
1357
1358/* macsu */
1359void
1360OP_1A00 ()
1361{
4f425a32 1362 int64 tmp;
87178dbd
MM		 1363
1364 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1365 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1366 if (State.FX)
1367 tmp = SEXT40( (tmp << 1) & MASK40);
1368
1369 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1370 trace_output (OP_ACCUM);
2934d1c9
MH		 1371}
1372
1373/* macu */
1374void
1375OP_3A00 ()
1376{
4f425a32 1377 int64 tmp;
87178dbd
MM		 1378
1379 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1380 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1381 if (State.FX)
1382 tmp = SEXT40( (tmp << 1) & MASK40);
1383 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1384 trace_output (OP_ACCUM);
2934d1c9
MH		 1385}
1386
1387/* max */
1388void
1389OP_2600 ()
1390{
87178dbd 1391 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1392 State.F1 = State.F0;
ea2155e8 1393 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1394 {
1395 State.regs[OP[0]] = State.regs[OP[1]];
1396 State.F0 = 1;
1397 }
1398 else
1399 State.F0 = 0;
87178dbd 1400 trace_output (OP_REG);
2934d1c9
MH		 1401}
1402
1403/* max */
1404void
1405OP_3600 ()
1406{
4f425a32 1407 int64 tmp;
87178dbd
MM		 1408
1409 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1410 State.F1 = State.F0;
1411 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1412 if (tmp > SEXT40(State.a[OP[0]]))
1413 {
1414 State.a[OP[0]] = tmp & MASK40;
1415 State.F0 = 1;
1416 }
1417 else
1418 State.F0 = 0;
87178dbd 1419 trace_output (OP_ACCUM);
2934d1c9
MH		 1420}
1421
1422/* max */
1423void
1424OP_3602 ()
1425{
87178dbd 1426 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1427 State.F1 = State.F0;
1428 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1429 {
1430 State.a[OP[0]] = State.a[OP[1]];
1431 State.F0 = 1;
1432 }
1433 else
1434 State.F0 = 0;
87178dbd 1435 trace_output (OP_ACCUM);
2934d1c9
MH		 1436}
1437
4f425a32 1438
2934d1c9
MH		 1439/* min */
1440void
1441OP_2601 ()
1442{
87178dbd 1443 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1444 State.F1 = State.F0;
ea2155e8 1445 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1446 {
1447 State.regs[OP[0]] = State.regs[OP[1]];
1448 State.F0 = 1;
1449 }
1450 else
1451 State.F0 = 0;
87178dbd 1452 trace_output (OP_REG);
2934d1c9
MH		 1453}
1454
1455/* min */
1456void
1457OP_3601 ()
1458{
4f425a32 1459 int64 tmp;
87178dbd
MM		 1460
1461 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1462 State.F1 = State.F0;
1463 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1464 if (tmp < SEXT40(State.a[OP[0]]))
1465 {
1466 State.a[OP[0]] = tmp & MASK40;
1467 State.F0 = 1;
1468 }
1469 else
1470 State.F0 = 0;
87178dbd 1471 trace_output (OP_ACCUM);
2934d1c9
MH		 1472}
1473
1474/* min */
1475void
1476OP_3603 ()
1477{
87178dbd 1478 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1479 State.F1 = State.F0;
1480 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1481 {
1482 State.a[OP[0]] = State.a[OP[1]];
1483 State.F0 = 1;
1484 }
1485 else
1486 State.F0 = 0;
87178dbd 1487 trace_output (OP_ACCUM);
2934d1c9
MH		 1488}
1489
1490/* msb */
1491void
1492OP_2800 ()
1493{
4f425a32 1494 int64 tmp;
87178dbd
MM		 1495
1496 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1497 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1498
1499 if (State.FX)
1500 tmp = SEXT40 ((tmp << 1) & MASK40);
1501
1502 if (State.ST && tmp > MAX32)
1503 tmp = MAX32;
1504
1505 tmp = SEXT40(State.a[OP[0]]) - tmp;
1506 if (State.ST)
1507 {
1508 if (tmp > MAX32)
1509 State.a[OP[0]] = MAX32;
1510 else if (tmp < MIN32)
1511 State.a[OP[0]] = MIN32;
1512 else
1513 State.a[OP[0]] = tmp & MASK40;
1514 }
1515 else
1516 State.a[OP[0]] = tmp & MASK40;
87178dbd 1517 trace_output (OP_ACCUM);
2934d1c9
MH		 1518}
1519
1520/* msbsu */
1521void
1522OP_1800 ()
1523{
4f425a32 1524 int64 tmp;
87178dbd
MM		 1525
1526 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1527 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1528 if (State.FX)
1529 tmp = SEXT40( (tmp << 1) & MASK40);
1530
1531 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1532 trace_output (OP_ACCUM);
2934d1c9
MH		 1533}
1534
1535/* msbu */
1536void
1537OP_3800 ()
1538{
4f425a32 1539 int64 tmp;
87178dbd
MM		 1540
1541 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1542 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1543 if (State.FX)
1544 tmp = SEXT40( (tmp << 1) & MASK40);
1545
1546 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1547 trace_output (OP_ACCUM);
2934d1c9
MH		 1548}
1549
1550/* mul */
1551void
1552OP_2E00 ()
1553{
87178dbd 1554 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1555 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1556 trace_output (OP_REG);
2934d1c9
MH		 1557}
1558
1559/* mulx */
1560void
1561OP_2C00 ()
1562{
4f425a32 1563 int64 tmp;
87178dbd
MM		 1564
1565 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1566 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1567
1568 if (State.FX)
1569 tmp = SEXT40 ((tmp << 1) & MASK40);
1570
1571 if (State.ST && tmp > MAX32)
1572 State.a[OP[0]] = MAX32;
1573 else
1574 State.a[OP[0]] = tmp & MASK40;
87178dbd 1575 trace_output (OP_ACCUM);
2934d1c9
MH		 1576}
1577
1578/* mulxsu */
1579void
1580OP_1C00 ()
1581{
4f425a32 1582 int64 tmp;
87178dbd
MM		 1583
1584 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1585 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1586
1587 if (State.FX)
1588 tmp <<= 1;
1589
1590 State.a[OP[0]] = tmp & MASK40;
87178dbd 1591 trace_output (OP_ACCUM);
2934d1c9
MH		 1592}
1593
1594/* mulxu */
1595void
1596OP_3C00 ()
1597{
4f425a32 1598 int64 tmp;
87178dbd
MM		 1599
1600 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1601 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1602
1603 if (State.FX)
1604 tmp <<= 1;
1605
1606 State.a[OP[0]] = tmp & MASK40;
87178dbd 1607 trace_output (OP_ACCUM);
2934d1c9
MH		 1608}
1609
1610/* mv */
1611void
1612OP_4000 ()
1613{
87178dbd 1614 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1615 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1616 trace_output (OP_REG);
2934d1c9
MH		 1617}
1618
1619/* mv2w */
1620void
1621OP_5000 ()
1622{
87178dbd 1623 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1624 State.regs[OP[0]] = State.regs[OP[1]];
1625 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1626 trace_output (OP_DREG);
2934d1c9
MH		 1627}
1628
1629/* mv2wfac */
1630void
1631OP_3E00 ()
1632{
87178dbd 1633 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1634 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1635 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1636 trace_output (OP_DREG);
2934d1c9
MH		 1637}
1638
1639/* mv2wtac */
1640void
1641OP_3E01 ()
1642{
87178dbd 1643 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
4f425a32 1644 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
87178dbd 1645 trace_output (OP_ACCUM);
2934d1c9
MH		 1646}
1647
1648/* mvac */
1649void
1650OP_3E03 ()
1651{
87178dbd 1652 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1653 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1654 trace_output (OP_ACCUM);
2934d1c9
MH		 1655}
1656
1657/* mvb */
1658void
1659OP_5400 ()
1660{
87178dbd 1661 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1662 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1663 trace_output (OP_REG);
2934d1c9
MH		 1664}
1665
1666/* mvf0f */
1667void
1668OP_4400 ()
1669{
87178dbd 1670 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1671 if (State.F0 == 0)
1672 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1673 trace_output (OP_REG);
2934d1c9
MH		 1674}
1675
1676/* mvf0t */
1677void
1678OP_4401 ()
1679{
87178dbd 1680 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1681 if (State.F0)
1682 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1683 trace_output (OP_REG);
2934d1c9
MH		 1684}
1685
1686/* mvfacg */
1687void
1688OP_1E04 ()
1689{
87178dbd 1690 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1691 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1692 trace_output (OP_ACCUM);
2934d1c9
MH		 1693}
1694
1695/* mvfachi */
1696void
1697OP_1E00 ()
1698{
87178dbd 1699 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1700 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1701 trace_output (OP_REG);
2934d1c9
MH		 1702}
1703
1704/* mvfaclo */
1705void
1706OP_1E02 ()
1707{
87178dbd 1708 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1709 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1710 trace_output (OP_REG);
2934d1c9
MH		 1711}
1712
1713/* mvfc */
1714void
1715OP_5200 ()
1716{
87178dbd 1717 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1718 if (OP[1] == 0)
1719 {
1720 /* PSW is treated specially */
1721 PSW = 0;
1722 if (State.SM) PSW |= 0x8000;
1723 if (State.EA) PSW |= 0x2000;
1724 if (State.DB) PSW |= 0x1000;
1725 if (State.IE) PSW |= 0x400;
1726 if (State.RP) PSW |= 0x200;
1727 if (State.MD) PSW |= 0x100;
1728 if (State.FX) PSW |= 0x80;
1729 if (State.ST) PSW |= 0x40;
1730 if (State.F0) PSW |= 8;
1731 if (State.F1) PSW |= 4;
1732 if (State.C) PSW |= 1;
1733 }
1734 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1735 trace_output (OP_REG);
2934d1c9
MH		 1736}
1737
1738/* mvtacg */
1739void
1740OP_1E41 ()
1741{
87178dbd 1742 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1743 State.a[OP[1]] &= MASK32;
1744 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1745 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1746}
1747
1748/* mvtachi */
1749void
1750OP_1E01 ()
1751{
1752 uint16 tmp;
87178dbd
MM		 1753
1754 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1755 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1756 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1757 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1758}
1759
1760/* mvtaclo */
1761void
1762OP_1E21 ()
1763{
87178dbd 1764 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1765 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1766 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1767}
1768
1769/* mvtc */
1770void
1771OP_5600 ()
1772{
87178dbd 1773 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1774 State.cregs[OP[1]] = State.regs[OP[0]];
1775 if (OP[1] == 0)
1776 {
1777 /* PSW is treated specially */
1778 State.SM = (PSW & 0x8000) ? 1 : 0;
1779 State.EA = (PSW & 0x2000) ? 1 : 0;
1780 State.DB = (PSW & 0x1000) ? 1 : 0;
1781 State.IE = (PSW & 0x400) ? 1 : 0;
1782 State.RP = (PSW & 0x200) ? 1 : 0;
1783 State.MD = (PSW & 0x100) ? 1 : 0;
1784 State.FX = (PSW & 0x80) ? 1 : 0;
1785 State.ST = (PSW & 0x40) ? 1 : 0;
1786 State.F0 = (PSW & 8) ? 1 : 0;
1787 State.F1 = (PSW & 4) ? 1 : 0;
1788 State.C = PSW & 1;
1789 if (State.ST && !State.FX)
1790 {
7eebfc62
MM		 1791 (*d10v_callback->printf_filtered) (d10v_callback,
1792 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1793 PC<<2);
4f425a32 1794 State.exception = SIGILL;
2934d1c9
MH		 1795 }
1796 }
87178dbd 1797 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1798}
1799
1800/* mvub */
1801void
1802OP_5401 ()
1803{
87178dbd 1804 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1805 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1806 trace_output (OP_REG);
2934d1c9
MH		 1807}
1808
1809/* neg */
1810void
1811OP_4605 ()
1812{
87178dbd 1813 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1814 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1815 trace_output (OP_REG);
2934d1c9
MH		 1816}
1817
1818/* neg */
1819void
1820OP_5605 ()
1821{
1822 int64 tmp;
87178dbd
MM		 1823
1824 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1825 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1826 if (State.ST)
1827 {
4c38885c 1828 if ( tmp > MAX32)
2934d1c9 1829 State.a[OP[0]] = MAX32;
4c38885c 1830 else if (tmp < MIN32)
2934d1c9
MH		 1831 State.a[OP[0]] = MIN32;
1832 else
4f425a32 1833 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1834 }
1835 else
4f425a32 1836 State.a[OP[0]] = tmp & MASK40;
87178dbd 1837 trace_output (OP_ACCUM);
2934d1c9
MH		 1838}
1839
1840
1841/* nop */
1842void
1843OP_5E00 ()
1844{
87178dbd 1845 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
7eebfc62 1846
c422ecc7
MH		 1847 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1848 switch (State.ins_type)
1849 {
1850 default:
1851 ins_type_counters[ (int)INS_UNKNOWN ]++;
1852 break;
1853
1854 case INS_LEFT_PARALLEL:
1855 /* Don't count a parallel op that includes a NOP as a true parallel op */
1856 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1857 ins_type_counters[ (int)INS_RIGHT ]++;
1858 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1859 break;
1860
1861 case INS_LEFT:
1862 case INS_LEFT_COND_EXE:
1863 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1864 break;
1865
1866 case INS_RIGHT_PARALLEL:
1867 /* Don't count a parallel op that includes a NOP as a true parallel op */
1868 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1869 ins_type_counters[ (int)INS_LEFT ]++;
1870 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1871 break;
1872
1873 case INS_RIGHT:
1874 case INS_RIGHT_COND_EXE:
1875 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1876 break;
1877 }
1878
1879 trace_output (OP_VOID);
2934d1c9
MH		 1880}
1881
1882/* not */
1883void
1884OP_4603 ()
1885{
87178dbd 1886 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1887 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1888 trace_output (OP_REG);
2934d1c9
MH		 1889}
1890
1891/* or */
1892void
1893OP_800 ()
1894{
87178dbd 1895 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1896 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1897 trace_output (OP_REG);
2934d1c9
MH		 1898}
1899
1900/* or3 */
1901void
1902OP_4000000 ()
1903{
87178dbd 1904 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1905 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1906 trace_output (OP_REG);
2934d1c9
MH		 1907}
1908
1909/* rac */
1910void
1911OP_5201 ()
1912{
1913 int64 tmp;
1914 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1915
1916 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1917 if (OP[1] != 0)
1918 {
7eebfc62
MM		 1919 (*d10v_callback->printf_filtered) (d10v_callback,
1920 "ERROR at PC 0x%x: instruction only valid for A0\n",
1921 PC<<2);
166acb9f
MH		 1922 State.exception = SIGILL;
1923 }
1924
2934d1c9
MH		 1925 State.F1 = State.F0;
1926 if (shift >=0)
1927 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1928 else
1929 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1930 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1931 if (tmp > MAX32)
2934d1c9
MH		 1932 {
1933 State.regs[OP[0]] = 0x7fff;
1934 State.regs[OP[0]+1] = 0xffff;
1935 State.F0 = 1;
1936 }
4c38885c 1937 else if (tmp < MIN32)
2934d1c9
MH		 1938 {
1939 State.regs[OP[0]] = 0x8000;
1940 State.regs[OP[0]+1] = 0;
1941 State.F0 = 1;
1942 }
1943 else
1944 {
1945 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1946 State.regs[OP[0]+1] = tmp & 0xffff;
1947 State.F0 = 0;
1948 }
87178dbd 1949 trace_output (OP_DREG);
2934d1c9
MH		 1950}
1951
1952/* rachi */
1953void
1954OP_4201 ()
1955{
4c38885c
MH		 1956 int64 tmp;
1957 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1958
1959 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1960 State.F1 = State.F0;
1961 if (shift >=0)
166acb9f 1962 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1963 else
166acb9f 1964 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1965 tmp += 0x8000;
63a91cfb 1966
4c38885c
MH		 1967 if (tmp > MAX32)
1968 {
1969 State.regs[OP[0]] = 0x7fff;
1970 State.F0 = 1;
1971 }
1972 else if (tmp < 0xfff80000000LL)
1973 {
1974 State.regs[OP[0]] = 0x8000;
1975 State.F0 = 1;
1976 }
1977 else
1978 {
1979 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1980 State.F0 = 0;
1981 }
87178dbd 1982 trace_output (OP_REG);
2934d1c9
MH		 1983}
1984
1985/* rep */
1986void
1987OP_27000000 ()
1988{
87178dbd 1989 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1990 RPT_S = PC + 1;
1991 RPT_E = PC + OP[1];
1992 RPT_C = State.regs[OP[0]];
1993 State.RP = 1;
1994 if (RPT_C == 0)
1995 {
7eebfc62 1996 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1997 State.exception = SIGILL;
2934d1c9 1998 }
4c38885c
MH		 1999 if (OP[1] < 4)
2000 {
7eebfc62 2001 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 2002 State.exception = SIGILL;
4c38885c 2003 }
87178dbd 2004 trace_output (OP_VOID);
2934d1c9
MH		 2005}
2006
2007/* repi */
2008void
2009OP_2F000000 ()
2010{
87178dbd 2011 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 2012 RPT_S = PC + 1;
2013 RPT_E = PC + OP[1];
2014 RPT_C = OP[0];
2015 State.RP = 1;
2016 if (RPT_C == 0)
2017 {
7eebfc62 2018 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 2019 State.exception = SIGILL;
4c38885c
MH		 2020 }
2021 if (OP[1] < 4)
2022 {
7eebfc62 2023 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 2024 State.exception = SIGILL;
2934d1c9 2025 }
87178dbd 2026 trace_output (OP_VOID);
2934d1c9
MH		 2027}
2028
2029/* rtd */
2030void
2031OP_5F60 ()
2032{
7eebfc62 2033 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 2034 State.exception = SIGILL;
2934d1c9
MH		 2035}
2036
2037/* rte */
2038void
2039OP_5F40 ()
2040{
87178dbd 2041 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 2042 PC = BPC;
2043 PSW = BPSW;
87178dbd 2044 trace_output (OP_VOID);
2934d1c9
MH		 2045}
2046
2047/* sadd */
2048void
2049OP_1223 ()
2050{
4c38885c 2051 int64 tmp;
87178dbd
MM		 2052
2053 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 2054 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 2055 if (State.ST)
2056 {
2057 if (tmp > MAX32)
2058 State.a[OP[0]] = MAX32;
2059 else if (tmp < MIN32)
2060 State.a[OP[0]] = MIN32;
2061 else
4f425a32 2062 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 2063 }
2064 else
4f425a32 2065 State.a[OP[0]] = tmp & MASK40;
87178dbd 2066 trace_output (OP_ACCUM);
2934d1c9
MH		 2067}
2068
2069/* setf0f */
2070void
2071OP_4611 ()
2072{
87178dbd 2073 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2074 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2075 trace_output (OP_REG);
2934d1c9
MH		 2076}
2077
2078/* setf0t */
2079void
2080OP_4613 ()
2081{
87178dbd 2082 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2083 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2084 trace_output (OP_REG);
2934d1c9
MH		 2085}
2086
2087/* sleep */
2088void
2089OP_5FC0 ()
2090{
87178dbd 2091 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2092 State.IE = 1;
87178dbd 2093 trace_output (OP_VOID);
2934d1c9
MH		 2094}
2095
2096/* sll */
2097void
2098OP_2200 ()
2099{
87178dbd 2100 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2101 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2102 trace_output (OP_REG);
2934d1c9
MH		 2103}
2104
2105/* sll */
2106void
2107OP_3200 ()
2108{
4c38885c 2109 int64 tmp;
87178dbd 2110 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2111 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2112 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2113 else
2114 {
2115 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2116 State.exception = SIGILL;
2117 return;
2118 }
4c38885c
MH		 2119
2120 if (State.ST)
2121 {
2122 if (tmp > MAX32)
2123 State.a[OP[0]] = MAX32;
2124 else if (tmp < 0xffffff80000000LL)
2125 State.a[OP[0]] = MIN32;
2126 else
2127 State.a[OP[0]] = tmp & MASK40;
2128 }
2129 else
2130 State.a[OP[0]] = tmp & MASK40;
87178dbd 2131 trace_output (OP_ACCUM);
2934d1c9
MH		 2132}
2133
2134/* slli */
2135void
2136OP_2201 ()
2137{
87178dbd 2138 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2139 State.regs[OP[0]] <<= OP[1];
87178dbd 2140 trace_output (OP_REG);
2934d1c9
MH		 2141}
2142
2143/* slli */
2144void
2145OP_3201 ()
2146{
4c38885c 2147 int64 tmp;
4f425a32
MH		 2148
2149 if (OP[1] == 0)
2150 OP[1] = 16;
4f425a32 2151
87178dbd 2152 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2153 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2154
2155 if (State.ST)
2156 {
2157 if (tmp > MAX32)
2158 State.a[OP[0]] = MAX32;
2159 else if (tmp < 0xffffff80000000LL)
2160 State.a[OP[0]] = MIN32;
2161 else
2162 State.a[OP[0]] = tmp & MASK40;
2163 }
2164 else
2165 State.a[OP[0]] = tmp & MASK40;
87178dbd 2166 trace_output (OP_ACCUM);
2934d1c9
MH		 2167}
2168
2169/* slx */
2170void
2171OP_460B ()
2172{
87178dbd 2173 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2174 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2175 trace_output (OP_REG);
2934d1c9
MH		 2176}
2177
2178/* sra */
2179void
2180OP_2400 ()
2181{
87178dbd 2182 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2183 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2184 trace_output (OP_REG);
2934d1c9
MH		 2185}
2186
2187/* sra */
2188void
2189OP_3400 ()
2190{
87178dbd 2191 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2192 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2193 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2194 else
2195 {
2196 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2197 State.exception = SIGILL;
2198 return;
2199 }
2200
87178dbd 2201 trace_output (OP_ACCUM);
2934d1c9
MH		 2202}
2203
2204/* srai */
2205void
2206OP_2401 ()
2207{
87178dbd 2208 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2209 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2210 trace_output (OP_REG);
2934d1c9
MH		 2211}
2212
2213/* srai */
2214void
2215OP_3401 ()
2216{
4f425a32
MH		 2217 if (OP[1] == 0)
2218 OP[1] = 16;
87178dbd
MM		 2219
2220 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2221 State.a[OP[0]] >>= OP[1];
2222 trace_output (OP_ACCUM);
2934d1c9
MH		 2223}
2224
2225/* srl */
2226void
2227OP_2000 ()
2228{
87178dbd 2229 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2230 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2231 trace_output (OP_REG);
2934d1c9
MH		 2232}
2233
2234/* srl */
2235void
2236OP_3000 ()
2237{
87178dbd 2238 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2239 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2240 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2241 else
2242 {
2243 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2244 State.exception = SIGILL;
2245 return;
2246 }
2247
87178dbd 2248 trace_output (OP_ACCUM);
2934d1c9
MH		 2249}
2250
2251/* srli */
2252void
2253OP_2001 ()
2254{
87178dbd 2255 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2256 State.regs[OP[0]] >>= OP[1];
87178dbd 2257 trace_output (OP_REG);
2934d1c9
MH		 2258}
2259
2260/* srli */
2261void
2262OP_3001 ()
2263{
4f425a32
MH		 2264 if (OP[1] == 0)
2265 OP[1] = 16;
87178dbd
MM		 2266
2267 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2268 State.a[OP[0]] >>= OP[1];
2269 trace_output (OP_ACCUM);
2934d1c9
MH		 2270}
2271
2272/* srx */
2273void
2274OP_4609 ()
2275{
2276 uint16 tmp;
87178dbd
MM		 2277
2278 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2279 tmp = State.F0 << 15;
2280 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2281 trace_output (OP_REG);
2934d1c9
MH		 2282}
2283
2284/* st */
2285void
2286OP_34000000 ()
2287{
87178dbd 2288 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2289 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2290 trace_output (OP_VOID);
2934d1c9
MH		 2291}
2292
2293/* st */
2294void
2295OP_6800 ()
2296{
87178dbd 2297 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2298 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2299 trace_output (OP_VOID);
2934d1c9
MH		 2300}
2301
2302/* st */
2303void
2304OP_6C1F ()
2305{
87178dbd 2306 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2307 if ( OP[1] != 15 )
2308 {
7eebfc62 2309 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2310 State.exception = SIGILL;
2311 return;
4c38885c
MH		 2312 }
2313 State.regs[OP[1]] -= 2;
2314 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2315 trace_output (OP_VOID);
2934d1c9
MH		 2316}
2317
2318/* st */
2319void
2320OP_6801 ()
2321{
87178dbd 2322 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2323 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2324 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2325 trace_output (OP_VOID);
2934d1c9
MH		 2326}
2327
2328/* st */
2329void
2330OP_6C01 ()
2331{
87178dbd 2332 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c 2333 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2334 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2335 trace_output (OP_VOID);
2934d1c9
MH		 2336}
2337
2338/* st2w */
2339void
2340OP_35000000 ()
2341{
87178dbd 2342 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2343 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2344 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2345 trace_output (OP_VOID);
2934d1c9
MH		 2346}
2347
2348/* st2w */
2349void
2350OP_6A00 ()
2351{
a18cb100 2352 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2353 SW (State.regs[OP[1]], State.regs[OP[0]]);
2354 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2355 trace_output (OP_VOID);
2934d1c9
MH		 2356}
2357
2358/* st2w */
2359void
2360OP_6E1F ()
2361{
a18cb100 2362 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2363 if ( OP[1] != 15 )
2364 {
7eebfc62 2365 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2366 State.exception = SIGILL;
2367 return;
4c38885c
MH		 2368 }
2369 State.regs[OP[1]] -= 4;
2370 SW (State.regs[OP[1]], State.regs[OP[0]]);
2371 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2372 trace_output (OP_VOID);
2934d1c9
MH		 2373}
2374
2375/* st2w */
2376void
2377OP_6A01 ()
2378{
a18cb100 2379 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
4c38885c
MH		 2380 SW (State.regs[OP[1]], State.regs[OP[0]]);
2381 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2382 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2383 trace_output (OP_VOID);
2934d1c9
MH		 2384}
2385
2386/* st2w */
2387void
2388OP_6E01 ()
2389{
a18cb100 2390 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2391 SW (State.regs[OP[1]], State.regs[OP[0]]);
2392 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2393 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2394 trace_output (OP_VOID);
2934d1c9
MH		 2395}
2396
2397/* stb */
2398void
2399OP_3C000000 ()
2400{
87178dbd 2401 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2402 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2403 trace_output (OP_VOID);
2934d1c9
MH		 2404}
2405
2406/* stb */
2407void
2408OP_7800 ()
2409{
87178dbd 2410 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2411 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2412 trace_output (OP_VOID);
2934d1c9
MH		 2413}
2414
2415/* stop */
2416void
2417OP_5FE0 ()
2418{
87178dbd 2419 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2420 State.exception = SIG_D10V_STOP;
87178dbd 2421 trace_output (OP_VOID);
2934d1c9
MH		 2422}
2423
2424/* sub */
2425void
2426OP_0 ()
4c38885c
MH		 2427{
2428 int32 tmp;
87178dbd
MM		 2429
2430 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
4c38885c
MH		 2431 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2432 State.C = (tmp & 0xffff0000) ? 1 : 0;
2433 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2434 trace_output (OP_REG);
4c38885c
MH		 2435}
2436
2437/* sub */
2438void
2439OP_1001 ()
2440{
4f425a32 2441 int64 tmp;
87178dbd
MM		 2442
2443 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2444 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2445 if (State.ST)
2446 {
2447 if ( tmp > MAX32)
2448 State.a[OP[0]] = MAX32;
2449 else if ( tmp < MIN32)
2450 State.a[OP[0]] = MIN32;
2451 else
2452 State.a[OP[0]] = tmp & MASK40;
2453 }
2454 else
2455 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2456
2457 trace_output (OP_ACCUM);
4c38885c
MH		 2458}
2459
2460/* sub */
2461
2462void
2463OP_1003 ()
2934d1c9 2464{
4f425a32 2465 int64 tmp;
87178dbd
MM		 2466
2467 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2468 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2469 if (State.ST)
2470 {
2471 if (tmp > MAX32)
2472 State.a[OP[0]] = MAX32;
2473 else if ( tmp < MIN32)
2474 State.a[OP[0]] = MIN32;
2475 else
2476 State.a[OP[0]] = tmp & MASK40;
2477 }
2478 else
2479 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2480
2481 trace_output (OP_ACCUM);
2934d1c9
MH		 2482}
2483
2484/* sub2w */
2485void
2486OP_1000 ()
2487{
4c38885c
MH		 2488 int64 tmp;
2489 int32 a,b;
4c38885c 2490
87178dbd 2491 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
4c38885c
MH		 2492 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2493 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2494 tmp = a-b;
2495 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2496 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2497 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2498 trace_output (OP_DREG);
2934d1c9
MH		 2499}
2500
2501/* subac3 */
2502void
2503OP_17000000 ()
2504{
4f425a32 2505 int64 tmp;
87178dbd
MM		 2506
2507 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2508 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2509 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2510 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2511 trace_output (OP_DREG);
2934d1c9
MH		 2512}
2513
2514/* subac3 */
2515void
2516OP_17000002 ()
2517{
4f425a32 2518 int64 tmp;
87178dbd
MM		 2519
2520 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2521 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2522 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2523 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2524 trace_output (OP_DREG);
2934d1c9
MH		 2525}
2526
2527/* subac3s */
2528void
2529OP_17001000 ()
2530{
4f425a32 2531 int64 tmp;
87178dbd
MM		 2532
2533 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2534 State.F1 = State.F0;
2535 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2536 if ( tmp > MAX32)
2537 {
2538 State.regs[OP[0]] = 0x7fff;
2539 State.regs[OP[0]+1] = 0xffff;
2540 State.F0 = 1;
2541 }
2542 else if (tmp < MIN32)
2543 {
2544 State.regs[OP[0]] = 0x8000;
2545 State.regs[OP[0]+1] = 0;
2546 State.F0 = 1;
2547 }
2548 else
2549 {
2550 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2551 State.regs[OP[0]+1] = tmp & 0xffff;
2552 State.F0 = 0;
2553 }
87178dbd 2554 trace_output (OP_DREG);
2934d1c9
MH		 2555}
2556
2557/* subac3s */
2558void
2559OP_17001002 ()
2560{
4f425a32 2561 int64 tmp;
87178dbd
MM		 2562
2563 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2564 State.F1 = State.F0;
2565 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2566 if ( tmp > MAX32)
2567 {
2568 State.regs[OP[0]] = 0x7fff;
2569 State.regs[OP[0]+1] = 0xffff;
2570 State.F0 = 1;
2571 }
2572 else if (tmp < MIN32)
2573 {
2574 State.regs[OP[0]] = 0x8000;
2575 State.regs[OP[0]+1] = 0;
2576 State.F0 = 1;
2577 }
2578 else
2579 {
2580 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2581 State.regs[OP[0]+1] = tmp & 0xffff;
2582 State.F0 = 0;
2583 }
87178dbd 2584 trace_output (OP_DREG);
2934d1c9
MH		 2585}
2586
2587/* subi */
2588void
2589OP_1 ()
2590{
4c38885c 2591 int32 tmp;
4f425a32
MH		 2592 if (OP[1] == 0)
2593 OP[1] = 16;
87178dbd
MM		 2594
2595 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c
MH		 2596 tmp = (int16)State.regs[OP[0]] - OP[1];
2597 State.C = (tmp & 0xffff0000) ? 1 : 0;
2598 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2599 trace_output (OP_REG);
2934d1c9
MH		 2600}
2601
2602/* trap */
2603void
2604OP_5F00 ()
2605{
a5719092 2606 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2607 trace_output (OP_VOID);
8918b3a7 2608
63a91cfb 2609 switch (OP[0])
2934d1c9 2610 {
63a91cfb 2611 default:
19d44375 2612#if 0
7eebfc62 2613 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb 2614 State.exception = SIGILL;
19d44375
MM		 2615#else
2616 /* Use any other traps for batch debugging. */
2617 {
2618 int i;
2619 static int first_time = 1;
2620
2621 if (first_time)
2622 {
2623 first_time = 0;
2624 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2625 for (i = 0; i < 16; i++)
2626 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2627 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2628 }
2629
2630 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2631
2632 for (i = 0; i < 16; i++)
2633 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2634
2635 for (i = 0; i < 2; i++)
2636 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
11ec4de6
MM		 2637 ((int)(State.a[i] >> 32) & 0xff),
2638 ((unsigned long)State.a[i]) & 0xffffffff);
19d44375
MM		 2639
2640 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2641 State.F0 != 0, State.F1 != 0, State.C != 0);
2642 break;
2643#endif
63a91cfb
MM		 2644
2645 case 0:
2646 /* Trap 0 is used for simulating low-level I/O */
2647 {
63a91cfb
MM		 2648 errno = 0;
2649
2650/* Registers passed to trap 0 */
2651
65c0d7de
MA		 2652#define FUNC State.regs[6] /* function number */
2653#define PARM1 State.regs[2] /* optional parm 1 */
2654#define PARM2 State.regs[3] /* optional parm 2 */
2655#define PARM3 State.regs[4] /* optional parm 3 */
2656#define PARM4 State.regs[5] /* optional parm 3 */
63a91cfb
MM		 2657
2658/* Registers set by trap 0 */
2659
65c0d7de
MA		 2660#define RETVAL State.regs[2] /* return value */
2661#define RETVAL_HIGH State.regs[2] /* return value */
2662#define RETVAL_LOW State.regs[3] /* return value */
2663#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2664
2665/* Turn a pointer in a register into a pointer into real memory. */
2666
c422ecc7 2667#define MEMPTR(x) ((char *)(dmem_addr(x)))
63a91cfb
MM		 2668
2669 switch (FUNC)
2670 {
2671#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2672 case SYS_fork:
2673 RETVAL = fork ();
8918b3a7
MM		 2674 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2675 trace_output (OP_R2);
63a91cfb 2676 break;
8918b3a7 2677
57bc1a72
MM		 2678 case SYS_getpid:
2679 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2680 RETVAL = getpid ();
2681 trace_output (OP_R2);
2682 break;
2683
2684 case SYS_kill:
2685 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2686 if (PARM1 == getpid ())
2687 {
2688 trace_output (OP_VOID);
2689 State.exception = PARM2;
2690 }
2691 else
2692 {
2693 int os_sig = -1;
2694 switch (PARM2)
2695 {
2696#ifdef SIGHUP
2697 case 1: os_sig = SIGHUP; break;
2698#endif
2699#ifdef SIGINT
2700 case 2: os_sig = SIGINT; break;
2701#endif
2702#ifdef SIGQUIT
2703 case 3: os_sig = SIGQUIT; break;
2704#endif
2705#ifdef SIGILL
2706 case 4: os_sig = SIGILL; break;
2707#endif
2708#ifdef SIGTRAP
2709 case 5: os_sig = SIGTRAP; break;
2710#endif
2711#ifdef SIGABRT
2712 case 6: os_sig = SIGABRT; break;
2713#elif defined(SIGIOT)
2714 case 6: os_sig = SIGIOT; break;
2715#endif
2716#ifdef SIGEMT
2717 case 7: os_sig = SIGEMT; break;
2718#endif
2719#ifdef SIGFPE
2720 case 8: os_sig = SIGFPE; break;
2721#endif
2722#ifdef SIGKILL
2723 case 9: os_sig = SIGKILL; break;
2724#endif
2725#ifdef SIGBUS
2726 case 10: os_sig = SIGBUS; break;
2727#endif
2728#ifdef SIGSEGV
2729 case 11: os_sig = SIGSEGV; break;
2730#endif
2731#ifdef SIGSYS
2732 case 12: os_sig = SIGSYS; break;
2733#endif
2734#ifdef SIGPIPE
2735 case 13: os_sig = SIGPIPE; break;
2736#endif
2737#ifdef SIGALRM
2738 case 14: os_sig = SIGALRM; break;
2739#endif
2740#ifdef SIGTERM
2741 case 15: os_sig = SIGTERM; break;
2742#endif
2743#ifdef SIGURG
2744 case 16: os_sig = SIGURG; break;
2745#endif
2746#ifdef SIGSTOP
2747 case 17: os_sig = SIGSTOP; break;
2748#endif
2749#ifdef SIGTSTP
2750 case 18: os_sig = SIGTSTP; break;
2751#endif
2752#ifdef SIGCONT
2753 case 19: os_sig = SIGCONT; break;
2754#endif
2755#ifdef SIGCHLD
2756 case 20: os_sig = SIGCHLD; break;
2757#elif defined(SIGCLD)
2758 case 20: os_sig = SIGCLD; break;
2759#endif
2760#ifdef SIGTTIN
2761 case 21: os_sig = SIGTTIN; break;
2762#endif
2763#ifdef SIGTTOU
2764 case 22: os_sig = SIGTTOU; break;
2765#endif
2766#ifdef SIGIO
2767 case 23: os_sig = SIGIO; break;
2768#elif defined (SIGPOLL)
2769 case 23: os_sig = SIGPOLL; break;
2770#endif
2771#ifdef SIGXCPU
2772 case 24: os_sig = SIGXCPU; break;
2773#endif
2774#ifdef SIGXFSZ
2775 case 25: os_sig = SIGXFSZ; break;
2776#endif
2777#ifdef SIGVTALRM
2778 case 26: os_sig = SIGVTALRM; break;
2779#endif
2780#ifdef SIGPROF
2781 case 27: os_sig = SIGPROF; break;
2782#endif
2783#ifdef SIGWINCH
2784 case 28: os_sig = SIGWINCH; break;
2785#endif
2786#ifdef SIGLOST
2787 case 29: os_sig = SIGLOST; break;
2788#endif
2789#ifdef SIGUSR1
2790 case 30: os_sig = SIGUSR1; break;
2791#endif
2792#ifdef SIGUSR2
2793 case 31: os_sig = SIGUSR2; break;
2794#endif
2795 }
2796
2797 if (os_sig == -1)
2798 {
2799 trace_output (OP_VOID);
2800 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2801 State.exception = SIGILL;
2802 }
2803 else
2804 {
2805 RETVAL = kill (PARM1, PARM2);
2806 trace_output (OP_R2);
2807 }
2808 }
2809 break;
2810
63a91cfb
MM		 2811 case SYS_execve:
2812 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2813 (char **)MEMPTR (PARM3));
8918b3a7
MM		 2814 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2815 trace_output (OP_R2);
63a91cfb 2816 break;
8918b3a7 2817
63a91cfb
MM		 2818 case SYS_execv:
2819 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
8918b3a7
MM		 2820 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2821 trace_output (OP_R2);
63a91cfb 2822 break;
8918b3a7 2823
63a91cfb
MM		 2824 case SYS_pipe:
2825 {
2826 reg_t buf;
2827 int host_fd[2];
2828
2829 buf = PARM1;
2830 RETVAL = pipe (host_fd);
2831 SW (buf, host_fd[0]);
2832 buf += sizeof(uint16);
2833 SW (buf, host_fd[1]);
8918b3a7
MM		 2834 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2835 trace_output (OP_R2);
63a91cfb
MM		 2836 }
2837 break;
8918b3a7 2838
63a91cfb
MM		 2839 case SYS_wait:
2840 {
2841 int status;
2842
2843 RETVAL = wait (&status);
8918b3a7
MM		 2844 if (PARM1)
2845 SW (PARM1, status);
2846 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2847 trace_output (OP_R2);
63a91cfb
MM		 2848 }
2849 break;
57bc1a72
MM		 2850#else
2851 case SYS_getpid:
2852 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2853 RETVAL = 1;
2854 trace_output (OP_R2);
2855 break;
2856
2857 case SYS_kill:
2858 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2859 trace_output (OP_VOID);
2860 State.exception = PARM2;
2861 break;
63a91cfb 2862#endif
8918b3a7 2863
63a91cfb
MM		 2864 case SYS_read:
2865 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2866 PARM3);
8918b3a7
MM		 2867 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2868 trace_output (OP_R2);
63a91cfb 2869 break;
8918b3a7 2870
63a91cfb
MM		 2871 case SYS_write:
2872 if (PARM1 == 1)
2873 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2874 MEMPTR (PARM2), PARM3);
2875 else
2876 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2877 MEMPTR (PARM2), PARM3);
8918b3a7
MM		 2878 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2879 trace_output (OP_R2);
63a91cfb 2880 break;
8918b3a7 2881
63a91cfb 2882 case SYS_lseek:
65c0d7de
MA		 2883 {
2884 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2885 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2886 PARM4);
2887 RETVAL_HIGH = ret >> 16;
2888 RETVAL_LOW = ret & 0xffff;
2889 }
8918b3a7
MM		 2890 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2891 trace_output (OP_R2R3);
63a91cfb 2892 break;
8918b3a7 2893
63a91cfb
MM		 2894 case SYS_close:
2895 RETVAL = d10v_callback->close (d10v_callback, PARM1);
8918b3a7
MM		 2896 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2897 trace_output (OP_R2);
63a91cfb 2898 break;
8918b3a7 2899
63a91cfb
MM		 2900 case SYS_open:
2901 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2902 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2903 trace_output (OP_R2);
2904 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2905 trace_output (OP_R2);
63a91cfb 2906 break;
8918b3a7 2907
63a91cfb 2908 case SYS_exit:
a49a15ad 2909 State.exception = SIG_D10V_EXIT;
8918b3a7
MM		 2910 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2911 trace_output (OP_VOID);
63a91cfb 2912 break;
63a91cfb 2913
8719be26 2914 case SYS_stat:
63a91cfb
MM		 2915 /* stat system call */
2916 {
2917 struct stat host_stat;
2918 reg_t buf;
2919
2920 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2921
2922 buf = PARM2;
2923
2924 /* The hard-coded offsets and sizes were determined by using
2925 * the D10V compiler on a test program that used struct stat.
2926 */
2927 SW (buf, host_stat.st_dev);
2928 SW (buf+2, host_stat.st_ino);
2929 SW (buf+4, host_stat.st_mode);
2930 SW (buf+6, host_stat.st_nlink);
2931 SW (buf+8, host_stat.st_uid);
2932 SW (buf+10, host_stat.st_gid);
2933 SW (buf+12, host_stat.st_rdev);
2934 SLW (buf+16, host_stat.st_size);
2935 SLW (buf+20, host_stat.st_atime);
2936 SLW (buf+28, host_stat.st_mtime);
2937 SLW (buf+36, host_stat.st_ctime);
2938 }
8918b3a7
MM		 2939 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2940 trace_output (OP_R2);
63a91cfb 2941 break;
63a91cfb 2942
63a91cfb
MM		 2943 case SYS_chown:
2944 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
8918b3a7
MM		 2945 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2946 trace_output (OP_R2);
63a91cfb 2947 break;
8918b3a7 2948
63a91cfb
MM		 2949 case SYS_chmod:
2950 RETVAL = chmod (MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2951 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2952 trace_output (OP_R2);
63a91cfb 2953 break;
8918b3a7 2954
63a91cfb
MM		 2955 case SYS_utime:
2956 /* Cast the second argument to void *, to avoid type mismatch
2957 if a prototype is present. */
2958 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
8918b3a7
MM		 2959 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2960 trace_output (OP_R2);
2961 break;
2962
2963 case SYS_time:
2964 {
2965 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2966 RETVAL_HIGH = ret >> 16;
2967 RETVAL_LOW = ret & 0xffff;
2968 }
2969 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2970 trace_output (OP_R2R3);
63a91cfb 2971 break;
8918b3a7 2972
63a91cfb
MM		 2973 default:
2974 abort ();
2975 }
65c0d7de 2976 RETERR = d10v_callback->get_errno(d10v_callback);
63a91cfb
MM		 2977 break;
2978 }
2979
2980 case 1:
2981 /* Trap 1 prints a string */
2982 {
c422ecc7 2983 char *fstr = dmem_addr(State.regs[2]);
63a91cfb
MM		 2984 fputs (fstr, stdout);
2985 break;
2986 }
2987
2988 case 2:
2989 /* Trap 2 calls printf */
2990 {
c422ecc7 2991 char *fstr = dmem_addr(State.regs[2]);
7eebfc62
MM		 2992 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2993 (int16)State.regs[3],
2994 (int16)State.regs[4],
2995 (int16)State.regs[5]);
63a91cfb
MM		 2996 break;
2997 }
2998
2999 case 3:
3000 /* Trap 3 writes a character */
3001 putchar (State.regs[2]);
3002 break;
19d44375 3003 }
2934d1c9
MH		 3004 }
3005}
3006
3007/* tst0i */
3008void
3009OP_7000000 ()
3010{
87178dbd 3011 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3012 State.F1 = State.F0;
4f425a32 3013 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 3014 trace_output (OP_FLAG);
2934d1c9
MH		 3015}
3016
3017/* tst1i */
3018void
3019OP_F000000 ()
3020{
87178dbd 3021 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3022 State.F1 = State.F0;
4f425a32 3023 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 3024 trace_output (OP_FLAG);
2934d1c9
MH		 3025}
3026
3027/* wait */
3028void
3029OP_5F80 ()
3030{
87178dbd 3031 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 3032 State.IE = 1;
87178dbd 3033 trace_output (OP_VOID);
2934d1c9
MH		 3034}
3035
3036/* xor */
3037void
3038OP_A00 ()
3039{
87178dbd 3040 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 3041 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 3042 trace_output (OP_REG);
2934d1c9
MH		 3043}
3044
3045/* xor3 */
3046void
3047OP_5000000 ()
3048{
87178dbd 3049 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 3050 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 3051 trace_output (OP_REG);
2934d1c9
MH		 3052}
3053
A mirror of the official binutils-gdb repository