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Portability fixes; re-add printf/putchar traps
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
4f425a32 1#include <signal.h>
63a91cfb
MM		 2#include <errno.h>
3#include <sys/types.h>
4#include <sys/stat.h>
5#include <unistd.h>
6
2934d1c9
MH		 7#include "d10v_sim.h"
8#include "simops.h"
63a91cfb 9#include "syscall.h"
2934d1c9
MH		 10
11/* #define DEBUG 1 */
12
13/* abs */
14void
15OP_4607 ()
16{
17#ifdef DEBUG
18 printf(" abs\tr%d\n",OP[0]);
19#endif
20 State.F1 = State.F0;
21 if ((int16)(State.regs[OP[0]]) < 0)
22 {
23 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
24 State.F0 = 1;
25 }
26 else
27 State.F0 = 0;
28}
29
30/* abs */
31void
32OP_5607 ()
33{
34 int64 tmp;
35
36#ifdef DEBUG
37 printf(" abs\ta%d\n",OP[0]);
38#endif
4f425a32
MH		 39 State.F1 = State.F0;
40 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
41
4c38885c 42 if (State.a[OP[0]] < 0 )
2934d1c9 43 {
4c38885c 44 tmp = -State.a[OP[0]];
2934d1c9
MH		 45 if (State.ST)
46 {
4c38885c 47 if (tmp > MAX32)
2934d1c9 48 State.a[OP[0]] = MAX32;
4c38885c 49 else if (tmp < MIN32)
2934d1c9
MH		 50 State.a[OP[0]] = MIN32;
51 else
4f425a32 52 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 53 }
54 else
4f425a32 55 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 56 State.F0 = 1;
57 }
58 else
59 State.F0 = 0;
60}
61
62/* add */
63void
64OP_200 ()
65{
66 uint16 tmp = State.regs[OP[0]];
67#ifdef DEBUG
68 printf(" add\tr%d,r%d\n",OP[0],OP[1]);
69#endif
70 State.regs[OP[0]] += State.regs[OP[1]];
71 if ( tmp > State.regs[OP[0]])
72 State.C = 1;
73 else
74 State.C = 0;
75}
76
77/* add */
78void
79OP_1201 ()
80{
4c38885c 81 int64 tmp;
2934d1c9
MH		 82#ifdef DEBUG
83 printf(" add\ta%d,r%d\n",OP[0],OP[1]);
84#endif
4f425a32 85 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
4c38885c
MH		 86 if (State.ST)
87 {
88 if ( tmp > MAX32)
89 State.a[OP[0]] = MAX32;
90 else if ( tmp < MIN32)
91 State.a[OP[0]] = MIN32;
92 else
4f425a32 93 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 94 }
95 else
4f425a32 96 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 97}
98
99/* add */
100void
101OP_1203 ()
102{
4c38885c 103 int64 tmp;
2934d1c9 104#ifdef DEBUG
4c38885c 105 printf(" add\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 106#endif
4f425a32 107 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
4c38885c
MH		 108 if (State.ST)
109 {
110 if (tmp > MAX32)
111 State.a[OP[0]] = MAX32;
112 else if ( tmp < MIN32)
113 State.a[OP[0]] = MIN32;
114 else
4f425a32 115 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 116 }
117 else
4f425a32 118 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 119}
120
121/* add2w */
122void
123OP_1200 ()
124{
125 uint32 tmp;
126 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
127 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
128#ifdef DEBUG
129 printf(" add2w\tr%d,r%d\n",OP[0],OP[1]);
130#endif
131 tmp = tmp1 + tmp2;
132 if ( (tmp < tmp1) || (tmp < tmp2) )
133 State.C = 1;
134 else
135 State.C = 0;
136 State.regs[OP[0]] = tmp >> 16;
137 State.regs[OP[0]+1] = tmp & 0xFFFF;
138}
139
140/* add3 */
141void
142OP_1000000 ()
143{
144 uint16 tmp = State.regs[OP[0]];
145#ifdef DEBUG
146 printf(" add3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
147#endif
148 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
149 if ( tmp > State.regs[OP[0]])
150 State.C = 1;
151 else
152 State.C = 0;
153}
154
155/* addac3 */
156void
157OP_17000200 ()
158{
4c38885c 159 int64 tmp;
2934d1c9 160#ifdef DEBUG
4c38885c 161 printf(" addac3\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 162#endif
4f425a32 163 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 164 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
165 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 166}
167
168/* addac3 */
169void
170OP_17000202 ()
171{
4c38885c 172 int64 tmp;
2934d1c9 173#ifdef DEBUG
4c38885c 174 printf(" addac3\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 175#endif
4f425a32 176 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 177 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
178 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 179}
180
181/* addac3s */
182void
183OP_17001200 ()
184{
4c38885c 185 int64 tmp;
2934d1c9 186#ifdef DEBUG
4c38885c 187 printf(" addac3s\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 188#endif
4c38885c 189 State.F1 = State.F0;
4f425a32 190 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 191 if ( tmp > MAX32)
192 {
193 State.regs[OP[0]] = 0x7fff;
194 State.regs[OP[0]+1] = 0xffff;
195 State.F0 = 1;
196 }
197 else if (tmp < MIN32)
198 {
199 State.regs[OP[0]] = 0x8000;
200 State.regs[OP[0]+1] = 0;
201 State.F0 = 1;
202 }
203 else
204 {
205 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
206 State.regs[OP[0]+1] = tmp & 0xffff;
207 State.F0 = 0;
208 }
2934d1c9
MH		 209}
210
211/* addac3s */
212void
213OP_17001202 ()
214{
4c38885c 215 int64 tmp;
2934d1c9 216#ifdef DEBUG
4c38885c 217 printf(" addac3s\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 218#endif
4c38885c 219 State.F1 = State.F0;
4f425a32 220 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 221 if ( tmp > MAX32)
222 {
223 State.regs[OP[0]] = 0x7fff;
224 State.regs[OP[0]+1] = 0xffff;
225 State.F0 = 1;
226 }
227 else if (tmp < MIN32)
228 {
229 State.regs[OP[0]] = 0x8000;
230 State.regs[OP[0]+1] = 0;
231 State.F0 = 1;
232 }
233 else
234 {
235 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
236 State.regs[OP[0]+1] = tmp & 0xffff;
237 State.F0 = 0;
238 }
2934d1c9
MH		 239}
240
241/* addi */
242void
243OP_201 ()
244{
4f425a32
MH		 245 if (OP[1] == 0)
246 OP[1] = 16;
2934d1c9
MH		 247#ifdef DEBUG
248 printf(" addi\tr%d,0x%x\n",OP[0],OP[1]);
249#endif
250 State.regs[OP[0]] += OP[1];
251}
252
253/* and */
254void
255OP_C00 ()
256{
257#ifdef DEBUG
258 printf(" and\tr%d,r%d\n",OP[0],OP[1]);
259#endif
260 State.regs[OP[0]] &= State.regs[OP[1]];
261}
262
263/* and3 */
264void
265OP_6000000 ()
266{
267#ifdef DEBUG
268 printf(" and3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
269#endif
270 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
271}
272
273/* bclri */
274void
275OP_C01 ()
276{
277#ifdef DEBUG
278 printf(" bclri\tr%d,%d\n",OP[0],OP[1]);
279#endif
280 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
281}
282
283/* bl.s */
284void
285OP_4900 ()
286{
287#ifdef DEBUG
288 printf(" bl.s\t0x%x\n",OP[0]);
289#endif
290 State.regs[13] = PC+1;
291 PC += SEXT8 (OP[0]);
292}
293
294/* bl.l */
295void
296OP_24800000 ()
297{
298#ifdef DEBUG
299 printf(" bl.l\t0x%x\n",OP[0]);
300#endif
301 State.regs[13] = PC+1;
302 PC += OP[0];
303}
304
305/* bnoti */
306void
307OP_A01 ()
308{
309#ifdef DEBUG
310 printf(" bnoti\tr%d,%d\n",OP[0],OP[1]);
311#endif
312 State.regs[OP[0]] ^= 0x8000 >> OP[1];
313}
314
315/* bra.s */
316void
317OP_4800 ()
318{
319#ifdef DEBUG
320 printf(" bra.s\t0x%x\n",OP[0]);
321#endif
322 PC += SEXT8 (OP[0]);
323}
324
325/* bra.l */
326void
327OP_24000000 ()
328{
329#ifdef DEBUG
330 printf(" bra.l\t0x%x\n",OP[0]);
331#endif
332 PC += OP[0];
333}
334
335/* brf0f.s */
336void
337OP_4A00 ()
338{
339#ifdef DEBUG
340 printf(" brf0f.s\t0x%x\n",OP[0]);
341#endif
342 if (State.F0 == 0)
343 PC += SEXT8 (OP[0]);
344}
345
346/* brf0f.l */
347void
348OP_25000000 ()
349{
350#ifdef DEBUG
351 printf(" brf0f.l\t0x%x\n",OP[0]);
352#endif
353 if (State.F0 == 0)
354 PC += OP[0];
355}
356
357/* brf0t.s */
358void
359OP_4B00 ()
360{
361#ifdef DEBUG
362 printf(" brf0t.s\t0x%x\n",OP[0]);
363#endif
364 if (State.F0)
365 PC += SEXT8 (OP[0]);
366}
367
368/* brf0t.l */
369void
370OP_25800000 ()
371{
372#ifdef DEBUG
373 printf(" brf0t.l\t0x%x\n",OP[0]);
374#endif
375 if (State.F0)
376 PC += OP[0];
377}
378
379/* bseti */
380void
381OP_801 ()
382{
383#ifdef DEBUG
384 printf(" bseti\tr%d,%d\n",OP[0],OP[1]);
385#endif
386 State.regs[OP[0]] |= 0x8000 >> OP[1];
387}
388
389/* btsti */
390void
391OP_E01 ()
392{
393#ifdef DEBUG
394 printf(" btsti\tr%d,%d\n",OP[0],OP[1]);
395#endif
396 State.F1 = State.F0;
397 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
398}
399
400/* clrac */
401void
402OP_5601 ()
403{
404#ifdef DEBUG
405 printf(" clrac\ta%d\n",OP[0]);
406#endif
407 State.a[OP[0]] = 0;
408}
409
410/* cmp */
411void
412OP_600 ()
413{
414#ifdef DEBUG
415 printf(" cmp\tr%d,r%d\n",OP[0],OP[1]);
416#endif
417 State.F1 = State.F0;
418 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
419}
420
421/* cmp */
422void
423OP_1603 ()
424{
425#ifdef DEBUG
4c38885c 426 printf(" cmp\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 427#endif
4c38885c 428 State.F1 = State.F0;
4f425a32 429 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
2934d1c9
MH		 430}
431
432/* cmpeq */
433void
434OP_400 ()
435{
436#ifdef DEBUG
437 printf(" cmpeq\tr%d,r%d\n",OP[0],OP[1]);
438#endif
439 State.F1 = State.F0;
440 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
441}
442
443/* cmpeq */
444void
445OP_1403 ()
446{
447#ifdef DEBUG
4c38885c 448 printf(" cmpeq\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 449#endif
4c38885c
MH		 450 State.F1 = State.F0;
451 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
2934d1c9
MH		 452}
453
454/* cmpeqi.s */
455void
456OP_401 ()
457{
458#ifdef DEBUG
459 printf(" cmpeqi.s\tr%d,0x%x\n",OP[0],OP[1]);
460#endif
461 State.F1 = State.F0;
462 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
463}
464
465/* cmpeqi.l */
466void
467OP_2000000 ()
468{
469#ifdef DEBUG
470 printf(" cmpeqi.l\tr%d,0x%x\n",OP[0],OP[1]);
471#endif
472 State.F1 = State.F0;
473 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
474}
475
476/* cmpi.s */
477void
478OP_601 ()
479{
480#ifdef DEBUG
481 printf(" cmpi.s\tr%d,0x%x\n",OP[0],OP[1]);
482#endif
483 State.F1 = State.F0;
484 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
485}
486
487/* cmpi.l */
488void
489OP_3000000 ()
490{
491#ifdef DEBUG
492 printf(" cmpi.l\tr%d,0x%x\n",OP[0],OP[1]);
493#endif
494 State.F1 = State.F0;
495 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
496}
497
498/* cmpu */
499void
500OP_4600 ()
501{
502#ifdef DEBUG
503 printf(" cmpu\tr%d,r%d\n",OP[0],OP[1]);
504#endif
505 State.F1 = State.F0;
506 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
507}
508
509/* cmpui */
510void
511OP_23000000 ()
512{
513#ifdef DEBUG
514 printf(" cmpui\tr%d,0x%x\n",OP[0],OP[1]);
515#endif
516 State.F1 = State.F0;
517 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
518}
519
520/* cpfg */
521void
522OP_4E09 ()
523{
524 uint8 *src, *dst;
525#ifdef DEBUG
526 printf(" cpfg\t%x,%x\n",OP[0],OP[1]);
527#endif
528
529 if (OP[0] == 0)
530 dst = &State.F0;
531 else
532 dst = &State.F1;
533
534 if (OP[1] == 0)
535 src = &State.F0;
536 else if (OP[1] == 1)
537 src = &State.F1;
538 else
539 src = &State.C;
540
541 *dst = *src;
542}
543
544/* dbt */
545void
546OP_5F20 ()
547{
4f425a32
MH		 548 printf("***** DBT ***** PC=%x\n",PC);
549 State.exception = SIGTRAP;
2934d1c9
MH		 550}
551
552/* divs */
553void
554OP_14002800 ()
555{
556 uint16 foo, tmp, tmpf;
557#ifdef DEBUG
558 printf(" divs\tr%d,r%d\n",OP[0],OP[1]);
559#endif
560 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
561 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
562 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
563 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
564 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
565}
566
567/* exef0f */
568void
569OP_4E04 ()
570{
571#ifdef DEBUG
572 printf(" exef0f\n");
573#endif
574 State.exe = (State.F0) ? 0 : 1;
575}
576
577/* exef0t */
578void
579OP_4E24 ()
580{
581#ifdef DEBUG
582 printf(" exef0t\n");
583#endif
584 State.exe = State.F0;
585}
586
587/* exef1f */
588void
589OP_4E40 ()
590{
591#ifdef DEBUG
592 printf(" exef1f\n");
593#endif
594 State.exe = (State.F1) ? 0 : 1;
595}
596
597/* exef1t */
598void
599OP_4E42 ()
600{
601#ifdef DEBUG
602 printf(" exef1t\n");
603#endif
604 State.exe = State.F1;
605}
606
607/* exefaf */
608void
609OP_4E00 ()
610{
611#ifdef DEBUG
612 printf(" exefaf\n");
613#endif
614 State.exe = (State.F0 | State.F1) ? 0 : 1;
615}
616
617/* exefat */
618void
619OP_4E02 ()
620{
621#ifdef DEBUG
622 printf(" exefat\n");
623#endif
624 State.exe = (State.F0) ? 0 : (State.F1);
625}
626
627/* exetaf */
628void
629OP_4E20 ()
630{
631#ifdef DEBUG
632 printf(" exetaf\n");
633#endif
634 State.exe = (State.F1) ? 0 : (State.F0);
635}
636
637/* exetat */
638void
639OP_4E22 ()
640{
641#ifdef DEBUG
642 printf(" exetat\n");
643#endif
644 State.exe = (State.F0) ? (State.F1) : 0;
645}
646
647/* exp */
648void
649OP_15002A00 ()
650{
651 uint32 tmp, foo;
652 int i;
653
654#ifdef DEBUG
655 printf(" exp\tr%d,r%d\n",OP[0],OP[1]);
656#endif
4c38885c
MH		 657 if (((int16)State.regs[OP[1]]) >= 0)
658 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 659 else
4c38885c 660 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 661
662 foo = 0x40000000;
4c38885c 663 for (i=1;i<17;i++)
2934d1c9
MH		 664 {
665 if (tmp & foo)
666 {
667 State.regs[OP[0]] = i-1;
668 return;
669 }
4c38885c 670 foo >>= 1;
2934d1c9
MH		 671 }
672 State.regs[OP[0]] = 16;
673}
674
675/* exp */
676void
677OP_15002A02 ()
678{
4c38885c
MH		 679 int64 tmp, foo;
680 int i;
2934d1c9 681#ifdef DEBUG
4c38885c 682 printf(" exp\tr%d,a%d\n",OP[0],OP[1]);
2934d1c9 683#endif
4f425a32 684 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 685 tmp = State.a[OP[1]];
686 else
687 tmp = ~(State.a[OP[1]]);
688
689 foo = 0x4000000000LL;
690 for (i=1;i<25;i++)
691 {
692 if (tmp & foo)
693 {
694 State.regs[OP[0]] = i-9;
695 return;
696 }
697 foo >>= 1;
698 }
699 State.regs[OP[0]] = 16;
2934d1c9
MH		 700}
701
702/* jl */
703void
704OP_4D00 ()
705{
706#ifdef DEBUG
707 printf(" jl\t%x\n",OP[0]);
708#endif
709 State.regs[13] = PC+1;
710 PC = State.regs[OP[0]];
711}
712
713/* jmp */
714void
715OP_4C00 ()
716{
717#ifdef DEBUG
718 printf(" jmp\tr%d\n",OP[0]);
719#endif
720 PC = State.regs[OP[0]];
721}
722
723/* ld */
724void
725OP_30000000 ()
726{
727#ifdef DEBUG
728 printf(" ld\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
729#endif
730 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
731}
732
733/* ld */
734void
735OP_6401 ()
736{
737#ifdef DEBUG
738 printf(" ld\tr%d,@r%d-\n",OP[0],OP[1]);
739#endif
4c38885c 740 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 741 INC_ADDR(State.regs[OP[1]],-2);
2934d1c9
MH		 742}
743
744/* ld */
745void
746OP_6001 ()
747{
748#ifdef DEBUG
749 printf(" ld\tr%d,@r%d+\n",OP[0],OP[1]);
750#endif
4c38885c 751 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 752 INC_ADDR(State.regs[OP[1]],2);
2934d1c9
MH		 753}
754
755/* ld */
756void
757OP_6000 ()
758{
759#ifdef DEBUG
760 printf(" ld\tr%d,@r%d\n",OP[0],OP[1]);
761#endif
762 State.regs[OP[0]] = RW (State.regs[OP[1]]);
763}
764
765/* ld2w */
766void
767OP_31000000 ()
768{
769#ifdef DEBUG
770 printf(" ld2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
771#endif
772 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
773 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
774}
775
776/* ld2w */
777void
778OP_6601 ()
779{
780#ifdef DEBUG
781 printf(" ld2w\tr%d,@r%d-\n",OP[0],OP[1]);
782#endif
4c38885c
MH		 783 State.regs[OP[0]] = RW (State.regs[OP[1]]);
784 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 785 INC_ADDR(State.regs[OP[1]],-4);
2934d1c9
MH		 786}
787
788/* ld2w */
789void
790OP_6201 ()
791{
792#ifdef DEBUG
793 printf(" ld2w\tr%d,@r%d+\n",OP[0],OP[1]);
794#endif
4c38885c
MH		 795 State.regs[OP[0]] = RW (State.regs[OP[1]]);
796 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 797 INC_ADDR(State.regs[OP[1]],4);
2934d1c9
MH		 798}
799
800/* ld2w */
801void
802OP_6200 ()
803{
804#ifdef DEBUG
805 printf(" ld2w\tr%d,@r%d\n",OP[0],OP[1]);
806#endif
4c38885c
MH		 807 State.regs[OP[0]] = RW (State.regs[OP[1]]);
808 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
2934d1c9
MH		 809}
810
811/* ldb */
812void
813OP_38000000 ()
814{
815#ifdef DEBUG
816 printf(" ldb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
817#endif
818 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
819 SEXT8 (State.regs[OP[0]]);
820}
821
822/* ldb */
823void
824OP_7000 ()
825{
826#ifdef DEBUG
827 printf(" ldb\tr%d,@r%d\n",OP[0],OP[1]);
828#endif
829 State.regs[OP[0]] = RB (State.regs[OP[1]]);
830 SEXT8 (State.regs[OP[0]]);
831}
832
833/* ldi.s */
834void
835OP_4001 ()
836{
837#ifdef DEBUG
838 printf(" ldi.s\tr%d,%x\n",OP[0],SEXT4(OP[1]));
839#endif
840 State.regs[OP[0]] = SEXT4(OP[1]);
841}
842
843/* ldi.l */
844void
845OP_20000000 ()
846{
847#ifdef DEBUG
848 printf(" ldi.l\tr%d,%d\t;0x%x\n",OP[0],OP[1],OP[1]);
849#endif
850 State.regs[OP[0]] = OP[1];
851}
852
853/* ldub */
854void
855OP_39000000 ()
856{
857#ifdef DEBUG
858 printf(" ldub\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
859#endif
860 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
861}
862
863/* ldub */
864void
865OP_7200 ()
866{
867#ifdef DEBUG
868 printf(" ldub\tr%d,@r%d\n",OP[0],OP[1]);
869#endif
870 State.regs[OP[0]] = RB (State.regs[OP[1]]);
871}
872
873/* mac */
874void
875OP_2A00 ()
876{
4c38885c 877 int64 tmp;
2934d1c9 878#ifdef DEBUG
4c38885c 879 printf(" mac\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 880#endif
4f425a32 881 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 882
883 if (State.FX)
4f425a32 884 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 885
886 if (State.ST && tmp > MAX32)
887 tmp = MAX32;
888
4f425a32 889 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 890 if (State.ST)
891 {
892 if (tmp > MAX32)
893 State.a[OP[0]] = MAX32;
894 else if (tmp < MIN32)
895 State.a[OP[0]] = MIN32;
896 else
4f425a32 897 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 898 }
899 else
4f425a32 900 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 901}
902
903/* macsu */
904void
905OP_1A00 ()
906{
4f425a32 907 int64 tmp;
2934d1c9 908#ifdef DEBUG
4f425a32 909 printf(" macsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 910#endif
4f425a32
MH		 911 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
912 if (State.FX)
913 tmp = SEXT40( (tmp << 1) & MASK40);
914
915 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
2934d1c9
MH		 916}
917
918/* macu */
919void
920OP_3A00 ()
921{
4f425a32 922 int64 tmp;
2934d1c9 923#ifdef DEBUG
4f425a32 924 printf(" macu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 925#endif
4f425a32
MH		 926 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
927 if (State.FX)
928 tmp = SEXT40( (tmp << 1) & MASK40);
929 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
2934d1c9
MH		 930}
931
932/* max */
933void
934OP_2600 ()
935{
936#ifdef DEBUG
937 printf(" max\tr%d,r%d\n",OP[0],OP[1]);
938#endif
939 State.F1 = State.F0;
940 if (State.regs[OP[1]] > State.regs[OP[0]])
941 {
942 State.regs[OP[0]] = State.regs[OP[1]];
943 State.F0 = 1;
944 }
945 else
946 State.F0 = 0;
947}
948
949/* max */
950void
951OP_3600 ()
952{
4f425a32 953 int64 tmp;
2934d1c9 954#ifdef DEBUG
4f425a32 955 printf(" max\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 956#endif
4f425a32
MH		 957 State.F1 = State.F0;
958 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
959 if (tmp > SEXT40(State.a[OP[0]]))
960 {
961 State.a[OP[0]] = tmp & MASK40;
962 State.F0 = 1;
963 }
964 else
965 State.F0 = 0;
2934d1c9
MH		 966}
967
968/* max */
969void
970OP_3602 ()
971{
972#ifdef DEBUG
4f425a32 973 printf(" max\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 974#endif
4f425a32
MH		 975 State.F1 = State.F0;
976 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
977 {
978 State.a[OP[0]] = State.a[OP[1]];
979 State.F0 = 1;
980 }
981 else
982 State.F0 = 0;
2934d1c9
MH		 983}
984
4f425a32 985
2934d1c9
MH		 986/* min */
987void
988OP_2601 ()
989{
990#ifdef DEBUG
991 printf(" min\tr%d,r%d\n",OP[0],OP[1]);
992#endif
993 State.F1 = State.F0;
994 if (State.regs[OP[1]] < State.regs[OP[0]])
995 {
996 State.regs[OP[0]] = State.regs[OP[1]];
997 State.F0 = 1;
998 }
999 else
1000 State.F0 = 0;
1001}
1002
1003/* min */
1004void
1005OP_3601 ()
1006{
4f425a32 1007 int64 tmp;
2934d1c9 1008#ifdef DEBUG
4f425a32 1009 printf(" min\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 1010#endif
4f425a32
MH		 1011 State.F1 = State.F0;
1012 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1013 if (tmp < SEXT40(State.a[OP[0]]))
1014 {
1015 State.a[OP[0]] = tmp & MASK40;
1016 State.F0 = 1;
1017 }
1018 else
1019 State.F0 = 0;
2934d1c9
MH		 1020}
1021
1022/* min */
1023void
1024OP_3603 ()
1025{
1026#ifdef DEBUG
4f425a32 1027 printf(" min\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 1028#endif
4f425a32
MH		 1029 State.F1 = State.F0;
1030 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1031 {
1032 State.a[OP[0]] = State.a[OP[1]];
1033 State.F0 = 1;
1034 }
1035 else
1036 State.F0 = 0;
2934d1c9
MH		 1037}
1038
1039/* msb */
1040void
1041OP_2800 ()
1042{
4f425a32 1043 int64 tmp;
2934d1c9 1044#ifdef DEBUG
4f425a32 1045 printf(" msb\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1046#endif
4f425a32
MH		 1047 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1048
1049 if (State.FX)
1050 tmp = SEXT40 ((tmp << 1) & MASK40);
1051
1052 if (State.ST && tmp > MAX32)
1053 tmp = MAX32;
1054
1055 tmp = SEXT40(State.a[OP[0]]) - tmp;
1056 if (State.ST)
1057 {
1058 if (tmp > MAX32)
1059 State.a[OP[0]] = MAX32;
1060 else if (tmp < MIN32)
1061 State.a[OP[0]] = MIN32;
1062 else
1063 State.a[OP[0]] = tmp & MASK40;
1064 }
1065 else
1066 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1067}
1068
1069/* msbsu */
1070void
1071OP_1800 ()
1072{
4f425a32 1073 int64 tmp;
2934d1c9 1074#ifdef DEBUG
4f425a32 1075 printf(" msbsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1076#endif
4f425a32
MH		 1077 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1078 if (State.FX)
1079 tmp = SEXT40( (tmp << 1) & MASK40);
1080
1081 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
2934d1c9
MH		 1082}
1083
1084/* msbu */
1085void
1086OP_3800 ()
1087{
4f425a32 1088 int64 tmp;
2934d1c9 1089#ifdef DEBUG
4f425a32 1090 printf(" msbu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1091#endif
4f425a32
MH		 1092 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1093 if (State.FX)
1094 tmp = SEXT40( (tmp << 1) & MASK40);
1095
1096 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
2934d1c9
MH		 1097}
1098
1099/* mul */
1100void
1101OP_2E00 ()
1102{
1103#ifdef DEBUG
1104 printf(" mul\tr%d,r%d\n",OP[0],OP[1]);
1105#endif
1106 State.regs[OP[0]] *= State.regs[OP[1]];
1107}
1108
1109/* mulx */
1110void
1111OP_2C00 ()
1112{
4f425a32 1113 int64 tmp;
2934d1c9 1114#ifdef DEBUG
4f425a32 1115 printf(" mulx\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1116#endif
4f425a32
MH		 1117 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1118
1119 if (State.FX)
1120 tmp = SEXT40 ((tmp << 1) & MASK40);
1121
1122 if (State.ST && tmp > MAX32)
1123 State.a[OP[0]] = MAX32;
1124 else
1125 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1126}
1127
1128/* mulxsu */
1129void
1130OP_1C00 ()
1131{
4f425a32 1132 int64 tmp;
2934d1c9 1133#ifdef DEBUG
4f425a32 1134 printf(" mulxsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1135#endif
4f425a32
MH		 1136 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1137
1138 if (State.FX)
1139 tmp <<= 1;
1140
1141 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1142}
1143
1144/* mulxu */
1145void
1146OP_3C00 ()
1147{
4f425a32 1148 int64 tmp;
2934d1c9 1149#ifdef DEBUG
4f425a32 1150 printf(" mulxu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1151#endif
4f425a32
MH		 1152 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1153
1154 if (State.FX)
1155 tmp <<= 1;
1156
1157 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1158}
1159
1160/* mv */
1161void
1162OP_4000 ()
1163{
1164#ifdef DEBUG
1165 printf(" mv\tr%d,r%d\n",OP[0],OP[1]);
1166#endif
1167 State.regs[OP[0]] = State.regs[OP[1]];
1168}
1169
1170/* mv2w */
1171void
1172OP_5000 ()
1173{
1174#ifdef DEBUG
1175 printf(" mv2w\tr%d,r%d\n",OP[0],OP[1]);
1176#endif
1177 State.regs[OP[0]] = State.regs[OP[1]];
1178 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1179}
1180
1181/* mv2wfac */
1182void
1183OP_3E00 ()
1184{
1185#ifdef DEBUG
1186 printf(" mv2wfac\tr%d,a%d\n",OP[0],OP[1]);
1187#endif
1188 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1189 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1190}
1191
1192/* mv2wtac */
1193void
1194OP_3E01 ()
1195{
1196#ifdef DEBUG
1197 printf(" mv2wtac\tr%d,a%d\n",OP[0],OP[1]);
1198#endif
4f425a32 1199 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
2934d1c9
MH		 1200}
1201
1202/* mvac */
1203void
1204OP_3E03 ()
1205{
1206#ifdef DEBUG
1207 printf(" mvac\ta%d,a%d\n",OP[0],OP[1]);
1208#endif
1209 State.a[OP[0]] = State.a[OP[1]];
1210}
1211
1212/* mvb */
1213void
1214OP_5400 ()
1215{
1216#ifdef DEBUG
1217 printf(" mvb\tr%d,r%d\n",OP[0],OP[1]);
1218#endif
1219 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1220}
1221
1222/* mvf0f */
1223void
1224OP_4400 ()
1225{
1226#ifdef DEBUG
1227 printf(" mvf0f\tr%d,r%d\n",OP[0],OP[1]);
1228#endif
1229 if (State.F0 == 0)
1230 State.regs[OP[0]] = State.regs[OP[1]];
1231}
1232
1233/* mvf0t */
1234void
1235OP_4401 ()
1236{
1237#ifdef DEBUG
1238 printf(" mvf0t\tr%d,r%d\n",OP[0],OP[1]);
1239#endif
1240 if (State.F0)
1241 State.regs[OP[0]] = State.regs[OP[1]];
1242}
1243
1244/* mvfacg */
1245void
1246OP_1E04 ()
1247{
1248#ifdef DEBUG
1249 printf(" mvfacg\tr%d,a%d\n",OP[0],OP[1]);
1250#endif
1251 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1252}
1253
1254/* mvfachi */
1255void
1256OP_1E00 ()
1257{
1258#ifdef DEBUG
1259 printf(" mvfachi\tr%d,a%d\n",OP[0],OP[1]);
1260#endif
1261 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1262}
1263
1264/* mvfaclo */
1265void
1266OP_1E02 ()
1267{
1268#ifdef DEBUG
1269 printf(" mvfaclo\tr%d,a%d\n",OP[0],OP[1]);
1270#endif
1271 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1272}
1273
1274/* mvfc */
1275void
1276OP_5200 ()
1277{
1278#ifdef DEBUG
1279 printf(" mvfc\tr%d,cr%d\n",OP[0],OP[1]);
1280#endif
1281 if (OP[1] == 0)
1282 {
1283 /* PSW is treated specially */
1284 PSW = 0;
1285 if (State.SM) PSW |= 0x8000;
1286 if (State.EA) PSW |= 0x2000;
1287 if (State.DB) PSW |= 0x1000;
1288 if (State.IE) PSW |= 0x400;
1289 if (State.RP) PSW |= 0x200;
1290 if (State.MD) PSW |= 0x100;
1291 if (State.FX) PSW |= 0x80;
1292 if (State.ST) PSW |= 0x40;
1293 if (State.F0) PSW |= 8;
1294 if (State.F1) PSW |= 4;
1295 if (State.C) PSW |= 1;
1296 }
1297 State.regs[OP[0]] = State.cregs[OP[1]];
1298}
1299
1300/* mvtacg */
1301void
1302OP_1E41 ()
1303{
1304#ifdef DEBUG
1305 printf(" mvtacg\tr%d,a%d\n",OP[0],OP[1]);
1306#endif
1307 State.a[OP[1]] &= MASK32;
1308 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1309}
1310
1311/* mvtachi */
1312void
1313OP_1E01 ()
1314{
1315 uint16 tmp;
1316#ifdef DEBUG
1317 printf(" mvtachi\tr%d,a%d\n",OP[0],OP[1]);
1318#endif
1319 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1320 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
2934d1c9
MH		 1321}
1322
1323/* mvtaclo */
1324void
1325OP_1E21 ()
1326{
1327#ifdef DEBUG
1328 printf(" mvtaclo\tr%d,a%d\n",OP[0],OP[1]);
1329#endif
4f425a32 1330 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
2934d1c9
MH		 1331}
1332
1333/* mvtc */
1334void
1335OP_5600 ()
1336{
1337#ifdef DEBUG
1338 printf(" mvtc\tr%d,cr%d\n",OP[0],OP[1]);
1339#endif
1340 State.cregs[OP[1]] = State.regs[OP[0]];
1341 if (OP[1] == 0)
1342 {
1343 /* PSW is treated specially */
1344 State.SM = (PSW & 0x8000) ? 1 : 0;
1345 State.EA = (PSW & 0x2000) ? 1 : 0;
1346 State.DB = (PSW & 0x1000) ? 1 : 0;
1347 State.IE = (PSW & 0x400) ? 1 : 0;
1348 State.RP = (PSW & 0x200) ? 1 : 0;
1349 State.MD = (PSW & 0x100) ? 1 : 0;
1350 State.FX = (PSW & 0x80) ? 1 : 0;
1351 State.ST = (PSW & 0x40) ? 1 : 0;
1352 State.F0 = (PSW & 8) ? 1 : 0;
1353 State.F1 = (PSW & 4) ? 1 : 0;
1354 State.C = PSW & 1;
1355 if (State.ST && !State.FX)
1356 {
1357 fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
4f425a32 1358 State.exception = SIGILL;
2934d1c9
MH		 1359 }
1360 }
1361}
1362
1363/* mvub */
1364void
1365OP_5401 ()
1366{
1367#ifdef DEBUG
1368 printf(" mvub\tr%d,r%d\n",OP[0],OP[1]);
1369#endif
1370 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1371}
1372
1373/* neg */
1374void
1375OP_4605 ()
1376{
1377#ifdef DEBUG
1378 printf(" neg\tr%d\n",OP[0]);
1379#endif
1380 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1381}
1382
1383/* neg */
1384void
1385OP_5605 ()
1386{
1387 int64 tmp;
1388#ifdef DEBUG
1389 printf(" neg\ta%d\n",OP[0]);
1390#endif
4f425a32 1391 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1392 if (State.ST)
1393 {
4c38885c 1394 if ( tmp > MAX32)
2934d1c9 1395 State.a[OP[0]] = MAX32;
4c38885c 1396 else if (tmp < MIN32)
2934d1c9
MH		 1397 State.a[OP[0]] = MIN32;
1398 else
4f425a32 1399 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1400 }
1401 else
4f425a32 1402 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1403}
1404
1405
1406/* nop */
1407void
1408OP_5E00 ()
1409{
1410}
1411
1412/* not */
1413void
1414OP_4603 ()
1415{
1416#ifdef DEBUG
1417 printf(" not\tr%d\n",OP[0]);
1418#endif
1419 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1420}
1421
1422/* or */
1423void
1424OP_800 ()
1425{
1426#ifdef DEBUG
1427 printf(" or\tr%d,r%d\n",OP[0],OP[1]);
1428#endif
1429 State.regs[OP[0]] |= State.regs[OP[1]];
1430}
1431
1432/* or3 */
1433void
1434OP_4000000 ()
1435{
1436#ifdef DEBUG
1437 printf(" or3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
1438#endif
1439 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1440}
1441
1442/* rac */
1443void
1444OP_5201 ()
1445{
1446 int64 tmp;
1447 int shift = SEXT3 (OP[2]);
1448#ifdef DEBUG
1449 printf(" rac\tr%d,a%d,%d\n",OP[0],OP[1],shift);
1450#endif
166acb9f
MH		 1451 if (OP[1] != 0)
1452 {
1453 fprintf (stderr,"ERROR at PC 0x%x: instruction only valid for A0\n",PC<<2);
1454 State.exception = SIGILL;
1455 }
1456
2934d1c9
MH		 1457 State.F1 = State.F0;
1458 if (shift >=0)
1459 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1460 else
1461 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1462 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1463 if (tmp > MAX32)
2934d1c9
MH		 1464 {
1465 State.regs[OP[0]] = 0x7fff;
1466 State.regs[OP[0]+1] = 0xffff;
1467 State.F0 = 1;
1468 }
4c38885c 1469 else if (tmp < MIN32)
2934d1c9
MH		 1470 {
1471 State.regs[OP[0]] = 0x8000;
1472 State.regs[OP[0]+1] = 0;
1473 State.F0 = 1;
1474 }
1475 else
1476 {
1477 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1478 State.regs[OP[0]+1] = tmp & 0xffff;
1479 State.F0 = 0;
1480 }
1481}
1482
1483/* rachi */
1484void
1485OP_4201 ()
1486{
4c38885c
MH		 1487 int64 tmp;
1488 int shift = SEXT3 (OP[2]);
2934d1c9 1489#ifdef DEBUG
4c38885c 1490 printf(" rachi\tr%d,a%d,%d\n",OP[0],OP[1],shift);
2934d1c9 1491#endif
4c38885c
MH		 1492 State.F1 = State.F0;
1493 if (shift >=0)
166acb9f 1494 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1495 else
166acb9f 1496 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1497 tmp += 0x8000;
63a91cfb 1498
4c38885c
MH		 1499 if (tmp > MAX32)
1500 {
1501 State.regs[OP[0]] = 0x7fff;
1502 State.F0 = 1;
1503 }
1504 else if (tmp < 0xfff80000000LL)
1505 {
1506 State.regs[OP[0]] = 0x8000;
1507 State.F0 = 1;
1508 }
1509 else
1510 {
1511 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1512 State.F0 = 0;
1513 }
2934d1c9
MH		 1514}
1515
1516/* rep */
1517void
1518OP_27000000 ()
1519{
1520#ifdef DEBUG
1521 printf(" rep\tr%d,0x%x\n",OP[0],OP[1]);
1522#endif
1523 RPT_S = PC + 1;
1524 RPT_E = PC + OP[1];
1525 RPT_C = State.regs[OP[0]];
1526 State.RP = 1;
1527 if (RPT_C == 0)
1528 {
1529 fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1530 State.exception = SIGILL;
2934d1c9 1531 }
4c38885c
MH		 1532 if (OP[1] < 4)
1533 {
1534 fprintf (stderr, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1535 State.exception = SIGILL;
4c38885c 1536 }
2934d1c9
MH		 1537}
1538
1539/* repi */
1540void
1541OP_2F000000 ()
1542{
1543#ifdef DEBUG
1544 printf(" repi\t%d,0x%x\n",OP[0],OP[1]);
1545#endif
1546 RPT_S = PC + 1;
1547 RPT_E = PC + OP[1];
1548 RPT_C = OP[0];
1549 State.RP = 1;
1550 if (RPT_C == 0)
1551 {
4c38885c 1552 fprintf (stderr, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1553 State.exception = SIGILL;
4c38885c
MH		 1554 }
1555 if (OP[1] < 4)
1556 {
1557 fprintf (stderr, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 1558 State.exception = SIGILL;
2934d1c9
MH		 1559 }
1560}
1561
1562/* rtd */
1563void
1564OP_5F60 ()
1565{
4c38885c 1566 printf(" rtd - NOT IMPLEMENTED\n");
2934d1c9
MH		 1567}
1568
1569/* rte */
1570void
1571OP_5F40 ()
1572{
1573#ifdef DEBUG
4c38885c 1574 printf(" rte\n");
2934d1c9 1575#endif
4c38885c
MH		 1576 PC = BPC;
1577 PSW = BPSW;
2934d1c9
MH		 1578}
1579
1580/* sadd */
1581void
1582OP_1223 ()
1583{
4c38885c 1584 int64 tmp;
2934d1c9 1585#ifdef DEBUG
4c38885c 1586 printf(" sadd\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 1587#endif
4f425a32 1588 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 1589 if (State.ST)
1590 {
1591 if (tmp > MAX32)
1592 State.a[OP[0]] = MAX32;
1593 else if (tmp < MIN32)
1594 State.a[OP[0]] = MIN32;
1595 else
4f425a32 1596 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1597 }
1598 else
4f425a32 1599 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1600}
1601
1602/* setf0f */
1603void
1604OP_4611 ()
1605{
1606#ifdef DEBUG
4c38885c 1607 printf(" setf0f\tr%d\n",OP[0]);
2934d1c9 1608#endif
4c38885c 1609 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2934d1c9
MH		 1610}
1611
1612/* setf0t */
1613void
1614OP_4613 ()
1615{
1616#ifdef DEBUG
4c38885c 1617 printf(" setf0t\tr%d\n",OP[0]);
2934d1c9 1618#endif
4c38885c 1619 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2934d1c9
MH		 1620}
1621
1622/* sleep */
1623void
1624OP_5FC0 ()
1625{
1626#ifdef DEBUG
4c38885c 1627 printf(" sleep\n");
2934d1c9 1628#endif
4c38885c 1629 State.IE = 1;
2934d1c9
MH		 1630}
1631
1632/* sll */
1633void
1634OP_2200 ()
1635{
1636#ifdef DEBUG
1637 printf(" sll\tr%d,r%d\n",OP[0],OP[1]);
1638#endif
1639 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1640}
1641
1642/* sll */
1643void
1644OP_3200 ()
1645{
4c38885c 1646 int64 tmp;
2934d1c9 1647#ifdef DEBUG
4c38885c 1648 printf(" sll\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 1649#endif
4c38885c
MH		 1650 if (State.regs[OP[1]] & 31 <= 16)
1651 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1652
1653 if (State.ST)
1654 {
1655 if (tmp > MAX32)
1656 State.a[OP[0]] = MAX32;
1657 else if (tmp < 0xffffff80000000LL)
1658 State.a[OP[0]] = MIN32;
1659 else
1660 State.a[OP[0]] = tmp & MASK40;
1661 }
1662 else
1663 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1664}
1665
1666/* slli */
1667void
1668OP_2201 ()
1669{
1670#ifdef DEBUG
1671 printf(" slli\tr%d,%d\n",OP[0],OP[1]);
1672#endif
1673 State.regs[OP[0]] <<= OP[1];
1674}
1675
1676/* slli */
1677void
1678OP_3201 ()
1679{
4c38885c 1680 int64 tmp;
4f425a32
MH		 1681
1682 if (OP[1] == 0)
1683 OP[1] = 16;
2934d1c9 1684#ifdef DEBUG
4c38885c 1685 printf(" slli\ta%d,%d\n",OP[0],OP[1]);
2934d1c9 1686#endif
4f425a32
MH		 1687
1688 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 1689
1690 if (State.ST)
1691 {
1692 if (tmp > MAX32)
1693 State.a[OP[0]] = MAX32;
1694 else if (tmp < 0xffffff80000000LL)
1695 State.a[OP[0]] = MIN32;
1696 else
1697 State.a[OP[0]] = tmp & MASK40;
1698 }
1699 else
1700 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1701}
1702
1703/* slx */
1704void
1705OP_460B ()
1706{
1707 uint16 tmp;
1708#ifdef DEBUG
1709 printf(" slx\tr%d\n",OP[0]);
1710#endif
1711 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1712}
1713
1714/* sra */
1715void
1716OP_2400 ()
1717{
1718#ifdef DEBUG
1719 printf(" sra\tr%d,r%d\n",OP[0],OP[1]);
1720#endif
1721 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
1722}
1723
1724/* sra */
1725void
1726OP_3400 ()
1727{
1728#ifdef DEBUG
4c38885c 1729 printf(" sra\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 1730#endif
4c38885c
MH		 1731 if (State.regs[OP[1]] & 31 <= 16)
1732 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2934d1c9
MH		 1733}
1734
1735/* srai */
1736void
1737OP_2401 ()
1738{
1739#ifdef DEBUG
1740 printf(" srai\tr%d,%d\n",OP[0],OP[1]);
1741#endif
1742 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
1743}
1744
1745/* srai */
1746void
1747OP_3401 ()
1748{
4f425a32
MH		 1749 if (OP[1] == 0)
1750 OP[1] = 16;
2934d1c9 1751#ifdef DEBUG
4c38885c 1752 printf(" srai\ta%d,%d\n",OP[0],OP[1]);
2934d1c9 1753#endif
4c38885c 1754 State.a[OP[0]] >>= OP[1];
2934d1c9
MH		 1755}
1756
1757/* srl */
1758void
1759OP_2000 ()
1760{
1761#ifdef DEBUG
1762 printf(" srl\tr%d,r%d\n",OP[0],OP[1]);
1763#endif
1764 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
1765}
1766
1767/* srl */
1768void
1769OP_3000 ()
1770{
1771#ifdef DEBUG
4c38885c 1772 printf(" srl\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 1773#endif
4c38885c
MH		 1774 if (State.regs[OP[1]] & 31 <= 16)
1775 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2934d1c9
MH		 1776}
1777
1778/* srli */
1779void
1780OP_2001 ()
1781{
1782#ifdef DEBUG
1783printf(" srli\tr%d,%d\n",OP[0],OP[1]);
1784#endif
1785 State.regs[OP[0]] >>= OP[1];
1786}
1787
1788/* srli */
1789void
1790OP_3001 ()
1791{
4f425a32
MH		 1792 if (OP[1] == 0)
1793 OP[1] = 16;
2934d1c9 1794#ifdef DEBUG
4c38885c 1795 printf(" srli\ta%d,%d\n",OP[0],OP[1]);
2934d1c9 1796#endif
4c38885c 1797 State.a[OP[0]] >>= OP[1];
2934d1c9
MH		 1798}
1799
1800/* srx */
1801void
1802OP_4609 ()
1803{
1804 uint16 tmp;
1805#ifdef DEBUG
1806 printf(" srx\tr%d\n",OP[0]);
1807#endif
1808 tmp = State.F0 << 15;
1809 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
1810}
1811
1812/* st */
1813void
1814OP_34000000 ()
1815{
1816#ifdef DEBUG
1817 printf(" st\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1818#endif
1819 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
1820}
1821
1822/* st */
1823void
1824OP_6800 ()
1825{
1826#ifdef DEBUG
1827 printf(" st\tr%d,@r%d\n",OP[0],OP[1]);
1828#endif
1829 SW (State.regs[OP[1]], State.regs[OP[0]]);
1830}
1831
1832/* st */
1833void
1834OP_6C1F ()
1835{
1836#ifdef DEBUG
4c38885c 1837 printf(" st\tr%d,@-r%d\n",OP[0],OP[1]);
2934d1c9 1838#endif
4c38885c
MH		 1839 if ( OP[1] != 15 )
1840 {
1841 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 1842 State.exception = SIGILL;
1843 return;
4c38885c
MH		 1844 }
1845 State.regs[OP[1]] -= 2;
1846 SW (State.regs[OP[1]], State.regs[OP[0]]);
2934d1c9
MH		 1847}
1848
1849/* st */
1850void
1851OP_6801 ()
1852{
1853#ifdef DEBUG
4c38885c 1854 printf(" st\tr%d,@r%d+\n",OP[0],OP[1]);
2934d1c9 1855#endif
4c38885c 1856 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 1857 INC_ADDR (State.regs[OP[1]],2);
2934d1c9
MH		 1858}
1859
1860/* st */
1861void
1862OP_6C01 ()
1863{
1864#ifdef DEBUG
4c38885c 1865 printf(" st\tr%d,@r%d-\n",OP[0],OP[1]);
2934d1c9 1866#endif
4c38885c 1867 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 1868 INC_ADDR (State.regs[OP[1]],-2);
2934d1c9
MH		 1869}
1870
1871/* st2w */
1872void
1873OP_35000000 ()
1874{
1875#ifdef DEBUG
4c38885c 1876 printf(" st2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
2934d1c9 1877#endif
4f425a32
MH		 1878 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
1879 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2934d1c9
MH		 1880}
1881
1882/* st2w */
1883void
1884OP_6A00 ()
1885{
1886#ifdef DEBUG
4c38885c 1887 printf(" st2w\tr%d,@r%d\n",OP[0],OP[1]);
2934d1c9 1888#endif
4c38885c
MH		 1889 SW (State.regs[OP[1]], State.regs[OP[0]]);
1890 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2934d1c9
MH		 1891}
1892
1893/* st2w */
1894void
1895OP_6E1F ()
1896{
1897#ifdef DEBUG
4c38885c 1898 printf(" st2w\tr%d,@-r%d\n",OP[0],OP[1]);
2934d1c9 1899#endif
4c38885c
MH		 1900 if ( OP[1] != 15 )
1901 {
1902 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 1903 State.exception = SIGILL;
1904 return;
4c38885c
MH		 1905 }
1906 State.regs[OP[1]] -= 4;
1907 SW (State.regs[OP[1]], State.regs[OP[0]]);
1908 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2934d1c9
MH		 1909}
1910
1911/* st2w */
1912void
1913OP_6A01 ()
1914{
1915#ifdef DEBUG
4c38885c 1916 printf(" st2w\tr%d,r%d+\n",OP[0],OP[1]);
2934d1c9 1917#endif
4c38885c
MH		 1918 SW (State.regs[OP[1]], State.regs[OP[0]]);
1919 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 1920 INC_ADDR (State.regs[OP[1]],4);
2934d1c9
MH		 1921}
1922
1923/* st2w */
1924void
1925OP_6E01 ()
1926{
1927#ifdef DEBUG
4c38885c 1928 printf(" st2w\tr%d,r%d-\n",OP[0],OP[1]);
2934d1c9 1929#endif
4c38885c
MH		 1930 SW (State.regs[OP[1]], State.regs[OP[0]]);
1931 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 1932 INC_ADDR (State.regs[OP[1]],-4);
2934d1c9
MH		 1933}
1934
1935/* stb */
1936void
1937OP_3C000000 ()
1938{
1939#ifdef DEBUG
4c38885c 1940 printf(" stb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
2934d1c9 1941#endif
4f425a32 1942 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2934d1c9
MH		 1943}
1944
1945/* stb */
1946void
1947OP_7800 ()
1948{
1949#ifdef DEBUG
4c38885c 1950 printf(" stb\tr%d,@r%d\n",OP[0],OP[1]);
2934d1c9 1951#endif
4c38885c 1952 SB (State.regs[OP[1]], State.regs[OP[0]]);
2934d1c9
MH		 1953}
1954
1955/* stop */
1956void
1957OP_5FE0 ()
1958{
1959#ifdef DEBUG
1960 printf(" stop\n");
1961#endif
4f425a32 1962 State.exception = SIGQUIT;
2934d1c9
MH		 1963}
1964
1965/* sub */
1966void
1967OP_0 ()
4c38885c
MH		 1968{
1969 int32 tmp;
1970#ifdef DEBUG
1971 printf(" sub\tr%d,r%d\n",OP[0],OP[1]);
1972#endif
1973 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
1974 State.C = (tmp & 0xffff0000) ? 1 : 0;
1975 State.regs[OP[0]] = tmp & 0xffff;
1976}
1977
1978/* sub */
1979void
1980OP_1001 ()
1981{
4f425a32 1982 int64 tmp;
4c38885c
MH		 1983#ifdef DEBUG
1984 printf(" sub\ta%d,r%d\n",OP[0],OP[1]);
1985#endif
4f425a32
MH		 1986 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
1987 if (State.ST)
1988 {
1989 if ( tmp > MAX32)
1990 State.a[OP[0]] = MAX32;
1991 else if ( tmp < MIN32)
1992 State.a[OP[0]] = MIN32;
1993 else
1994 State.a[OP[0]] = tmp & MASK40;
1995 }
1996 else
1997 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1998}
1999
2000/* sub */
2001
2002void
2003OP_1003 ()
2934d1c9 2004{
4f425a32 2005 int64 tmp;
2934d1c9 2006#ifdef DEBUG
4c38885c 2007 printf(" sub\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 2008#endif
4f425a32
MH		 2009 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2010 if (State.ST)
2011 {
2012 if (tmp > MAX32)
2013 State.a[OP[0]] = MAX32;
2014 else if ( tmp < MIN32)
2015 State.a[OP[0]] = MIN32;
2016 else
2017 State.a[OP[0]] = tmp & MASK40;
2018 }
2019 else
2020 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 2021}
2022
2023/* sub2w */
2024void
2025OP_1000 ()
2026{
4c38885c
MH		 2027 int64 tmp;
2028 int32 a,b;
2934d1c9 2029#ifdef DEBUG
4c38885c 2030 printf(" sub2w\tr%d,r%d\n",OP[0],OP[1]);
2934d1c9 2031#endif
4c38885c
MH		 2032
2033 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2034 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2035 tmp = a-b;
2036 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2037 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2038 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 2039}
2040
2041/* subac3 */
2042void
2043OP_17000000 ()
2044{
4f425a32 2045 int64 tmp;
2934d1c9 2046#ifdef DEBUG
4f425a32 2047 printf(" subac3\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 2048#endif
4f425a32
MH		 2049 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2050 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2051 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 2052}
2053
2054/* subac3 */
2055void
2056OP_17000002 ()
2057{
4f425a32 2058 int64 tmp;
2934d1c9 2059#ifdef DEBUG
4f425a32 2060 printf(" subac3\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 2061#endif
4f425a32
MH		 2062 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2063 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2064 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 2065}
2066
2067/* subac3s */
2068void
2069OP_17001000 ()
2070{
4f425a32 2071 int64 tmp;
2934d1c9 2072#ifdef DEBUG
4f425a32 2073 printf(" subac3s\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 2074#endif
4f425a32
MH		 2075 State.F1 = State.F0;
2076 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2077 if ( tmp > MAX32)
2078 {
2079 State.regs[OP[0]] = 0x7fff;
2080 State.regs[OP[0]+1] = 0xffff;
2081 State.F0 = 1;
2082 }
2083 else if (tmp < MIN32)
2084 {
2085 State.regs[OP[0]] = 0x8000;
2086 State.regs[OP[0]+1] = 0;
2087 State.F0 = 1;
2088 }
2089 else
2090 {
2091 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2092 State.regs[OP[0]+1] = tmp & 0xffff;
2093 State.F0 = 0;
2094 }
2934d1c9
MH		 2095}
2096
2097/* subac3s */
2098void
2099OP_17001002 ()
2100{
4f425a32 2101 int64 tmp;
2934d1c9 2102#ifdef DEBUG
4f425a32 2103 printf(" subac3s\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 2104#endif
4f425a32
MH		 2105 State.F1 = State.F0;
2106 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2107 if ( tmp > MAX32)
2108 {
2109 State.regs[OP[0]] = 0x7fff;
2110 State.regs[OP[0]+1] = 0xffff;
2111 State.F0 = 1;
2112 }
2113 else if (tmp < MIN32)
2114 {
2115 State.regs[OP[0]] = 0x8000;
2116 State.regs[OP[0]+1] = 0;
2117 State.F0 = 1;
2118 }
2119 else
2120 {
2121 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2122 State.regs[OP[0]+1] = tmp & 0xffff;
2123 State.F0 = 0;
2124 }
2934d1c9
MH		 2125}
2126
2127/* subi */
2128void
2129OP_1 ()
2130{
4c38885c 2131 int32 tmp;
4f425a32
MH		 2132 if (OP[1] == 0)
2133 OP[1] = 16;
2934d1c9 2134#ifdef DEBUG
4c38885c 2135 printf(" subi\tr%d,%d\n",OP[0],OP[1]);
2934d1c9 2136#endif
4c38885c
MH		 2137 tmp = (int16)State.regs[OP[0]] - OP[1];
2138 State.C = (tmp & 0xffff0000) ? 1 : 0;
2139 State.regs[OP[0]] = tmp & 0xffff;
2934d1c9
MH		 2140}
2141
2142/* trap */
2143void
2144OP_5F00 ()
2145{
2146#ifdef DEBUG
2147 printf(" trap\t%d\n",OP[0]);
2148#endif
2149
63a91cfb 2150 switch (OP[0])
2934d1c9 2151 {
63a91cfb
MM		 2152 default:
2153 fprintf (stderr, "Unknown trap code %d\n", OP[0]);
2154 State.exception = SIGILL;
2155
2156 case 0:
2157 /* Trap 0 is used for simulating low-level I/O */
2158 {
2159 int save_errno = errno;
2160 errno = 0;
2161
2162/* Registers passed to trap 0 */
2163
2164#define FUNC State.regs[2] /* function number, return value */
2165#define PARM1 State.regs[3] /* optional parm 1 */
2166#define PARM2 State.regs[4] /* optional parm 2 */
2167#define PARM3 State.regs[5] /* optional parm 3 */
2168
2169/* Registers set by trap 0 */
2170
2171#define RETVAL State.regs[2] /* return value */
2172#define RETERR State.regs[3] /* return error code */
2173
2174/* Turn a pointer in a register into a pointer into real memory. */
2175
2176#define MEMPTR(x) ((char *)((x) + State.imem))
2177
2178 switch (FUNC)
2179 {
2180#if !defined(__GO32__) && !defined(_WIN32)
2181#ifdef SYS_fork
2182 case SYS_fork:
2183 RETVAL = fork ();
2184 break;
2185#endif
2186#ifdef SYS_execve
2187 case SYS_execve:
2188 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2189 (char **)MEMPTR (PARM3));
2190 break;
2191#endif
2192#ifdef SYS_execv
2193 case SYS_execv:
2194 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2195 break;
2196#endif
2197#ifdef SYS_pipe
2198 case SYS_pipe:
2199 {
2200 reg_t buf;
2201 int host_fd[2];
2202
2203 buf = PARM1;
2204 RETVAL = pipe (host_fd);
2205 SW (buf, host_fd[0]);
2206 buf += sizeof(uint16);
2207 SW (buf, host_fd[1]);
2208 }
2209 break;
2210#endif
2211#ifdef SYS_wait
2212 case SYS_wait:
2213 {
2214 int status;
2215
2216 RETVAL = wait (&status);
2217 SW (PARM1, status);
2218 }
2219 break;
2220#endif
2221#endif
2222
2223#ifdef SYS_read
2224 case SYS_read:
2225 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2226 PARM3);
2227 break;
2228#endif
2229#ifdef SYS_write
2230 case SYS_write:
2231 if (PARM1 == 1)
2232 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2233 MEMPTR (PARM2), PARM3);
2234 else
2235 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2236 MEMPTR (PARM2), PARM3);
2237 break;
2238#endif
2239#ifdef SYS_lseek
2240 case SYS_lseek:
2241 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2242 break;
2243#endif
2244#ifdef SYS_close
2245 case SYS_close:
2246 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2247 break;
2248#endif
2249#ifdef SYS_open
2250 case SYS_open:
2251 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2252 break;
2253#endif
2254#ifdef SYS_exit
2255 case SYS_exit:
2256 /* EXIT - caller can look in PARM1 to work out the
2257 reason */
2258 State.exception = SIGQUIT;
2259 break;
2260#endif
2261
2262#ifdef SYS_stat: /* added at hmsi *
2263 case SYS_stat: /* added at hmsi */
2264 /* stat system call */
2265 {
2266 struct stat host_stat;
2267 reg_t buf;
2268
2269 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2270
2271 buf = PARM2;
2272
2273 /* The hard-coded offsets and sizes were determined by using
2274 * the D10V compiler on a test program that used struct stat.
2275 */
2276 SW (buf, host_stat.st_dev);
2277 SW (buf+2, host_stat.st_ino);
2278 SW (buf+4, host_stat.st_mode);
2279 SW (buf+6, host_stat.st_nlink);
2280 SW (buf+8, host_stat.st_uid);
2281 SW (buf+10, host_stat.st_gid);
2282 SW (buf+12, host_stat.st_rdev);
2283 SLW (buf+16, host_stat.st_size);
2284 SLW (buf+20, host_stat.st_atime);
2285 SLW (buf+28, host_stat.st_mtime);
2286 SLW (buf+36, host_stat.st_ctime);
2287 }
2288 break;
2289#endif
2290
2291#ifdef SYS_chown
2292 case SYS_chown:
2293 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2294 break;
2295#endif
2296#ifdef SYS_chmod
2297 case SYS_chmod:
2298 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2299 break;
2300#endif
2301#ifdef SYS_utime
2302 case SYS_utime:
2303 /* Cast the second argument to void *, to avoid type mismatch
2304 if a prototype is present. */
2305 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2306 break;
2307#endif
2308 default:
2309 abort ();
2310 }
2311 RETERR = errno;
2312 errno = save_errno;
2313 break;
2314 }
2315
2316 case 1:
2317 /* Trap 1 prints a string */
2318 {
2319 char *fstr = State.regs[2] + State.imem;
2320 fputs (fstr, stdout);
2321 break;
2322 }
2323
2324 case 2:
2325 /* Trap 2 calls printf */
2326 {
2327 char *fstr = State.regs[2] + State.imem;
2328 printf (fstr,State.regs[3],State.regs[4],State.regs[5]);
2329 break;
2330 }
2331
2332 case 3:
2333 /* Trap 3 writes a character */
2334 putchar (State.regs[2]);
2335 break;
2934d1c9
MH		 2336 }
2337}
2338
2339/* tst0i */
2340void
2341OP_7000000 ()
2342{
2343#ifdef DEBUG
4c38885c 2344 printf(" tst0i\tr%d,0x%x\n",OP[0],OP[1]);
2934d1c9 2345#endif
4c38885c 2346 State.F1 = State.F0;
4f425a32 2347 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2934d1c9
MH		 2348}
2349
2350/* tst1i */
2351void
2352OP_F000000 ()
2353{
2354#ifdef DEBUG
4c38885c 2355 printf(" tst1i\tr%d,0x%x\n",OP[0],OP[1]);
2934d1c9 2356#endif
4c38885c 2357 State.F1 = State.F0;
4f425a32 2358 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2934d1c9
MH		 2359}
2360
2361/* wait */
2362void
2363OP_5F80 ()
2364{
2365#ifdef DEBUG
4c38885c 2366 printf(" wait\n");
2934d1c9 2367#endif
4c38885c 2368 State.IE = 1;
2934d1c9
MH		 2369}
2370
2371/* xor */
2372void
2373OP_A00 ()
2374{
2375#ifdef DEBUG
4c38885c 2376 printf(" xor\tr%d,r%d\n",OP[0],OP[1]);
2934d1c9 2377#endif
4c38885c 2378 State.regs[OP[0]] ^= State.regs[OP[1]];
2934d1c9
MH		 2379}
2380
2381/* xor3 */
2382void
2383OP_5000000 ()
2384{
2385#ifdef DEBUG
4c38885c 2386 printf(" xor3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
2934d1c9 2387#endif
4c38885c 2388 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2934d1c9
MH		 2389}
2390
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