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Rework sim/common/sim-alu.h to differentiate between direcct
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
fd435e9f
MM		 1#include "config.h"
2
4f425a32 3#include <signal.h>
63a91cfb
MM		 4#include <errno.h>
5#include <sys/types.h>
6#include <sys/stat.h>
fd435e9f 7#ifdef HAVE_UNISTD_H
63a91cfb 8#include <unistd.h>
fd435e9f 9#endif
63a91cfb 10
2934d1c9
MH		 11#include "d10v_sim.h"
12#include "simops.h"
8719be26 13#include "sys/syscall.h"
2934d1c9 14
c422ecc7
MH		 15extern char *strrchr ();
16
87178dbd
MM		 17enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
60fc5b72 30 OP_FLAG_OUTPUT,
87178dbd 31 OP_CONSTANT16,
a18cb100 32 OP_CONSTANT8,
87178dbd
MM		 33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
a18cb100
MM		 39 OP_PREDEC,
40 OP_R2,
8918b3a7
MM		 41 OP_R3,
42 OP_R4,
43 OP_R2R3
87178dbd
MM		 44};
45
7eebfc62 46#ifdef DEBUG
a49a15ad
MM		 47static void trace_input_func PARAMS ((char *name,
48 enum op_types in1,
49 enum op_types in2,
50 enum op_types in3));
87178dbd 51
a49a15ad
MM		 52#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
53
54static void trace_output_func PARAMS ((enum op_types result));
55
56#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
57
87178dbd 58#ifndef SIZE_INSTRUCTION
a49a15ad 59#define SIZE_INSTRUCTION 8
87178dbd
MM		 60#endif
61
62#ifndef SIZE_OPERANDS
a49a15ad 63#define SIZE_OPERANDS 18
87178dbd
MM		 64#endif
65
66#ifndef SIZE_VALUES
67#define SIZE_VALUES 13
68#endif
69
a49a15ad
MM		 70#ifndef SIZE_LOCATION
71#define SIZE_LOCATION 20
72#endif
73
891513ee
MM		 74#ifndef SIZE_PC
75#define SIZE_PC 6
76#endif
77
78#ifndef SIZE_LINE_NUMBER
79#define SIZE_LINE_NUMBER 4
80#endif
81
87178dbd 82static void
a49a15ad 83trace_input_func (name, in1, in2, in3)
87178dbd
MM		 84 char *name;
85 enum op_types in1;
86 enum op_types in2;
87 enum op_types in3;
88{
89 char *comma;
90 enum op_types in[3];
91 int i;
a49a15ad 92 char buf[1024];
87178dbd
MM		 93 char *p;
94 long tmp;
95 char *type;
a49a15ad
MM		 96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
87178dbd 100
7eebfc62
MM		 101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
87178dbd
MM		 104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
c422ecc7
MH		 112 case INS_LEFT_COND_TEST: type = "?L"; break;
113 case INS_RIGHT_COND_TEST: type = "?R"; break;
114 case INS_LEFT_COND_EXE: type = "&L"; break;
115 case INS_RIGHT_COND_EXE: type = "&R"; break;
87178dbd
MM		 116 case INS_LONG: type = " B"; break;
117 }
118
a49a15ad
MM		 119 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
120 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 121 "0x%.*x %s: %-*s ",
891513ee
MM		 122 SIZE_PC, (unsigned)PC,
123 type,
a49a15ad
MM		 124 SIZE_INSTRUCTION, name);
125
126 else
127 {
891513ee 128 buf[0] = '\0';
b30cdd35 129 byte_pc = decode_pc ();
a49a15ad
MM		 130 if (text && byte_pc >= text_start && byte_pc < text_end)
131 {
132 filename = (const char *)0;
133 functionname = (const char *)0;
134 linenumber = 0;
b83093ff 135 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 136 &filename, &functionname, &linenumber))
137 {
138 p = buf;
139 if (linenumber)
140 {
891513ee 141 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 142 p += strlen (p);
143 }
891513ee
MM		 144 else
145 {
146 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
147 p += SIZE_LINE_NUMBER+2;
148 }
a49a15ad
MM		 149
150 if (functionname)
151 {
152 sprintf (p, "%s ", functionname);
153 p += strlen (p);
154 }
155 else if (filename)
156 {
c422ecc7 157 char *q = strrchr (filename, '/');
a49a15ad
MM		 158 sprintf (p, "%s ", (q) ? q+1 : filename);
159 p += strlen (p);
160 }
161
162 if (*p == ' ')
163 *p = '\0';
164 }
165 }
166
167 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 168 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 169 SIZE_PC, (unsigned)PC,
170 type,
a49a15ad
MM		 171 SIZE_LOCATION, SIZE_LOCATION, buf,
172 SIZE_INSTRUCTION, name);
173 }
87178dbd
MM		 174
175 in[0] = in1;
176 in[1] = in2;
177 in[2] = in3;
178 comma = "";
179 p = buf;
180 for (i = 0; i < 3; i++)
181 {
182 switch (in[i])
183 {
184 case OP_VOID:
a18cb100
MM		 185 case OP_R2:
186 case OP_R3:
8918b3a7 187 case OP_R4:
c422ecc7 188 case OP_R2R3:
87178dbd
MM		 189 break;
190
191 case OP_REG:
192 case OP_REG_OUTPUT:
193 case OP_DREG:
194 case OP_DREG_OUTPUT:
195 sprintf (p, "%sr%d", comma, OP[i]);
196 p += strlen (p);
197 comma = ",";
198 break;
199
200 case OP_CR:
201 case OP_CR_OUTPUT:
202 case OP_CR_REVERSE:
203 sprintf (p, "%scr%d", comma, OP[i]);
204 p += strlen (p);
205 comma = ",";
206 break;
207
208 case OP_ACCUM:
209 case OP_ACCUM_OUTPUT:
210 case OP_ACCUM_REVERSE:
211 sprintf (p, "%sa%d", comma, OP[i]);
212 p += strlen (p);
213 comma = ",";
214 break;
215
216 case OP_CONSTANT16:
217 sprintf (p, "%s%d", comma, OP[i]);
218 p += strlen (p);
219 comma = ",";
220 break;
221
a18cb100
MM		 222 case OP_CONSTANT8:
223 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
224 p += strlen (p);
225 comma = ",";
226 break;
227
87178dbd
MM		 228 case OP_CONSTANT4:
229 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
230 p += strlen (p);
231 comma = ",";
232 break;
233
234 case OP_CONSTANT3:
235 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
236 p += strlen (p);
237 comma = ",";
238 break;
239
240 case OP_MEMREF:
241 sprintf (p, "%s@r%d", comma, OP[i]);
242 p += strlen (p);
243 comma = ",";
244 break;
245
246 case OP_MEMREF2:
247 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
248 p += strlen (p);
249 comma = ",";
250 break;
251
252 case OP_POSTINC:
253 sprintf (p, "%s@r%d+", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_POSTDEC:
259 sprintf (p, "%s@r%d-", comma, OP[i]);
260 p += strlen (p);
261 comma = ",";
262 break;
263
264 case OP_PREDEC:
265 sprintf (p, "%s@-r%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_FLAG:
60fc5b72 271 case OP_FLAG_OUTPUT:
87178dbd
MM		 272 if (OP[i] == 0)
273 sprintf (p, "%sf0", comma);
274
275 else if (OP[i] == 1)
276 sprintf (p, "%sf1", comma);
277
278 else
60fc5b72 279 sprintf (p, "%sc", comma);
87178dbd
MM		 280
281 p += strlen (p);
282 comma = ",";
283 break;
284 }
285 }
286
7eebfc62
MM		 287 if ((d10v_debug & DEBUG_VALUES) == 0)
288 {
289 *p++ = '\n';
290 *p = '\0';
291 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
292 }
293 else
294 {
295 *p = '\0';
296 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 297
7eebfc62
MM		 298 p = buf;
299 for (i = 0; i < 3; i++)
300 {
301 buf[0] = '\0';
302 switch (in[i])
303 {
304 case OP_VOID:
305 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
306 break;
307
308 case OP_REG_OUTPUT:
309 case OP_DREG_OUTPUT:
310 case OP_CR_OUTPUT:
311 case OP_ACCUM_OUTPUT:
60fc5b72 312 case OP_FLAG_OUTPUT:
7eebfc62
MM		 313 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
314 break;
315
316 case OP_REG:
317 case OP_MEMREF:
318 case OP_POSTDEC:
319 case OP_POSTINC:
320 case OP_PREDEC:
321 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
322 (uint16)State.regs[OP[i]]);
323 break;
324
325 case OP_DREG:
326 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
327 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
328 break;
329
330 case OP_CR:
331 case OP_CR_REVERSE:
332 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
333 (uint16)State.cregs[OP[i]]);
334 break;
335
336 case OP_ACCUM:
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[i]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
341 break;
342
343 case OP_CONSTANT16:
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
345 (uint16)OP[i]);
346 break;
347
348 case OP_CONSTANT4:
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)SEXT4(OP[i]));
351 break;
352
a18cb100
MM		 353 case OP_CONSTANT8:
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)SEXT8(OP[i]));
356 break;
357
7eebfc62
MM		 358 case OP_CONSTANT3:
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT3(OP[i]));
361 break;
362
363 case OP_FLAG:
364 if (OP[i] == 0)
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
366 State.F0 != 0);
367
368 else if (OP[i] == 1)
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
370 State.F1 != 0);
371
372 else
373 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
374 State.C != 0);
375
376 break;
377
378 case OP_MEMREF2:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16)OP[i]);
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
382 (uint16)State.regs[OP[++i]]);
383 break;
a18cb100
MM		 384
385 case OP_R2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)State.regs[2]);
388 break;
389
390 case OP_R3:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[3]);
393 break;
8918b3a7
MM		 394
395 case OP_R4:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[4]);
398 break;
c422ecc7
MH		 399
400 case OP_R2R3:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[2]);
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[3]);
405 i++;
406 break;
7eebfc62
MM		 407 }
408 }
409 }
fd435e9f
MM		 410
411 (*d10v_callback->flush_stdout) (d10v_callback);
7eebfc62 412}
87178dbd 413
7eebfc62 414static void
a49a15ad 415trace_output_func (result)
7eebfc62
MM		 416 enum op_types result;
417{
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 419 {
7eebfc62 420 long tmp;
87178dbd 421
7eebfc62
MM		 422 switch (result)
423 {
424 default:
425 putchar ('\n');
87178dbd
MM		 426 break;
427
428 case OP_REG:
7eebfc62
MM		 429 case OP_REG_OUTPUT:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 433 break;
434
435 case OP_DREG:
7eebfc62
MM		 436 case OP_DREG_OUTPUT:
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 440 break;
441
442 case OP_CR:
7eebfc62
MM		 443 case OP_CR_OUTPUT:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 447 break;
448
7eebfc62
MM		 449 case OP_CR_REVERSE:
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 453 break;
454
7eebfc62
MM		 455 case OP_ACCUM:
456 case OP_ACCUM_OUTPUT:
069398aa 457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 461 break;
462
7eebfc62 463 case OP_ACCUM_REVERSE:
069398aa 464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 468 break;
469
470 case OP_FLAG:
60fc5b72 471 case OP_FLAG_OUTPUT:
7eebfc62
MM		 472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd 474 break;
8918b3a7
MM		 475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
481
482 case OP_R2R3:
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
486 break;
87178dbd
MM		 487 }
488 }
fd435e9f
MM		 489
490 (*d10v_callback->flush_stdout) (d10v_callback);
87178dbd
MM		 491}
492
493#else
494#define trace_input(NAME, IN1, IN2, IN3)
495#define trace_output(RESULT)
496#endif
2934d1c9
MH		 497
498/* abs */
499void
500OP_4607 ()
501{
87178dbd 502 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 503 State.F1 = State.F0;
504 if ((int16)(State.regs[OP[0]]) < 0)
505 {
506 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
507 State.F0 = 1;
508 }
509 else
510 State.F0 = 0;
87178dbd 511 trace_output (OP_REG);
2934d1c9
MH		 512}
513
514/* abs */
515void
516OP_5607 ()
517{
518 int64 tmp;
519
87178dbd 520 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 521 State.F1 = State.F0;
522 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
523
4c38885c 524 if (State.a[OP[0]] < 0 )
2934d1c9 525 {
4c38885c 526 tmp = -State.a[OP[0]];
2934d1c9
MH		 527 if (State.ST)
528 {
4c38885c 529 if (tmp > MAX32)
2934d1c9 530 State.a[OP[0]] = MAX32;
4c38885c 531 else if (tmp < MIN32)
2934d1c9
MH		 532 State.a[OP[0]] = MIN32;
533 else
4f425a32 534 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 535 }
536 else
4f425a32 537 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 538 State.F0 = 1;
539 }
540 else
541 State.F0 = 0;
87178dbd 542 trace_output (OP_ACCUM);
2934d1c9
MH		 543}
544
545/* add */
546void
547OP_200 ()
548{
549 uint16 tmp = State.regs[OP[0]];
87178dbd 550 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 551 State.regs[OP[0]] += State.regs[OP[1]];
552 if ( tmp > State.regs[OP[0]])
553 State.C = 1;
554 else
555 State.C = 0;
87178dbd 556 trace_output (OP_REG);
2934d1c9
MH		 557}
558
559/* add */
560void
561OP_1201 ()
562{
4c38885c 563 int64 tmp;
4f425a32 564 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 565
566 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 567 if (State.ST)
568 {
569 if ( tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
4f425a32 574 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 575 }
576 else
4f425a32 577 State.a[OP[0]] = tmp & MASK40;
87178dbd 578 trace_output (OP_ACCUM);
2934d1c9
MH		 579}
580
581/* add */
582void
583OP_1203 ()
584{
4c38885c 585 int64 tmp;
4f425a32 586 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 587
588 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 589 if (State.ST)
590 {
591 if (tmp > MAX32)
592 State.a[OP[0]] = MAX32;
593 else if ( tmp < MIN32)
594 State.a[OP[0]] = MIN32;
595 else
4f425a32 596 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 597 }
598 else
4f425a32 599 State.a[OP[0]] = tmp & MASK40;
87178dbd 600 trace_output (OP_ACCUM);
2934d1c9
MH		 601}
602
603/* add2w */
604void
605OP_1200 ()
606{
607 uint32 tmp;
f4b022d3
MM		 608 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
609 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 610
611 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 612 tmp = a + b;
613 State.C = (tmp < a);
2934d1c9
MH		 614 State.regs[OP[0]] = tmp >> 16;
615 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 616 trace_output (OP_DREG);
2934d1c9
MH		 617}
618
619/* add3 */
620void
621OP_1000000 ()
622{
f4b022d3
MM		 623 uint16 tmp = State.regs[OP[1]];
624 State.regs[OP[0]] = tmp + OP[2];
87178dbd
MM		 625
626 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
f4b022d3 627 State.C = (State.regs[OP[0]] < tmp);
87178dbd 628 trace_output (OP_REG);
2934d1c9
MH		 629}
630
631/* addac3 */
632void
633OP_17000200 ()
634{
4c38885c 635 int64 tmp;
4f425a32 636 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 637
638 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 639 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
640 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 641 trace_output (OP_DREG);
2934d1c9
MH		 642}
643
644/* addac3 */
645void
646OP_17000202 ()
647{
4c38885c 648 int64 tmp;
4f425a32 649 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 650
651 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 652 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
653 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 654 trace_output (OP_DREG);
2934d1c9
MH		 655}
656
657/* addac3s */
658void
659OP_17001200 ()
660{
4c38885c 661 int64 tmp;
4c38885c 662 State.F1 = State.F0;
87178dbd
MM		 663
664 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 665 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 666 if ( tmp > MAX32)
667 {
668 State.regs[OP[0]] = 0x7fff;
669 State.regs[OP[0]+1] = 0xffff;
670 State.F0 = 1;
671 }
672 else if (tmp < MIN32)
673 {
674 State.regs[OP[0]] = 0x8000;
675 State.regs[OP[0]+1] = 0;
676 State.F0 = 1;
677 }
678 else
679 {
680 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
681 State.regs[OP[0]+1] = tmp & 0xffff;
682 State.F0 = 0;
683 }
87178dbd 684 trace_output (OP_DREG);
2934d1c9
MH		 685}
686
687/* addac3s */
688void
689OP_17001202 ()
690{
4c38885c 691 int64 tmp;
4c38885c 692 State.F1 = State.F0;
87178dbd
MM		 693
694 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 695 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 696 if ( tmp > MAX32)
697 {
698 State.regs[OP[0]] = 0x7fff;
699 State.regs[OP[0]+1] = 0xffff;
700 State.F0 = 1;
701 }
702 else if (tmp < MIN32)
703 {
704 State.regs[OP[0]] = 0x8000;
705 State.regs[OP[0]+1] = 0;
706 State.F0 = 1;
707 }
708 else
709 {
710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
712 State.F0 = 0;
713 }
87178dbd 714 trace_output (OP_DREG);
2934d1c9
MH		 715}
716
717/* addi */
718void
719OP_201 ()
720{
2254cd90 721 uint tmp = State.regs[OP[0]];
4f425a32
MH		 722 if (OP[1] == 0)
723 OP[1] = 16;
f4b022d3 724
87178dbd 725 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 726 State.regs[OP[0]] += OP[1];
f4b022d3 727 State.C = (State.regs[OP[0]] < tmp);
87178dbd 728 trace_output (OP_REG);
2934d1c9
MH		 729}
730
731/* and */
732void
733OP_C00 ()
734{
87178dbd 735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 736 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 737 trace_output (OP_REG);
2934d1c9
MH		 738}
739
740/* and3 */
741void
742OP_6000000 ()
743{
87178dbd 744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 746 trace_output (OP_REG);
2934d1c9
MH		 747}
748
749/* bclri */
750void
751OP_C01 ()
752{
87178dbd 753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 755 trace_output (OP_REG);
2934d1c9
MH		 756}
757
758/* bl.s */
759void
760OP_4900 ()
761{
a18cb100 762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
2934d1c9 763 State.regs[13] = PC+1;
fd435e9f 764 JMP( PC + SEXT8 (OP[0]));
87178dbd 765 trace_output (OP_VOID);
2934d1c9
MH		 766}
767
768/* bl.l */
769void
770OP_24800000 ()
771{
a18cb100 772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
2934d1c9 773 State.regs[13] = PC+1;
fd435e9f 774 JMP (PC + OP[0]);
87178dbd 775 trace_output (OP_VOID);
2934d1c9
MH		 776}
777
778/* bnoti */
779void
780OP_A01 ()
781{
87178dbd 782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 784 trace_output (OP_REG);
2934d1c9
MH		 785}
786
787/* bra.s */
788void
789OP_4800 ()
790{
a18cb100 791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
fd435e9f 792 JMP (PC + SEXT8 (OP[0]));
87178dbd 793 trace_output (OP_VOID);
2934d1c9
MH		 794}
795
796/* bra.l */
797void
798OP_24000000 ()
799{
87178dbd 800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
fd435e9f 801 JMP (PC + OP[0]);
87178dbd 802 trace_output (OP_VOID);
2934d1c9
MH		 803}
804
805/* brf0f.s */
806void
807OP_4A00 ()
808{
a18cb100 809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 810 if (State.F0 == 0)
fd435e9f 811 JMP (PC + SEXT8 (OP[0]));
87178dbd 812 trace_output (OP_FLAG);
2934d1c9
MH		 813}
814
815/* brf0f.l */
816void
817OP_25000000 ()
818{
87178dbd 819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 820 if (State.F0 == 0)
fd435e9f 821 JMP (PC + OP[0]);
87178dbd 822 trace_output (OP_FLAG);
2934d1c9
MH		 823}
824
825/* brf0t.s */
826void
827OP_4B00 ()
828{
a18cb100 829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 830 if (State.F0)
fd435e9f 831 JMP (PC + SEXT8 (OP[0]));
87178dbd 832 trace_output (OP_FLAG);
2934d1c9
MH		 833}
834
835/* brf0t.l */
836void
837OP_25800000 ()
838{
87178dbd 839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 840 if (State.F0)
fd435e9f 841 JMP (PC + OP[0]);
87178dbd 842 trace_output (OP_FLAG);
2934d1c9
MH		 843}
844
845/* bseti */
846void
847OP_801 ()
848{
87178dbd 849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 850 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 851 trace_output (OP_REG);
2934d1c9
MH		 852}
853
854/* btsti */
855void
856OP_E01 ()
857{
87178dbd 858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 859 State.F1 = State.F0;
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 861 trace_output (OP_FLAG);
2934d1c9
MH		 862}
863
864/* clrac */
865void
866OP_5601 ()
867{
87178dbd 868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 869 State.a[OP[0]] = 0;
87178dbd 870 trace_output (OP_ACCUM);
2934d1c9
MH		 871}
872
873/* cmp */
874void
875OP_600 ()
876{
87178dbd 877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 878 State.F1 = State.F0;
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 880 trace_output (OP_FLAG);
2934d1c9
MH		 881}
882
883/* cmp */
884void
885OP_1603 ()
886{
87178dbd 887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 888 State.F1 = State.F0;
4f425a32 889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 890 trace_output (OP_FLAG);
2934d1c9
MH		 891}
892
893/* cmpeq */
894void
895OP_400 ()
896{
87178dbd 897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 898 State.F1 = State.F0;
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 900 trace_output (OP_FLAG);
2934d1c9
MH		 901}
902
903/* cmpeq */
904void
905OP_1403 ()
906{
87178dbd 907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 908 State.F1 = State.F0;
fd435e9f 909 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
87178dbd 910 trace_output (OP_FLAG);
2934d1c9
MH		 911}
912
913/* cmpeqi.s */
914void
915OP_401 ()
916{
c12f5c67 917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 918 State.F1 = State.F0;
c12f5c67 919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 920 trace_output (OP_FLAG);
2934d1c9
MH		 921}
922
923/* cmpeqi.l */
924void
925OP_2000000 ()
926{
87178dbd 927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 928 State.F1 = State.F0;
c12f5c67 929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 930 trace_output (OP_FLAG);
2934d1c9
MH		 931}
932
933/* cmpi.s */
934void
935OP_601 ()
936{
87178dbd 937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 938 State.F1 = State.F0;
c12f5c67 939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 940 trace_output (OP_FLAG);
2934d1c9
MH		 941}
942
943/* cmpi.l */
944void
945OP_3000000 ()
946{
87178dbd 947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 950 trace_output (OP_FLAG);
2934d1c9
MH		 951}
952
953/* cmpu */
954void
955OP_4600 ()
956{
87178dbd 957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 958 State.F1 = State.F0;
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 960 trace_output (OP_FLAG);
2934d1c9
MH		 961}
962
963/* cmpui */
964void
965OP_23000000 ()
966{
87178dbd 967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 968 State.F1 = State.F0;
c12f5c67 969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 970 trace_output (OP_FLAG);
2934d1c9
MH		 971}
972
973/* cpfg */
974void
975OP_4E09 ()
976{
977 uint8 *src, *dst;
2934d1c9 978
60fc5b72 979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 980 if (OP[0] == 0)
981 dst = &State.F0;
982 else
983 dst = &State.F1;
984
985 if (OP[1] == 0)
986 src = &State.F0;
987 else if (OP[1] == 1)
988 src = &State.F1;
989 else
990 src = &State.C;
991
992 *dst = *src;
87178dbd 993 trace_output (OP_FLAG);
2934d1c9
MH		 994}
995
996/* dbt */
997void
998OP_5F20 ()
999{
a49a15ad 1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 1001 State.exception = SIGTRAP;
2934d1c9
MH		 1002}
1003
1004/* divs */
1005void
1006OP_14002800 ()
1007{
1008 uint16 foo, tmp, tmpf;
87178dbd
MM		 1009
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1016 trace_output (OP_DREG);
2934d1c9
MH		 1017}
1018
1019/* exef0f */
1020void
1021OP_4E04 ()
1022{
87178dbd 1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1024 State.exe = (State.F0 == 0);
87178dbd 1025 trace_output (OP_FLAG);
2934d1c9
MH		 1026}
1027
1028/* exef0t */
1029void
1030OP_4E24 ()
1031{
87178dbd 1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1033 State.exe = (State.F0 != 0);
87178dbd 1034 trace_output (OP_FLAG);
2934d1c9
MH		 1035}
1036
1037/* exef1f */
1038void
1039OP_4E40 ()
1040{
87178dbd 1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1042 State.exe = (State.F1 == 0);
87178dbd 1043 trace_output (OP_FLAG);
2934d1c9
MH		 1044}
1045
1046/* exef1t */
1047void
1048OP_4E42 ()
1049{
87178dbd 1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1051 State.exe = (State.F1 != 0);
87178dbd 1052 trace_output (OP_FLAG);
2934d1c9
MH		 1053}
1054
1055/* exefaf */
1056void
1057OP_4E00 ()
1058{
87178dbd 1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1061 trace_output (OP_FLAG);
2934d1c9
MH		 1062}
1063
1064/* exefat */
1065void
1066OP_4E02 ()
1067{
87178dbd 1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1070 trace_output (OP_FLAG);
2934d1c9
MH		 1071}
1072
1073/* exetaf */
1074void
1075OP_4E20 ()
1076{
87178dbd 1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1079 trace_output (OP_FLAG);
2934d1c9
MH		 1080}
1081
1082/* exetat */
1083void
1084OP_4E22 ()
1085{
87178dbd 1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1088 trace_output (OP_FLAG);
2934d1c9
MH		 1089}
1090
1091/* exp */
1092void
1093OP_15002A00 ()
1094{
1095 uint32 tmp, foo;
1096 int i;
1097
87178dbd 1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1101 else
4c38885c 1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1103
1104 foo = 0x40000000;
4c38885c 1105 for (i=1;i<17;i++)
2934d1c9
MH		 1106 {
1107 if (tmp & foo)
1108 {
1109 State.regs[OP[0]] = i-1;
87178dbd 1110 trace_output (OP_REG);
2934d1c9
MH		 1111 return;
1112 }
4c38885c 1113 foo >>= 1;
2934d1c9
MH		 1114 }
1115 State.regs[OP[0]] = 16;
87178dbd 1116 trace_output (OP_REG);
2934d1c9
MH		 1117}
1118
1119/* exp */
1120void
1121OP_15002A02 ()
1122{
4c38885c
MH		 1123 int64 tmp, foo;
1124 int i;
87178dbd
MM		 1125
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
fd435e9f
MM		 1127 tmp = SEXT40(State.a[OP[1]]);
1128 if (tmp < 0)
1129 tmp = ~tmp & MASK40;
4c38885c
MH		 1130
1131 foo = 0x4000000000LL;
1132 for (i=1;i<25;i++)
1133 {
1134 if (tmp & foo)
1135 {
1136 State.regs[OP[0]] = i-9;
87178dbd 1137 trace_output (OP_REG);
4c38885c
MH		 1138 return;
1139 }
1140 foo >>= 1;
1141 }
1142 State.regs[OP[0]] = 16;
87178dbd 1143 trace_output (OP_REG);
2934d1c9
MH		 1144}
1145
1146/* jl */
1147void
1148OP_4D00 ()
1149{
a18cb100 1150 trace_input ("jl", OP_REG, OP_R2, OP_R3);
2934d1c9 1151 State.regs[13] = PC+1;
fd435e9f 1152 JMP (State.regs[OP[0]]);
87178dbd 1153 trace_output (OP_VOID);
2934d1c9
MH		 1154}
1155
1156/* jmp */
1157void
1158OP_4C00 ()
1159{
a18cb100
MM		 1160 trace_input ("jmp", OP_REG,
1161 (OP[0] == 13) ? OP_R2 : OP_VOID,
1162 (OP[0] == 13) ? OP_R3 : OP_VOID);
1163
fd435e9f 1164 JMP (State.regs[OP[0]]);
87178dbd 1165 trace_output (OP_VOID);
2934d1c9
MH		 1166}
1167
1168/* ld */
1169void
1170OP_30000000 ()
1171{
87178dbd 1172 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1173 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1174 trace_output (OP_REG);
2934d1c9
MH		 1175}
1176
1177/* ld */
1178void
1179OP_6401 ()
1180{
87178dbd 1181 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1182 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1183 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1184 trace_output (OP_REG);
2934d1c9
MH		 1185}
1186
1187/* ld */
1188void
1189OP_6001 ()
1190{
87178dbd 1191 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1192 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1193 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1194 trace_output (OP_REG);
2934d1c9
MH		 1195}
1196
1197/* ld */
1198void
1199OP_6000 ()
1200{
87178dbd 1201 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1202 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1203 trace_output (OP_REG);
2934d1c9
MH		 1204}
1205
1206/* ld2w */
1207void
1208OP_31000000 ()
1209{
8918b3a7 1210 uint16 addr = State.regs[OP[2]];
308f64d3 1211 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
8918b3a7
MM		 1212 State.regs[OP[0]] = RW (OP[1] + addr);
1213 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
87178dbd 1214 trace_output (OP_DREG);
2934d1c9
MH		 1215}
1216
1217/* ld2w */
1218void
1219OP_6601 ()
1220{
8918b3a7 1221 uint16 addr = State.regs[OP[1]];
87178dbd 1222 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
8918b3a7
MM		 1223 State.regs[OP[0]] = RW (addr);
1224 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1225 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1226 trace_output (OP_DREG);
2934d1c9
MH		 1227}
1228
1229/* ld2w */
1230void
1231OP_6201 ()
1232{
8918b3a7 1233 uint16 addr = State.regs[OP[1]];
87178dbd 1234 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
8918b3a7
MM		 1235 State.regs[OP[0]] = RW (addr);
1236 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1237 INC_ADDR(State.regs[OP[1]],4);
8918b3a7 1238 trace_output (OP_DREG);
2934d1c9
MH		 1239}
1240
1241/* ld2w */
1242void
1243OP_6200 ()
1244{
8918b3a7 1245 uint16 addr = State.regs[OP[1]];
addb61a5 1246 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
8918b3a7
MM		 1247 State.regs[OP[0]] = RW (addr);
1248 State.regs[OP[0]+1] = RW (addr+2);
1249 trace_output (OP_DREG);
2934d1c9
MH		 1250}
1251
1252/* ldb */
1253void
1254OP_38000000 ()
1255{
87178dbd 1256 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
c422ecc7 1257 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
87178dbd 1258 trace_output (OP_REG);
2934d1c9
MH		 1259}
1260
1261/* ldb */
1262void
1263OP_7000 ()
1264{
87178dbd 1265 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
c422ecc7 1266 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
87178dbd 1267 trace_output (OP_REG);
2934d1c9
MH		 1268}
1269
1270/* ldi.s */
1271void
1272OP_4001 ()
1273{
87178dbd 1274 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1275 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1276 trace_output (OP_REG);
2934d1c9
MH		 1277}
1278
1279/* ldi.l */
1280void
1281OP_20000000 ()
1282{
fd435e9f 1283 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1284 State.regs[OP[0]] = OP[1];
87178dbd 1285 trace_output (OP_REG);
2934d1c9
MH		 1286}
1287
1288/* ldub */
1289void
1290OP_39000000 ()
1291{
87178dbd 1292 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1293 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1294 trace_output (OP_REG);
2934d1c9
MH		 1295}
1296
1297/* ldub */
1298void
1299OP_7200 ()
1300{
87178dbd 1301 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1302 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1303 trace_output (OP_REG);
2934d1c9
MH		 1304}
1305
1306/* mac */
1307void
1308OP_2A00 ()
1309{
4c38885c 1310 int64 tmp;
87178dbd
MM		 1311
1312 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1313 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1314
1315 if (State.FX)
4f425a32 1316 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1317
1318 if (State.ST && tmp > MAX32)
1319 tmp = MAX32;
1320
4f425a32 1321 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1322 if (State.ST)
1323 {
1324 if (tmp > MAX32)
1325 State.a[OP[0]] = MAX32;
1326 else if (tmp < MIN32)
1327 State.a[OP[0]] = MIN32;
1328 else
4f425a32 1329 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1330 }
1331 else
4f425a32 1332 State.a[OP[0]] = tmp & MASK40;
87178dbd 1333 trace_output (OP_ACCUM);
2934d1c9
MH		 1334}
1335
1336/* macsu */
1337void
1338OP_1A00 ()
1339{
4f425a32 1340 int64 tmp;
87178dbd
MM		 1341
1342 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1343 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1344 if (State.FX)
1345 tmp = SEXT40( (tmp << 1) & MASK40);
1346
1347 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1348 trace_output (OP_ACCUM);
2934d1c9
MH		 1349}
1350
1351/* macu */
1352void
1353OP_3A00 ()
1354{
4f425a32 1355 int64 tmp;
87178dbd
MM		 1356
1357 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1358 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1359 if (State.FX)
1360 tmp = SEXT40( (tmp << 1) & MASK40);
1361 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1362 trace_output (OP_ACCUM);
2934d1c9
MH		 1363}
1364
1365/* max */
1366void
1367OP_2600 ()
1368{
87178dbd 1369 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1370 State.F1 = State.F0;
ea2155e8 1371 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1372 {
1373 State.regs[OP[0]] = State.regs[OP[1]];
1374 State.F0 = 1;
1375 }
1376 else
1377 State.F0 = 0;
87178dbd 1378 trace_output (OP_REG);
2934d1c9
MH		 1379}
1380
1381/* max */
1382void
1383OP_3600 ()
1384{
4f425a32 1385 int64 tmp;
87178dbd
MM		 1386
1387 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1388 State.F1 = State.F0;
1389 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1390 if (tmp > SEXT40(State.a[OP[0]]))
1391 {
1392 State.a[OP[0]] = tmp & MASK40;
1393 State.F0 = 1;
1394 }
1395 else
1396 State.F0 = 0;
87178dbd 1397 trace_output (OP_ACCUM);
2934d1c9
MH		 1398}
1399
1400/* max */
1401void
1402OP_3602 ()
1403{
87178dbd 1404 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1405 State.F1 = State.F0;
1406 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1407 {
1408 State.a[OP[0]] = State.a[OP[1]];
1409 State.F0 = 1;
1410 }
1411 else
1412 State.F0 = 0;
87178dbd 1413 trace_output (OP_ACCUM);
2934d1c9
MH		 1414}
1415
4f425a32 1416
2934d1c9
MH		 1417/* min */
1418void
1419OP_2601 ()
1420{
87178dbd 1421 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1422 State.F1 = State.F0;
ea2155e8 1423 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1424 {
1425 State.regs[OP[0]] = State.regs[OP[1]];
1426 State.F0 = 1;
1427 }
1428 else
1429 State.F0 = 0;
87178dbd 1430 trace_output (OP_REG);
2934d1c9
MH		 1431}
1432
1433/* min */
1434void
1435OP_3601 ()
1436{
4f425a32 1437 int64 tmp;
87178dbd
MM		 1438
1439 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1440 State.F1 = State.F0;
1441 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1442 if (tmp < SEXT40(State.a[OP[0]]))
1443 {
1444 State.a[OP[0]] = tmp & MASK40;
1445 State.F0 = 1;
1446 }
1447 else
1448 State.F0 = 0;
87178dbd 1449 trace_output (OP_ACCUM);
2934d1c9
MH		 1450}
1451
1452/* min */
1453void
1454OP_3603 ()
1455{
87178dbd 1456 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1457 State.F1 = State.F0;
1458 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1459 {
1460 State.a[OP[0]] = State.a[OP[1]];
1461 State.F0 = 1;
1462 }
1463 else
1464 State.F0 = 0;
87178dbd 1465 trace_output (OP_ACCUM);
2934d1c9
MH		 1466}
1467
1468/* msb */
1469void
1470OP_2800 ()
1471{
4f425a32 1472 int64 tmp;
87178dbd
MM		 1473
1474 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1475 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1476
1477 if (State.FX)
1478 tmp = SEXT40 ((tmp << 1) & MASK40);
1479
1480 if (State.ST && tmp > MAX32)
1481 tmp = MAX32;
1482
1483 tmp = SEXT40(State.a[OP[0]]) - tmp;
1484 if (State.ST)
1485 {
1486 if (tmp > MAX32)
1487 State.a[OP[0]] = MAX32;
1488 else if (tmp < MIN32)
1489 State.a[OP[0]] = MIN32;
1490 else
1491 State.a[OP[0]] = tmp & MASK40;
1492 }
1493 else
1494 State.a[OP[0]] = tmp & MASK40;
87178dbd 1495 trace_output (OP_ACCUM);
2934d1c9
MH		 1496}
1497
1498/* msbsu */
1499void
1500OP_1800 ()
1501{
4f425a32 1502 int64 tmp;
87178dbd
MM		 1503
1504 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1505 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1506 if (State.FX)
1507 tmp = SEXT40( (tmp << 1) & MASK40);
1508
1509 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1510 trace_output (OP_ACCUM);
2934d1c9
MH		 1511}
1512
1513/* msbu */
1514void
1515OP_3800 ()
1516{
4f425a32 1517 int64 tmp;
87178dbd
MM		 1518
1519 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1520 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1521 if (State.FX)
1522 tmp = SEXT40( (tmp << 1) & MASK40);
1523
1524 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1525 trace_output (OP_ACCUM);
2934d1c9
MH		 1526}
1527
1528/* mul */
1529void
1530OP_2E00 ()
1531{
87178dbd 1532 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1533 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1534 trace_output (OP_REG);
2934d1c9
MH		 1535}
1536
1537/* mulx */
1538void
1539OP_2C00 ()
1540{
4f425a32 1541 int64 tmp;
87178dbd
MM		 1542
1543 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1544 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1545
1546 if (State.FX)
1547 tmp = SEXT40 ((tmp << 1) & MASK40);
1548
1549 if (State.ST && tmp > MAX32)
1550 State.a[OP[0]] = MAX32;
1551 else
1552 State.a[OP[0]] = tmp & MASK40;
87178dbd 1553 trace_output (OP_ACCUM);
2934d1c9
MH		 1554}
1555
1556/* mulxsu */
1557void
1558OP_1C00 ()
1559{
4f425a32 1560 int64 tmp;
87178dbd
MM		 1561
1562 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1563 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1564
1565 if (State.FX)
1566 tmp <<= 1;
1567
1568 State.a[OP[0]] = tmp & MASK40;
87178dbd 1569 trace_output (OP_ACCUM);
2934d1c9
MH		 1570}
1571
1572/* mulxu */
1573void
1574OP_3C00 ()
1575{
4f425a32 1576 int64 tmp;
87178dbd
MM		 1577
1578 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1579 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1580
1581 if (State.FX)
1582 tmp <<= 1;
1583
1584 State.a[OP[0]] = tmp & MASK40;
87178dbd 1585 trace_output (OP_ACCUM);
2934d1c9
MH		 1586}
1587
1588/* mv */
1589void
1590OP_4000 ()
1591{
87178dbd 1592 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1593 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1594 trace_output (OP_REG);
2934d1c9
MH		 1595}
1596
1597/* mv2w */
1598void
1599OP_5000 ()
1600{
87178dbd 1601 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1602 State.regs[OP[0]] = State.regs[OP[1]];
1603 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1604 trace_output (OP_DREG);
2934d1c9
MH		 1605}
1606
1607/* mv2wfac */
1608void
1609OP_3E00 ()
1610{
87178dbd 1611 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1612 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1613 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1614 trace_output (OP_DREG);
2934d1c9
MH		 1615}
1616
1617/* mv2wtac */
1618void
1619OP_3E01 ()
1620{
fd435e9f 1621 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
4f425a32 1622 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
fd435e9f 1623 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1624}
1625
1626/* mvac */
1627void
1628OP_3E03 ()
1629{
87178dbd 1630 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1631 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1632 trace_output (OP_ACCUM);
2934d1c9
MH		 1633}
1634
1635/* mvb */
1636void
1637OP_5400 ()
1638{
87178dbd 1639 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1640 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1641 trace_output (OP_REG);
2934d1c9
MH		 1642}
1643
1644/* mvf0f */
1645void
1646OP_4400 ()
1647{
87178dbd 1648 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1649 if (State.F0 == 0)
1650 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1651 trace_output (OP_REG);
2934d1c9
MH		 1652}
1653
1654/* mvf0t */
1655void
1656OP_4401 ()
1657{
87178dbd 1658 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1659 if (State.F0)
1660 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1661 trace_output (OP_REG);
2934d1c9
MH		 1662}
1663
1664/* mvfacg */
1665void
1666OP_1E04 ()
1667{
87178dbd 1668 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1669 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1670 trace_output (OP_ACCUM);
2934d1c9
MH		 1671}
1672
1673/* mvfachi */
1674void
1675OP_1E00 ()
1676{
87178dbd 1677 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1678 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1679 trace_output (OP_REG);
2934d1c9
MH		 1680}
1681
1682/* mvfaclo */
1683void
1684OP_1E02 ()
1685{
87178dbd 1686 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1687 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1688 trace_output (OP_REG);
2934d1c9
MH		 1689}
1690
1691/* mvfc */
1692void
1693OP_5200 ()
1694{
87178dbd 1695 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1696 if (OP[1] == 0)
1697 {
1698 /* PSW is treated specially */
1699 PSW = 0;
1700 if (State.SM) PSW |= 0x8000;
1701 if (State.EA) PSW |= 0x2000;
1702 if (State.DB) PSW |= 0x1000;
1703 if (State.IE) PSW |= 0x400;
1704 if (State.RP) PSW |= 0x200;
1705 if (State.MD) PSW |= 0x100;
1706 if (State.FX) PSW |= 0x80;
1707 if (State.ST) PSW |= 0x40;
1708 if (State.F0) PSW |= 8;
1709 if (State.F1) PSW |= 4;
1710 if (State.C) PSW |= 1;
1711 }
1712 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1713 trace_output (OP_REG);
2934d1c9
MH		 1714}
1715
1716/* mvtacg */
1717void
1718OP_1E41 ()
1719{
87178dbd 1720 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1721 State.a[OP[1]] &= MASK32;
1722 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1723 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1724}
1725
1726/* mvtachi */
1727void
1728OP_1E01 ()
1729{
1730 uint16 tmp;
87178dbd
MM		 1731
1732 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1733 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1734 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1735 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1736}
1737
1738/* mvtaclo */
1739void
1740OP_1E21 ()
1741{
87178dbd 1742 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1743 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1744 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1745}
1746
1747/* mvtc */
1748void
1749OP_5600 ()
1750{
87178dbd 1751 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1752 State.cregs[OP[1]] = State.regs[OP[0]];
1753 if (OP[1] == 0)
1754 {
1755 /* PSW is treated specially */
1756 State.SM = (PSW & 0x8000) ? 1 : 0;
1757 State.EA = (PSW & 0x2000) ? 1 : 0;
1758 State.DB = (PSW & 0x1000) ? 1 : 0;
1759 State.IE = (PSW & 0x400) ? 1 : 0;
1760 State.RP = (PSW & 0x200) ? 1 : 0;
1761 State.MD = (PSW & 0x100) ? 1 : 0;
1762 State.FX = (PSW & 0x80) ? 1 : 0;
1763 State.ST = (PSW & 0x40) ? 1 : 0;
1764 State.F0 = (PSW & 8) ? 1 : 0;
1765 State.F1 = (PSW & 4) ? 1 : 0;
1766 State.C = PSW & 1;
1767 if (State.ST && !State.FX)
1768 {
7eebfc62
MM		 1769 (*d10v_callback->printf_filtered) (d10v_callback,
1770 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1771 PC<<2);
4f425a32 1772 State.exception = SIGILL;
2934d1c9
MH		 1773 }
1774 }
87178dbd 1775 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1776}
1777
1778/* mvub */
1779void
1780OP_5401 ()
1781{
87178dbd 1782 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1783 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1784 trace_output (OP_REG);
2934d1c9
MH		 1785}
1786
1787/* neg */
1788void
1789OP_4605 ()
1790{
87178dbd 1791 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1792 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1793 trace_output (OP_REG);
2934d1c9
MH		 1794}
1795
1796/* neg */
1797void
1798OP_5605 ()
1799{
1800 int64 tmp;
87178dbd
MM		 1801
1802 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1803 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1804 if (State.ST)
1805 {
4c38885c 1806 if ( tmp > MAX32)
2934d1c9 1807 State.a[OP[0]] = MAX32;
4c38885c 1808 else if (tmp < MIN32)
2934d1c9
MH		 1809 State.a[OP[0]] = MIN32;
1810 else
4f425a32 1811 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1812 }
1813 else
4f425a32 1814 State.a[OP[0]] = tmp & MASK40;
87178dbd 1815 trace_output (OP_ACCUM);
2934d1c9
MH		 1816}
1817
1818
1819/* nop */
1820void
1821OP_5E00 ()
1822{
87178dbd 1823 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
7eebfc62 1824
c422ecc7
MH		 1825 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1826 switch (State.ins_type)
1827 {
1828 default:
1829 ins_type_counters[ (int)INS_UNKNOWN ]++;
1830 break;
1831
1832 case INS_LEFT_PARALLEL:
1833 /* Don't count a parallel op that includes a NOP as a true parallel op */
1834 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1835 ins_type_counters[ (int)INS_RIGHT ]++;
1836 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1837 break;
1838
1839 case INS_LEFT:
1840 case INS_LEFT_COND_EXE:
1841 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1842 break;
1843
1844 case INS_RIGHT_PARALLEL:
1845 /* Don't count a parallel op that includes a NOP as a true parallel op */
1846 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1847 ins_type_counters[ (int)INS_LEFT ]++;
1848 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1849 break;
1850
1851 case INS_RIGHT:
1852 case INS_RIGHT_COND_EXE:
1853 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1854 break;
1855 }
1856
1857 trace_output (OP_VOID);
2934d1c9
MH		 1858}
1859
1860/* not */
1861void
1862OP_4603 ()
1863{
87178dbd 1864 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1865 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1866 trace_output (OP_REG);
2934d1c9
MH		 1867}
1868
1869/* or */
1870void
1871OP_800 ()
1872{
87178dbd 1873 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1874 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1875 trace_output (OP_REG);
2934d1c9
MH		 1876}
1877
1878/* or3 */
1879void
1880OP_4000000 ()
1881{
87178dbd 1882 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1883 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1884 trace_output (OP_REG);
2934d1c9
MH		 1885}
1886
1887/* rac */
1888void
1889OP_5201 ()
1890{
1891 int64 tmp;
1892 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1893
1894 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1895 if (OP[1] != 0)
1896 {
7eebfc62
MM		 1897 (*d10v_callback->printf_filtered) (d10v_callback,
1898 "ERROR at PC 0x%x: instruction only valid for A0\n",
1899 PC<<2);
166acb9f
MH		 1900 State.exception = SIGILL;
1901 }
1902
2934d1c9
MH		 1903 State.F1 = State.F0;
1904 if (shift >=0)
1905 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1906 else
1907 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1908 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1909 if (tmp > MAX32)
2934d1c9
MH		 1910 {
1911 State.regs[OP[0]] = 0x7fff;
1912 State.regs[OP[0]+1] = 0xffff;
1913 State.F0 = 1;
1914 }
4c38885c 1915 else if (tmp < MIN32)
2934d1c9
MH		 1916 {
1917 State.regs[OP[0]] = 0x8000;
1918 State.regs[OP[0]+1] = 0;
1919 State.F0 = 1;
1920 }
1921 else
1922 {
1923 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1924 State.regs[OP[0]+1] = tmp & 0xffff;
1925 State.F0 = 0;
1926 }
87178dbd 1927 trace_output (OP_DREG);
2934d1c9
MH		 1928}
1929
1930/* rachi */
1931void
1932OP_4201 ()
1933{
70ee56c5 1934 signed64 tmp;
4c38885c 1935 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1936
1937 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1938 State.F1 = State.F0;
1939 if (shift >=0)
70ee56c5 1940 tmp = SEXT40 (State.a[OP[1]]) << shift;
4c38885c 1941 else
70ee56c5 1942 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
4c38885c 1943 tmp += 0x8000;
63a91cfb 1944
70ee56c5 1945 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
4c38885c
MH		 1946 {
1947 State.regs[OP[0]] = 0x7fff;
1948 State.F0 = 1;
1949 }
70ee56c5 1950 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
4c38885c
MH		 1951 {
1952 State.regs[OP[0]] = 0x8000;
1953 State.F0 = 1;
1954 }
1955 else
1956 {
1957 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1958 State.F0 = 0;
1959 }
87178dbd 1960 trace_output (OP_REG);
2934d1c9
MH		 1961}
1962
1963/* rep */
1964void
1965OP_27000000 ()
1966{
87178dbd 1967 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1968 RPT_S = PC + 1;
1969 RPT_E = PC + OP[1];
1970 RPT_C = State.regs[OP[0]];
1971 State.RP = 1;
1972 if (RPT_C == 0)
1973 {
7eebfc62 1974 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1975 State.exception = SIGILL;
2934d1c9 1976 }
4c38885c
MH		 1977 if (OP[1] < 4)
1978 {
7eebfc62 1979 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1980 State.exception = SIGILL;
4c38885c 1981 }
87178dbd 1982 trace_output (OP_VOID);
2934d1c9
MH		 1983}
1984
1985/* repi */
1986void
1987OP_2F000000 ()
1988{
87178dbd 1989 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1990 RPT_S = PC + 1;
1991 RPT_E = PC + OP[1];
1992 RPT_C = OP[0];
1993 State.RP = 1;
1994 if (RPT_C == 0)
1995 {
7eebfc62 1996 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1997 State.exception = SIGILL;
4c38885c
MH		 1998 }
1999 if (OP[1] < 4)
2000 {
7eebfc62 2001 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 2002 State.exception = SIGILL;
2934d1c9 2003 }
87178dbd 2004 trace_output (OP_VOID);
2934d1c9
MH		 2005}
2006
2007/* rtd */
2008void
2009OP_5F60 ()
2010{
7eebfc62 2011 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 2012 State.exception = SIGILL;
2934d1c9
MH		 2013}
2014
2015/* rte */
2016void
2017OP_5F40 ()
2018{
87178dbd 2019 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 2020 PC = BPC;
2021 PSW = BPSW;
87178dbd 2022 trace_output (OP_VOID);
2934d1c9
MH		 2023}
2024
2025/* sadd */
2026void
2027OP_1223 ()
2028{
4c38885c 2029 int64 tmp;
87178dbd
MM		 2030
2031 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 2032 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 2033 if (State.ST)
2034 {
2035 if (tmp > MAX32)
2036 State.a[OP[0]] = MAX32;
2037 else if (tmp < MIN32)
2038 State.a[OP[0]] = MIN32;
2039 else
4f425a32 2040 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 2041 }
2042 else
4f425a32 2043 State.a[OP[0]] = tmp & MASK40;
87178dbd 2044 trace_output (OP_ACCUM);
2934d1c9
MH		 2045}
2046
2047/* setf0f */
2048void
2049OP_4611 ()
2050{
87178dbd 2051 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2052 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2053 trace_output (OP_REG);
2934d1c9
MH		 2054}
2055
2056/* setf0t */
2057void
2058OP_4613 ()
2059{
87178dbd 2060 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2061 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2062 trace_output (OP_REG);
2934d1c9
MH		 2063}
2064
2065/* sleep */
2066void
2067OP_5FC0 ()
2068{
87178dbd 2069 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2070 State.IE = 1;
87178dbd 2071 trace_output (OP_VOID);
2934d1c9
MH		 2072}
2073
2074/* sll */
2075void
2076OP_2200 ()
2077{
87178dbd 2078 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2079 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2080 trace_output (OP_REG);
2934d1c9
MH		 2081}
2082
2083/* sll */
2084void
2085OP_3200 ()
2086{
4c38885c 2087 int64 tmp;
87178dbd 2088 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2089 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2090 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2091 else
2092 {
2093 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2094 State.exception = SIGILL;
2095 return;
2096 }
4c38885c
MH		 2097
2098 if (State.ST)
2099 {
2100 if (tmp > MAX32)
2101 State.a[OP[0]] = MAX32;
2102 else if (tmp < 0xffffff80000000LL)
2103 State.a[OP[0]] = MIN32;
2104 else
2105 State.a[OP[0]] = tmp & MASK40;
2106 }
2107 else
2108 State.a[OP[0]] = tmp & MASK40;
87178dbd 2109 trace_output (OP_ACCUM);
2934d1c9
MH		 2110}
2111
2112/* slli */
2113void
2114OP_2201 ()
2115{
87178dbd 2116 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2117 State.regs[OP[0]] <<= OP[1];
87178dbd 2118 trace_output (OP_REG);
2934d1c9
MH		 2119}
2120
2121/* slli */
2122void
2123OP_3201 ()
2124{
4c38885c 2125 int64 tmp;
4f425a32
MH		 2126
2127 if (OP[1] == 0)
2128 OP[1] = 16;
4f425a32 2129
87178dbd 2130 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2131 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2132
2133 if (State.ST)
2134 {
2135 if (tmp > MAX32)
2136 State.a[OP[0]] = MAX32;
2137 else if (tmp < 0xffffff80000000LL)
2138 State.a[OP[0]] = MIN32;
2139 else
2140 State.a[OP[0]] = tmp & MASK40;
2141 }
2142 else
2143 State.a[OP[0]] = tmp & MASK40;
87178dbd 2144 trace_output (OP_ACCUM);
2934d1c9
MH		 2145}
2146
2147/* slx */
2148void
2149OP_460B ()
2150{
87178dbd 2151 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2152 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2153 trace_output (OP_REG);
2934d1c9
MH		 2154}
2155
2156/* sra */
2157void
2158OP_2400 ()
2159{
87178dbd 2160 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2161 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2162 trace_output (OP_REG);
2934d1c9
MH		 2163}
2164
2165/* sra */
2166void
2167OP_3400 ()
2168{
87178dbd 2169 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2170 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2171 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
069398aa
MM		 2172 else
2173 {
2174 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2175 State.exception = SIGILL;
2176 return;
2177 }
2178
87178dbd 2179 trace_output (OP_ACCUM);
2934d1c9
MH		 2180}
2181
2182/* srai */
2183void
2184OP_2401 ()
2185{
87178dbd 2186 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2187 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2188 trace_output (OP_REG);
2934d1c9
MH		 2189}
2190
2191/* srai */
2192void
2193OP_3401 ()
2194{
4f425a32
MH		 2195 if (OP[1] == 0)
2196 OP[1] = 16;
87178dbd
MM		 2197
2198 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2199 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
87178dbd 2200 trace_output (OP_ACCUM);
2934d1c9
MH		 2201}
2202
2203/* srl */
2204void
2205OP_2000 ()
2206{
87178dbd 2207 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2208 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2209 trace_output (OP_REG);
2934d1c9
MH		 2210}
2211
2212/* srl */
2213void
2214OP_3000 ()
2215{
87178dbd 2216 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2217 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2218 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
069398aa
MM		 2219 else
2220 {
2221 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2222 State.exception = SIGILL;
2223 return;
2224 }
2225
87178dbd 2226 trace_output (OP_ACCUM);
2934d1c9
MH		 2227}
2228
2229/* srli */
2230void
2231OP_2001 ()
2232{
87178dbd 2233 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2234 State.regs[OP[0]] >>= OP[1];
87178dbd 2235 trace_output (OP_REG);
2934d1c9
MH		 2236}
2237
2238/* srli */
2239void
2240OP_3001 ()
2241{
4f425a32
MH		 2242 if (OP[1] == 0)
2243 OP[1] = 16;
87178dbd
MM		 2244
2245 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2246 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
87178dbd 2247 trace_output (OP_ACCUM);
2934d1c9
MH		 2248}
2249
2250/* srx */
2251void
2252OP_4609 ()
2253{
2254 uint16 tmp;
87178dbd
MM		 2255
2256 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2257 tmp = State.F0 << 15;
2258 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2259 trace_output (OP_REG);
2934d1c9
MH		 2260}
2261
2262/* st */
2263void
2264OP_34000000 ()
2265{
87178dbd 2266 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2267 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2268 trace_output (OP_VOID);
2934d1c9
MH		 2269}
2270
2271/* st */
2272void
2273OP_6800 ()
2274{
87178dbd 2275 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2276 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2277 trace_output (OP_VOID);
2934d1c9
MH		 2278}
2279
2280/* st */
2281void
2282OP_6C1F ()
2283{
87178dbd 2284 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2285 if ( OP[1] != 15 )
2286 {
7eebfc62 2287 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2288 State.exception = SIGILL;
2289 return;
4c38885c
MH		 2290 }
2291 State.regs[OP[1]] -= 2;
2292 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2293 trace_output (OP_VOID);
2934d1c9
MH		 2294}
2295
2296/* st */
2297void
2298OP_6801 ()
2299{
87178dbd 2300 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2301 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2302 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2303 trace_output (OP_VOID);
2934d1c9
MH		 2304}
2305
2306/* st */
2307void
2308OP_6C01 ()
2309{
87178dbd 2310 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
fd435e9f
MM		 2311 if ( OP[1] == 15 )
2312 {
2313 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2314 State.exception = SIGILL;
2315 return;
2316 }
4c38885c 2317 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2318 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2319 trace_output (OP_VOID);
2934d1c9
MH		 2320}
2321
2322/* st2w */
2323void
2324OP_35000000 ()
2325{
87178dbd 2326 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2327 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2328 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2329 trace_output (OP_VOID);
2934d1c9
MH		 2330}
2331
2332/* st2w */
2333void
2334OP_6A00 ()
2335{
a18cb100 2336 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2337 SW (State.regs[OP[1]], State.regs[OP[0]]);
2338 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2339 trace_output (OP_VOID);
2934d1c9
MH		 2340}
2341
2342/* st2w */
2343void
2344OP_6E1F ()
2345{
a18cb100 2346 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2347 if ( OP[1] != 15 )
2348 {
7eebfc62 2349 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2350 State.exception = SIGILL;
2351 return;
4c38885c
MH		 2352 }
2353 State.regs[OP[1]] -= 4;
2354 SW (State.regs[OP[1]], State.regs[OP[0]]);
2355 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2356 trace_output (OP_VOID);
2934d1c9
MH		 2357}
2358
2359/* st2w */
2360void
2361OP_6A01 ()
2362{
1155e06e 2363 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2364 SW (State.regs[OP[1]], State.regs[OP[0]]);
2365 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2366 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2367 trace_output (OP_VOID);
2934d1c9
MH		 2368}
2369
2370/* st2w */
2371void
2372OP_6E01 ()
2373{
1155e06e
FF		 2374 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2375 if ( OP[1] == 15 )
2376 {
2377 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2378 State.exception = SIGILL;
2379 return;
2380 }
4c38885c
MH		 2381 SW (State.regs[OP[1]], State.regs[OP[0]]);
2382 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2383 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2384 trace_output (OP_VOID);
2934d1c9
MH		 2385}
2386
2387/* stb */
2388void
2389OP_3C000000 ()
2390{
87178dbd 2391 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2392 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2393 trace_output (OP_VOID);
2934d1c9
MH		 2394}
2395
2396/* stb */
2397void
2398OP_7800 ()
2399{
87178dbd 2400 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2401 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2402 trace_output (OP_VOID);
2934d1c9
MH		 2403}
2404
2405/* stop */
2406void
2407OP_5FE0 ()
2408{
87178dbd 2409 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2410 State.exception = SIG_D10V_STOP;
87178dbd 2411 trace_output (OP_VOID);
2934d1c9
MH		 2412}
2413
2414/* sub */
2415void
2416OP_0 ()
4c38885c 2417{
f4b022d3 2418 uint16 tmp;
87178dbd
MM		 2419
2420 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
f4b022d3
MM		 2421 tmp = State.regs[OP[0]] - State.regs[OP[1]];
2422 State.C = (tmp > State.regs[OP[0]]);
2423 State.regs[OP[0]] = tmp;
87178dbd 2424 trace_output (OP_REG);
4c38885c
MH		 2425}
2426
2427/* sub */
2428void
2429OP_1001 ()
2430{
4f425a32 2431 int64 tmp;
87178dbd
MM		 2432
2433 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2434 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2435 if (State.ST)
2436 {
2437 if ( tmp > MAX32)
2438 State.a[OP[0]] = MAX32;
2439 else if ( tmp < MIN32)
2440 State.a[OP[0]] = MIN32;
2441 else
2442 State.a[OP[0]] = tmp & MASK40;
2443 }
2444 else
2445 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2446
2447 trace_output (OP_ACCUM);
4c38885c
MH		 2448}
2449
2450/* sub */
2451
2452void
2453OP_1003 ()
2934d1c9 2454{
4f425a32 2455 int64 tmp;
87178dbd
MM		 2456
2457 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2458 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2459 if (State.ST)
2460 {
2461 if (tmp > MAX32)
2462 State.a[OP[0]] = MAX32;
2463 else if ( tmp < MIN32)
2464 State.a[OP[0]] = MIN32;
2465 else
2466 State.a[OP[0]] = tmp & MASK40;
2467 }
2468 else
2469 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2470
2471 trace_output (OP_ACCUM);
2934d1c9
MH		 2472}
2473
2474/* sub2w */
2475void
2476OP_1000 ()
2477{
f4b022d3 2478 uint32 tmp,a,b;
4c38885c 2479
87178dbd 2480 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 2481 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2482 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
70ee56c5
AC		 2483 /* see ../common/sim-alu.h for a more extensive discussion on how to
2484 compute the carry/overflow bits */
2485 tmp = a - b;
2486 State.C = (a < b);
4c38885c
MH		 2487 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2488 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2489 trace_output (OP_DREG);
2934d1c9
MH		 2490}
2491
2492/* subac3 */
2493void
2494OP_17000000 ()
2495{
4f425a32 2496 int64 tmp;
87178dbd
MM		 2497
2498 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2499 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2500 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2501 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2502 trace_output (OP_DREG);
2934d1c9
MH		 2503}
2504
2505/* subac3 */
2506void
2507OP_17000002 ()
2508{
4f425a32 2509 int64 tmp;
87178dbd
MM		 2510
2511 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2512 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2513 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2514 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2515 trace_output (OP_DREG);
2934d1c9
MH		 2516}
2517
2518/* subac3s */
2519void
2520OP_17001000 ()
2521{
4f425a32 2522 int64 tmp;
87178dbd
MM		 2523
2524 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2525 State.F1 = State.F0;
2526 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2527 if ( tmp > MAX32)
2528 {
2529 State.regs[OP[0]] = 0x7fff;
2530 State.regs[OP[0]+1] = 0xffff;
2531 State.F0 = 1;
2532 }
2533 else if (tmp < MIN32)
2534 {
2535 State.regs[OP[0]] = 0x8000;
2536 State.regs[OP[0]+1] = 0;
2537 State.F0 = 1;
2538 }
2539 else
2540 {
2541 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2542 State.regs[OP[0]+1] = tmp & 0xffff;
2543 State.F0 = 0;
2544 }
87178dbd 2545 trace_output (OP_DREG);
2934d1c9
MH		 2546}
2547
2548/* subac3s */
2549void
2550OP_17001002 ()
2551{
4f425a32 2552 int64 tmp;
87178dbd
MM		 2553
2554 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2555 State.F1 = State.F0;
2556 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2557 if ( tmp > MAX32)
2558 {
2559 State.regs[OP[0]] = 0x7fff;
2560 State.regs[OP[0]+1] = 0xffff;
2561 State.F0 = 1;
2562 }
2563 else if (tmp < MIN32)
2564 {
2565 State.regs[OP[0]] = 0x8000;
2566 State.regs[OP[0]+1] = 0;
2567 State.F0 = 1;
2568 }
2569 else
2570 {
2571 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2572 State.regs[OP[0]+1] = tmp & 0xffff;
2573 State.F0 = 0;
2574 }
87178dbd 2575 trace_output (OP_DREG);
2934d1c9
MH		 2576}
2577
2578/* subi */
2579void
2580OP_1 ()
2581{
70ee56c5 2582 unsigned tmp;
4f425a32
MH		 2583 if (OP[1] == 0)
2584 OP[1] = 16;
87178dbd
MM		 2585
2586 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
70ee56c5
AC		 2587 /* see ../common/sim-alu.h for a more extensive discussion on how to
2588 compute the carry/overflow bits */
2589 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2590 + (unsigned)(unsigned16) ( - OP[1]));
2591 State.C = (tmp >= (1 << 16));
2592 State.regs[OP[0]] = tmp;
87178dbd 2593 trace_output (OP_REG);
2934d1c9
MH		 2594}
2595
2596/* trap */
2597void
2598OP_5F00 ()
2599{
a5719092 2600 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2601 trace_output (OP_VOID);
8918b3a7 2602
63a91cfb 2603 switch (OP[0])
2934d1c9 2604 {
63a91cfb 2605 default:
19d44375 2606#if 0
7eebfc62 2607 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb 2608 State.exception = SIGILL;
19d44375
MM		 2609#else
2610 /* Use any other traps for batch debugging. */
2611 {
2612 int i;
2613 static int first_time = 1;
2614
2615 if (first_time)
2616 {
2617 first_time = 0;
2618 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2619 for (i = 0; i < 16; i++)
2620 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2621 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2622 }
2623
87e43259 2624 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
19d44375 2625
87e43259
AC		 2626 for (i = 0; i < 16; i++)
2627 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
19d44375 2628
87e43259
AC		 2629 for (i = 0; i < 2; i++)
2630 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2631 ((int)(State.a[i] >> 32) & 0xff),
2632 ((unsigned long)State.a[i]) & 0xffffffff);
19d44375 2633
87e43259
AC		 2634 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2635 State.F0 != 0, State.F1 != 0, State.C != 0);
2636 (*d10v_callback->flush_stdout) (d10v_callback);
2637 break;
2638 }
19d44375 2639#endif
63a91cfb 2640
87e43259
AC		 2641 case 0: /* old system call trap, to be deleted */
2642 case 15: /* new system call trap */
2643 /* Trap 15 is used for simulating low-level I/O */
63a91cfb 2644 {
63a91cfb
MM		 2645 errno = 0;
2646
2647/* Registers passed to trap 0 */
2648
65c0d7de
MA		 2649#define FUNC State.regs[6] /* function number */
2650#define PARM1 State.regs[2] /* optional parm 1 */
2651#define PARM2 State.regs[3] /* optional parm 2 */
2652#define PARM3 State.regs[4] /* optional parm 3 */
2653#define PARM4 State.regs[5] /* optional parm 3 */
63a91cfb
MM		 2654
2655/* Registers set by trap 0 */
2656
65c0d7de
MA		 2657#define RETVAL State.regs[2] /* return value */
2658#define RETVAL_HIGH State.regs[2] /* return value */
2659#define RETVAL_LOW State.regs[3] /* return value */
2660#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2661
2662/* Turn a pointer in a register into a pointer into real memory. */
2663
c422ecc7 2664#define MEMPTR(x) ((char *)(dmem_addr(x)))
63a91cfb
MM		 2665
2666 switch (FUNC)
2667 {
2668#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2669 case SYS_fork:
2670 RETVAL = fork ();
8918b3a7
MM		 2671 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2672 trace_output (OP_R2);
63a91cfb 2673 break;
8918b3a7 2674
57bc1a72
MM		 2675 case SYS_getpid:
2676 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2677 RETVAL = getpid ();
2678 trace_output (OP_R2);
2679 break;
2680
2681 case SYS_kill:
2682 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2683 if (PARM1 == getpid ())
2684 {
2685 trace_output (OP_VOID);
2686 State.exception = PARM2;
2687 }
2688 else
2689 {
2690 int os_sig = -1;
2691 switch (PARM2)
2692 {
2693#ifdef SIGHUP
2694 case 1: os_sig = SIGHUP; break;
2695#endif
2696#ifdef SIGINT
2697 case 2: os_sig = SIGINT; break;
2698#endif
2699#ifdef SIGQUIT
2700 case 3: os_sig = SIGQUIT; break;
2701#endif
2702#ifdef SIGILL
2703 case 4: os_sig = SIGILL; break;
2704#endif
2705#ifdef SIGTRAP
2706 case 5: os_sig = SIGTRAP; break;
2707#endif
2708#ifdef SIGABRT
2709 case 6: os_sig = SIGABRT; break;
2710#elif defined(SIGIOT)
2711 case 6: os_sig = SIGIOT; break;
2712#endif
2713#ifdef SIGEMT
2714 case 7: os_sig = SIGEMT; break;
2715#endif
2716#ifdef SIGFPE
2717 case 8: os_sig = SIGFPE; break;
2718#endif
2719#ifdef SIGKILL
2720 case 9: os_sig = SIGKILL; break;
2721#endif
2722#ifdef SIGBUS
2723 case 10: os_sig = SIGBUS; break;
2724#endif
2725#ifdef SIGSEGV
2726 case 11: os_sig = SIGSEGV; break;
2727#endif
2728#ifdef SIGSYS
2729 case 12: os_sig = SIGSYS; break;
2730#endif
2731#ifdef SIGPIPE
2732 case 13: os_sig = SIGPIPE; break;
2733#endif
2734#ifdef SIGALRM
2735 case 14: os_sig = SIGALRM; break;
2736#endif
2737#ifdef SIGTERM
2738 case 15: os_sig = SIGTERM; break;
2739#endif
2740#ifdef SIGURG
2741 case 16: os_sig = SIGURG; break;
2742#endif
2743#ifdef SIGSTOP
2744 case 17: os_sig = SIGSTOP; break;
2745#endif
2746#ifdef SIGTSTP
2747 case 18: os_sig = SIGTSTP; break;
2748#endif
2749#ifdef SIGCONT
2750 case 19: os_sig = SIGCONT; break;
2751#endif
2752#ifdef SIGCHLD
2753 case 20: os_sig = SIGCHLD; break;
2754#elif defined(SIGCLD)
2755 case 20: os_sig = SIGCLD; break;
2756#endif
2757#ifdef SIGTTIN
2758 case 21: os_sig = SIGTTIN; break;
2759#endif
2760#ifdef SIGTTOU
2761 case 22: os_sig = SIGTTOU; break;
2762#endif
2763#ifdef SIGIO
2764 case 23: os_sig = SIGIO; break;
2765#elif defined (SIGPOLL)
2766 case 23: os_sig = SIGPOLL; break;
2767#endif
2768#ifdef SIGXCPU
2769 case 24: os_sig = SIGXCPU; break;
2770#endif
2771#ifdef SIGXFSZ
2772 case 25: os_sig = SIGXFSZ; break;
2773#endif
2774#ifdef SIGVTALRM
2775 case 26: os_sig = SIGVTALRM; break;
2776#endif
2777#ifdef SIGPROF
2778 case 27: os_sig = SIGPROF; break;
2779#endif
2780#ifdef SIGWINCH
2781 case 28: os_sig = SIGWINCH; break;
2782#endif
2783#ifdef SIGLOST
2784 case 29: os_sig = SIGLOST; break;
2785#endif
2786#ifdef SIGUSR1
2787 case 30: os_sig = SIGUSR1; break;
2788#endif
2789#ifdef SIGUSR2
2790 case 31: os_sig = SIGUSR2; break;
2791#endif
2792 }
2793
2794 if (os_sig == -1)
2795 {
2796 trace_output (OP_VOID);
2797 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
fd435e9f 2798 (*d10v_callback->flush_stdout) (d10v_callback);
57bc1a72
MM		 2799 State.exception = SIGILL;
2800 }
2801 else
2802 {
2803 RETVAL = kill (PARM1, PARM2);
2804 trace_output (OP_R2);
2805 }
2806 }
2807 break;
2808
63a91cfb
MM		 2809 case SYS_execve:
2810 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2811 (char **)MEMPTR (PARM3));
8918b3a7
MM		 2812 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2813 trace_output (OP_R2);
63a91cfb 2814 break;
8918b3a7 2815
87e43259 2816#ifdef SYS_execv
63a91cfb
MM		 2817 case SYS_execv:
2818 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
8918b3a7
MM		 2819 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2820 trace_output (OP_R2);
63a91cfb 2821 break;
87e43259 2822#endif
8918b3a7 2823
63a91cfb
MM		 2824 case SYS_pipe:
2825 {
2826 reg_t buf;
2827 int host_fd[2];
2828
2829 buf = PARM1;
2830 RETVAL = pipe (host_fd);
2831 SW (buf, host_fd[0]);
2832 buf += sizeof(uint16);
2833 SW (buf, host_fd[1]);
8918b3a7
MM		 2834 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2835 trace_output (OP_R2);
63a91cfb
MM		 2836 }
2837 break;
8918b3a7 2838
87e43259 2839#ifdef SYS_wait
63a91cfb
MM		 2840 case SYS_wait:
2841 {
2842 int status;
2843
2844 RETVAL = wait (&status);
8918b3a7
MM		 2845 if (PARM1)
2846 SW (PARM1, status);
2847 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2848 trace_output (OP_R2);
63a91cfb
MM		 2849 }
2850 break;
87e43259 2851#endif
57bc1a72
MM		 2852#else
2853 case SYS_getpid:
2854 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2855 RETVAL = 1;
2856 trace_output (OP_R2);
2857 break;
2858
2859 case SYS_kill:
2860 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2861 trace_output (OP_VOID);
2862 State.exception = PARM2;
2863 break;
63a91cfb 2864#endif
8918b3a7 2865
63a91cfb
MM		 2866 case SYS_read:
2867 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2868 PARM3);
8918b3a7
MM		 2869 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2870 trace_output (OP_R2);
63a91cfb 2871 break;
8918b3a7 2872
63a91cfb
MM		 2873 case SYS_write:
2874 if (PARM1 == 1)
2875 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2876 MEMPTR (PARM2), PARM3);
2877 else
2878 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2879 MEMPTR (PARM2), PARM3);
8918b3a7
MM		 2880 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2881 trace_output (OP_R2);
63a91cfb 2882 break;
8918b3a7 2883
63a91cfb 2884 case SYS_lseek:
65c0d7de
MA		 2885 {
2886 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2887 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2888 PARM4);
2889 RETVAL_HIGH = ret >> 16;
2890 RETVAL_LOW = ret & 0xffff;
2891 }
8918b3a7
MM		 2892 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2893 trace_output (OP_R2R3);
63a91cfb 2894 break;
8918b3a7 2895
63a91cfb
MM		 2896 case SYS_close:
2897 RETVAL = d10v_callback->close (d10v_callback, PARM1);
8918b3a7
MM		 2898 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2899 trace_output (OP_R2);
63a91cfb 2900 break;
8918b3a7 2901
63a91cfb
MM		 2902 case SYS_open:
2903 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2904 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2905 trace_output (OP_R2);
2906 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2907 trace_output (OP_R2);
63a91cfb 2908 break;
8918b3a7 2909
63a91cfb 2910 case SYS_exit:
a49a15ad 2911 State.exception = SIG_D10V_EXIT;
8918b3a7
MM		 2912 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2913 trace_output (OP_VOID);
63a91cfb 2914 break;
63a91cfb 2915
8719be26 2916 case SYS_stat:
63a91cfb
MM		 2917 /* stat system call */
2918 {
2919 struct stat host_stat;
2920 reg_t buf;
2921
2922 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2923
2924 buf = PARM2;
2925
2926 /* The hard-coded offsets and sizes were determined by using
2927 * the D10V compiler on a test program that used struct stat.
2928 */
2929 SW (buf, host_stat.st_dev);
2930 SW (buf+2, host_stat.st_ino);
2931 SW (buf+4, host_stat.st_mode);
2932 SW (buf+6, host_stat.st_nlink);
2933 SW (buf+8, host_stat.st_uid);
2934 SW (buf+10, host_stat.st_gid);
2935 SW (buf+12, host_stat.st_rdev);
2936 SLW (buf+16, host_stat.st_size);
2937 SLW (buf+20, host_stat.st_atime);
2938 SLW (buf+28, host_stat.st_mtime);
2939 SLW (buf+36, host_stat.st_ctime);
2940 }
8918b3a7
MM		 2941 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2942 trace_output (OP_R2);
63a91cfb 2943 break;
63a91cfb 2944
63a91cfb
MM		 2945 case SYS_chown:
2946 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
8918b3a7
MM		 2947 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2948 trace_output (OP_R2);
63a91cfb 2949 break;
8918b3a7 2950
63a91cfb
MM		 2951 case SYS_chmod:
2952 RETVAL = chmod (MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2953 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2954 trace_output (OP_R2);
63a91cfb 2955 break;
8918b3a7 2956
87e43259 2957#ifdef SYS_utime
63a91cfb
MM		 2958 case SYS_utime:
2959 /* Cast the second argument to void *, to avoid type mismatch
2960 if a prototype is present. */
2961 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
8918b3a7
MM		 2962 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2963 trace_output (OP_R2);
2964 break;
87e43259 2965#endif
8918b3a7 2966
87e43259 2967#ifdef SYS_time
8918b3a7
MM		 2968 case SYS_time:
2969 {
2970 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2971 RETVAL_HIGH = ret >> 16;
2972 RETVAL_LOW = ret & 0xffff;
2973 }
2974 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2975 trace_output (OP_R2R3);
63a91cfb 2976 break;
87e43259 2977#endif
8918b3a7 2978
63a91cfb
MM		 2979 default:
2980 abort ();
2981 }
87e43259 2982 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
63a91cfb
MM		 2983 break;
2984 }
2934d1c9
MH		 2985 }
2986}
2987
2988/* tst0i */
2989void
2990OP_7000000 ()
2991{
87178dbd 2992 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2993 State.F1 = State.F0;
4f425a32 2994 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 2995 trace_output (OP_FLAG);
2934d1c9
MH		 2996}
2997
2998/* tst1i */
2999void
3000OP_F000000 ()
3001{
87178dbd 3002 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3003 State.F1 = State.F0;
4f425a32 3004 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 3005 trace_output (OP_FLAG);
2934d1c9
MH		 3006}
3007
3008/* wait */
3009void
3010OP_5F80 ()
3011{
87178dbd 3012 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 3013 State.IE = 1;
87178dbd 3014 trace_output (OP_VOID);
2934d1c9
MH		 3015}
3016
3017/* xor */
3018void
3019OP_A00 ()
3020{
87178dbd 3021 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 3022 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 3023 trace_output (OP_REG);
2934d1c9
MH		 3024}
3025
3026/* xor3 */
3027void
3028OP_5000000 ()
3029{
87178dbd 3030 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 3031 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 3032 trace_output (OP_REG);
2934d1c9
MH		 3033}
3034
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