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Correct trap tracing information
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
4f425a32 1#include <signal.h>
63a91cfb
MM		 2#include <errno.h>
3#include <sys/types.h>
4#include <sys/stat.h>
5#include <unistd.h>
6
2934d1c9
MH		 7#include "d10v_sim.h"
8#include "simops.h"
8719be26 9#include "sys/syscall.h"
2934d1c9 10
87178dbd
MM		 11enum op_types {
12 OP_VOID,
13 OP_REG,
14 OP_REG_OUTPUT,
15 OP_DREG,
16 OP_DREG_OUTPUT,
17 OP_ACCUM,
18 OP_ACCUM_OUTPUT,
19 OP_ACCUM_REVERSE,
20 OP_CR,
21 OP_CR_OUTPUT,
22 OP_CR_REVERSE,
23 OP_FLAG,
60fc5b72 24 OP_FLAG_OUTPUT,
87178dbd
MM		 25 OP_CONSTANT16,
26 OP_CONSTANT3,
27 OP_CONSTANT4,
28 OP_MEMREF,
29 OP_MEMREF2,
30 OP_POSTDEC,
31 OP_POSTINC,
32 OP_PREDEC
33};
34
7eebfc62 35#ifdef DEBUG
87178dbd
MM		 36static void trace_input PARAMS ((char *name,
37 enum op_types in1,
38 enum op_types in2,
39 enum op_types in3));
40
41static void trace_output PARAMS ((enum op_types result));
42
43#ifndef SIZE_INSTRUCTION
44#define SIZE_INSTRUCTION 10
45#endif
46
47#ifndef SIZE_OPERANDS
48#define SIZE_OPERANDS 24
49#endif
50
51#ifndef SIZE_VALUES
52#define SIZE_VALUES 13
53#endif
54
55static void
56trace_input (name, in1, in2, in3)
57 char *name;
58 enum op_types in1;
59 enum op_types in2;
60 enum op_types in3;
61{
62 char *comma;
63 enum op_types in[3];
64 int i;
65 char buf[80];
66 char *p;
67 long tmp;
68 char *type;
69
7eebfc62
MM		 70 if ((d10v_debug & DEBUG_TRACE) == 0)
71 return;
72
87178dbd
MM		 73 switch (State.ins_type)
74 {
75 default:
76 case INS_UNKNOWN: type = " ?"; break;
77 case INS_LEFT: type = " L"; break;
78 case INS_RIGHT: type = " R"; break;
79 case INS_LEFT_PARALLEL: type = "*L"; break;
80 case INS_RIGHT_PARALLEL: type = "*R"; break;
81 case INS_LONG: type = " B"; break;
82 }
83
7eebfc62
MM		 84 (*d10v_callback->printf_filtered) (d10v_callback,
85 "0x%.6x %s: %-*s",
86 (unsigned)PC, type,
87 SIZE_INSTRUCTION, name);
87178dbd
MM		 88
89 in[0] = in1;
90 in[1] = in2;
91 in[2] = in3;
92 comma = "";
93 p = buf;
94 for (i = 0; i < 3; i++)
95 {
96 switch (in[i])
97 {
98 case OP_VOID:
99 break;
100
101 case OP_REG:
102 case OP_REG_OUTPUT:
103 case OP_DREG:
104 case OP_DREG_OUTPUT:
105 sprintf (p, "%sr%d", comma, OP[i]);
106 p += strlen (p);
107 comma = ",";
108 break;
109
110 case OP_CR:
111 case OP_CR_OUTPUT:
112 case OP_CR_REVERSE:
113 sprintf (p, "%scr%d", comma, OP[i]);
114 p += strlen (p);
115 comma = ",";
116 break;
117
118 case OP_ACCUM:
119 case OP_ACCUM_OUTPUT:
120 case OP_ACCUM_REVERSE:
121 sprintf (p, "%sa%d", comma, OP[i]);
122 p += strlen (p);
123 comma = ",";
124 break;
125
126 case OP_CONSTANT16:
127 sprintf (p, "%s%d", comma, OP[i]);
128 p += strlen (p);
129 comma = ",";
130 break;
131
132 case OP_CONSTANT4:
133 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
134 p += strlen (p);
135 comma = ",";
136 break;
137
138 case OP_CONSTANT3:
139 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
140 p += strlen (p);
141 comma = ",";
142 break;
143
144 case OP_MEMREF:
145 sprintf (p, "%s@r%d", comma, OP[i]);
146 p += strlen (p);
147 comma = ",";
148 break;
149
150 case OP_MEMREF2:
151 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
152 p += strlen (p);
153 comma = ",";
154 break;
155
156 case OP_POSTINC:
157 sprintf (p, "%s@r%d+", comma, OP[i]);
158 p += strlen (p);
159 comma = ",";
160 break;
161
162 case OP_POSTDEC:
163 sprintf (p, "%s@r%d-", comma, OP[i]);
164 p += strlen (p);
165 comma = ",";
166 break;
167
168 case OP_PREDEC:
169 sprintf (p, "%s@-r%d", comma, OP[i]);
170 p += strlen (p);
171 comma = ",";
172 break;
173
174 case OP_FLAG:
60fc5b72 175 case OP_FLAG_OUTPUT:
87178dbd
MM		 176 if (OP[i] == 0)
177 sprintf (p, "%sf0", comma);
178
179 else if (OP[i] == 1)
180 sprintf (p, "%sf1", comma);
181
182 else
60fc5b72 183 sprintf (p, "%sc", comma);
87178dbd
MM		 184
185 p += strlen (p);
186 comma = ",";
187 break;
188 }
189 }
190
7eebfc62
MM		 191 if ((d10v_debug & DEBUG_VALUES) == 0)
192 {
193 *p++ = '\n';
194 *p = '\0';
195 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
196 }
197 else
198 {
199 *p = '\0';
200 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 201
7eebfc62
MM		 202 p = buf;
203 for (i = 0; i < 3; i++)
204 {
205 buf[0] = '\0';
206 switch (in[i])
207 {
208 case OP_VOID:
209 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
210 break;
211
212 case OP_REG_OUTPUT:
213 case OP_DREG_OUTPUT:
214 case OP_CR_OUTPUT:
215 case OP_ACCUM_OUTPUT:
60fc5b72 216 case OP_FLAG_OUTPUT:
7eebfc62
MM		 217 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
218 break;
219
220 case OP_REG:
221 case OP_MEMREF:
222 case OP_POSTDEC:
223 case OP_POSTINC:
224 case OP_PREDEC:
225 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
226 (uint16)State.regs[OP[i]]);
227 break;
228
229 case OP_DREG:
230 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
231 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
232 break;
233
234 case OP_CR:
235 case OP_CR_REVERSE:
236 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
237 (uint16)State.cregs[OP[i]]);
238 break;
239
240 case OP_ACCUM:
241 case OP_ACCUM_REVERSE:
242 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
243 ((int)(State.a[OP[i]] >> 32) & 0xff),
244 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
245 break;
246
247 case OP_CONSTANT16:
248 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
249 (uint16)OP[i]);
250 break;
251
252 case OP_CONSTANT4:
253 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
254 (uint16)SEXT4(OP[i]));
255 break;
256
257 case OP_CONSTANT3:
258 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
259 (uint16)SEXT3(OP[i]));
260 break;
261
262 case OP_FLAG:
263 if (OP[i] == 0)
264 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
265 State.F0 != 0);
266
267 else if (OP[i] == 1)
268 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
269 State.F1 != 0);
270
271 else
272 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
273 State.C != 0);
274
275 break;
276
277 case OP_MEMREF2:
278 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
279 (uint16)OP[i]);
280 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
281 (uint16)State.regs[OP[++i]]);
282 break;
283 }
284 }
285 }
286}
87178dbd 287
7eebfc62
MM		 288static void
289trace_output (result)
290 enum op_types result;
291{
292 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 293 {
7eebfc62 294 long tmp;
87178dbd 295
7eebfc62
MM		 296 switch (result)
297 {
298 default:
299 putchar ('\n');
87178dbd
MM		 300 break;
301
302 case OP_REG:
7eebfc62
MM		 303 case OP_REG_OUTPUT:
304 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
305 (uint16)State.regs[OP[0]],
306 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 307 break;
308
309 case OP_DREG:
7eebfc62
MM		 310 case OP_DREG_OUTPUT:
311 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
312 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
313 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 314 break;
315
316 case OP_CR:
7eebfc62
MM		 317 case OP_CR_OUTPUT:
318 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
319 (uint16)State.cregs[OP[0]],
320 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 321 break;
322
7eebfc62
MM		 323 case OP_CR_REVERSE:
324 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
325 (uint16)State.cregs[OP[1]],
326 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 327 break;
328
7eebfc62
MM		 329 case OP_ACCUM:
330 case OP_ACCUM_OUTPUT:
069398aa 331 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 332 ((int)(State.a[OP[0]] >> 32) & 0xff),
333 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
334 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 335 break;
336
7eebfc62 337 case OP_ACCUM_REVERSE:
069398aa 338 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 339 ((int)(State.a[OP[1]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
341 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 342 break;
343
344 case OP_FLAG:
60fc5b72 345 case OP_FLAG_OUTPUT:
7eebfc62
MM		 346 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
347 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 348 break;
349 }
350 }
87178dbd
MM		 351}
352
353#else
354#define trace_input(NAME, IN1, IN2, IN3)
355#define trace_output(RESULT)
356#endif
2934d1c9
MH		 357
358/* abs */
359void
360OP_4607 ()
361{
87178dbd 362 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 363 State.F1 = State.F0;
364 if ((int16)(State.regs[OP[0]]) < 0)
365 {
366 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
367 State.F0 = 1;
368 }
369 else
370 State.F0 = 0;
87178dbd 371 trace_output (OP_REG);
2934d1c9
MH		 372}
373
374/* abs */
375void
376OP_5607 ()
377{
378 int64 tmp;
379
87178dbd 380 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 381 State.F1 = State.F0;
382 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
383
4c38885c 384 if (State.a[OP[0]] < 0 )
2934d1c9 385 {
4c38885c 386 tmp = -State.a[OP[0]];
2934d1c9
MH		 387 if (State.ST)
388 {
4c38885c 389 if (tmp > MAX32)
2934d1c9 390 State.a[OP[0]] = MAX32;
4c38885c 391 else if (tmp < MIN32)
2934d1c9
MH		 392 State.a[OP[0]] = MIN32;
393 else
4f425a32 394 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 395 }
396 else
4f425a32 397 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 398 State.F0 = 1;
399 }
400 else
401 State.F0 = 0;
87178dbd 402 trace_output (OP_ACCUM);
2934d1c9
MH		 403}
404
405/* add */
406void
407OP_200 ()
408{
409 uint16 tmp = State.regs[OP[0]];
87178dbd 410 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 411 State.regs[OP[0]] += State.regs[OP[1]];
412 if ( tmp > State.regs[OP[0]])
413 State.C = 1;
414 else
415 State.C = 0;
87178dbd 416 trace_output (OP_REG);
2934d1c9
MH		 417}
418
419/* add */
420void
421OP_1201 ()
422{
4c38885c 423 int64 tmp;
4f425a32 424 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 425
426 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 427 if (State.ST)
428 {
429 if ( tmp > MAX32)
430 State.a[OP[0]] = MAX32;
431 else if ( tmp < MIN32)
432 State.a[OP[0]] = MIN32;
433 else
4f425a32 434 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 435 }
436 else
4f425a32 437 State.a[OP[0]] = tmp & MASK40;
87178dbd 438 trace_output (OP_ACCUM);
2934d1c9
MH		 439}
440
441/* add */
442void
443OP_1203 ()
444{
4c38885c 445 int64 tmp;
4f425a32 446 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 447
448 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 449 if (State.ST)
450 {
451 if (tmp > MAX32)
452 State.a[OP[0]] = MAX32;
453 else if ( tmp < MIN32)
454 State.a[OP[0]] = MIN32;
455 else
4f425a32 456 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 457 }
458 else
4f425a32 459 State.a[OP[0]] = tmp & MASK40;
87178dbd 460 trace_output (OP_ACCUM);
2934d1c9
MH		 461}
462
463/* add2w */
464void
465OP_1200 ()
466{
467 uint32 tmp;
468 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
469 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 470
471 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
2934d1c9
MH		 472 tmp = tmp1 + tmp2;
473 if ( (tmp < tmp1) || (tmp < tmp2) )
474 State.C = 1;
475 else
476 State.C = 0;
477 State.regs[OP[0]] = tmp >> 16;
478 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 479 trace_output (OP_DREG);
2934d1c9
MH		 480}
481
482/* add3 */
483void
484OP_1000000 ()
485{
486 uint16 tmp = State.regs[OP[0]];
2934d1c9 487 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
87178dbd
MM		 488
489 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9
MH		 490 if ( tmp > State.regs[OP[0]])
491 State.C = 1;
492 else
493 State.C = 0;
87178dbd 494 trace_output (OP_REG);
2934d1c9
MH		 495}
496
497/* addac3 */
498void
499OP_17000200 ()
500{
4c38885c 501 int64 tmp;
4f425a32 502 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 503
504 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 505 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
506 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 507 trace_output (OP_DREG);
2934d1c9
MH		 508}
509
510/* addac3 */
511void
512OP_17000202 ()
513{
4c38885c 514 int64 tmp;
4f425a32 515 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 516
517 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 518 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
519 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 520 trace_output (OP_DREG);
2934d1c9
MH		 521}
522
523/* addac3s */
524void
525OP_17001200 ()
526{
4c38885c 527 int64 tmp;
4c38885c 528 State.F1 = State.F0;
87178dbd
MM		 529
530 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 531 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 532 if ( tmp > MAX32)
533 {
534 State.regs[OP[0]] = 0x7fff;
535 State.regs[OP[0]+1] = 0xffff;
536 State.F0 = 1;
537 }
538 else if (tmp < MIN32)
539 {
540 State.regs[OP[0]] = 0x8000;
541 State.regs[OP[0]+1] = 0;
542 State.F0 = 1;
543 }
544 else
545 {
546 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
547 State.regs[OP[0]+1] = tmp & 0xffff;
548 State.F0 = 0;
549 }
87178dbd 550 trace_output (OP_DREG);
2934d1c9
MH		 551}
552
553/* addac3s */
554void
555OP_17001202 ()
556{
4c38885c 557 int64 tmp;
4c38885c 558 State.F1 = State.F0;
87178dbd
MM		 559
560 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 561 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 562 if ( tmp > MAX32)
563 {
564 State.regs[OP[0]] = 0x7fff;
565 State.regs[OP[0]+1] = 0xffff;
566 State.F0 = 1;
567 }
568 else if (tmp < MIN32)
569 {
570 State.regs[OP[0]] = 0x8000;
571 State.regs[OP[0]+1] = 0;
572 State.F0 = 1;
573 }
574 else
575 {
576 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
577 State.regs[OP[0]+1] = tmp & 0xffff;
578 State.F0 = 0;
579 }
87178dbd 580 trace_output (OP_DREG);
2934d1c9
MH		 581}
582
583/* addi */
584void
585OP_201 ()
586{
2254cd90 587 uint tmp = State.regs[OP[0]];
4f425a32
MH		 588 if (OP[1] == 0)
589 OP[1] = 16;
87178dbd 590 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 591 State.regs[OP[0]] += OP[1];
2254cd90
MM		 592 if (tmp > State.regs[OP[0]])
593 State.C = 1;
594 else
595 State.C = 0;
87178dbd 596 trace_output (OP_REG);
2934d1c9
MH		 597}
598
599/* and */
600void
601OP_C00 ()
602{
87178dbd 603 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 604 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 605 trace_output (OP_REG);
2934d1c9
MH		 606}
607
608/* and3 */
609void
610OP_6000000 ()
611{
87178dbd 612 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 613 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 614 trace_output (OP_REG);
2934d1c9
MH		 615}
616
617/* bclri */
618void
619OP_C01 ()
620{
87178dbd 621 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 622 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 623 trace_output (OP_REG);
2934d1c9
MH		 624}
625
626/* bl.s */
627void
628OP_4900 ()
629{
87178dbd 630 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 631 State.regs[13] = PC+1;
632 PC += SEXT8 (OP[0]);
87178dbd 633 trace_output (OP_VOID);
2934d1c9
MH		 634}
635
636/* bl.l */
637void
638OP_24800000 ()
639{
87178dbd 640 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 641 State.regs[13] = PC+1;
642 PC += OP[0];
87178dbd 643 trace_output (OP_VOID);
2934d1c9
MH		 644}
645
646/* bnoti */
647void
648OP_A01 ()
649{
87178dbd 650 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 651 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 652 trace_output (OP_REG);
2934d1c9
MH		 653}
654
655/* bra.s */
656void
657OP_4800 ()
658{
87178dbd 659 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 660 PC += SEXT8 (OP[0]);
87178dbd 661 trace_output (OP_VOID);
2934d1c9
MH		 662}
663
664/* bra.l */
665void
666OP_24000000 ()
667{
87178dbd 668 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 669 PC += OP[0];
87178dbd 670 trace_output (OP_VOID);
2934d1c9
MH		 671}
672
673/* brf0f.s */
674void
675OP_4A00 ()
676{
87178dbd 677 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 678 if (State.F0 == 0)
679 PC += SEXT8 (OP[0]);
87178dbd 680 trace_output (OP_FLAG);
2934d1c9
MH		 681}
682
683/* brf0f.l */
684void
685OP_25000000 ()
686{
87178dbd 687 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 688 if (State.F0 == 0)
689 PC += OP[0];
87178dbd 690 trace_output (OP_FLAG);
2934d1c9
MH		 691}
692
693/* brf0t.s */
694void
695OP_4B00 ()
696{
87178dbd 697 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 698 if (State.F0)
699 PC += SEXT8 (OP[0]);
87178dbd 700 trace_output (OP_FLAG);
2934d1c9
MH		 701}
702
703/* brf0t.l */
704void
705OP_25800000 ()
706{
87178dbd 707 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 708 if (State.F0)
709 PC += OP[0];
87178dbd 710 trace_output (OP_FLAG);
2934d1c9
MH		 711}
712
713/* bseti */
714void
715OP_801 ()
716{
87178dbd 717 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 718 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 719 trace_output (OP_REG);
2934d1c9
MH		 720}
721
722/* btsti */
723void
724OP_E01 ()
725{
87178dbd 726 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 727 State.F1 = State.F0;
728 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 729 trace_output (OP_FLAG);
2934d1c9
MH		 730}
731
732/* clrac */
733void
734OP_5601 ()
735{
87178dbd 736 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 737 State.a[OP[0]] = 0;
87178dbd 738 trace_output (OP_ACCUM);
2934d1c9
MH		 739}
740
741/* cmp */
742void
743OP_600 ()
744{
87178dbd 745 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 746 State.F1 = State.F0;
747 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 748 trace_output (OP_FLAG);
2934d1c9
MH		 749}
750
751/* cmp */
752void
753OP_1603 ()
754{
87178dbd 755 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 756 State.F1 = State.F0;
4f425a32 757 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 758 trace_output (OP_FLAG);
2934d1c9
MH		 759}
760
761/* cmpeq */
762void
763OP_400 ()
764{
87178dbd 765 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 766 State.F1 = State.F0;
767 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 768 trace_output (OP_FLAG);
2934d1c9
MH		 769}
770
771/* cmpeq */
772void
773OP_1403 ()
774{
87178dbd 775 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 776 State.F1 = State.F0;
777 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
87178dbd 778 trace_output (OP_FLAG);
2934d1c9
MH		 779}
780
781/* cmpeqi.s */
782void
783OP_401 ()
784{
87178dbd 785 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 786 State.F1 = State.F0;
787 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
87178dbd 788 trace_output (OP_FLAG);
2934d1c9
MH		 789}
790
791/* cmpeqi.l */
792void
793OP_2000000 ()
794{
87178dbd 795 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 796 State.F1 = State.F0;
797 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
87178dbd 798 trace_output (OP_FLAG);
2934d1c9
MH		 799}
800
801/* cmpi.s */
802void
803OP_601 ()
804{
87178dbd 805 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9
MH		 806 State.F1 = State.F0;
807 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
87178dbd 808 trace_output (OP_FLAG);
2934d1c9
MH		 809}
810
811/* cmpi.l */
812void
813OP_3000000 ()
814{
87178dbd 815 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 816 State.F1 = State.F0;
817 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 818 trace_output (OP_FLAG);
2934d1c9
MH		 819}
820
821/* cmpu */
822void
823OP_4600 ()
824{
87178dbd 825 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 826 State.F1 = State.F0;
827 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 828 trace_output (OP_FLAG);
2934d1c9
MH		 829}
830
831/* cmpui */
832void
833OP_23000000 ()
834{
87178dbd 835 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 836 State.F1 = State.F0;
837 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
87178dbd 838 trace_output (OP_FLAG);
2934d1c9
MH		 839}
840
841/* cpfg */
842void
843OP_4E09 ()
844{
845 uint8 *src, *dst;
2934d1c9 846
60fc5b72 847 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 848 if (OP[0] == 0)
849 dst = &State.F0;
850 else
851 dst = &State.F1;
852
853 if (OP[1] == 0)
854 src = &State.F0;
855 else if (OP[1] == 1)
856 src = &State.F1;
857 else
858 src = &State.C;
859
860 *dst = *src;
87178dbd 861 trace_output (OP_FLAG);
2934d1c9
MH		 862}
863
864/* dbt */
865void
866OP_5F20 ()
867{
7eebfc62 868 d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC);
4f425a32 869 State.exception = SIGTRAP;
2934d1c9
MH		 870}
871
872/* divs */
873void
874OP_14002800 ()
875{
876 uint16 foo, tmp, tmpf;
87178dbd
MM		 877
878 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 879 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
880 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
881 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
882 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
883 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 884 trace_output (OP_DREG);
2934d1c9
MH		 885}
886
887/* exef0f */
888void
889OP_4E04 ()
890{
87178dbd 891 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 892 State.exe = (State.F0 == 0);
87178dbd 893 trace_output (OP_FLAG);
2934d1c9
MH		 894}
895
896/* exef0t */
897void
898OP_4E24 ()
899{
87178dbd 900 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 901 State.exe = (State.F0 != 0);
87178dbd 902 trace_output (OP_FLAG);
2934d1c9
MH		 903}
904
905/* exef1f */
906void
907OP_4E40 ()
908{
87178dbd 909 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 910 State.exe = (State.F1 == 0);
87178dbd 911 trace_output (OP_FLAG);
2934d1c9
MH		 912}
913
914/* exef1t */
915void
916OP_4E42 ()
917{
87178dbd 918 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 919 State.exe = (State.F1 != 0);
87178dbd 920 trace_output (OP_FLAG);
2934d1c9
MH		 921}
922
923/* exefaf */
924void
925OP_4E00 ()
926{
87178dbd 927 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 928 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 929 trace_output (OP_FLAG);
2934d1c9
MH		 930}
931
932/* exefat */
933void
934OP_4E02 ()
935{
87178dbd 936 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 937 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 938 trace_output (OP_FLAG);
2934d1c9
MH		 939}
940
941/* exetaf */
942void
943OP_4E20 ()
944{
87178dbd 945 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 946 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 947 trace_output (OP_FLAG);
2934d1c9
MH		 948}
949
950/* exetat */
951void
952OP_4E22 ()
953{
87178dbd 954 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 955 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 956 trace_output (OP_FLAG);
2934d1c9
MH		 957}
958
959/* exp */
960void
961OP_15002A00 ()
962{
963 uint32 tmp, foo;
964 int i;
965
87178dbd 966 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 967 if (((int16)State.regs[OP[1]]) >= 0)
968 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 969 else
4c38885c 970 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 971
972 foo = 0x40000000;
4c38885c 973 for (i=1;i<17;i++)
2934d1c9
MH		 974 {
975 if (tmp & foo)
976 {
977 State.regs[OP[0]] = i-1;
87178dbd 978 trace_output (OP_REG);
2934d1c9
MH		 979 return;
980 }
4c38885c 981 foo >>= 1;
2934d1c9
MH		 982 }
983 State.regs[OP[0]] = 16;
87178dbd 984 trace_output (OP_REG);
2934d1c9
MH		 985}
986
987/* exp */
988void
989OP_15002A02 ()
990{
4c38885c
MH		 991 int64 tmp, foo;
992 int i;
87178dbd
MM		 993
994 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
4f425a32 995 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 996 tmp = State.a[OP[1]];
997 else
998 tmp = ~(State.a[OP[1]]);
999
1000 foo = 0x4000000000LL;
1001 for (i=1;i<25;i++)
1002 {
1003 if (tmp & foo)
1004 {
1005 State.regs[OP[0]] = i-9;
87178dbd 1006 trace_output (OP_REG);
4c38885c
MH		 1007 return;
1008 }
1009 foo >>= 1;
1010 }
1011 State.regs[OP[0]] = 16;
87178dbd 1012 trace_output (OP_REG);
2934d1c9
MH		 1013}
1014
1015/* jl */
1016void
1017OP_4D00 ()
1018{
87178dbd 1019 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 1020 State.regs[13] = PC+1;
1021 PC = State.regs[OP[0]];
87178dbd 1022 trace_output (OP_VOID);
2934d1c9
MH		 1023}
1024
1025/* jmp */
1026void
1027OP_4C00 ()
1028{
87178dbd 1029 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1030 PC = State.regs[OP[0]];
87178dbd 1031 trace_output (OP_VOID);
2934d1c9
MH		 1032}
1033
1034/* ld */
1035void
1036OP_30000000 ()
1037{
87178dbd 1038 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1039 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1040 trace_output (OP_REG);
2934d1c9
MH		 1041}
1042
1043/* ld */
1044void
1045OP_6401 ()
1046{
87178dbd 1047 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1048 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1049 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1050 trace_output (OP_REG);
2934d1c9
MH		 1051}
1052
1053/* ld */
1054void
1055OP_6001 ()
1056{
87178dbd 1057 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1058 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1059 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1060 trace_output (OP_REG);
2934d1c9
MH		 1061}
1062
1063/* ld */
1064void
1065OP_6000 ()
1066{
87178dbd 1067 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1068 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1069 trace_output (OP_REG);
2934d1c9
MH		 1070}
1071
1072/* ld2w */
1073void
1074OP_31000000 ()
1075{
308f64d3 1076 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9
MH		 1077 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1078 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
87178dbd 1079 trace_output (OP_DREG);
2934d1c9
MH		 1080}
1081
1082/* ld2w */
1083void
1084OP_6601 ()
1085{
87178dbd 1086 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c
MH		 1087 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1088 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 1089 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1090 trace_output (OP_DREG);
2934d1c9
MH		 1091}
1092
1093/* ld2w */
1094void
1095OP_6201 ()
1096{
87178dbd 1097 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c
MH		 1098 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1099 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 1100 INC_ADDR(State.regs[OP[1]],4);
87178dbd 1101 trace_output (OP_REG);
2934d1c9
MH		 1102}
1103
1104/* ld2w */
1105void
1106OP_6200 ()
1107{
87178dbd 1108 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
4c38885c
MH		 1109 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1110 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
87178dbd 1111 trace_output (OP_REG);
2934d1c9
MH		 1112}
1113
1114/* ldb */
1115void
1116OP_38000000 ()
1117{
87178dbd 1118 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9
MH		 1119 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1120 SEXT8 (State.regs[OP[0]]);
87178dbd 1121 trace_output (OP_REG);
2934d1c9
MH		 1122}
1123
1124/* ldb */
1125void
1126OP_7000 ()
1127{
87178dbd 1128 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9
MH		 1129 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1130 SEXT8 (State.regs[OP[0]]);
87178dbd 1131 trace_output (OP_REG);
2934d1c9
MH		 1132}
1133
1134/* ldi.s */
1135void
1136OP_4001 ()
1137{
87178dbd 1138 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1139 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1140 trace_output (OP_REG);
2934d1c9
MH		 1141}
1142
1143/* ldi.l */
1144void
1145OP_20000000 ()
1146{
87178dbd 1147 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1148 State.regs[OP[0]] = OP[1];
87178dbd 1149 trace_output (OP_REG);
2934d1c9
MH		 1150}
1151
1152/* ldub */
1153void
1154OP_39000000 ()
1155{
87178dbd 1156 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1157 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1158 trace_output (OP_REG);
2934d1c9
MH		 1159}
1160
1161/* ldub */
1162void
1163OP_7200 ()
1164{
87178dbd 1165 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1166 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1167 trace_output (OP_REG);
2934d1c9
MH		 1168}
1169
1170/* mac */
1171void
1172OP_2A00 ()
1173{
4c38885c 1174 int64 tmp;
87178dbd
MM		 1175
1176 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1177 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1178
1179 if (State.FX)
4f425a32 1180 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1181
1182 if (State.ST && tmp > MAX32)
1183 tmp = MAX32;
1184
4f425a32 1185 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1186 if (State.ST)
1187 {
1188 if (tmp > MAX32)
1189 State.a[OP[0]] = MAX32;
1190 else if (tmp < MIN32)
1191 State.a[OP[0]] = MIN32;
1192 else
4f425a32 1193 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1194 }
1195 else
4f425a32 1196 State.a[OP[0]] = tmp & MASK40;
87178dbd 1197 trace_output (OP_ACCUM);
2934d1c9
MH		 1198}
1199
1200/* macsu */
1201void
1202OP_1A00 ()
1203{
4f425a32 1204 int64 tmp;
87178dbd
MM		 1205
1206 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1207 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1208 if (State.FX)
1209 tmp = SEXT40( (tmp << 1) & MASK40);
1210
1211 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1212 trace_output (OP_ACCUM);
2934d1c9
MH		 1213}
1214
1215/* macu */
1216void
1217OP_3A00 ()
1218{
4f425a32 1219 int64 tmp;
87178dbd
MM		 1220
1221 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1222 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1223 if (State.FX)
1224 tmp = SEXT40( (tmp << 1) & MASK40);
1225 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1226 trace_output (OP_ACCUM);
2934d1c9
MH		 1227}
1228
1229/* max */
1230void
1231OP_2600 ()
1232{
87178dbd 1233 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1234 State.F1 = State.F0;
ea2155e8 1235 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1236 {
1237 State.regs[OP[0]] = State.regs[OP[1]];
1238 State.F0 = 1;
1239 }
1240 else
1241 State.F0 = 0;
87178dbd 1242 trace_output (OP_REG);
2934d1c9
MH		 1243}
1244
1245/* max */
1246void
1247OP_3600 ()
1248{
4f425a32 1249 int64 tmp;
87178dbd
MM		 1250
1251 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1252 State.F1 = State.F0;
1253 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1254 if (tmp > SEXT40(State.a[OP[0]]))
1255 {
1256 State.a[OP[0]] = tmp & MASK40;
1257 State.F0 = 1;
1258 }
1259 else
1260 State.F0 = 0;
87178dbd 1261 trace_output (OP_ACCUM);
2934d1c9
MH		 1262}
1263
1264/* max */
1265void
1266OP_3602 ()
1267{
87178dbd 1268 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1269 State.F1 = State.F0;
1270 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1271 {
1272 State.a[OP[0]] = State.a[OP[1]];
1273 State.F0 = 1;
1274 }
1275 else
1276 State.F0 = 0;
87178dbd 1277 trace_output (OP_ACCUM);
2934d1c9
MH		 1278}
1279
4f425a32 1280
2934d1c9
MH		 1281/* min */
1282void
1283OP_2601 ()
1284{
87178dbd 1285 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1286 State.F1 = State.F0;
ea2155e8 1287 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1288 {
1289 State.regs[OP[0]] = State.regs[OP[1]];
1290 State.F0 = 1;
1291 }
1292 else
1293 State.F0 = 0;
87178dbd 1294 trace_output (OP_REG);
2934d1c9
MH		 1295}
1296
1297/* min */
1298void
1299OP_3601 ()
1300{
4f425a32 1301 int64 tmp;
87178dbd
MM		 1302
1303 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1304 State.F1 = State.F0;
1305 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1306 if (tmp < SEXT40(State.a[OP[0]]))
1307 {
1308 State.a[OP[0]] = tmp & MASK40;
1309 State.F0 = 1;
1310 }
1311 else
1312 State.F0 = 0;
87178dbd 1313 trace_output (OP_ACCUM);
2934d1c9
MH		 1314}
1315
1316/* min */
1317void
1318OP_3603 ()
1319{
87178dbd 1320 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1321 State.F1 = State.F0;
1322 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1323 {
1324 State.a[OP[0]] = State.a[OP[1]];
1325 State.F0 = 1;
1326 }
1327 else
1328 State.F0 = 0;
87178dbd 1329 trace_output (OP_ACCUM);
2934d1c9
MH		 1330}
1331
1332/* msb */
1333void
1334OP_2800 ()
1335{
4f425a32 1336 int64 tmp;
87178dbd
MM		 1337
1338 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1339 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1340
1341 if (State.FX)
1342 tmp = SEXT40 ((tmp << 1) & MASK40);
1343
1344 if (State.ST && tmp > MAX32)
1345 tmp = MAX32;
1346
1347 tmp = SEXT40(State.a[OP[0]]) - tmp;
1348 if (State.ST)
1349 {
1350 if (tmp > MAX32)
1351 State.a[OP[0]] = MAX32;
1352 else if (tmp < MIN32)
1353 State.a[OP[0]] = MIN32;
1354 else
1355 State.a[OP[0]] = tmp & MASK40;
1356 }
1357 else
1358 State.a[OP[0]] = tmp & MASK40;
87178dbd 1359 trace_output (OP_ACCUM);
2934d1c9
MH		 1360}
1361
1362/* msbsu */
1363void
1364OP_1800 ()
1365{
4f425a32 1366 int64 tmp;
87178dbd
MM		 1367
1368 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1369 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1370 if (State.FX)
1371 tmp = SEXT40( (tmp << 1) & MASK40);
1372
1373 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1374 trace_output (OP_ACCUM);
2934d1c9
MH		 1375}
1376
1377/* msbu */
1378void
1379OP_3800 ()
1380{
4f425a32 1381 int64 tmp;
87178dbd
MM		 1382
1383 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1384 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1385 if (State.FX)
1386 tmp = SEXT40( (tmp << 1) & MASK40);
1387
1388 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1389 trace_output (OP_ACCUM);
2934d1c9
MH		 1390}
1391
1392/* mul */
1393void
1394OP_2E00 ()
1395{
87178dbd 1396 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1397 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1398 trace_output (OP_REG);
2934d1c9
MH		 1399}
1400
1401/* mulx */
1402void
1403OP_2C00 ()
1404{
4f425a32 1405 int64 tmp;
87178dbd
MM		 1406
1407 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1408 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1409
1410 if (State.FX)
1411 tmp = SEXT40 ((tmp << 1) & MASK40);
1412
1413 if (State.ST && tmp > MAX32)
1414 State.a[OP[0]] = MAX32;
1415 else
1416 State.a[OP[0]] = tmp & MASK40;
87178dbd 1417 trace_output (OP_ACCUM);
2934d1c9
MH		 1418}
1419
1420/* mulxsu */
1421void
1422OP_1C00 ()
1423{
4f425a32 1424 int64 tmp;
87178dbd
MM		 1425
1426 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1427 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1428
1429 if (State.FX)
1430 tmp <<= 1;
1431
1432 State.a[OP[0]] = tmp & MASK40;
87178dbd 1433 trace_output (OP_ACCUM);
2934d1c9
MH		 1434}
1435
1436/* mulxu */
1437void
1438OP_3C00 ()
1439{
4f425a32 1440 int64 tmp;
87178dbd
MM		 1441
1442 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1443 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1444
1445 if (State.FX)
1446 tmp <<= 1;
1447
1448 State.a[OP[0]] = tmp & MASK40;
87178dbd 1449 trace_output (OP_ACCUM);
2934d1c9
MH		 1450}
1451
1452/* mv */
1453void
1454OP_4000 ()
1455{
87178dbd 1456 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1457 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1458 trace_output (OP_REG);
2934d1c9
MH		 1459}
1460
1461/* mv2w */
1462void
1463OP_5000 ()
1464{
87178dbd 1465 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1466 State.regs[OP[0]] = State.regs[OP[1]];
1467 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1468 trace_output (OP_DREG);
2934d1c9
MH		 1469}
1470
1471/* mv2wfac */
1472void
1473OP_3E00 ()
1474{
87178dbd 1475 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1476 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1477 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1478 trace_output (OP_DREG);
2934d1c9
MH		 1479}
1480
1481/* mv2wtac */
1482void
1483OP_3E01 ()
1484{
87178dbd 1485 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
4f425a32 1486 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
87178dbd 1487 trace_output (OP_ACCUM);
2934d1c9
MH		 1488}
1489
1490/* mvac */
1491void
1492OP_3E03 ()
1493{
87178dbd 1494 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1495 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1496 trace_output (OP_ACCUM);
2934d1c9
MH		 1497}
1498
1499/* mvb */
1500void
1501OP_5400 ()
1502{
87178dbd 1503 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1504 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1505 trace_output (OP_REG);
2934d1c9
MH		 1506}
1507
1508/* mvf0f */
1509void
1510OP_4400 ()
1511{
87178dbd 1512 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1513 if (State.F0 == 0)
1514 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1515 trace_output (OP_REG);
2934d1c9
MH		 1516}
1517
1518/* mvf0t */
1519void
1520OP_4401 ()
1521{
87178dbd 1522 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1523 if (State.F0)
1524 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1525 trace_output (OP_REG);
2934d1c9
MH		 1526}
1527
1528/* mvfacg */
1529void
1530OP_1E04 ()
1531{
87178dbd 1532 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1533 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1534 trace_output (OP_ACCUM);
2934d1c9
MH		 1535}
1536
1537/* mvfachi */
1538void
1539OP_1E00 ()
1540{
87178dbd 1541 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1542 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1543 trace_output (OP_REG);
2934d1c9
MH		 1544}
1545
1546/* mvfaclo */
1547void
1548OP_1E02 ()
1549{
87178dbd 1550 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1551 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1552 trace_output (OP_REG);
2934d1c9
MH		 1553}
1554
1555/* mvfc */
1556void
1557OP_5200 ()
1558{
87178dbd 1559 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1560 if (OP[1] == 0)
1561 {
1562 /* PSW is treated specially */
1563 PSW = 0;
1564 if (State.SM) PSW |= 0x8000;
1565 if (State.EA) PSW |= 0x2000;
1566 if (State.DB) PSW |= 0x1000;
1567 if (State.IE) PSW |= 0x400;
1568 if (State.RP) PSW |= 0x200;
1569 if (State.MD) PSW |= 0x100;
1570 if (State.FX) PSW |= 0x80;
1571 if (State.ST) PSW |= 0x40;
1572 if (State.F0) PSW |= 8;
1573 if (State.F1) PSW |= 4;
1574 if (State.C) PSW |= 1;
1575 }
1576 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1577 trace_output (OP_REG);
2934d1c9
MH		 1578}
1579
1580/* mvtacg */
1581void
1582OP_1E41 ()
1583{
87178dbd 1584 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1585 State.a[OP[1]] &= MASK32;
1586 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1587 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1588}
1589
1590/* mvtachi */
1591void
1592OP_1E01 ()
1593{
1594 uint16 tmp;
87178dbd
MM		 1595
1596 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1597 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1598 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1599 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1600}
1601
1602/* mvtaclo */
1603void
1604OP_1E21 ()
1605{
87178dbd 1606 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1607 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1608 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1609}
1610
1611/* mvtc */
1612void
1613OP_5600 ()
1614{
87178dbd 1615 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1616 State.cregs[OP[1]] = State.regs[OP[0]];
1617 if (OP[1] == 0)
1618 {
1619 /* PSW is treated specially */
1620 State.SM = (PSW & 0x8000) ? 1 : 0;
1621 State.EA = (PSW & 0x2000) ? 1 : 0;
1622 State.DB = (PSW & 0x1000) ? 1 : 0;
1623 State.IE = (PSW & 0x400) ? 1 : 0;
1624 State.RP = (PSW & 0x200) ? 1 : 0;
1625 State.MD = (PSW & 0x100) ? 1 : 0;
1626 State.FX = (PSW & 0x80) ? 1 : 0;
1627 State.ST = (PSW & 0x40) ? 1 : 0;
1628 State.F0 = (PSW & 8) ? 1 : 0;
1629 State.F1 = (PSW & 4) ? 1 : 0;
1630 State.C = PSW & 1;
1631 if (State.ST && !State.FX)
1632 {
7eebfc62
MM		 1633 (*d10v_callback->printf_filtered) (d10v_callback,
1634 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1635 PC<<2);
4f425a32 1636 State.exception = SIGILL;
2934d1c9
MH		 1637 }
1638 }
87178dbd 1639 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1640}
1641
1642/* mvub */
1643void
1644OP_5401 ()
1645{
87178dbd 1646 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1647 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1648 trace_output (OP_REG);
2934d1c9
MH		 1649}
1650
1651/* neg */
1652void
1653OP_4605 ()
1654{
87178dbd 1655 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1656 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1657 trace_output (OP_REG);
2934d1c9
MH		 1658}
1659
1660/* neg */
1661void
1662OP_5605 ()
1663{
1664 int64 tmp;
87178dbd
MM		 1665
1666 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1667 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1668 if (State.ST)
1669 {
4c38885c 1670 if ( tmp > MAX32)
2934d1c9 1671 State.a[OP[0]] = MAX32;
4c38885c 1672 else if (tmp < MIN32)
2934d1c9
MH		 1673 State.a[OP[0]] = MIN32;
1674 else
4f425a32 1675 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1676 }
1677 else
4f425a32 1678 State.a[OP[0]] = tmp & MASK40;
87178dbd 1679 trace_output (OP_ACCUM);
2934d1c9
MH		 1680}
1681
1682
1683/* nop */
1684void
1685OP_5E00 ()
1686{
87178dbd
MM		 1687 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1688 trace_output (OP_VOID);
7eebfc62
MM		 1689
1690 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1691 left_nops++;
1692 else
1693 right_nops++;
2934d1c9
MH		 1694}
1695
1696/* not */
1697void
1698OP_4603 ()
1699{
87178dbd 1700 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1701 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1702 trace_output (OP_REG);
2934d1c9
MH		 1703}
1704
1705/* or */
1706void
1707OP_800 ()
1708{
87178dbd 1709 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1710 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1711 trace_output (OP_REG);
2934d1c9
MH		 1712}
1713
1714/* or3 */
1715void
1716OP_4000000 ()
1717{
87178dbd 1718 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1719 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1720 trace_output (OP_REG);
2934d1c9
MH		 1721}
1722
1723/* rac */
1724void
1725OP_5201 ()
1726{
1727 int64 tmp;
1728 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1729
1730 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1731 if (OP[1] != 0)
1732 {
7eebfc62
MM		 1733 (*d10v_callback->printf_filtered) (d10v_callback,
1734 "ERROR at PC 0x%x: instruction only valid for A0\n",
1735 PC<<2);
166acb9f
MH		 1736 State.exception = SIGILL;
1737 }
1738
2934d1c9
MH		 1739 State.F1 = State.F0;
1740 if (shift >=0)
1741 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1742 else
1743 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1744 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1745 if (tmp > MAX32)
2934d1c9
MH		 1746 {
1747 State.regs[OP[0]] = 0x7fff;
1748 State.regs[OP[0]+1] = 0xffff;
1749 State.F0 = 1;
1750 }
4c38885c 1751 else if (tmp < MIN32)
2934d1c9
MH		 1752 {
1753 State.regs[OP[0]] = 0x8000;
1754 State.regs[OP[0]+1] = 0;
1755 State.F0 = 1;
1756 }
1757 else
1758 {
1759 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1760 State.regs[OP[0]+1] = tmp & 0xffff;
1761 State.F0 = 0;
1762 }
87178dbd 1763 trace_output (OP_DREG);
2934d1c9
MH		 1764}
1765
1766/* rachi */
1767void
1768OP_4201 ()
1769{
4c38885c
MH		 1770 int64 tmp;
1771 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1772
1773 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1774 State.F1 = State.F0;
1775 if (shift >=0)
166acb9f 1776 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1777 else
166acb9f 1778 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1779 tmp += 0x8000;
63a91cfb 1780
4c38885c
MH		 1781 if (tmp > MAX32)
1782 {
1783 State.regs[OP[0]] = 0x7fff;
1784 State.F0 = 1;
1785 }
1786 else if (tmp < 0xfff80000000LL)
1787 {
1788 State.regs[OP[0]] = 0x8000;
1789 State.F0 = 1;
1790 }
1791 else
1792 {
1793 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1794 State.F0 = 0;
1795 }
87178dbd 1796 trace_output (OP_REG);
2934d1c9
MH		 1797}
1798
1799/* rep */
1800void
1801OP_27000000 ()
1802{
87178dbd 1803 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1804 RPT_S = PC + 1;
1805 RPT_E = PC + OP[1];
1806 RPT_C = State.regs[OP[0]];
1807 State.RP = 1;
1808 if (RPT_C == 0)
1809 {
7eebfc62 1810 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1811 State.exception = SIGILL;
2934d1c9 1812 }
4c38885c
MH		 1813 if (OP[1] < 4)
1814 {
7eebfc62 1815 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1816 State.exception = SIGILL;
4c38885c 1817 }
87178dbd 1818 trace_output (OP_VOID);
2934d1c9
MH		 1819}
1820
1821/* repi */
1822void
1823OP_2F000000 ()
1824{
87178dbd 1825 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1826 RPT_S = PC + 1;
1827 RPT_E = PC + OP[1];
1828 RPT_C = OP[0];
1829 State.RP = 1;
1830 if (RPT_C == 0)
1831 {
7eebfc62 1832 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1833 State.exception = SIGILL;
4c38885c
MH		 1834 }
1835 if (OP[1] < 4)
1836 {
7eebfc62 1837 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 1838 State.exception = SIGILL;
2934d1c9 1839 }
87178dbd 1840 trace_output (OP_VOID);
2934d1c9
MH		 1841}
1842
1843/* rtd */
1844void
1845OP_5F60 ()
1846{
7eebfc62 1847 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 1848 State.exception = SIGILL;
2934d1c9
MH		 1849}
1850
1851/* rte */
1852void
1853OP_5F40 ()
1854{
87178dbd 1855 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 1856 PC = BPC;
1857 PSW = BPSW;
87178dbd 1858 trace_output (OP_VOID);
2934d1c9
MH		 1859}
1860
1861/* sadd */
1862void
1863OP_1223 ()
1864{
4c38885c 1865 int64 tmp;
87178dbd
MM		 1866
1867 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 1868 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 1869 if (State.ST)
1870 {
1871 if (tmp > MAX32)
1872 State.a[OP[0]] = MAX32;
1873 else if (tmp < MIN32)
1874 State.a[OP[0]] = MIN32;
1875 else
4f425a32 1876 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1877 }
1878 else
4f425a32 1879 State.a[OP[0]] = tmp & MASK40;
87178dbd 1880 trace_output (OP_ACCUM);
2934d1c9
MH		 1881}
1882
1883/* setf0f */
1884void
1885OP_4611 ()
1886{
87178dbd 1887 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 1888 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 1889 trace_output (OP_REG);
2934d1c9
MH		 1890}
1891
1892/* setf0t */
1893void
1894OP_4613 ()
1895{
87178dbd 1896 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 1897 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 1898 trace_output (OP_REG);
2934d1c9
MH		 1899}
1900
1901/* sleep */
1902void
1903OP_5FC0 ()
1904{
87178dbd 1905 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 1906 State.IE = 1;
87178dbd 1907 trace_output (OP_VOID);
2934d1c9
MH		 1908}
1909
1910/* sll */
1911void
1912OP_2200 ()
1913{
87178dbd 1914 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 1915 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 1916 trace_output (OP_REG);
2934d1c9
MH		 1917}
1918
1919/* sll */
1920void
1921OP_3200 ()
1922{
4c38885c 1923 int64 tmp;
87178dbd 1924 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 1925 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 1926 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 1927 else
1928 {
1929 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
1930 State.exception = SIGILL;
1931 return;
1932 }
4c38885c
MH		 1933
1934 if (State.ST)
1935 {
1936 if (tmp > MAX32)
1937 State.a[OP[0]] = MAX32;
1938 else if (tmp < 0xffffff80000000LL)
1939 State.a[OP[0]] = MIN32;
1940 else
1941 State.a[OP[0]] = tmp & MASK40;
1942 }
1943 else
1944 State.a[OP[0]] = tmp & MASK40;
87178dbd 1945 trace_output (OP_ACCUM);
2934d1c9
MH		 1946}
1947
1948/* slli */
1949void
1950OP_2201 ()
1951{
87178dbd 1952 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 1953 State.regs[OP[0]] <<= OP[1];
87178dbd 1954 trace_output (OP_REG);
2934d1c9
MH		 1955}
1956
1957/* slli */
1958void
1959OP_3201 ()
1960{
4c38885c 1961 int64 tmp;
4f425a32
MH		 1962
1963 if (OP[1] == 0)
1964 OP[1] = 16;
4f425a32 1965
87178dbd 1966 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 1967 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 1968
1969 if (State.ST)
1970 {
1971 if (tmp > MAX32)
1972 State.a[OP[0]] = MAX32;
1973 else if (tmp < 0xffffff80000000LL)
1974 State.a[OP[0]] = MIN32;
1975 else
1976 State.a[OP[0]] = tmp & MASK40;
1977 }
1978 else
1979 State.a[OP[0]] = tmp & MASK40;
87178dbd 1980 trace_output (OP_ACCUM);
2934d1c9
MH		 1981}
1982
1983/* slx */
1984void
1985OP_460B ()
1986{
1987 uint16 tmp;
87178dbd
MM		 1988
1989 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 1990 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 1991 trace_output (OP_REG);
2934d1c9
MH		 1992}
1993
1994/* sra */
1995void
1996OP_2400 ()
1997{
87178dbd 1998 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 1999 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2000 trace_output (OP_REG);
2934d1c9
MH		 2001}
2002
2003/* sra */
2004void
2005OP_3400 ()
2006{
87178dbd 2007 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2008 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2009 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2010 else
2011 {
2012 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2013 State.exception = SIGILL;
2014 return;
2015 }
2016
87178dbd 2017 trace_output (OP_ACCUM);
2934d1c9
MH		 2018}
2019
2020/* srai */
2021void
2022OP_2401 ()
2023{
87178dbd 2024 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2025 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2026 trace_output (OP_REG);
2934d1c9
MH		 2027}
2028
2029/* srai */
2030void
2031OP_3401 ()
2032{
4f425a32
MH		 2033 if (OP[1] == 0)
2034 OP[1] = 16;
87178dbd
MM		 2035
2036 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2037 State.a[OP[0]] >>= OP[1];
2038 trace_output (OP_ACCUM);
2934d1c9
MH		 2039}
2040
2041/* srl */
2042void
2043OP_2000 ()
2044{
87178dbd 2045 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2046 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2047 trace_output (OP_REG);
2934d1c9
MH		 2048}
2049
2050/* srl */
2051void
2052OP_3000 ()
2053{
87178dbd 2054 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2055 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2056 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2057 else
2058 {
2059 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2060 State.exception = SIGILL;
2061 return;
2062 }
2063
87178dbd 2064 trace_output (OP_ACCUM);
2934d1c9
MH		 2065}
2066
2067/* srli */
2068void
2069OP_2001 ()
2070{
87178dbd 2071 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2072 State.regs[OP[0]] >>= OP[1];
87178dbd 2073 trace_output (OP_REG);
2934d1c9
MH		 2074}
2075
2076/* srli */
2077void
2078OP_3001 ()
2079{
4f425a32
MH		 2080 if (OP[1] == 0)
2081 OP[1] = 16;
87178dbd
MM		 2082
2083 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2084 State.a[OP[0]] >>= OP[1];
2085 trace_output (OP_ACCUM);
2934d1c9
MH		 2086}
2087
2088/* srx */
2089void
2090OP_4609 ()
2091{
2092 uint16 tmp;
87178dbd
MM		 2093
2094 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2095 tmp = State.F0 << 15;
2096 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2097 trace_output (OP_REG);
2934d1c9
MH		 2098}
2099
2100/* st */
2101void
2102OP_34000000 ()
2103{
87178dbd 2104 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2105 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2106 trace_output (OP_VOID);
2934d1c9
MH		 2107}
2108
2109/* st */
2110void
2111OP_6800 ()
2112{
87178dbd 2113 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2114 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2115 trace_output (OP_VOID);
2934d1c9
MH		 2116}
2117
2118/* st */
2119void
2120OP_6C1F ()
2121{
87178dbd 2122 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2123 if ( OP[1] != 15 )
2124 {
7eebfc62 2125 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2126 State.exception = SIGILL;
2127 return;
4c38885c
MH		 2128 }
2129 State.regs[OP[1]] -= 2;
2130 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2131 trace_output (OP_VOID);
2934d1c9
MH		 2132}
2133
2134/* st */
2135void
2136OP_6801 ()
2137{
87178dbd 2138 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2139 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2140 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2141 trace_output (OP_VOID);
2934d1c9
MH		 2142}
2143
2144/* st */
2145void
2146OP_6C01 ()
2147{
87178dbd 2148 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c 2149 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2150 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2151 trace_output (OP_VOID);
2934d1c9
MH		 2152}
2153
2154/* st2w */
2155void
2156OP_35000000 ()
2157{
87178dbd 2158 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2159 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2160 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2161 trace_output (OP_VOID);
2934d1c9
MH		 2162}
2163
2164/* st2w */
2165void
2166OP_6A00 ()
2167{
87178dbd 2168 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2169 SW (State.regs[OP[1]], State.regs[OP[0]]);
2170 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2171 trace_output (OP_VOID);
2934d1c9
MH		 2172}
2173
2174/* st2w */
2175void
2176OP_6E1F ()
2177{
87178dbd 2178 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2179 if ( OP[1] != 15 )
2180 {
7eebfc62 2181 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2182 State.exception = SIGILL;
2183 return;
4c38885c
MH		 2184 }
2185 State.regs[OP[1]] -= 4;
2186 SW (State.regs[OP[1]], State.regs[OP[0]]);
2187 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2188 trace_output (OP_VOID);
2934d1c9
MH		 2189}
2190
2191/* st2w */
2192void
2193OP_6A01 ()
2194{
87178dbd 2195 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c
MH		 2196 SW (State.regs[OP[1]], State.regs[OP[0]]);
2197 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2198 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2199 trace_output (OP_VOID);
2934d1c9
MH		 2200}
2201
2202/* st2w */
2203void
2204OP_6E01 ()
2205{
87178dbd 2206 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2207 SW (State.regs[OP[1]], State.regs[OP[0]]);
2208 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2209 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2210 trace_output (OP_VOID);
2934d1c9
MH		 2211}
2212
2213/* stb */
2214void
2215OP_3C000000 ()
2216{
87178dbd 2217 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2218 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2219 trace_output (OP_VOID);
2934d1c9
MH		 2220}
2221
2222/* stb */
2223void
2224OP_7800 ()
2225{
87178dbd 2226 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2227 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2228 trace_output (OP_VOID);
2934d1c9
MH		 2229}
2230
2231/* stop */
2232void
2233OP_5FE0 ()
2234{
87178dbd 2235 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
4f425a32 2236 State.exception = SIGQUIT;
87178dbd 2237 trace_output (OP_VOID);
2934d1c9
MH		 2238}
2239
2240/* sub */
2241void
2242OP_0 ()
4c38885c
MH		 2243{
2244 int32 tmp;
87178dbd
MM		 2245
2246 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
4c38885c
MH		 2247 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2248 State.C = (tmp & 0xffff0000) ? 1 : 0;
2249 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2250 trace_output (OP_REG);
4c38885c
MH		 2251}
2252
2253/* sub */
2254void
2255OP_1001 ()
2256{
4f425a32 2257 int64 tmp;
87178dbd
MM		 2258
2259 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2260 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2261 if (State.ST)
2262 {
2263 if ( tmp > MAX32)
2264 State.a[OP[0]] = MAX32;
2265 else if ( tmp < MIN32)
2266 State.a[OP[0]] = MIN32;
2267 else
2268 State.a[OP[0]] = tmp & MASK40;
2269 }
2270 else
2271 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2272
2273 trace_output (OP_ACCUM);
4c38885c
MH		 2274}
2275
2276/* sub */
2277
2278void
2279OP_1003 ()
2934d1c9 2280{
4f425a32 2281 int64 tmp;
87178dbd
MM		 2282
2283 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2284 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2285 if (State.ST)
2286 {
2287 if (tmp > MAX32)
2288 State.a[OP[0]] = MAX32;
2289 else if ( tmp < MIN32)
2290 State.a[OP[0]] = MIN32;
2291 else
2292 State.a[OP[0]] = tmp & MASK40;
2293 }
2294 else
2295 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2296
2297 trace_output (OP_ACCUM);
2934d1c9
MH		 2298}
2299
2300/* sub2w */
2301void
2302OP_1000 ()
2303{
4c38885c
MH		 2304 int64 tmp;
2305 int32 a,b;
4c38885c 2306
87178dbd 2307 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
4c38885c
MH		 2308 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2309 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2310 tmp = a-b;
2311 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2312 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2313 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2314 trace_output (OP_DREG);
2934d1c9
MH		 2315}
2316
2317/* subac3 */
2318void
2319OP_17000000 ()
2320{
4f425a32 2321 int64 tmp;
87178dbd
MM		 2322
2323 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2324 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2325 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2326 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2327 trace_output (OP_DREG);
2934d1c9
MH		 2328}
2329
2330/* subac3 */
2331void
2332OP_17000002 ()
2333{
4f425a32 2334 int64 tmp;
87178dbd
MM		 2335
2336 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2337 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2338 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2339 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2340 trace_output (OP_DREG);
2934d1c9
MH		 2341}
2342
2343/* subac3s */
2344void
2345OP_17001000 ()
2346{
4f425a32 2347 int64 tmp;
87178dbd
MM		 2348
2349 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2350 State.F1 = State.F0;
2351 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2352 if ( tmp > MAX32)
2353 {
2354 State.regs[OP[0]] = 0x7fff;
2355 State.regs[OP[0]+1] = 0xffff;
2356 State.F0 = 1;
2357 }
2358 else if (tmp < MIN32)
2359 {
2360 State.regs[OP[0]] = 0x8000;
2361 State.regs[OP[0]+1] = 0;
2362 State.F0 = 1;
2363 }
2364 else
2365 {
2366 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2367 State.regs[OP[0]+1] = tmp & 0xffff;
2368 State.F0 = 0;
2369 }
87178dbd 2370 trace_output (OP_DREG);
2934d1c9
MH		 2371}
2372
2373/* subac3s */
2374void
2375OP_17001002 ()
2376{
4f425a32 2377 int64 tmp;
87178dbd
MM		 2378
2379 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2380 State.F1 = State.F0;
2381 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2382 if ( tmp > MAX32)
2383 {
2384 State.regs[OP[0]] = 0x7fff;
2385 State.regs[OP[0]+1] = 0xffff;
2386 State.F0 = 1;
2387 }
2388 else if (tmp < MIN32)
2389 {
2390 State.regs[OP[0]] = 0x8000;
2391 State.regs[OP[0]+1] = 0;
2392 State.F0 = 1;
2393 }
2394 else
2395 {
2396 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2397 State.regs[OP[0]+1] = tmp & 0xffff;
2398 State.F0 = 0;
2399 }
87178dbd 2400 trace_output (OP_DREG);
2934d1c9
MH		 2401}
2402
2403/* subi */
2404void
2405OP_1 ()
2406{
4c38885c 2407 int32 tmp;
4f425a32
MH		 2408 if (OP[1] == 0)
2409 OP[1] = 16;
87178dbd
MM		 2410
2411 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c
MH		 2412 tmp = (int16)State.regs[OP[0]] - OP[1];
2413 State.C = (tmp & 0xffff0000) ? 1 : 0;
2414 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2415 trace_output (OP_REG);
2934d1c9
MH		 2416}
2417
2418/* trap */
2419void
2420OP_5F00 ()
2421{
a5719092 2422 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2423 trace_output (OP_VOID);
2934d1c9 2424
63a91cfb 2425 switch (OP[0])
2934d1c9 2426 {
63a91cfb 2427 default:
7eebfc62 2428 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb
MM		 2429 State.exception = SIGILL;
2430
2431 case 0:
2432 /* Trap 0 is used for simulating low-level I/O */
2433 {
2434 int save_errno = errno;
2435 errno = 0;
2436
2437/* Registers passed to trap 0 */
2438
2439#define FUNC State.regs[2] /* function number, return value */
2440#define PARM1 State.regs[3] /* optional parm 1 */
2441#define PARM2 State.regs[4] /* optional parm 2 */
2442#define PARM3 State.regs[5] /* optional parm 3 */
2443
2444/* Registers set by trap 0 */
2445
2446#define RETVAL State.regs[2] /* return value */
2447#define RETERR State.regs[3] /* return error code */
2448
2449/* Turn a pointer in a register into a pointer into real memory. */
2450
2451#define MEMPTR(x) ((char *)((x) + State.imem))
2452
2453 switch (FUNC)
2454 {
2455#if !defined(__GO32__) && !defined(_WIN32)
2456#ifdef SYS_fork
2457 case SYS_fork:
2458 RETVAL = fork ();
2459 break;
2460#endif
2461#ifdef SYS_execve
2462 case SYS_execve:
2463 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2464 (char **)MEMPTR (PARM3));
2465 break;
2466#endif
2467#ifdef SYS_execv
2468 case SYS_execv:
2469 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2470 break;
2471#endif
2472#ifdef SYS_pipe
2473 case SYS_pipe:
2474 {
2475 reg_t buf;
2476 int host_fd[2];
2477
2478 buf = PARM1;
2479 RETVAL = pipe (host_fd);
2480 SW (buf, host_fd[0]);
2481 buf += sizeof(uint16);
2482 SW (buf, host_fd[1]);
2483 }
2484 break;
2485#endif
2486#ifdef SYS_wait
2487 case SYS_wait:
2488 {
2489 int status;
2490
2491 RETVAL = wait (&status);
2492 SW (PARM1, status);
2493 }
2494 break;
2495#endif
2496#endif
2497
2498#ifdef SYS_read
2499 case SYS_read:
2500 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2501 PARM3);
2502 break;
2503#endif
2504#ifdef SYS_write
2505 case SYS_write:
2506 if (PARM1 == 1)
2507 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2508 MEMPTR (PARM2), PARM3);
2509 else
2510 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2511 MEMPTR (PARM2), PARM3);
2512 break;
2513#endif
2514#ifdef SYS_lseek
2515 case SYS_lseek:
2516 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2517 break;
2518#endif
2519#ifdef SYS_close
2520 case SYS_close:
2521 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2522 break;
2523#endif
2524#ifdef SYS_open
2525 case SYS_open:
2526 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2527 break;
2528#endif
2529#ifdef SYS_exit
2530 case SYS_exit:
2531 /* EXIT - caller can look in PARM1 to work out the
2532 reason */
2533 State.exception = SIGQUIT;
2534 break;
2535#endif
2536
8719be26
MA		 2537#ifdef SYS_stat
2538 case SYS_stat:
63a91cfb
MM		 2539 /* stat system call */
2540 {
2541 struct stat host_stat;
2542 reg_t buf;
2543
2544 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2545
2546 buf = PARM2;
2547
2548 /* The hard-coded offsets and sizes were determined by using
2549 * the D10V compiler on a test program that used struct stat.
2550 */
2551 SW (buf, host_stat.st_dev);
2552 SW (buf+2, host_stat.st_ino);
2553 SW (buf+4, host_stat.st_mode);
2554 SW (buf+6, host_stat.st_nlink);
2555 SW (buf+8, host_stat.st_uid);
2556 SW (buf+10, host_stat.st_gid);
2557 SW (buf+12, host_stat.st_rdev);
2558 SLW (buf+16, host_stat.st_size);
2559 SLW (buf+20, host_stat.st_atime);
2560 SLW (buf+28, host_stat.st_mtime);
2561 SLW (buf+36, host_stat.st_ctime);
2562 }
2563 break;
2564#endif
2565
2566#ifdef SYS_chown
2567 case SYS_chown:
2568 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2569 break;
2570#endif
2571#ifdef SYS_chmod
2572 case SYS_chmod:
2573 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2574 break;
2575#endif
2576#ifdef SYS_utime
2577 case SYS_utime:
2578 /* Cast the second argument to void *, to avoid type mismatch
2579 if a prototype is present. */
2580 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2581 break;
2582#endif
2583 default:
2584 abort ();
2585 }
2586 RETERR = errno;
2587 errno = save_errno;
2588 break;
2589 }
2590
2591 case 1:
2592 /* Trap 1 prints a string */
2593 {
2594 char *fstr = State.regs[2] + State.imem;
2595 fputs (fstr, stdout);
2596 break;
2597 }
2598
2599 case 2:
2600 /* Trap 2 calls printf */
2601 {
2602 char *fstr = State.regs[2] + State.imem;
7eebfc62
MM		 2603 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2604 (int16)State.regs[3],
2605 (int16)State.regs[4],
2606 (int16)State.regs[5]);
63a91cfb
MM		 2607 break;
2608 }
2609
2610 case 3:
2611 /* Trap 3 writes a character */
2612 putchar (State.regs[2]);
2613 break;
2934d1c9
MH		 2614 }
2615}
2616
2617/* tst0i */
2618void
2619OP_7000000 ()
2620{
87178dbd 2621 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2622 State.F1 = State.F0;
4f425a32 2623 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 2624 trace_output (OP_FLAG);
2934d1c9
MH		 2625}
2626
2627/* tst1i */
2628void
2629OP_F000000 ()
2630{
87178dbd 2631 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2632 State.F1 = State.F0;
4f425a32 2633 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 2634 trace_output (OP_FLAG);
2934d1c9
MH		 2635}
2636
2637/* wait */
2638void
2639OP_5F80 ()
2640{
87178dbd 2641 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2642 State.IE = 1;
87178dbd 2643 trace_output (OP_VOID);
2934d1c9
MH		 2644}
2645
2646/* xor */
2647void
2648OP_A00 ()
2649{
87178dbd 2650 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 2651 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 2652 trace_output (OP_REG);
2934d1c9
MH		 2653}
2654
2655/* xor3 */
2656void
2657OP_5000000 ()
2658{
87178dbd 2659 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 2660 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 2661 trace_output (OP_REG);
2934d1c9
MH		 2662}
2663
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