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* configure.in: Only build the V850 simulator if
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
4f425a32 1#include <signal.h>
63a91cfb
MM		 2#include <errno.h>
3#include <sys/types.h>
4#include <sys/stat.h>
5#include <unistd.h>
6
2934d1c9
MH		 7#include "d10v_sim.h"
8#include "simops.h"
8719be26 9#include "sys/syscall.h"
a49a15ad 10#include "bfd.h"
2934d1c9 11
87178dbd
MM		 12enum op_types {
13 OP_VOID,
14 OP_REG,
15 OP_REG_OUTPUT,
16 OP_DREG,
17 OP_DREG_OUTPUT,
18 OP_ACCUM,
19 OP_ACCUM_OUTPUT,
20 OP_ACCUM_REVERSE,
21 OP_CR,
22 OP_CR_OUTPUT,
23 OP_CR_REVERSE,
24 OP_FLAG,
60fc5b72 25 OP_FLAG_OUTPUT,
87178dbd 26 OP_CONSTANT16,
a18cb100 27 OP_CONSTANT8,
87178dbd
MM		 28 OP_CONSTANT3,
29 OP_CONSTANT4,
30 OP_MEMREF,
31 OP_MEMREF2,
32 OP_POSTDEC,
33 OP_POSTINC,
a18cb100
MM		 34 OP_PREDEC,
35 OP_R2,
36 OP_R3
87178dbd
MM		 37};
38
7eebfc62 39#ifdef DEBUG
a49a15ad
MM		 40static void trace_input_func PARAMS ((char *name,
41 enum op_types in1,
42 enum op_types in2,
43 enum op_types in3));
87178dbd 44
a49a15ad
MM		 45#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
46
47static void trace_output_func PARAMS ((enum op_types result));
48
49#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
50
51static int init_text_p = 0;
52static asection *text;
53static bfd_vma text_start;
54static bfd_vma text_end;
0535fa1a 55extern bfd *exec_bfd;
87178dbd
MM		 56
57#ifndef SIZE_INSTRUCTION
a49a15ad 58#define SIZE_INSTRUCTION 8
87178dbd
MM		 59#endif
60
61#ifndef SIZE_OPERANDS
a49a15ad 62#define SIZE_OPERANDS 18
87178dbd
MM		 63#endif
64
65#ifndef SIZE_VALUES
66#define SIZE_VALUES 13
67#endif
68
a49a15ad
MM		 69#ifndef SIZE_LOCATION
70#define SIZE_LOCATION 20
71#endif
72
891513ee
MM		 73#ifndef SIZE_PC
74#define SIZE_PC 6
75#endif
76
77#ifndef SIZE_LINE_NUMBER
78#define SIZE_LINE_NUMBER 4
79#endif
80
87178dbd 81static void
a49a15ad 82trace_input_func (name, in1, in2, in3)
87178dbd
MM		 83 char *name;
84 enum op_types in1;
85 enum op_types in2;
86 enum op_types in3;
87{
88 char *comma;
89 enum op_types in[3];
90 int i;
a49a15ad 91 char buf[1024];
87178dbd
MM		 92 char *p;
93 long tmp;
94 char *type;
a49a15ad
MM		 95 asection *s;
96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
87178dbd 100
7eebfc62
MM		 101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
87178dbd
MM		 104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
112 case INS_LONG: type = " B"; break;
113 }
114
a49a15ad
MM		 115 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
116 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 117 "0x%.*x %s: %-*s ",
891513ee
MM		 118 SIZE_PC, (unsigned)PC,
119 type,
a49a15ad
MM		 120 SIZE_INSTRUCTION, name);
121
122 else
123 {
a49a15ad
MM		 124 if (!init_text_p)
125 {
126 init_text_p = 1;
0535fa1a
MM		 127 for (s = exec_bfd->sections; s; s = s->next)
128 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
a49a15ad
MM		 129 {
130 text = s;
0535fa1a
MM		 131 text_start = bfd_get_section_vma (exec_bfd, s);
132 text_end = text_start + bfd_section_size (exec_bfd, s);
a49a15ad
MM		 133 break;
134 }
135 }
136
891513ee 137 buf[0] = '\0';
a49a15ad
MM		 138 byte_pc = (bfd_vma)PC << 2;
139 if (text && byte_pc >= text_start && byte_pc < text_end)
140 {
141 filename = (const char *)0;
142 functionname = (const char *)0;
143 linenumber = 0;
0535fa1a 144 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 145 &filename, &functionname, &linenumber))
146 {
147 p = buf;
148 if (linenumber)
149 {
891513ee 150 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 151 p += strlen (p);
152 }
891513ee
MM		 153 else
154 {
155 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
156 p += SIZE_LINE_NUMBER+2;
157 }
a49a15ad
MM		 158
159 if (functionname)
160 {
161 sprintf (p, "%s ", functionname);
162 p += strlen (p);
163 }
164 else if (filename)
165 {
166 char *q = (char *) strrchr (filename, '/');
167 sprintf (p, "%s ", (q) ? q+1 : filename);
168 p += strlen (p);
169 }
170
171 if (*p == ' ')
172 *p = '\0';
173 }
174 }
175
176 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 177 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 178 SIZE_PC, (unsigned)PC,
179 type,
a49a15ad
MM		 180 SIZE_LOCATION, SIZE_LOCATION, buf,
181 SIZE_INSTRUCTION, name);
182 }
87178dbd
MM		 183
184 in[0] = in1;
185 in[1] = in2;
186 in[2] = in3;
187 comma = "";
188 p = buf;
189 for (i = 0; i < 3; i++)
190 {
191 switch (in[i])
192 {
193 case OP_VOID:
a18cb100
MM		 194 case OP_R2:
195 case OP_R3:
87178dbd
MM		 196 break;
197
198 case OP_REG:
199 case OP_REG_OUTPUT:
200 case OP_DREG:
201 case OP_DREG_OUTPUT:
202 sprintf (p, "%sr%d", comma, OP[i]);
203 p += strlen (p);
204 comma = ",";
205 break;
206
207 case OP_CR:
208 case OP_CR_OUTPUT:
209 case OP_CR_REVERSE:
210 sprintf (p, "%scr%d", comma, OP[i]);
211 p += strlen (p);
212 comma = ",";
213 break;
214
215 case OP_ACCUM:
216 case OP_ACCUM_OUTPUT:
217 case OP_ACCUM_REVERSE:
218 sprintf (p, "%sa%d", comma, OP[i]);
219 p += strlen (p);
220 comma = ",";
221 break;
222
223 case OP_CONSTANT16:
224 sprintf (p, "%s%d", comma, OP[i]);
225 p += strlen (p);
226 comma = ",";
227 break;
228
a18cb100
MM		 229 case OP_CONSTANT8:
230 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
231 p += strlen (p);
232 comma = ",";
233 break;
234
87178dbd
MM		 235 case OP_CONSTANT4:
236 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
237 p += strlen (p);
238 comma = ",";
239 break;
240
241 case OP_CONSTANT3:
242 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
243 p += strlen (p);
244 comma = ",";
245 break;
246
247 case OP_MEMREF:
248 sprintf (p, "%s@r%d", comma, OP[i]);
249 p += strlen (p);
250 comma = ",";
251 break;
252
253 case OP_MEMREF2:
254 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
255 p += strlen (p);
256 comma = ",";
257 break;
258
259 case OP_POSTINC:
260 sprintf (p, "%s@r%d+", comma, OP[i]);
261 p += strlen (p);
262 comma = ",";
263 break;
264
265 case OP_POSTDEC:
266 sprintf (p, "%s@r%d-", comma, OP[i]);
267 p += strlen (p);
268 comma = ",";
269 break;
270
271 case OP_PREDEC:
272 sprintf (p, "%s@-r%d", comma, OP[i]);
273 p += strlen (p);
274 comma = ",";
275 break;
276
277 case OP_FLAG:
60fc5b72 278 case OP_FLAG_OUTPUT:
87178dbd
MM		 279 if (OP[i] == 0)
280 sprintf (p, "%sf0", comma);
281
282 else if (OP[i] == 1)
283 sprintf (p, "%sf1", comma);
284
285 else
60fc5b72 286 sprintf (p, "%sc", comma);
87178dbd
MM		 287
288 p += strlen (p);
289 comma = ",";
290 break;
291 }
292 }
293
7eebfc62
MM		 294 if ((d10v_debug & DEBUG_VALUES) == 0)
295 {
296 *p++ = '\n';
297 *p = '\0';
298 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
299 }
300 else
301 {
302 *p = '\0';
303 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 304
7eebfc62
MM		 305 p = buf;
306 for (i = 0; i < 3; i++)
307 {
308 buf[0] = '\0';
309 switch (in[i])
310 {
311 case OP_VOID:
312 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
313 break;
314
315 case OP_REG_OUTPUT:
316 case OP_DREG_OUTPUT:
317 case OP_CR_OUTPUT:
318 case OP_ACCUM_OUTPUT:
60fc5b72 319 case OP_FLAG_OUTPUT:
7eebfc62
MM		 320 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
321 break;
322
323 case OP_REG:
324 case OP_MEMREF:
325 case OP_POSTDEC:
326 case OP_POSTINC:
327 case OP_PREDEC:
328 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
329 (uint16)State.regs[OP[i]]);
330 break;
331
332 case OP_DREG:
333 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
334 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
335 break;
336
337 case OP_CR:
338 case OP_CR_REVERSE:
339 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
340 (uint16)State.cregs[OP[i]]);
341 break;
342
343 case OP_ACCUM:
344 case OP_ACCUM_REVERSE:
345 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
346 ((int)(State.a[OP[i]] >> 32) & 0xff),
347 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
348 break;
349
350 case OP_CONSTANT16:
351 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
352 (uint16)OP[i]);
353 break;
354
355 case OP_CONSTANT4:
356 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
357 (uint16)SEXT4(OP[i]));
358 break;
359
a18cb100
MM		 360 case OP_CONSTANT8:
361 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
362 (uint16)SEXT8(OP[i]));
363 break;
364
7eebfc62
MM		 365 case OP_CONSTANT3:
366 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
367 (uint16)SEXT3(OP[i]));
368 break;
369
370 case OP_FLAG:
371 if (OP[i] == 0)
372 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
373 State.F0 != 0);
374
375 else if (OP[i] == 1)
376 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
377 State.F1 != 0);
378
379 else
380 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
381 State.C != 0);
382
383 break;
384
385 case OP_MEMREF2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)OP[i]);
388 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
389 (uint16)State.regs[OP[++i]]);
390 break;
a18cb100
MM		 391
392 case OP_R2:
393 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
394 (uint16)State.regs[2]);
395 break;
396
397 case OP_R3:
398 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
399 (uint16)State.regs[3]);
400 break;
7eebfc62
MM		 401 }
402 }
403 }
404}
87178dbd 405
7eebfc62 406static void
a49a15ad 407trace_output_func (result)
7eebfc62
MM		 408 enum op_types result;
409{
410 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 411 {
7eebfc62 412 long tmp;
87178dbd 413
7eebfc62
MM		 414 switch (result)
415 {
416 default:
417 putchar ('\n');
87178dbd
MM		 418 break;
419
420 case OP_REG:
7eebfc62
MM		 421 case OP_REG_OUTPUT:
422 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
423 (uint16)State.regs[OP[0]],
424 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 425 break;
426
427 case OP_DREG:
7eebfc62
MM		 428 case OP_DREG_OUTPUT:
429 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
431 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 432 break;
433
434 case OP_CR:
7eebfc62
MM		 435 case OP_CR_OUTPUT:
436 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
437 (uint16)State.cregs[OP[0]],
438 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 439 break;
440
7eebfc62
MM		 441 case OP_CR_REVERSE:
442 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
443 (uint16)State.cregs[OP[1]],
444 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 445 break;
446
7eebfc62
MM		 447 case OP_ACCUM:
448 case OP_ACCUM_OUTPUT:
069398aa 449 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 450 ((int)(State.a[OP[0]] >> 32) & 0xff),
451 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
452 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 453 break;
454
7eebfc62 455 case OP_ACCUM_REVERSE:
069398aa 456 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 457 ((int)(State.a[OP[1]] >> 32) & 0xff),
458 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
459 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 460 break;
461
462 case OP_FLAG:
60fc5b72 463 case OP_FLAG_OUTPUT:
7eebfc62
MM		 464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
465 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 466 break;
467 }
468 }
87178dbd
MM		 469}
470
471#else
472#define trace_input(NAME, IN1, IN2, IN3)
473#define trace_output(RESULT)
474#endif
2934d1c9
MH		 475
476/* abs */
477void
478OP_4607 ()
479{
87178dbd 480 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 481 State.F1 = State.F0;
482 if ((int16)(State.regs[OP[0]]) < 0)
483 {
484 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
485 State.F0 = 1;
486 }
487 else
488 State.F0 = 0;
87178dbd 489 trace_output (OP_REG);
2934d1c9
MH		 490}
491
492/* abs */
493void
494OP_5607 ()
495{
496 int64 tmp;
497
87178dbd 498 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 499 State.F1 = State.F0;
500 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
501
4c38885c 502 if (State.a[OP[0]] < 0 )
2934d1c9 503 {
4c38885c 504 tmp = -State.a[OP[0]];
2934d1c9
MH		 505 if (State.ST)
506 {
4c38885c 507 if (tmp > MAX32)
2934d1c9 508 State.a[OP[0]] = MAX32;
4c38885c 509 else if (tmp < MIN32)
2934d1c9
MH		 510 State.a[OP[0]] = MIN32;
511 else
4f425a32 512 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 513 }
514 else
4f425a32 515 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 516 State.F0 = 1;
517 }
518 else
519 State.F0 = 0;
87178dbd 520 trace_output (OP_ACCUM);
2934d1c9
MH		 521}
522
523/* add */
524void
525OP_200 ()
526{
527 uint16 tmp = State.regs[OP[0]];
87178dbd 528 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 529 State.regs[OP[0]] += State.regs[OP[1]];
530 if ( tmp > State.regs[OP[0]])
531 State.C = 1;
532 else
533 State.C = 0;
87178dbd 534 trace_output (OP_REG);
2934d1c9
MH		 535}
536
537/* add */
538void
539OP_1201 ()
540{
4c38885c 541 int64 tmp;
4f425a32 542 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 543
544 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 545 if (State.ST)
546 {
547 if ( tmp > MAX32)
548 State.a[OP[0]] = MAX32;
549 else if ( tmp < MIN32)
550 State.a[OP[0]] = MIN32;
551 else
4f425a32 552 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 553 }
554 else
4f425a32 555 State.a[OP[0]] = tmp & MASK40;
87178dbd 556 trace_output (OP_ACCUM);
2934d1c9
MH		 557}
558
559/* add */
560void
561OP_1203 ()
562{
4c38885c 563 int64 tmp;
4f425a32 564 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 565
566 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 567 if (State.ST)
568 {
569 if (tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
4f425a32 574 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 575 }
576 else
4f425a32 577 State.a[OP[0]] = tmp & MASK40;
87178dbd 578 trace_output (OP_ACCUM);
2934d1c9
MH		 579}
580
581/* add2w */
582void
583OP_1200 ()
584{
585 uint32 tmp;
586 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
587 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 588
589 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
2934d1c9
MH		 590 tmp = tmp1 + tmp2;
591 if ( (tmp < tmp1) || (tmp < tmp2) )
592 State.C = 1;
593 else
594 State.C = 0;
595 State.regs[OP[0]] = tmp >> 16;
596 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 597 trace_output (OP_DREG);
2934d1c9
MH		 598}
599
600/* add3 */
601void
602OP_1000000 ()
603{
604 uint16 tmp = State.regs[OP[0]];
2934d1c9 605 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
87178dbd
MM		 606
607 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9
MH		 608 if ( tmp > State.regs[OP[0]])
609 State.C = 1;
610 else
611 State.C = 0;
87178dbd 612 trace_output (OP_REG);
2934d1c9
MH		 613}
614
615/* addac3 */
616void
617OP_17000200 ()
618{
4c38885c 619 int64 tmp;
4f425a32 620 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 621
622 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 623 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
624 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 625 trace_output (OP_DREG);
2934d1c9
MH		 626}
627
628/* addac3 */
629void
630OP_17000202 ()
631{
4c38885c 632 int64 tmp;
4f425a32 633 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 634
635 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 636 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
637 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 638 trace_output (OP_DREG);
2934d1c9
MH		 639}
640
641/* addac3s */
642void
643OP_17001200 ()
644{
4c38885c 645 int64 tmp;
4c38885c 646 State.F1 = State.F0;
87178dbd
MM		 647
648 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 649 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 650 if ( tmp > MAX32)
651 {
652 State.regs[OP[0]] = 0x7fff;
653 State.regs[OP[0]+1] = 0xffff;
654 State.F0 = 1;
655 }
656 else if (tmp < MIN32)
657 {
658 State.regs[OP[0]] = 0x8000;
659 State.regs[OP[0]+1] = 0;
660 State.F0 = 1;
661 }
662 else
663 {
664 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
665 State.regs[OP[0]+1] = tmp & 0xffff;
666 State.F0 = 0;
667 }
87178dbd 668 trace_output (OP_DREG);
2934d1c9
MH		 669}
670
671/* addac3s */
672void
673OP_17001202 ()
674{
4c38885c 675 int64 tmp;
4c38885c 676 State.F1 = State.F0;
87178dbd
MM		 677
678 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 679 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 680 if ( tmp > MAX32)
681 {
682 State.regs[OP[0]] = 0x7fff;
683 State.regs[OP[0]+1] = 0xffff;
684 State.F0 = 1;
685 }
686 else if (tmp < MIN32)
687 {
688 State.regs[OP[0]] = 0x8000;
689 State.regs[OP[0]+1] = 0;
690 State.F0 = 1;
691 }
692 else
693 {
694 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
695 State.regs[OP[0]+1] = tmp & 0xffff;
696 State.F0 = 0;
697 }
87178dbd 698 trace_output (OP_DREG);
2934d1c9
MH		 699}
700
701/* addi */
702void
703OP_201 ()
704{
2254cd90 705 uint tmp = State.regs[OP[0]];
4f425a32
MH		 706 if (OP[1] == 0)
707 OP[1] = 16;
87178dbd 708 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 709 State.regs[OP[0]] += OP[1];
2254cd90
MM		 710 if (tmp > State.regs[OP[0]])
711 State.C = 1;
712 else
713 State.C = 0;
87178dbd 714 trace_output (OP_REG);
2934d1c9
MH		 715}
716
717/* and */
718void
719OP_C00 ()
720{
87178dbd 721 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 722 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 723 trace_output (OP_REG);
2934d1c9
MH		 724}
725
726/* and3 */
727void
728OP_6000000 ()
729{
87178dbd 730 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 731 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 732 trace_output (OP_REG);
2934d1c9
MH		 733}
734
735/* bclri */
736void
737OP_C01 ()
738{
87178dbd 739 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 740 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 741 trace_output (OP_REG);
2934d1c9
MH		 742}
743
744/* bl.s */
745void
746OP_4900 ()
747{
a18cb100 748 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
2934d1c9
MH		 749 State.regs[13] = PC+1;
750 PC += SEXT8 (OP[0]);
87178dbd 751 trace_output (OP_VOID);
2934d1c9
MH		 752}
753
754/* bl.l */
755void
756OP_24800000 ()
757{
a18cb100 758 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
2934d1c9
MH		 759 State.regs[13] = PC+1;
760 PC += OP[0];
87178dbd 761 trace_output (OP_VOID);
2934d1c9
MH		 762}
763
764/* bnoti */
765void
766OP_A01 ()
767{
87178dbd 768 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 769 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 770 trace_output (OP_REG);
2934d1c9
MH		 771}
772
773/* bra.s */
774void
775OP_4800 ()
776{
a18cb100 777 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 778 PC += SEXT8 (OP[0]);
87178dbd 779 trace_output (OP_VOID);
2934d1c9
MH		 780}
781
782/* bra.l */
783void
784OP_24000000 ()
785{
87178dbd 786 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 787 PC += OP[0];
87178dbd 788 trace_output (OP_VOID);
2934d1c9
MH		 789}
790
791/* brf0f.s */
792void
793OP_4A00 ()
794{
a18cb100 795 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9
MH		 796 if (State.F0 == 0)
797 PC += SEXT8 (OP[0]);
87178dbd 798 trace_output (OP_FLAG);
2934d1c9
MH		 799}
800
801/* brf0f.l */
802void
803OP_25000000 ()
804{
87178dbd 805 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 806 if (State.F0 == 0)
807 PC += OP[0];
87178dbd 808 trace_output (OP_FLAG);
2934d1c9
MH		 809}
810
811/* brf0t.s */
812void
813OP_4B00 ()
814{
a18cb100 815 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9
MH		 816 if (State.F0)
817 PC += SEXT8 (OP[0]);
87178dbd 818 trace_output (OP_FLAG);
2934d1c9
MH		 819}
820
821/* brf0t.l */
822void
823OP_25800000 ()
824{
87178dbd 825 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 826 if (State.F0)
827 PC += OP[0];
87178dbd 828 trace_output (OP_FLAG);
2934d1c9
MH		 829}
830
831/* bseti */
832void
833OP_801 ()
834{
87178dbd 835 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 836 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 837 trace_output (OP_REG);
2934d1c9
MH		 838}
839
840/* btsti */
841void
842OP_E01 ()
843{
87178dbd 844 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 845 State.F1 = State.F0;
846 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 847 trace_output (OP_FLAG);
2934d1c9
MH		 848}
849
850/* clrac */
851void
852OP_5601 ()
853{
87178dbd 854 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 855 State.a[OP[0]] = 0;
87178dbd 856 trace_output (OP_ACCUM);
2934d1c9
MH		 857}
858
859/* cmp */
860void
861OP_600 ()
862{
87178dbd 863 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 864 State.F1 = State.F0;
865 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 866 trace_output (OP_FLAG);
2934d1c9
MH		 867}
868
869/* cmp */
870void
871OP_1603 ()
872{
87178dbd 873 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 874 State.F1 = State.F0;
4f425a32 875 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 876 trace_output (OP_FLAG);
2934d1c9
MH		 877}
878
879/* cmpeq */
880void
881OP_400 ()
882{
87178dbd 883 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 884 State.F1 = State.F0;
885 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 886 trace_output (OP_FLAG);
2934d1c9
MH		 887}
888
889/* cmpeq */
890void
891OP_1403 ()
892{
87178dbd 893 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 894 State.F1 = State.F0;
895 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
87178dbd 896 trace_output (OP_FLAG);
2934d1c9
MH		 897}
898
899/* cmpeqi.s */
900void
901OP_401 ()
902{
c12f5c67 903 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 904 State.F1 = State.F0;
c12f5c67 905 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 906 trace_output (OP_FLAG);
2934d1c9
MH		 907}
908
909/* cmpeqi.l */
910void
911OP_2000000 ()
912{
87178dbd 913 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 914 State.F1 = State.F0;
c12f5c67 915 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 916 trace_output (OP_FLAG);
2934d1c9
MH		 917}
918
919/* cmpi.s */
920void
921OP_601 ()
922{
87178dbd 923 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 924 State.F1 = State.F0;
c12f5c67 925 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 926 trace_output (OP_FLAG);
2934d1c9
MH		 927}
928
929/* cmpi.l */
930void
931OP_3000000 ()
932{
87178dbd 933 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 934 State.F1 = State.F0;
935 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 936 trace_output (OP_FLAG);
2934d1c9
MH		 937}
938
939/* cmpu */
940void
941OP_4600 ()
942{
87178dbd 943 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 944 State.F1 = State.F0;
945 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 946 trace_output (OP_FLAG);
2934d1c9
MH		 947}
948
949/* cmpui */
950void
951OP_23000000 ()
952{
87178dbd 953 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 954 State.F1 = State.F0;
c12f5c67 955 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 956 trace_output (OP_FLAG);
2934d1c9
MH		 957}
958
959/* cpfg */
960void
961OP_4E09 ()
962{
963 uint8 *src, *dst;
2934d1c9 964
60fc5b72 965 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 966 if (OP[0] == 0)
967 dst = &State.F0;
968 else
969 dst = &State.F1;
970
971 if (OP[1] == 0)
972 src = &State.F0;
973 else if (OP[1] == 1)
974 src = &State.F1;
975 else
976 src = &State.C;
977
978 *dst = *src;
87178dbd 979 trace_output (OP_FLAG);
2934d1c9
MH		 980}
981
982/* dbt */
983void
984OP_5F20 ()
985{
a49a15ad 986 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 987 State.exception = SIGTRAP;
2934d1c9
MH		 988}
989
990/* divs */
991void
992OP_14002800 ()
993{
994 uint16 foo, tmp, tmpf;
87178dbd
MM		 995
996 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 997 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
998 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
999 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1000 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1001 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1002 trace_output (OP_DREG);
2934d1c9
MH		 1003}
1004
1005/* exef0f */
1006void
1007OP_4E04 ()
1008{
87178dbd 1009 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1010 State.exe = (State.F0 == 0);
87178dbd 1011 trace_output (OP_FLAG);
2934d1c9
MH		 1012}
1013
1014/* exef0t */
1015void
1016OP_4E24 ()
1017{
87178dbd 1018 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1019 State.exe = (State.F0 != 0);
87178dbd 1020 trace_output (OP_FLAG);
2934d1c9
MH		 1021}
1022
1023/* exef1f */
1024void
1025OP_4E40 ()
1026{
87178dbd 1027 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1028 State.exe = (State.F1 == 0);
87178dbd 1029 trace_output (OP_FLAG);
2934d1c9
MH		 1030}
1031
1032/* exef1t */
1033void
1034OP_4E42 ()
1035{
87178dbd 1036 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1037 State.exe = (State.F1 != 0);
87178dbd 1038 trace_output (OP_FLAG);
2934d1c9
MH		 1039}
1040
1041/* exefaf */
1042void
1043OP_4E00 ()
1044{
87178dbd 1045 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1046 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1047 trace_output (OP_FLAG);
2934d1c9
MH		 1048}
1049
1050/* exefat */
1051void
1052OP_4E02 ()
1053{
87178dbd 1054 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1055 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1056 trace_output (OP_FLAG);
2934d1c9
MH		 1057}
1058
1059/* exetaf */
1060void
1061OP_4E20 ()
1062{
87178dbd 1063 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1064 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1065 trace_output (OP_FLAG);
2934d1c9
MH		 1066}
1067
1068/* exetat */
1069void
1070OP_4E22 ()
1071{
87178dbd 1072 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1073 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1074 trace_output (OP_FLAG);
2934d1c9
MH		 1075}
1076
1077/* exp */
1078void
1079OP_15002A00 ()
1080{
1081 uint32 tmp, foo;
1082 int i;
1083
87178dbd 1084 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1085 if (((int16)State.regs[OP[1]]) >= 0)
1086 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1087 else
4c38885c 1088 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1089
1090 foo = 0x40000000;
4c38885c 1091 for (i=1;i<17;i++)
2934d1c9
MH		 1092 {
1093 if (tmp & foo)
1094 {
1095 State.regs[OP[0]] = i-1;
87178dbd 1096 trace_output (OP_REG);
2934d1c9
MH		 1097 return;
1098 }
4c38885c 1099 foo >>= 1;
2934d1c9
MH		 1100 }
1101 State.regs[OP[0]] = 16;
87178dbd 1102 trace_output (OP_REG);
2934d1c9
MH		 1103}
1104
1105/* exp */
1106void
1107OP_15002A02 ()
1108{
4c38885c
MH		 1109 int64 tmp, foo;
1110 int i;
87178dbd
MM		 1111
1112 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
4f425a32 1113 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 1114 tmp = State.a[OP[1]];
1115 else
1116 tmp = ~(State.a[OP[1]]);
1117
1118 foo = 0x4000000000LL;
1119 for (i=1;i<25;i++)
1120 {
1121 if (tmp & foo)
1122 {
1123 State.regs[OP[0]] = i-9;
87178dbd 1124 trace_output (OP_REG);
4c38885c
MH		 1125 return;
1126 }
1127 foo >>= 1;
1128 }
1129 State.regs[OP[0]] = 16;
87178dbd 1130 trace_output (OP_REG);
2934d1c9
MH		 1131}
1132
1133/* jl */
1134void
1135OP_4D00 ()
1136{
a18cb100 1137 trace_input ("jl", OP_REG, OP_R2, OP_R3);
2934d1c9
MH		 1138 State.regs[13] = PC+1;
1139 PC = State.regs[OP[0]];
87178dbd 1140 trace_output (OP_VOID);
2934d1c9
MH		 1141}
1142
1143/* jmp */
1144void
1145OP_4C00 ()
1146{
a18cb100
MM		 1147 trace_input ("jmp", OP_REG,
1148 (OP[0] == 13) ? OP_R2 : OP_VOID,
1149 (OP[0] == 13) ? OP_R3 : OP_VOID);
1150
2934d1c9 1151 PC = State.regs[OP[0]];
87178dbd 1152 trace_output (OP_VOID);
2934d1c9
MH		 1153}
1154
1155/* ld */
1156void
1157OP_30000000 ()
1158{
87178dbd 1159 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1160 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1161 trace_output (OP_REG);
2934d1c9
MH		 1162}
1163
1164/* ld */
1165void
1166OP_6401 ()
1167{
87178dbd 1168 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1169 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1170 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1171 trace_output (OP_REG);
2934d1c9
MH		 1172}
1173
1174/* ld */
1175void
1176OP_6001 ()
1177{
87178dbd 1178 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1179 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1180 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1181 trace_output (OP_REG);
2934d1c9
MH		 1182}
1183
1184/* ld */
1185void
1186OP_6000 ()
1187{
87178dbd 1188 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1189 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1190 trace_output (OP_REG);
2934d1c9
MH		 1191}
1192
1193/* ld2w */
1194void
1195OP_31000000 ()
1196{
308f64d3 1197 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9
MH		 1198 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1199 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
87178dbd 1200 trace_output (OP_DREG);
2934d1c9
MH		 1201}
1202
1203/* ld2w */
1204void
1205OP_6601 ()
1206{
87178dbd 1207 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c
MH		 1208 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1209 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 1210 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1211 trace_output (OP_DREG);
2934d1c9
MH		 1212}
1213
1214/* ld2w */
1215void
1216OP_6201 ()
1217{
87178dbd 1218 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c
MH		 1219 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1220 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 1221 INC_ADDR(State.regs[OP[1]],4);
87178dbd 1222 trace_output (OP_REG);
2934d1c9
MH		 1223}
1224
1225/* ld2w */
1226void
1227OP_6200 ()
1228{
addb61a5 1229 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
4c38885c
MH		 1230 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1231 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
87178dbd 1232 trace_output (OP_REG);
2934d1c9
MH		 1233}
1234
1235/* ldb */
1236void
1237OP_38000000 ()
1238{
87178dbd 1239 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9
MH		 1240 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1241 SEXT8 (State.regs[OP[0]]);
87178dbd 1242 trace_output (OP_REG);
2934d1c9
MH		 1243}
1244
1245/* ldb */
1246void
1247OP_7000 ()
1248{
87178dbd 1249 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9
MH		 1250 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1251 SEXT8 (State.regs[OP[0]]);
87178dbd 1252 trace_output (OP_REG);
2934d1c9
MH		 1253}
1254
1255/* ldi.s */
1256void
1257OP_4001 ()
1258{
87178dbd 1259 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1260 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1261 trace_output (OP_REG);
2934d1c9
MH		 1262}
1263
1264/* ldi.l */
1265void
1266OP_20000000 ()
1267{
87178dbd 1268 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1269 State.regs[OP[0]] = OP[1];
87178dbd 1270 trace_output (OP_REG);
2934d1c9
MH		 1271}
1272
1273/* ldub */
1274void
1275OP_39000000 ()
1276{
87178dbd 1277 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1278 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1279 trace_output (OP_REG);
2934d1c9
MH		 1280}
1281
1282/* ldub */
1283void
1284OP_7200 ()
1285{
87178dbd 1286 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1287 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1288 trace_output (OP_REG);
2934d1c9
MH		 1289}
1290
1291/* mac */
1292void
1293OP_2A00 ()
1294{
4c38885c 1295 int64 tmp;
87178dbd
MM		 1296
1297 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1298 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1299
1300 if (State.FX)
4f425a32 1301 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1302
1303 if (State.ST && tmp > MAX32)
1304 tmp = MAX32;
1305
4f425a32 1306 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1307 if (State.ST)
1308 {
1309 if (tmp > MAX32)
1310 State.a[OP[0]] = MAX32;
1311 else if (tmp < MIN32)
1312 State.a[OP[0]] = MIN32;
1313 else
4f425a32 1314 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1315 }
1316 else
4f425a32 1317 State.a[OP[0]] = tmp & MASK40;
87178dbd 1318 trace_output (OP_ACCUM);
2934d1c9
MH		 1319}
1320
1321/* macsu */
1322void
1323OP_1A00 ()
1324{
4f425a32 1325 int64 tmp;
87178dbd
MM		 1326
1327 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1328 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1329 if (State.FX)
1330 tmp = SEXT40( (tmp << 1) & MASK40);
1331
1332 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1333 trace_output (OP_ACCUM);
2934d1c9
MH		 1334}
1335
1336/* macu */
1337void
1338OP_3A00 ()
1339{
4f425a32 1340 int64 tmp;
87178dbd
MM		 1341
1342 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1343 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1344 if (State.FX)
1345 tmp = SEXT40( (tmp << 1) & MASK40);
1346 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1347 trace_output (OP_ACCUM);
2934d1c9
MH		 1348}
1349
1350/* max */
1351void
1352OP_2600 ()
1353{
87178dbd 1354 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1355 State.F1 = State.F0;
ea2155e8 1356 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1357 {
1358 State.regs[OP[0]] = State.regs[OP[1]];
1359 State.F0 = 1;
1360 }
1361 else
1362 State.F0 = 0;
87178dbd 1363 trace_output (OP_REG);
2934d1c9
MH		 1364}
1365
1366/* max */
1367void
1368OP_3600 ()
1369{
4f425a32 1370 int64 tmp;
87178dbd
MM		 1371
1372 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1373 State.F1 = State.F0;
1374 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1375 if (tmp > SEXT40(State.a[OP[0]]))
1376 {
1377 State.a[OP[0]] = tmp & MASK40;
1378 State.F0 = 1;
1379 }
1380 else
1381 State.F0 = 0;
87178dbd 1382 trace_output (OP_ACCUM);
2934d1c9
MH		 1383}
1384
1385/* max */
1386void
1387OP_3602 ()
1388{
87178dbd 1389 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1390 State.F1 = State.F0;
1391 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1392 {
1393 State.a[OP[0]] = State.a[OP[1]];
1394 State.F0 = 1;
1395 }
1396 else
1397 State.F0 = 0;
87178dbd 1398 trace_output (OP_ACCUM);
2934d1c9
MH		 1399}
1400
4f425a32 1401
2934d1c9
MH		 1402/* min */
1403void
1404OP_2601 ()
1405{
87178dbd 1406 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1407 State.F1 = State.F0;
ea2155e8 1408 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1409 {
1410 State.regs[OP[0]] = State.regs[OP[1]];
1411 State.F0 = 1;
1412 }
1413 else
1414 State.F0 = 0;
87178dbd 1415 trace_output (OP_REG);
2934d1c9
MH		 1416}
1417
1418/* min */
1419void
1420OP_3601 ()
1421{
4f425a32 1422 int64 tmp;
87178dbd
MM		 1423
1424 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1425 State.F1 = State.F0;
1426 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1427 if (tmp < SEXT40(State.a[OP[0]]))
1428 {
1429 State.a[OP[0]] = tmp & MASK40;
1430 State.F0 = 1;
1431 }
1432 else
1433 State.F0 = 0;
87178dbd 1434 trace_output (OP_ACCUM);
2934d1c9
MH		 1435}
1436
1437/* min */
1438void
1439OP_3603 ()
1440{
87178dbd 1441 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1442 State.F1 = State.F0;
1443 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1444 {
1445 State.a[OP[0]] = State.a[OP[1]];
1446 State.F0 = 1;
1447 }
1448 else
1449 State.F0 = 0;
87178dbd 1450 trace_output (OP_ACCUM);
2934d1c9
MH		 1451}
1452
1453/* msb */
1454void
1455OP_2800 ()
1456{
4f425a32 1457 int64 tmp;
87178dbd
MM		 1458
1459 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1460 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1461
1462 if (State.FX)
1463 tmp = SEXT40 ((tmp << 1) & MASK40);
1464
1465 if (State.ST && tmp > MAX32)
1466 tmp = MAX32;
1467
1468 tmp = SEXT40(State.a[OP[0]]) - tmp;
1469 if (State.ST)
1470 {
1471 if (tmp > MAX32)
1472 State.a[OP[0]] = MAX32;
1473 else if (tmp < MIN32)
1474 State.a[OP[0]] = MIN32;
1475 else
1476 State.a[OP[0]] = tmp & MASK40;
1477 }
1478 else
1479 State.a[OP[0]] = tmp & MASK40;
87178dbd 1480 trace_output (OP_ACCUM);
2934d1c9
MH		 1481}
1482
1483/* msbsu */
1484void
1485OP_1800 ()
1486{
4f425a32 1487 int64 tmp;
87178dbd
MM		 1488
1489 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1490 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1491 if (State.FX)
1492 tmp = SEXT40( (tmp << 1) & MASK40);
1493
1494 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1495 trace_output (OP_ACCUM);
2934d1c9
MH		 1496}
1497
1498/* msbu */
1499void
1500OP_3800 ()
1501{
4f425a32 1502 int64 tmp;
87178dbd
MM		 1503
1504 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1505 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1506 if (State.FX)
1507 tmp = SEXT40( (tmp << 1) & MASK40);
1508
1509 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1510 trace_output (OP_ACCUM);
2934d1c9
MH		 1511}
1512
1513/* mul */
1514void
1515OP_2E00 ()
1516{
87178dbd 1517 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1518 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1519 trace_output (OP_REG);
2934d1c9
MH		 1520}
1521
1522/* mulx */
1523void
1524OP_2C00 ()
1525{
4f425a32 1526 int64 tmp;
87178dbd
MM		 1527
1528 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1529 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1530
1531 if (State.FX)
1532 tmp = SEXT40 ((tmp << 1) & MASK40);
1533
1534 if (State.ST && tmp > MAX32)
1535 State.a[OP[0]] = MAX32;
1536 else
1537 State.a[OP[0]] = tmp & MASK40;
87178dbd 1538 trace_output (OP_ACCUM);
2934d1c9
MH		 1539}
1540
1541/* mulxsu */
1542void
1543OP_1C00 ()
1544{
4f425a32 1545 int64 tmp;
87178dbd
MM		 1546
1547 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1548 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1549
1550 if (State.FX)
1551 tmp <<= 1;
1552
1553 State.a[OP[0]] = tmp & MASK40;
87178dbd 1554 trace_output (OP_ACCUM);
2934d1c9
MH		 1555}
1556
1557/* mulxu */
1558void
1559OP_3C00 ()
1560{
4f425a32 1561 int64 tmp;
87178dbd
MM		 1562
1563 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1564 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1565
1566 if (State.FX)
1567 tmp <<= 1;
1568
1569 State.a[OP[0]] = tmp & MASK40;
87178dbd 1570 trace_output (OP_ACCUM);
2934d1c9
MH		 1571}
1572
1573/* mv */
1574void
1575OP_4000 ()
1576{
87178dbd 1577 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1578 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1579 trace_output (OP_REG);
2934d1c9
MH		 1580}
1581
1582/* mv2w */
1583void
1584OP_5000 ()
1585{
87178dbd 1586 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1587 State.regs[OP[0]] = State.regs[OP[1]];
1588 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1589 trace_output (OP_DREG);
2934d1c9
MH		 1590}
1591
1592/* mv2wfac */
1593void
1594OP_3E00 ()
1595{
87178dbd 1596 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1597 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1598 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1599 trace_output (OP_DREG);
2934d1c9
MH		 1600}
1601
1602/* mv2wtac */
1603void
1604OP_3E01 ()
1605{
87178dbd 1606 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
4f425a32 1607 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
87178dbd 1608 trace_output (OP_ACCUM);
2934d1c9
MH		 1609}
1610
1611/* mvac */
1612void
1613OP_3E03 ()
1614{
87178dbd 1615 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1616 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1617 trace_output (OP_ACCUM);
2934d1c9
MH		 1618}
1619
1620/* mvb */
1621void
1622OP_5400 ()
1623{
87178dbd 1624 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1625 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1626 trace_output (OP_REG);
2934d1c9
MH		 1627}
1628
1629/* mvf0f */
1630void
1631OP_4400 ()
1632{
87178dbd 1633 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1634 if (State.F0 == 0)
1635 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1636 trace_output (OP_REG);
2934d1c9
MH		 1637}
1638
1639/* mvf0t */
1640void
1641OP_4401 ()
1642{
87178dbd 1643 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1644 if (State.F0)
1645 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1646 trace_output (OP_REG);
2934d1c9
MH		 1647}
1648
1649/* mvfacg */
1650void
1651OP_1E04 ()
1652{
87178dbd 1653 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1654 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1655 trace_output (OP_ACCUM);
2934d1c9
MH		 1656}
1657
1658/* mvfachi */
1659void
1660OP_1E00 ()
1661{
87178dbd 1662 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1663 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1664 trace_output (OP_REG);
2934d1c9
MH		 1665}
1666
1667/* mvfaclo */
1668void
1669OP_1E02 ()
1670{
87178dbd 1671 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1672 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1673 trace_output (OP_REG);
2934d1c9
MH		 1674}
1675
1676/* mvfc */
1677void
1678OP_5200 ()
1679{
87178dbd 1680 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1681 if (OP[1] == 0)
1682 {
1683 /* PSW is treated specially */
1684 PSW = 0;
1685 if (State.SM) PSW |= 0x8000;
1686 if (State.EA) PSW |= 0x2000;
1687 if (State.DB) PSW |= 0x1000;
1688 if (State.IE) PSW |= 0x400;
1689 if (State.RP) PSW |= 0x200;
1690 if (State.MD) PSW |= 0x100;
1691 if (State.FX) PSW |= 0x80;
1692 if (State.ST) PSW |= 0x40;
1693 if (State.F0) PSW |= 8;
1694 if (State.F1) PSW |= 4;
1695 if (State.C) PSW |= 1;
1696 }
1697 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1698 trace_output (OP_REG);
2934d1c9
MH		 1699}
1700
1701/* mvtacg */
1702void
1703OP_1E41 ()
1704{
87178dbd 1705 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1706 State.a[OP[1]] &= MASK32;
1707 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1708 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1709}
1710
1711/* mvtachi */
1712void
1713OP_1E01 ()
1714{
1715 uint16 tmp;
87178dbd
MM		 1716
1717 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1718 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1719 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1720 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1721}
1722
1723/* mvtaclo */
1724void
1725OP_1E21 ()
1726{
87178dbd 1727 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1728 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1729 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1730}
1731
1732/* mvtc */
1733void
1734OP_5600 ()
1735{
87178dbd 1736 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1737 State.cregs[OP[1]] = State.regs[OP[0]];
1738 if (OP[1] == 0)
1739 {
1740 /* PSW is treated specially */
1741 State.SM = (PSW & 0x8000) ? 1 : 0;
1742 State.EA = (PSW & 0x2000) ? 1 : 0;
1743 State.DB = (PSW & 0x1000) ? 1 : 0;
1744 State.IE = (PSW & 0x400) ? 1 : 0;
1745 State.RP = (PSW & 0x200) ? 1 : 0;
1746 State.MD = (PSW & 0x100) ? 1 : 0;
1747 State.FX = (PSW & 0x80) ? 1 : 0;
1748 State.ST = (PSW & 0x40) ? 1 : 0;
1749 State.F0 = (PSW & 8) ? 1 : 0;
1750 State.F1 = (PSW & 4) ? 1 : 0;
1751 State.C = PSW & 1;
1752 if (State.ST && !State.FX)
1753 {
7eebfc62
MM		 1754 (*d10v_callback->printf_filtered) (d10v_callback,
1755 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1756 PC<<2);
4f425a32 1757 State.exception = SIGILL;
2934d1c9
MH		 1758 }
1759 }
87178dbd 1760 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1761}
1762
1763/* mvub */
1764void
1765OP_5401 ()
1766{
87178dbd 1767 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1768 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1769 trace_output (OP_REG);
2934d1c9
MH		 1770}
1771
1772/* neg */
1773void
1774OP_4605 ()
1775{
87178dbd 1776 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1777 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1778 trace_output (OP_REG);
2934d1c9
MH		 1779}
1780
1781/* neg */
1782void
1783OP_5605 ()
1784{
1785 int64 tmp;
87178dbd
MM		 1786
1787 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1788 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1789 if (State.ST)
1790 {
4c38885c 1791 if ( tmp > MAX32)
2934d1c9 1792 State.a[OP[0]] = MAX32;
4c38885c 1793 else if (tmp < MIN32)
2934d1c9
MH		 1794 State.a[OP[0]] = MIN32;
1795 else
4f425a32 1796 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1797 }
1798 else
4f425a32 1799 State.a[OP[0]] = tmp & MASK40;
87178dbd 1800 trace_output (OP_ACCUM);
2934d1c9
MH		 1801}
1802
1803
1804/* nop */
1805void
1806OP_5E00 ()
1807{
87178dbd
MM		 1808 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1809 trace_output (OP_VOID);
7eebfc62
MM		 1810
1811 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1812 left_nops++;
1813 else
1814 right_nops++;
2934d1c9
MH		 1815}
1816
1817/* not */
1818void
1819OP_4603 ()
1820{
87178dbd 1821 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1822 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1823 trace_output (OP_REG);
2934d1c9
MH		 1824}
1825
1826/* or */
1827void
1828OP_800 ()
1829{
87178dbd 1830 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1831 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1832 trace_output (OP_REG);
2934d1c9
MH		 1833}
1834
1835/* or3 */
1836void
1837OP_4000000 ()
1838{
87178dbd 1839 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1840 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1841 trace_output (OP_REG);
2934d1c9
MH		 1842}
1843
1844/* rac */
1845void
1846OP_5201 ()
1847{
1848 int64 tmp;
1849 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1850
1851 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1852 if (OP[1] != 0)
1853 {
7eebfc62
MM		 1854 (*d10v_callback->printf_filtered) (d10v_callback,
1855 "ERROR at PC 0x%x: instruction only valid for A0\n",
1856 PC<<2);
166acb9f
MH		 1857 State.exception = SIGILL;
1858 }
1859
2934d1c9
MH		 1860 State.F1 = State.F0;
1861 if (shift >=0)
1862 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1863 else
1864 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1865 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1866 if (tmp > MAX32)
2934d1c9
MH		 1867 {
1868 State.regs[OP[0]] = 0x7fff;
1869 State.regs[OP[0]+1] = 0xffff;
1870 State.F0 = 1;
1871 }
4c38885c 1872 else if (tmp < MIN32)
2934d1c9
MH		 1873 {
1874 State.regs[OP[0]] = 0x8000;
1875 State.regs[OP[0]+1] = 0;
1876 State.F0 = 1;
1877 }
1878 else
1879 {
1880 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1881 State.regs[OP[0]+1] = tmp & 0xffff;
1882 State.F0 = 0;
1883 }
87178dbd 1884 trace_output (OP_DREG);
2934d1c9
MH		 1885}
1886
1887/* rachi */
1888void
1889OP_4201 ()
1890{
4c38885c
MH		 1891 int64 tmp;
1892 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1893
1894 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1895 State.F1 = State.F0;
1896 if (shift >=0)
166acb9f 1897 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1898 else
166acb9f 1899 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1900 tmp += 0x8000;
63a91cfb 1901
4c38885c
MH		 1902 if (tmp > MAX32)
1903 {
1904 State.regs[OP[0]] = 0x7fff;
1905 State.F0 = 1;
1906 }
1907 else if (tmp < 0xfff80000000LL)
1908 {
1909 State.regs[OP[0]] = 0x8000;
1910 State.F0 = 1;
1911 }
1912 else
1913 {
1914 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1915 State.F0 = 0;
1916 }
87178dbd 1917 trace_output (OP_REG);
2934d1c9
MH		 1918}
1919
1920/* rep */
1921void
1922OP_27000000 ()
1923{
87178dbd 1924 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1925 RPT_S = PC + 1;
1926 RPT_E = PC + OP[1];
1927 RPT_C = State.regs[OP[0]];
1928 State.RP = 1;
1929 if (RPT_C == 0)
1930 {
7eebfc62 1931 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1932 State.exception = SIGILL;
2934d1c9 1933 }
4c38885c
MH		 1934 if (OP[1] < 4)
1935 {
7eebfc62 1936 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1937 State.exception = SIGILL;
4c38885c 1938 }
87178dbd 1939 trace_output (OP_VOID);
2934d1c9
MH		 1940}
1941
1942/* repi */
1943void
1944OP_2F000000 ()
1945{
87178dbd 1946 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1947 RPT_S = PC + 1;
1948 RPT_E = PC + OP[1];
1949 RPT_C = OP[0];
1950 State.RP = 1;
1951 if (RPT_C == 0)
1952 {
7eebfc62 1953 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1954 State.exception = SIGILL;
4c38885c
MH		 1955 }
1956 if (OP[1] < 4)
1957 {
7eebfc62 1958 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 1959 State.exception = SIGILL;
2934d1c9 1960 }
87178dbd 1961 trace_output (OP_VOID);
2934d1c9
MH		 1962}
1963
1964/* rtd */
1965void
1966OP_5F60 ()
1967{
7eebfc62 1968 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 1969 State.exception = SIGILL;
2934d1c9
MH		 1970}
1971
1972/* rte */
1973void
1974OP_5F40 ()
1975{
87178dbd 1976 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 1977 PC = BPC;
1978 PSW = BPSW;
87178dbd 1979 trace_output (OP_VOID);
2934d1c9
MH		 1980}
1981
1982/* sadd */
1983void
1984OP_1223 ()
1985{
4c38885c 1986 int64 tmp;
87178dbd
MM		 1987
1988 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 1989 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 1990 if (State.ST)
1991 {
1992 if (tmp > MAX32)
1993 State.a[OP[0]] = MAX32;
1994 else if (tmp < MIN32)
1995 State.a[OP[0]] = MIN32;
1996 else
4f425a32 1997 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1998 }
1999 else
4f425a32 2000 State.a[OP[0]] = tmp & MASK40;
87178dbd 2001 trace_output (OP_ACCUM);
2934d1c9
MH		 2002}
2003
2004/* setf0f */
2005void
2006OP_4611 ()
2007{
87178dbd 2008 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2009 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2010 trace_output (OP_REG);
2934d1c9
MH		 2011}
2012
2013/* setf0t */
2014void
2015OP_4613 ()
2016{
87178dbd 2017 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2018 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2019 trace_output (OP_REG);
2934d1c9
MH		 2020}
2021
2022/* sleep */
2023void
2024OP_5FC0 ()
2025{
87178dbd 2026 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2027 State.IE = 1;
87178dbd 2028 trace_output (OP_VOID);
2934d1c9
MH		 2029}
2030
2031/* sll */
2032void
2033OP_2200 ()
2034{
87178dbd 2035 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2036 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2037 trace_output (OP_REG);
2934d1c9
MH		 2038}
2039
2040/* sll */
2041void
2042OP_3200 ()
2043{
4c38885c 2044 int64 tmp;
87178dbd 2045 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2046 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2047 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2048 else
2049 {
2050 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2051 State.exception = SIGILL;
2052 return;
2053 }
4c38885c
MH		 2054
2055 if (State.ST)
2056 {
2057 if (tmp > MAX32)
2058 State.a[OP[0]] = MAX32;
2059 else if (tmp < 0xffffff80000000LL)
2060 State.a[OP[0]] = MIN32;
2061 else
2062 State.a[OP[0]] = tmp & MASK40;
2063 }
2064 else
2065 State.a[OP[0]] = tmp & MASK40;
87178dbd 2066 trace_output (OP_ACCUM);
2934d1c9
MH		 2067}
2068
2069/* slli */
2070void
2071OP_2201 ()
2072{
87178dbd 2073 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2074 State.regs[OP[0]] <<= OP[1];
87178dbd 2075 trace_output (OP_REG);
2934d1c9
MH		 2076}
2077
2078/* slli */
2079void
2080OP_3201 ()
2081{
4c38885c 2082 int64 tmp;
4f425a32
MH		 2083
2084 if (OP[1] == 0)
2085 OP[1] = 16;
4f425a32 2086
87178dbd 2087 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2088 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2089
2090 if (State.ST)
2091 {
2092 if (tmp > MAX32)
2093 State.a[OP[0]] = MAX32;
2094 else if (tmp < 0xffffff80000000LL)
2095 State.a[OP[0]] = MIN32;
2096 else
2097 State.a[OP[0]] = tmp & MASK40;
2098 }
2099 else
2100 State.a[OP[0]] = tmp & MASK40;
87178dbd 2101 trace_output (OP_ACCUM);
2934d1c9
MH		 2102}
2103
2104/* slx */
2105void
2106OP_460B ()
2107{
2108 uint16 tmp;
87178dbd
MM		 2109
2110 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2111 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2112 trace_output (OP_REG);
2934d1c9
MH		 2113}
2114
2115/* sra */
2116void
2117OP_2400 ()
2118{
87178dbd 2119 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2120 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2121 trace_output (OP_REG);
2934d1c9
MH		 2122}
2123
2124/* sra */
2125void
2126OP_3400 ()
2127{
87178dbd 2128 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2129 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2130 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2131 else
2132 {
2133 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2134 State.exception = SIGILL;
2135 return;
2136 }
2137
87178dbd 2138 trace_output (OP_ACCUM);
2934d1c9
MH		 2139}
2140
2141/* srai */
2142void
2143OP_2401 ()
2144{
87178dbd 2145 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2146 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2147 trace_output (OP_REG);
2934d1c9
MH		 2148}
2149
2150/* srai */
2151void
2152OP_3401 ()
2153{
4f425a32
MH		 2154 if (OP[1] == 0)
2155 OP[1] = 16;
87178dbd
MM		 2156
2157 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2158 State.a[OP[0]] >>= OP[1];
2159 trace_output (OP_ACCUM);
2934d1c9
MH		 2160}
2161
2162/* srl */
2163void
2164OP_2000 ()
2165{
87178dbd 2166 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2167 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2168 trace_output (OP_REG);
2934d1c9
MH		 2169}
2170
2171/* srl */
2172void
2173OP_3000 ()
2174{
87178dbd 2175 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2176 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2177 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2178 else
2179 {
2180 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2181 State.exception = SIGILL;
2182 return;
2183 }
2184
87178dbd 2185 trace_output (OP_ACCUM);
2934d1c9
MH		 2186}
2187
2188/* srli */
2189void
2190OP_2001 ()
2191{
87178dbd 2192 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2193 State.regs[OP[0]] >>= OP[1];
87178dbd 2194 trace_output (OP_REG);
2934d1c9
MH		 2195}
2196
2197/* srli */
2198void
2199OP_3001 ()
2200{
4f425a32
MH		 2201 if (OP[1] == 0)
2202 OP[1] = 16;
87178dbd
MM		 2203
2204 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2205 State.a[OP[0]] >>= OP[1];
2206 trace_output (OP_ACCUM);
2934d1c9
MH		 2207}
2208
2209/* srx */
2210void
2211OP_4609 ()
2212{
2213 uint16 tmp;
87178dbd
MM		 2214
2215 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2216 tmp = State.F0 << 15;
2217 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2218 trace_output (OP_REG);
2934d1c9
MH		 2219}
2220
2221/* st */
2222void
2223OP_34000000 ()
2224{
87178dbd 2225 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2226 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2227 trace_output (OP_VOID);
2934d1c9
MH		 2228}
2229
2230/* st */
2231void
2232OP_6800 ()
2233{
87178dbd 2234 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2235 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2236 trace_output (OP_VOID);
2934d1c9
MH		 2237}
2238
2239/* st */
2240void
2241OP_6C1F ()
2242{
87178dbd 2243 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2244 if ( OP[1] != 15 )
2245 {
7eebfc62 2246 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2247 State.exception = SIGILL;
2248 return;
4c38885c
MH		 2249 }
2250 State.regs[OP[1]] -= 2;
2251 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2252 trace_output (OP_VOID);
2934d1c9
MH		 2253}
2254
2255/* st */
2256void
2257OP_6801 ()
2258{
87178dbd 2259 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2260 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2261 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2262 trace_output (OP_VOID);
2934d1c9
MH		 2263}
2264
2265/* st */
2266void
2267OP_6C01 ()
2268{
87178dbd 2269 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c 2270 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2271 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2272 trace_output (OP_VOID);
2934d1c9
MH		 2273}
2274
2275/* st2w */
2276void
2277OP_35000000 ()
2278{
87178dbd 2279 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2280 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2281 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2282 trace_output (OP_VOID);
2934d1c9
MH		 2283}
2284
2285/* st2w */
2286void
2287OP_6A00 ()
2288{
a18cb100 2289 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2290 SW (State.regs[OP[1]], State.regs[OP[0]]);
2291 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2292 trace_output (OP_VOID);
2934d1c9
MH		 2293}
2294
2295/* st2w */
2296void
2297OP_6E1F ()
2298{
a18cb100 2299 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2300 if ( OP[1] != 15 )
2301 {
7eebfc62 2302 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2303 State.exception = SIGILL;
2304 return;
4c38885c
MH		 2305 }
2306 State.regs[OP[1]] -= 4;
2307 SW (State.regs[OP[1]], State.regs[OP[0]]);
2308 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2309 trace_output (OP_VOID);
2934d1c9
MH		 2310}
2311
2312/* st2w */
2313void
2314OP_6A01 ()
2315{
a18cb100 2316 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
4c38885c
MH		 2317 SW (State.regs[OP[1]], State.regs[OP[0]]);
2318 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2319 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2320 trace_output (OP_VOID);
2934d1c9
MH		 2321}
2322
2323/* st2w */
2324void
2325OP_6E01 ()
2326{
a18cb100 2327 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2328 SW (State.regs[OP[1]], State.regs[OP[0]]);
2329 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2330 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2331 trace_output (OP_VOID);
2934d1c9
MH		 2332}
2333
2334/* stb */
2335void
2336OP_3C000000 ()
2337{
87178dbd 2338 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2339 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2340 trace_output (OP_VOID);
2934d1c9
MH		 2341}
2342
2343/* stb */
2344void
2345OP_7800 ()
2346{
87178dbd 2347 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2348 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2349 trace_output (OP_VOID);
2934d1c9
MH		 2350}
2351
2352/* stop */
2353void
2354OP_5FE0 ()
2355{
87178dbd 2356 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2357 State.exception = SIG_D10V_STOP;
87178dbd 2358 trace_output (OP_VOID);
2934d1c9
MH		 2359}
2360
2361/* sub */
2362void
2363OP_0 ()
4c38885c
MH		 2364{
2365 int32 tmp;
87178dbd
MM		 2366
2367 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
4c38885c
MH		 2368 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2369 State.C = (tmp & 0xffff0000) ? 1 : 0;
2370 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2371 trace_output (OP_REG);
4c38885c
MH		 2372}
2373
2374/* sub */
2375void
2376OP_1001 ()
2377{
4f425a32 2378 int64 tmp;
87178dbd
MM		 2379
2380 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2381 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2382 if (State.ST)
2383 {
2384 if ( tmp > MAX32)
2385 State.a[OP[0]] = MAX32;
2386 else if ( tmp < MIN32)
2387 State.a[OP[0]] = MIN32;
2388 else
2389 State.a[OP[0]] = tmp & MASK40;
2390 }
2391 else
2392 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2393
2394 trace_output (OP_ACCUM);
4c38885c
MH		 2395}
2396
2397/* sub */
2398
2399void
2400OP_1003 ()
2934d1c9 2401{
4f425a32 2402 int64 tmp;
87178dbd
MM		 2403
2404 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2405 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2406 if (State.ST)
2407 {
2408 if (tmp > MAX32)
2409 State.a[OP[0]] = MAX32;
2410 else if ( tmp < MIN32)
2411 State.a[OP[0]] = MIN32;
2412 else
2413 State.a[OP[0]] = tmp & MASK40;
2414 }
2415 else
2416 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2417
2418 trace_output (OP_ACCUM);
2934d1c9
MH		 2419}
2420
2421/* sub2w */
2422void
2423OP_1000 ()
2424{
4c38885c
MH		 2425 int64 tmp;
2426 int32 a,b;
4c38885c 2427
87178dbd 2428 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
4c38885c
MH		 2429 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2430 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2431 tmp = a-b;
2432 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2433 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2434 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2435 trace_output (OP_DREG);
2934d1c9
MH		 2436}
2437
2438/* subac3 */
2439void
2440OP_17000000 ()
2441{
4f425a32 2442 int64 tmp;
87178dbd
MM		 2443
2444 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2445 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2446 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2447 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2448 trace_output (OP_DREG);
2934d1c9
MH		 2449}
2450
2451/* subac3 */
2452void
2453OP_17000002 ()
2454{
4f425a32 2455 int64 tmp;
87178dbd
MM		 2456
2457 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2458 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2459 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2460 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2461 trace_output (OP_DREG);
2934d1c9
MH		 2462}
2463
2464/* subac3s */
2465void
2466OP_17001000 ()
2467{
4f425a32 2468 int64 tmp;
87178dbd
MM		 2469
2470 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2471 State.F1 = State.F0;
2472 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2473 if ( tmp > MAX32)
2474 {
2475 State.regs[OP[0]] = 0x7fff;
2476 State.regs[OP[0]+1] = 0xffff;
2477 State.F0 = 1;
2478 }
2479 else if (tmp < MIN32)
2480 {
2481 State.regs[OP[0]] = 0x8000;
2482 State.regs[OP[0]+1] = 0;
2483 State.F0 = 1;
2484 }
2485 else
2486 {
2487 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2488 State.regs[OP[0]+1] = tmp & 0xffff;
2489 State.F0 = 0;
2490 }
87178dbd 2491 trace_output (OP_DREG);
2934d1c9
MH		 2492}
2493
2494/* subac3s */
2495void
2496OP_17001002 ()
2497{
4f425a32 2498 int64 tmp;
87178dbd
MM		 2499
2500 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2501 State.F1 = State.F0;
2502 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2503 if ( tmp > MAX32)
2504 {
2505 State.regs[OP[0]] = 0x7fff;
2506 State.regs[OP[0]+1] = 0xffff;
2507 State.F0 = 1;
2508 }
2509 else if (tmp < MIN32)
2510 {
2511 State.regs[OP[0]] = 0x8000;
2512 State.regs[OP[0]+1] = 0;
2513 State.F0 = 1;
2514 }
2515 else
2516 {
2517 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2518 State.regs[OP[0]+1] = tmp & 0xffff;
2519 State.F0 = 0;
2520 }
87178dbd 2521 trace_output (OP_DREG);
2934d1c9
MH		 2522}
2523
2524/* subi */
2525void
2526OP_1 ()
2527{
4c38885c 2528 int32 tmp;
4f425a32
MH		 2529 if (OP[1] == 0)
2530 OP[1] = 16;
87178dbd
MM		 2531
2532 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c
MH		 2533 tmp = (int16)State.regs[OP[0]] - OP[1];
2534 State.C = (tmp & 0xffff0000) ? 1 : 0;
2535 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2536 trace_output (OP_REG);
2934d1c9
MH		 2537}
2538
2539/* trap */
2540void
2541OP_5F00 ()
2542{
a5719092 2543 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2544 trace_output (OP_VOID);
2934d1c9 2545
63a91cfb 2546 switch (OP[0])
2934d1c9 2547 {
63a91cfb 2548 default:
19d44375 2549#if 0
7eebfc62 2550 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb 2551 State.exception = SIGILL;
19d44375
MM		 2552#else
2553 /* Use any other traps for batch debugging. */
2554 {
2555 int i;
2556 static int first_time = 1;
2557
2558 if (first_time)
2559 {
2560 first_time = 0;
2561 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2562 for (i = 0; i < 16; i++)
2563 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2564 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2565 }
2566
2567 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2568
2569 for (i = 0; i < 16; i++)
2570 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2571
2572 for (i = 0; i < 2; i++)
2573 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2574 ((int)(State.a[OP[i]] >> 32) & 0xff),
2575 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
2576
2577 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2578 State.F0 != 0, State.F1 != 0, State.C != 0);
2579 break;
2580#endif
63a91cfb
MM		 2581
2582 case 0:
2583 /* Trap 0 is used for simulating low-level I/O */
2584 {
2585 int save_errno = errno;
2586 errno = 0;
2587
2588/* Registers passed to trap 0 */
2589
65c0d7de
MA		 2590#define FUNC State.regs[6] /* function number */
2591#define PARM1 State.regs[2] /* optional parm 1 */
2592#define PARM2 State.regs[3] /* optional parm 2 */
2593#define PARM3 State.regs[4] /* optional parm 3 */
2594#define PARM4 State.regs[5] /* optional parm 3 */
63a91cfb
MM		 2595
2596/* Registers set by trap 0 */
2597
65c0d7de
MA		 2598#define RETVAL State.regs[2] /* return value */
2599#define RETVAL_HIGH State.regs[2] /* return value */
2600#define RETVAL_LOW State.regs[3] /* return value */
2601#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2602
2603/* Turn a pointer in a register into a pointer into real memory. */
2604
2605#define MEMPTR(x) ((char *)((x) + State.imem))
2606
2607 switch (FUNC)
2608 {
2609#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2610 case SYS_fork:
2611 RETVAL = fork ();
2612 break;
63a91cfb
MM		 2613 case SYS_execve:
2614 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2615 (char **)MEMPTR (PARM3));
2616 break;
63a91cfb
MM		 2617 case SYS_execv:
2618 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2619 break;
63a91cfb
MM		 2620 case SYS_pipe:
2621 {
2622 reg_t buf;
2623 int host_fd[2];
2624
2625 buf = PARM1;
2626 RETVAL = pipe (host_fd);
2627 SW (buf, host_fd[0]);
2628 buf += sizeof(uint16);
2629 SW (buf, host_fd[1]);
2630 }
2631 break;
63a91cfb
MM		 2632 case SYS_wait:
2633 {
2634 int status;
2635
2636 RETVAL = wait (&status);
2637 SW (PARM1, status);
2638 }
2639 break;
2640#endif
63a91cfb
MM		 2641 case SYS_read:
2642 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2643 PARM3);
2644 break;
63a91cfb
MM		 2645 case SYS_write:
2646 if (PARM1 == 1)
2647 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2648 MEMPTR (PARM2), PARM3);
2649 else
2650 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2651 MEMPTR (PARM2), PARM3);
2652 break;
63a91cfb 2653 case SYS_lseek:
65c0d7de
MA		 2654 {
2655 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2656 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2657 PARM4);
2658 RETVAL_HIGH = ret >> 16;
2659 RETVAL_LOW = ret & 0xffff;
2660 }
63a91cfb 2661 break;
63a91cfb
MM		 2662 case SYS_close:
2663 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2664 break;
63a91cfb
MM		 2665 case SYS_open:
2666 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2667 break;
63a91cfb 2668 case SYS_exit:
a49a15ad 2669 State.exception = SIG_D10V_EXIT;
63a91cfb 2670 break;
63a91cfb 2671
8719be26 2672 case SYS_stat:
63a91cfb
MM		 2673 /* stat system call */
2674 {
2675 struct stat host_stat;
2676 reg_t buf;
2677
2678 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2679
2680 buf = PARM2;
2681
2682 /* The hard-coded offsets and sizes were determined by using
2683 * the D10V compiler on a test program that used struct stat.
2684 */
2685 SW (buf, host_stat.st_dev);
2686 SW (buf+2, host_stat.st_ino);
2687 SW (buf+4, host_stat.st_mode);
2688 SW (buf+6, host_stat.st_nlink);
2689 SW (buf+8, host_stat.st_uid);
2690 SW (buf+10, host_stat.st_gid);
2691 SW (buf+12, host_stat.st_rdev);
2692 SLW (buf+16, host_stat.st_size);
2693 SLW (buf+20, host_stat.st_atime);
2694 SLW (buf+28, host_stat.st_mtime);
2695 SLW (buf+36, host_stat.st_ctime);
2696 }
2697 break;
63a91cfb 2698
63a91cfb
MM		 2699 case SYS_chown:
2700 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2701 break;
63a91cfb
MM		 2702 case SYS_chmod:
2703 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2704 break;
63a91cfb
MM		 2705 case SYS_utime:
2706 /* Cast the second argument to void *, to avoid type mismatch
2707 if a prototype is present. */
2708 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2709 break;
63a91cfb
MM		 2710 default:
2711 abort ();
2712 }
65c0d7de 2713 RETERR = d10v_callback->get_errno(d10v_callback);
63a91cfb
MM		 2714 break;
2715 }
2716
2717 case 1:
2718 /* Trap 1 prints a string */
2719 {
2720 char *fstr = State.regs[2] + State.imem;
2721 fputs (fstr, stdout);
2722 break;
2723 }
2724
2725 case 2:
2726 /* Trap 2 calls printf */
2727 {
2728 char *fstr = State.regs[2] + State.imem;
7eebfc62
MM		 2729 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2730 (int16)State.regs[3],
2731 (int16)State.regs[4],
2732 (int16)State.regs[5]);
63a91cfb
MM		 2733 break;
2734 }
2735
2736 case 3:
2737 /* Trap 3 writes a character */
2738 putchar (State.regs[2]);
2739 break;
19d44375 2740 }
2934d1c9
MH		 2741 }
2742}
2743
2744/* tst0i */
2745void
2746OP_7000000 ()
2747{
87178dbd 2748 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2749 State.F1 = State.F0;
4f425a32 2750 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 2751 trace_output (OP_FLAG);
2934d1c9
MH		 2752}
2753
2754/* tst1i */
2755void
2756OP_F000000 ()
2757{
87178dbd 2758 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2759 State.F1 = State.F0;
4f425a32 2760 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 2761 trace_output (OP_FLAG);
2934d1c9
MH		 2762}
2763
2764/* wait */
2765void
2766OP_5F80 ()
2767{
87178dbd 2768 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2769 State.IE = 1;
87178dbd 2770 trace_output (OP_VOID);
2934d1c9
MH		 2771}
2772
2773/* xor */
2774void
2775OP_A00 ()
2776{
87178dbd 2777 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 2778 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 2779 trace_output (OP_REG);
2934d1c9
MH		 2780}
2781
2782/* xor3 */
2783void
2784OP_5000000 ()
2785{
87178dbd 2786 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 2787 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 2788 trace_output (OP_REG);
2934d1c9
MH		 2789}
2790
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