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b34f6357 DB |
1 | /* frv simulator fr400 dependent profiling code. |
2 | ||
1d506c26 | 3 | Copyright (C) 2001-2024 Free Software Foundation, Inc. |
b34f6357 DB |
4 | Contributed by Red Hat |
5 | ||
6 | This file is part of the GNU simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
10 | the Free Software Foundation; either version 3 of the License, or |
11 | (at your option) any later version. | |
b34f6357 DB |
12 | |
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
4744ac1b | 18 | You should have received a copy of the GNU General Public License |
6df01ab8 MF |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
20 | ||
21 | /* This must come before any other includes. */ | |
22 | #include "defs.h" | |
b34f6357 | 23 | |
b34f6357 DB |
24 | #define WANT_CPU |
25 | #define WANT_CPU_FRVBF | |
26 | ||
27 | #include "sim-main.h" | |
28 | #include "bfd.h" | |
29 | ||
30 | #if WITH_PROFILE_MODEL_P | |
31 | ||
32 | #include "profile.h" | |
33 | #include "profile-fr400.h" | |
34 | ||
35 | /* These functions get and set flags representing the use of | |
36 | registers/resources. */ | |
37 | static void set_use_not_fp_load (SIM_CPU *, INT); | |
38 | static void set_use_not_media_p4 (SIM_CPU *, INT); | |
39 | static void set_use_not_media_p6 (SIM_CPU *, INT); | |
40 | ||
41 | static void set_acc_use_not_media_p2 (SIM_CPU *, INT); | |
42 | static void set_acc_use_not_media_p4 (SIM_CPU *, INT); | |
43 | ||
44 | void | |
45 | fr400_reset_gr_flags (SIM_CPU *cpu, INT fr) | |
46 | { | |
47 | set_use_not_gr_complex (cpu, fr); | |
48 | } | |
49 | ||
50 | void | |
51 | fr400_reset_fr_flags (SIM_CPU *cpu, INT fr) | |
52 | { | |
53 | set_use_not_fp_load (cpu, fr); | |
54 | set_use_not_media_p4 (cpu, fr); | |
55 | set_use_not_media_p6 (cpu, fr); | |
56 | } | |
57 | ||
58 | void | |
59 | fr400_reset_acc_flags (SIM_CPU *cpu, INT acc) | |
60 | { | |
61 | set_acc_use_not_media_p2 (cpu, acc); | |
62 | set_acc_use_not_media_p4 (cpu, acc); | |
63 | } | |
64 | ||
65 | static void | |
66 | set_use_is_fp_load (SIM_CPU *cpu, INT fr, INT fr_double) | |
67 | { | |
68 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
69 | if (fr != -1) | |
70 | { | |
71 | fr400_reset_fr_flags (cpu, fr); | |
72 | d->cur_fp_load |= (((DI)1) << fr); | |
73 | } | |
74 | if (fr_double != -1) | |
75 | { | |
76 | fr400_reset_fr_flags (cpu, fr_double); | |
77 | d->cur_fp_load |= (((DI)1) << fr_double); | |
78 | if (fr_double < 63) | |
79 | { | |
80 | fr400_reset_fr_flags (cpu, fr_double + 1); | |
81 | d->cur_fp_load |= (((DI)1) << (fr_double + 1)); | |
82 | } | |
83 | } | |
84 | ||
85 | } | |
86 | ||
87 | static void | |
88 | set_use_not_fp_load (SIM_CPU *cpu, INT fr) | |
89 | { | |
90 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
91 | if (fr != -1) | |
92 | d->cur_fp_load &= ~(((DI)1) << fr); | |
93 | } | |
94 | ||
95 | static int | |
96 | use_is_fp_load (SIM_CPU *cpu, INT fr) | |
97 | { | |
98 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
99 | if (fr != -1) | |
100 | return (d->prev_fp_load >> fr) & 1; | |
101 | return 0; | |
102 | } | |
103 | ||
104 | static void | |
105 | set_acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) | |
106 | { | |
107 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
108 | if (acc != -1) | |
109 | { | |
110 | fr400_reset_acc_flags (cpu, acc); | |
111 | d->cur_acc_p2 |= (((DI)1) << acc); | |
112 | } | |
113 | } | |
114 | ||
115 | static void | |
116 | set_acc_use_not_media_p2 (SIM_CPU *cpu, INT acc) | |
117 | { | |
118 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
119 | if (acc != -1) | |
120 | d->cur_acc_p2 &= ~(((DI)1) << acc); | |
121 | } | |
122 | ||
123 | static int | |
124 | acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) | |
125 | { | |
126 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
127 | if (acc != -1) | |
128 | return d->cur_acc_p2 & (((DI)1) << acc); | |
129 | return 0; | |
130 | } | |
131 | ||
132 | static void | |
133 | set_use_is_media_p4 (SIM_CPU *cpu, INT fr) | |
134 | { | |
135 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
136 | if (fr != -1) | |
137 | { | |
138 | fr400_reset_fr_flags (cpu, fr); | |
139 | d->cur_fr_p4 |= (((DI)1) << fr); | |
140 | } | |
141 | } | |
142 | ||
143 | static void | |
144 | set_use_not_media_p4 (SIM_CPU *cpu, INT fr) | |
145 | { | |
146 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
147 | if (fr != -1) | |
148 | d->cur_fr_p4 &= ~(((DI)1) << fr); | |
149 | } | |
150 | ||
151 | static int | |
152 | use_is_media_p4 (SIM_CPU *cpu, INT fr) | |
153 | { | |
154 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
155 | if (fr != -1) | |
156 | return d->cur_fr_p4 & (((DI)1) << fr); | |
157 | return 0; | |
158 | } | |
159 | ||
160 | static void | |
161 | set_acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) | |
162 | { | |
163 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
164 | if (acc != -1) | |
165 | { | |
166 | fr400_reset_acc_flags (cpu, acc); | |
167 | d->cur_acc_p4 |= (((DI)1) << acc); | |
168 | } | |
169 | } | |
170 | ||
171 | static void | |
172 | set_acc_use_not_media_p4 (SIM_CPU *cpu, INT acc) | |
173 | { | |
174 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
175 | if (acc != -1) | |
176 | d->cur_acc_p4 &= ~(((DI)1) << acc); | |
177 | } | |
178 | ||
a9d20039 | 179 | #if 0 |
b34f6357 DB |
180 | static int |
181 | acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) | |
182 | { | |
183 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
184 | if (acc != -1) | |
185 | return d->cur_acc_p4 & (((DI)1) << acc); | |
186 | return 0; | |
187 | } | |
a9d20039 | 188 | #endif |
b34f6357 DB |
189 | |
190 | static void | |
191 | set_use_is_media_p6 (SIM_CPU *cpu, INT fr) | |
192 | { | |
193 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
194 | if (fr != -1) | |
195 | { | |
196 | fr400_reset_fr_flags (cpu, fr); | |
197 | d->cur_fr_p6 |= (((DI)1) << fr); | |
198 | } | |
199 | } | |
200 | ||
201 | static void | |
202 | set_use_not_media_p6 (SIM_CPU *cpu, INT fr) | |
203 | { | |
204 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
205 | if (fr != -1) | |
206 | d->cur_fr_p6 &= ~(((DI)1) << fr); | |
207 | } | |
208 | ||
209 | static int | |
210 | use_is_media_p6 (SIM_CPU *cpu, INT fr) | |
211 | { | |
212 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
213 | if (fr != -1) | |
214 | return d->cur_fr_p6 & (((DI)1) << fr); | |
215 | return 0; | |
216 | } | |
217 | ||
218 | /* Initialize cycle counting for an insn. | |
219 | FIRST_P is non-zero if this is the first insn in a set of parallel | |
220 | insns. */ | |
221 | void | |
222 | fr400_model_insn_before (SIM_CPU *cpu, int first_p) | |
223 | { | |
224 | if (first_p) | |
225 | { | |
226 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
227 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); | |
228 | ps->cur_gr_complex = ps->prev_gr_complex; | |
229 | d->cur_fp_load = d->prev_fp_load; | |
230 | d->cur_fr_p4 = d->prev_fr_p4; | |
231 | d->cur_fr_p6 = d->prev_fr_p6; | |
232 | d->cur_acc_p2 = d->prev_acc_p2; | |
233 | d->cur_acc_p4 = d->prev_acc_p4; | |
234 | } | |
235 | } | |
236 | ||
237 | /* Record the cycles computed for an insn. | |
238 | LAST_P is non-zero if this is the last insn in a set of parallel insns, | |
239 | and we update the total cycle count. | |
240 | CYCLES is the cycle count of the insn. */ | |
241 | void | |
242 | fr400_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) | |
243 | { | |
244 | if (last_p) | |
245 | { | |
246 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
247 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); | |
248 | ps->prev_gr_complex = ps->cur_gr_complex; | |
249 | d->prev_fp_load = d->cur_fp_load; | |
250 | d->prev_fr_p4 = d->cur_fr_p4; | |
251 | d->prev_fr_p6 = d->cur_fr_p6; | |
252 | d->prev_acc_p2 = d->cur_acc_p2; | |
253 | d->prev_acc_p4 = d->cur_acc_p4; | |
254 | } | |
255 | } | |
256 | ||
257 | int | |
258 | frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
259 | int unit_num, int referenced) | |
260 | { | |
261 | return idesc->timing->units[unit_num].done; | |
262 | } | |
263 | ||
264 | int | |
265 | frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc, | |
266 | int unit_num, int referenced, | |
267 | INT in_GRi, INT in_GRj, INT out_GRk, | |
268 | INT out_ICCi_1) | |
269 | { | |
270 | /* Modelling for this unit is the same as for fr500. */ | |
271 | return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced, | |
272 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
273 | } | |
274 | ||
275 | int | |
276 | frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc, | |
277 | int unit_num, int referenced, | |
278 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
279 | { | |
280 | /* Modelling for this unit is the same as for fr500. */ | |
281 | return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced, | |
282 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
283 | } | |
284 | ||
285 | int | |
286 | frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc, | |
287 | int unit_num, int referenced, | |
288 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
289 | { | |
290 | int cycles; | |
291 | FRV_VLIW *vliw; | |
292 | int slot; | |
293 | ||
294 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
295 | if (out_ICCi_1 >= 0) | |
296 | out_ICCi_1 += 4; | |
297 | ||
298 | vliw = CPU_VLIW (cpu); | |
299 | slot = vliw->next_slot - 1; | |
300 | slot = (*vliw->current_vliw)[slot] - UNIT_I0; | |
301 | ||
302 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
303 | { | |
304 | /* The entire VLIW insn must wait if there is a dependency on a register | |
305 | which is not ready yet. | |
306 | The latency of the registers may be less than previously recorded, | |
307 | depending on how they were used previously. | |
308 | See Table 13-8 in the LSI. */ | |
309 | if (in_GRi != out_GRk && in_GRi >= 0) | |
310 | { | |
311 | if (use_is_gr_complex (cpu, in_GRi)) | |
312 | decrease_GR_busy (cpu, in_GRi, 1); | |
313 | } | |
314 | if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) | |
315 | { | |
316 | if (use_is_gr_complex (cpu, in_GRj)) | |
317 | decrease_GR_busy (cpu, in_GRj, 1); | |
318 | } | |
319 | vliw_wait_for_GR (cpu, in_GRi); | |
320 | vliw_wait_for_GR (cpu, in_GRj); | |
321 | vliw_wait_for_GR (cpu, out_GRk); | |
322 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
323 | vliw_wait_for_idiv_resource (cpu, slot); | |
324 | handle_resource_wait (cpu); | |
325 | load_wait_for_GR (cpu, in_GRi); | |
326 | load_wait_for_GR (cpu, in_GRj); | |
327 | load_wait_for_GR (cpu, out_GRk); | |
328 | trace_vliw_wait_cycles (cpu); | |
329 | return 0; | |
330 | } | |
331 | ||
332 | /* GRk has a latency of 19 cycles! */ | |
333 | cycles = idesc->timing->units[unit_num].done; | |
334 | update_GR_latency (cpu, out_GRk, cycles + 19); | |
335 | set_use_is_gr_complex (cpu, out_GRk); | |
336 | ||
337 | /* ICCi_1 has a latency of 18 cycles. */ | |
338 | update_CCR_latency (cpu, out_ICCi_1, cycles + 18); | |
339 | ||
340 | /* the idiv resource has a latency of 18 cycles! */ | |
341 | update_idiv_resource_latency (cpu, slot, cycles + 18); | |
342 | ||
343 | return cycles; | |
344 | } | |
345 | ||
346 | int | |
347 | frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc, | |
348 | int unit_num, int referenced, | |
349 | INT in_GRi, INT in_GRj, | |
350 | INT in_ICCi_2, INT in_ICCi_3) | |
351 | { | |
352 | #define BRANCH_PREDICTED(ps) ((ps)->branch_hint & 2) | |
353 | FRV_PROFILE_STATE *ps; | |
354 | int cycles; | |
355 | ||
356 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
357 | { | |
358 | /* Modelling for this unit is the same as for fr500 in pass 1. */ | |
359 | return frvbf_model_fr500_u_branch (cpu, idesc, unit_num, referenced, | |
360 | in_GRi, in_GRj, in_ICCi_2, in_ICCi_3); | |
361 | } | |
362 | ||
363 | cycles = idesc->timing->units[unit_num].done; | |
364 | ||
365 | /* Compute the branch penalty, based on the the prediction and the out | |
366 | come. When counting branches taken or not taken, don't consider branches | |
367 | after the first taken branch in a vliw insn. */ | |
368 | ps = CPU_PROFILE_STATE (cpu); | |
369 | if (! ps->vliw_branch_taken) | |
370 | { | |
371 | int penalty; | |
372 | /* (1 << 4): The pc is the 5th element in inputs, outputs. | |
373 | ??? can be cleaned up */ | |
374 | PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); | |
375 | int taken = (referenced & (1 << 4)) != 0; | |
376 | if (taken) | |
377 | { | |
378 | ++PROFILE_MODEL_TAKEN_COUNT (p); | |
379 | ps->vliw_branch_taken = 1; | |
380 | if (BRANCH_PREDICTED (ps)) | |
381 | penalty = 1; | |
382 | else | |
383 | penalty = 3; | |
384 | } | |
385 | else | |
386 | { | |
387 | ++PROFILE_MODEL_UNTAKEN_COUNT (p); | |
388 | if (BRANCH_PREDICTED (ps)) | |
389 | penalty = 3; | |
390 | else | |
391 | penalty = 0; | |
392 | } | |
393 | if (penalty > 0) | |
394 | { | |
395 | /* Additional 1 cycle penalty if the branch address is not 8 byte | |
396 | aligned. */ | |
397 | if (ps->branch_address & 7) | |
398 | ++penalty; | |
399 | update_branch_penalty (cpu, penalty); | |
400 | PROFILE_MODEL_CTI_STALL_CYCLES (p) += penalty; | |
401 | } | |
402 | } | |
403 | ||
404 | return cycles; | |
405 | } | |
406 | ||
407 | int | |
408 | frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc, | |
409 | int unit_num, int referenced, | |
410 | INT in_GRi, INT in_GRj, | |
411 | INT in_ICCi_2, INT in_FCCi_2) | |
412 | { | |
413 | /* Modelling for this unit is the same as for fr500. */ | |
414 | return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced, | |
415 | in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); | |
416 | } | |
417 | ||
418 | int | |
419 | frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc, | |
420 | int unit_num, int referenced, | |
421 | INT in_ICCi_3, INT in_FCCi_3) | |
422 | { | |
423 | /* Modelling for this unit is the same as for fr500. */ | |
424 | return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, | |
425 | in_ICCi_3, in_FCCi_3); | |
426 | } | |
427 | ||
428 | int | |
429 | frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
430 | int unit_num, int referenced, | |
431 | INT out_GRkhi, INT out_GRklo) | |
432 | { | |
433 | /* Modelling for this unit is the same as for fr500. */ | |
434 | return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced, | |
435 | out_GRkhi, out_GRklo); | |
436 | } | |
437 | ||
438 | int | |
439 | frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, | |
440 | int unit_num, int referenced, | |
441 | INT in_GRi, INT in_GRj, | |
442 | INT out_GRk, INT out_GRdoublek) | |
443 | { | |
444 | /* Modelling for this unit is the same as for fr500. */ | |
445 | return frvbf_model_fr500_u_gr_load (cpu, idesc, unit_num, referenced, | |
446 | in_GRi, in_GRj, out_GRk, out_GRdoublek); | |
447 | } | |
448 | ||
449 | int | |
450 | frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, | |
451 | int unit_num, int referenced, | |
452 | INT in_GRi, INT in_GRj, | |
453 | INT in_GRk, INT in_GRdoublek) | |
454 | { | |
455 | /* Modelling for this unit is the same as for fr500. */ | |
456 | return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, | |
457 | in_GRi, in_GRj, in_GRk, in_GRdoublek); | |
458 | } | |
459 | ||
460 | int | |
461 | frvbf_model_fr400_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, | |
462 | int unit_num, int referenced, | |
463 | INT in_GRi, INT in_GRj, | |
464 | INT out_FRk, INT out_FRdoublek) | |
465 | { | |
466 | int cycles; | |
467 | ||
468 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
469 | { | |
470 | /* Pass 1 is the same as for fr500. */ | |
471 | return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced, | |
472 | in_GRi, in_GRj, out_FRk, | |
473 | out_FRdoublek); | |
474 | } | |
475 | ||
476 | cycles = idesc->timing->units[unit_num].done; | |
477 | ||
478 | /* The latency of FRk for a load will depend on how long it takes to retrieve | |
479 | the the data from the cache or memory. */ | |
480 | update_FR_latency_for_load (cpu, out_FRk, cycles); | |
481 | update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); | |
482 | ||
483 | set_use_is_fp_load (cpu, out_FRk, out_FRdoublek); | |
484 | ||
485 | return cycles; | |
486 | } | |
487 | ||
488 | int | |
489 | frvbf_model_fr400_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, | |
490 | int unit_num, int referenced, | |
491 | INT in_GRi, INT in_GRj, | |
492 | INT in_FRk, INT in_FRdoublek) | |
493 | { | |
494 | int cycles; | |
495 | ||
496 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
497 | { | |
498 | /* The entire VLIW insn must wait if there is a dependency on a register | |
499 | which is not ready yet. | |
500 | The latency of the registers may be less than previously recorded, | |
501 | depending on how they were used previously. | |
502 | See Table 13-8 in the LSI. */ | |
503 | if (in_GRi >= 0) | |
504 | { | |
505 | if (use_is_gr_complex (cpu, in_GRi)) | |
506 | decrease_GR_busy (cpu, in_GRi, 1); | |
507 | } | |
508 | if (in_GRj != in_GRi && in_GRj >= 0) | |
509 | { | |
510 | if (use_is_gr_complex (cpu, in_GRj)) | |
511 | decrease_GR_busy (cpu, in_GRj, 1); | |
512 | } | |
513 | if (in_FRk >= 0) | |
514 | { | |
515 | if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) | |
516 | decrease_FR_busy (cpu, in_FRk, 1); | |
517 | else | |
518 | enforce_full_fr_latency (cpu, in_FRk); | |
519 | } | |
520 | vliw_wait_for_GR (cpu, in_GRi); | |
521 | vliw_wait_for_GR (cpu, in_GRj); | |
522 | vliw_wait_for_FR (cpu, in_FRk); | |
523 | vliw_wait_for_FRdouble (cpu, in_FRdoublek); | |
524 | handle_resource_wait (cpu); | |
525 | load_wait_for_GR (cpu, in_GRi); | |
526 | load_wait_for_GR (cpu, in_GRj); | |
527 | load_wait_for_FR (cpu, in_FRk); | |
528 | load_wait_for_FRdouble (cpu, in_FRdoublek); | |
529 | trace_vliw_wait_cycles (cpu); | |
530 | return 0; | |
531 | } | |
532 | ||
533 | cycles = idesc->timing->units[unit_num].done; | |
534 | ||
535 | return cycles; | |
536 | } | |
537 | ||
538 | int | |
539 | frvbf_model_fr400_u_swap (SIM_CPU *cpu, const IDESC *idesc, | |
540 | int unit_num, int referenced, | |
541 | INT in_GRi, INT in_GRj, INT out_GRk) | |
542 | { | |
543 | /* Modelling for this unit is the same as for fr500. */ | |
544 | return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced, | |
545 | in_GRi, in_GRj, out_GRk); | |
546 | } | |
547 | ||
548 | int | |
549 | frvbf_model_fr400_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
550 | int unit_num, int referenced, | |
551 | INT in_FRk, INT out_GRj) | |
552 | { | |
553 | int cycles; | |
554 | ||
555 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
556 | { | |
557 | /* The entire VLIW insn must wait if there is a dependency on a register | |
558 | which is not ready yet. | |
559 | The latency of the registers may be less than previously recorded, | |
560 | depending on how they were used previously. | |
561 | See Table 13-8 in the LSI. */ | |
562 | if (in_FRk >= 0) | |
563 | { | |
564 | if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) | |
565 | decrease_FR_busy (cpu, in_FRk, 1); | |
566 | else | |
567 | enforce_full_fr_latency (cpu, in_FRk); | |
568 | } | |
569 | vliw_wait_for_FR (cpu, in_FRk); | |
570 | vliw_wait_for_GR (cpu, out_GRj); | |
571 | handle_resource_wait (cpu); | |
572 | load_wait_for_FR (cpu, in_FRk); | |
573 | load_wait_for_GR (cpu, out_GRj); | |
574 | trace_vliw_wait_cycles (cpu); | |
575 | return 0; | |
576 | } | |
577 | ||
578 | /* The latency of GRj is 2 cycles. */ | |
579 | cycles = idesc->timing->units[unit_num].done; | |
580 | update_GR_latency (cpu, out_GRj, cycles + 2); | |
581 | set_use_is_gr_complex (cpu, out_GRj); | |
582 | ||
583 | return cycles; | |
584 | } | |
585 | ||
586 | int | |
587 | frvbf_model_fr400_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
588 | int unit_num, int referenced, | |
589 | INT in_spr, INT out_GRj) | |
590 | { | |
591 | /* Modelling for this unit is the same as for fr500. */ | |
592 | return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, | |
593 | in_spr, out_GRj); | |
594 | } | |
595 | ||
596 | int | |
597 | frvbf_model_fr400_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, | |
598 | int unit_num, int referenced, | |
599 | INT in_GRj, INT out_FRk) | |
600 | { | |
601 | int cycles; | |
602 | ||
603 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
604 | { | |
605 | /* Pass 1 is the same as for fr500. */ | |
606 | frvbf_model_fr500_u_gr2fr (cpu, idesc, unit_num, referenced, | |
607 | in_GRj, out_FRk); | |
608 | } | |
609 | ||
610 | /* The latency of FRk is 1 cycles. */ | |
611 | cycles = idesc->timing->units[unit_num].done; | |
612 | update_FR_latency (cpu, out_FRk, cycles + 1); | |
613 | ||
614 | return cycles; | |
615 | } | |
616 | ||
617 | int | |
618 | frvbf_model_fr400_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, | |
619 | int unit_num, int referenced, | |
620 | INT in_GRj, INT out_spr) | |
621 | { | |
622 | /* Modelling for this unit is the same as for fr500. */ | |
623 | return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced, | |
624 | in_GRj, out_spr); | |
625 | } | |
626 | ||
b34f6357 DB |
627 | int |
628 | frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, | |
629 | int unit_num, int referenced, | |
630 | INT in_FRi, INT in_FRj, | |
631 | INT out_FRk) | |
632 | { | |
633 | int cycles; | |
634 | FRV_PROFILE_STATE *ps; | |
b34f6357 DB |
635 | int busy_adjustment[] = {0, 0}; |
636 | int *fr; | |
637 | ||
638 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
639 | return 0; | |
640 | ||
641 | /* The preprocessing can execute right away. */ | |
642 | cycles = idesc->timing->units[unit_num].done; | |
643 | ||
644 | ps = CPU_PROFILE_STATE (cpu); | |
b34f6357 DB |
645 | |
646 | /* The latency of the registers may be less than previously recorded, | |
647 | depending on how they were used previously. | |
648 | See Table 13-8 in the LSI. */ | |
649 | if (in_FRi >= 0) | |
650 | { | |
651 | if (use_is_fp_load (cpu, in_FRi)) | |
652 | { | |
653 | busy_adjustment[0] = 1; | |
654 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
655 | } | |
656 | else | |
657 | enforce_full_fr_latency (cpu, in_FRi); | |
658 | } | |
659 | if (in_FRj >= 0 && in_FRj != in_FRi) | |
660 | { | |
661 | if (use_is_fp_load (cpu, in_FRj)) | |
662 | { | |
663 | busy_adjustment[1] = 1; | |
664 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); | |
665 | } | |
666 | else | |
667 | enforce_full_fr_latency (cpu, in_FRj); | |
668 | } | |
669 | ||
670 | /* The post processing must wait if there is a dependency on a FR | |
671 | which is not ready yet. */ | |
672 | ps->post_wait = cycles; | |
673 | post_wait_for_FR (cpu, in_FRi); | |
674 | post_wait_for_FR (cpu, in_FRj); | |
675 | post_wait_for_FR (cpu, out_FRk); | |
676 | ||
677 | /* Restore the busy cycles of the registers we used. */ | |
678 | fr = ps->fr_busy; | |
679 | if (in_FRi >= 0) | |
680 | fr[in_FRi] += busy_adjustment[0]; | |
681 | if (in_FRj >= 0) | |
682 | fr[in_FRj] += busy_adjustment[1]; | |
683 | ||
684 | /* The latency of the output register will be at least the latency of the | |
685 | other inputs. Once initiated, post-processing has no latency. */ | |
686 | if (out_FRk >= 0) | |
687 | { | |
688 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
689 | update_FR_ptime (cpu, out_FRk, 0); | |
690 | } | |
691 | ||
692 | return cycles; | |
693 | } | |
694 | ||
695 | int | |
696 | frvbf_model_fr400_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc, | |
697 | int unit_num, int referenced, | |
698 | INT in_FRi, INT in_FRj, | |
699 | INT out_FRk) | |
700 | { | |
701 | int cycles; | |
702 | INT dual_FRi; | |
703 | INT dual_FRj; | |
704 | INT dual_FRk; | |
705 | FRV_PROFILE_STATE *ps; | |
706 | int busy_adjustment[] = {0, 0, 0, 0}; | |
707 | int *fr; | |
708 | ||
709 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
710 | return 0; | |
711 | ||
712 | /* The preprocessing can execute right away. */ | |
713 | cycles = idesc->timing->units[unit_num].done; | |
714 | ||
715 | ps = CPU_PROFILE_STATE (cpu); | |
716 | dual_FRi = DUAL_REG (in_FRi); | |
717 | dual_FRj = DUAL_REG (in_FRj); | |
718 | dual_FRk = DUAL_REG (out_FRk); | |
719 | ||
720 | /* The latency of the registers may be less than previously recorded, | |
721 | depending on how they were used previously. | |
722 | See Table 13-8 in the LSI. */ | |
723 | if (use_is_fp_load (cpu, in_FRi)) | |
724 | { | |
725 | busy_adjustment[0] = 1; | |
726 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
727 | } | |
728 | else | |
729 | enforce_full_fr_latency (cpu, in_FRi); | |
730 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
731 | { | |
732 | busy_adjustment[1] = 1; | |
733 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
734 | } | |
735 | else | |
736 | enforce_full_fr_latency (cpu, dual_FRi); | |
737 | if (in_FRj != in_FRi) | |
738 | { | |
739 | if (use_is_fp_load (cpu, in_FRj)) | |
740 | { | |
741 | busy_adjustment[2] = 1; | |
742 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
743 | } | |
744 | else | |
745 | enforce_full_fr_latency (cpu, in_FRj); | |
746 | if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) | |
747 | { | |
748 | busy_adjustment[3] = 1; | |
749 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); | |
750 | } | |
751 | else | |
752 | enforce_full_fr_latency (cpu, dual_FRj); | |
753 | } | |
754 | ||
755 | /* The post processing must wait if there is a dependency on a FR | |
756 | which is not ready yet. */ | |
757 | ps->post_wait = cycles; | |
758 | post_wait_for_FR (cpu, in_FRi); | |
759 | post_wait_for_FR (cpu, dual_FRi); | |
760 | post_wait_for_FR (cpu, in_FRj); | |
761 | post_wait_for_FR (cpu, dual_FRj); | |
762 | post_wait_for_FR (cpu, out_FRk); | |
763 | post_wait_for_FR (cpu, dual_FRk); | |
764 | ||
765 | /* Restore the busy cycles of the registers we used. */ | |
766 | fr = ps->fr_busy; | |
767 | fr[in_FRi] += busy_adjustment[0]; | |
768 | if (dual_FRi >= 0) | |
769 | fr[dual_FRi] += busy_adjustment[1]; | |
770 | fr[in_FRj] += busy_adjustment[2]; | |
771 | if (dual_FRj >= 0) | |
772 | fr[dual_FRj] += busy_adjustment[3]; | |
773 | ||
774 | /* The latency of the output register will be at least the latency of the | |
775 | other inputs. */ | |
776 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
777 | ||
778 | /* Once initiated, post-processing has no latency. */ | |
779 | update_FR_ptime (cpu, out_FRk, 0); | |
780 | ||
781 | if (dual_FRk >= 0) | |
782 | { | |
783 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
784 | update_FR_ptime (cpu, dual_FRk, 0); | |
785 | } | |
786 | ||
787 | return cycles; | |
788 | } | |
789 | ||
790 | int | |
791 | frvbf_model_fr400_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
792 | int unit_num, int referenced, | |
793 | INT out_FRkhi, INT out_FRklo) | |
794 | { | |
795 | int cycles; | |
796 | FRV_PROFILE_STATE *ps; | |
797 | ||
798 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
799 | return 0; | |
800 | ||
801 | /* The preprocessing can execute right away. */ | |
802 | cycles = idesc->timing->units[unit_num].done; | |
803 | ||
804 | ps = CPU_PROFILE_STATE (cpu); | |
805 | ||
806 | /* The post processing must wait if there is a dependency on a FR | |
807 | which is not ready yet. */ | |
808 | ps->post_wait = cycles; | |
809 | post_wait_for_FR (cpu, out_FRkhi); | |
810 | post_wait_for_FR (cpu, out_FRklo); | |
811 | ||
812 | /* The latency of the output register will be at least the latency of the | |
813 | other inputs. Once initiated, post-processing has no latency. */ | |
814 | if (out_FRkhi >= 0) | |
815 | { | |
816 | update_FR_latency (cpu, out_FRkhi, ps->post_wait); | |
817 | update_FR_ptime (cpu, out_FRkhi, 0); | |
818 | } | |
819 | if (out_FRklo >= 0) | |
820 | { | |
821 | update_FR_latency (cpu, out_FRklo, ps->post_wait); | |
822 | update_FR_ptime (cpu, out_FRklo, 0); | |
823 | } | |
824 | ||
825 | return cycles; | |
826 | } | |
827 | ||
828 | int | |
829 | frvbf_model_fr400_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, | |
830 | int unit_num, int referenced, | |
831 | INT in_FRi, INT in_FRj, | |
832 | INT out_ACC40Sk, INT out_ACC40Uk) | |
833 | { | |
834 | int cycles; | |
835 | INT dual_ACC40Sk; | |
836 | INT dual_ACC40Uk; | |
837 | FRV_PROFILE_STATE *ps; | |
838 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
839 | int *fr; | |
840 | int *acc; | |
841 | ||
842 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
843 | return 0; | |
844 | ||
845 | /* The preprocessing can execute right away. */ | |
846 | cycles = idesc->timing->units[unit_num].done; | |
847 | ||
848 | ps = CPU_PROFILE_STATE (cpu); | |
849 | dual_ACC40Sk = DUAL_REG (out_ACC40Sk); | |
850 | dual_ACC40Uk = DUAL_REG (out_ACC40Uk); | |
851 | ||
852 | /* The latency of the registers may be less than previously recorded, | |
853 | depending on how they were used previously. | |
854 | See Table 13-8 in the LSI. */ | |
855 | if (in_FRi >= 0) | |
856 | { | |
857 | if (use_is_fp_load (cpu, in_FRi)) | |
858 | { | |
859 | busy_adjustment[0] = 1; | |
860 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
861 | } | |
862 | else | |
863 | enforce_full_fr_latency (cpu, in_FRi); | |
864 | } | |
865 | if (in_FRj >= 0 && in_FRj != in_FRi) | |
866 | { | |
867 | if (use_is_fp_load (cpu, in_FRj)) | |
868 | { | |
869 | busy_adjustment[1] = 1; | |
870 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); | |
871 | } | |
872 | else | |
873 | enforce_full_fr_latency (cpu, in_FRj); | |
874 | } | |
875 | if (out_ACC40Sk >= 0) | |
876 | { | |
877 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
878 | { | |
879 | busy_adjustment[2] = 1; | |
880 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
881 | } | |
882 | } | |
883 | if (dual_ACC40Sk >= 0) | |
884 | { | |
885 | if (acc_use_is_media_p2 (cpu, dual_ACC40Sk)) | |
886 | { | |
887 | busy_adjustment[3] = 1; | |
888 | decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]); | |
889 | } | |
890 | } | |
891 | if (out_ACC40Uk >= 0) | |
892 | { | |
893 | if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) | |
894 | { | |
895 | busy_adjustment[4] = 1; | |
896 | decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); | |
897 | } | |
898 | } | |
899 | if (dual_ACC40Uk >= 0) | |
900 | { | |
901 | if (acc_use_is_media_p2 (cpu, dual_ACC40Uk)) | |
902 | { | |
903 | busy_adjustment[5] = 1; | |
904 | decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]); | |
905 | } | |
906 | } | |
907 | ||
908 | /* The post processing must wait if there is a dependency on a FR | |
909 | which is not ready yet. */ | |
910 | ps->post_wait = cycles; | |
911 | post_wait_for_FR (cpu, in_FRi); | |
912 | post_wait_for_FR (cpu, in_FRj); | |
913 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
914 | post_wait_for_ACC (cpu, dual_ACC40Sk); | |
915 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
916 | post_wait_for_ACC (cpu, dual_ACC40Uk); | |
917 | ||
918 | /* Restore the busy cycles of the registers we used. */ | |
919 | fr = ps->fr_busy; | |
920 | acc = ps->acc_busy; | |
921 | fr[in_FRi] += busy_adjustment[0]; | |
922 | fr[in_FRj] += busy_adjustment[1]; | |
923 | if (out_ACC40Sk >= 0) | |
924 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
925 | if (dual_ACC40Sk >= 0) | |
926 | acc[dual_ACC40Sk] += busy_adjustment[3]; | |
927 | if (out_ACC40Uk >= 0) | |
928 | acc[out_ACC40Uk] += busy_adjustment[4]; | |
929 | if (dual_ACC40Uk >= 0) | |
930 | acc[dual_ACC40Uk] += busy_adjustment[5]; | |
931 | ||
932 | /* The latency of the output register will be at least the latency of the | |
933 | other inputs. Once initiated, post-processing will take 1 cycles. */ | |
934 | if (out_ACC40Sk >= 0) | |
935 | { | |
936 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
937 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
938 | } | |
939 | if (dual_ACC40Sk >= 0) | |
940 | { | |
941 | update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); | |
942 | set_acc_use_is_media_p2 (cpu, dual_ACC40Sk); | |
943 | } | |
944 | if (out_ACC40Uk >= 0) | |
945 | { | |
946 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
947 | set_acc_use_is_media_p2 (cpu, out_ACC40Uk); | |
948 | } | |
949 | if (dual_ACC40Uk >= 0) | |
950 | { | |
951 | update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); | |
952 | set_acc_use_is_media_p2 (cpu, dual_ACC40Uk); | |
953 | } | |
954 | ||
955 | return cycles; | |
956 | } | |
957 | ||
958 | int | |
959 | frvbf_model_fr400_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, | |
960 | int unit_num, int referenced, | |
961 | INT in_FRi, INT in_FRj, | |
962 | INT out_ACC40Sk, INT out_ACC40Uk) | |
963 | { | |
964 | int cycles; | |
965 | INT dual_FRi; | |
966 | INT dual_FRj; | |
967 | INT ACC40Sk_1; | |
968 | INT ACC40Sk_2; | |
969 | INT ACC40Sk_3; | |
970 | INT ACC40Uk_1; | |
971 | INT ACC40Uk_2; | |
972 | INT ACC40Uk_3; | |
973 | FRV_PROFILE_STATE *ps; | |
974 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0}; | |
975 | int *fr; | |
976 | int *acc; | |
977 | ||
978 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
979 | return 0; | |
980 | ||
981 | /* The preprocessing can execute right away. */ | |
982 | cycles = idesc->timing->units[unit_num].done; | |
983 | ||
984 | dual_FRi = DUAL_REG (in_FRi); | |
985 | dual_FRj = DUAL_REG (in_FRj); | |
986 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
987 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
988 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
989 | ACC40Uk_1 = DUAL_REG (out_ACC40Uk); | |
990 | ACC40Uk_2 = DUAL_REG (ACC40Uk_1); | |
991 | ACC40Uk_3 = DUAL_REG (ACC40Uk_2); | |
992 | ||
993 | ps = CPU_PROFILE_STATE (cpu); | |
994 | /* The latency of the registers may be less than previously recorded, | |
995 | depending on how they were used previously. | |
996 | See Table 13-8 in the LSI. */ | |
997 | if (use_is_fp_load (cpu, in_FRi)) | |
998 | { | |
999 | busy_adjustment[0] = 1; | |
1000 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1001 | } | |
1002 | else | |
1003 | enforce_full_fr_latency (cpu, in_FRi); | |
1004 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
1005 | { | |
1006 | busy_adjustment[1] = 1; | |
1007 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
1008 | } | |
1009 | else | |
1010 | enforce_full_fr_latency (cpu, dual_FRi); | |
1011 | if (in_FRj != in_FRi) | |
1012 | { | |
1013 | if (use_is_fp_load (cpu, in_FRj)) | |
1014 | { | |
1015 | busy_adjustment[2] = 1; | |
1016 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
1017 | } | |
1018 | else | |
1019 | enforce_full_fr_latency (cpu, in_FRj); | |
1020 | if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) | |
1021 | { | |
1022 | busy_adjustment[3] = 1; | |
1023 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); | |
1024 | } | |
1025 | else | |
1026 | enforce_full_fr_latency (cpu, dual_FRj); | |
1027 | } | |
1028 | if (out_ACC40Sk >= 0) | |
1029 | { | |
1030 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1031 | { | |
1032 | busy_adjustment[4] = 1; | |
1033 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1034 | } | |
1035 | if (ACC40Sk_1 >= 0) | |
1036 | { | |
1037 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1038 | { | |
1039 | busy_adjustment[5] = 1; | |
1040 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1041 | } | |
1042 | } | |
1043 | if (ACC40Sk_2 >= 0) | |
1044 | { | |
1045 | if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) | |
1046 | { | |
1047 | busy_adjustment[6] = 1; | |
1048 | decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); | |
1049 | } | |
1050 | } | |
1051 | if (ACC40Sk_3 >= 0) | |
1052 | { | |
1053 | if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) | |
1054 | { | |
1055 | busy_adjustment[7] = 1; | |
1056 | decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); | |
1057 | } | |
1058 | } | |
1059 | } | |
1060 | else if (out_ACC40Uk >= 0) | |
1061 | { | |
1062 | if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) | |
1063 | { | |
1064 | busy_adjustment[4] = 1; | |
1065 | decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); | |
1066 | } | |
1067 | if (ACC40Uk_1 >= 0) | |
1068 | { | |
1069 | if (acc_use_is_media_p2 (cpu, ACC40Uk_1)) | |
1070 | { | |
1071 | busy_adjustment[5] = 1; | |
1072 | decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]); | |
1073 | } | |
1074 | } | |
1075 | if (ACC40Uk_2 >= 0) | |
1076 | { | |
1077 | if (acc_use_is_media_p2 (cpu, ACC40Uk_2)) | |
1078 | { | |
1079 | busy_adjustment[6] = 1; | |
1080 | decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]); | |
1081 | } | |
1082 | } | |
1083 | if (ACC40Uk_3 >= 0) | |
1084 | { | |
1085 | if (acc_use_is_media_p2 (cpu, ACC40Uk_3)) | |
1086 | { | |
1087 | busy_adjustment[7] = 1; | |
1088 | decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]); | |
1089 | } | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | /* The post processing must wait if there is a dependency on a FR | |
1094 | which is not ready yet. */ | |
1095 | ps->post_wait = cycles; | |
1096 | post_wait_for_FR (cpu, in_FRi); | |
1097 | post_wait_for_FR (cpu, dual_FRi); | |
1098 | post_wait_for_FR (cpu, in_FRj); | |
1099 | post_wait_for_FR (cpu, dual_FRj); | |
1100 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1101 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1102 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
1103 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
1104 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
1105 | post_wait_for_ACC (cpu, ACC40Uk_1); | |
1106 | post_wait_for_ACC (cpu, ACC40Uk_2); | |
1107 | post_wait_for_ACC (cpu, ACC40Uk_3); | |
1108 | ||
1109 | /* Restore the busy cycles of the registers we used. */ | |
1110 | fr = ps->fr_busy; | |
1111 | acc = ps->acc_busy; | |
1112 | fr[in_FRi] += busy_adjustment[0]; | |
1113 | if (dual_FRi >= 0) | |
1114 | fr[dual_FRi] += busy_adjustment[1]; | |
1115 | fr[in_FRj] += busy_adjustment[2]; | |
1116 | if (dual_FRj > 0) | |
1117 | fr[dual_FRj] += busy_adjustment[3]; | |
1118 | if (out_ACC40Sk >= 0) | |
1119 | { | |
1120 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1121 | if (ACC40Sk_1 >= 0) | |
1122 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1123 | if (ACC40Sk_2 >= 0) | |
1124 | acc[ACC40Sk_2] += busy_adjustment[6]; | |
1125 | if (ACC40Sk_3 >= 0) | |
1126 | acc[ACC40Sk_3] += busy_adjustment[7]; | |
1127 | } | |
1128 | else if (out_ACC40Uk >= 0) | |
1129 | { | |
1130 | acc[out_ACC40Uk] += busy_adjustment[4]; | |
1131 | if (ACC40Uk_1 >= 0) | |
1132 | acc[ACC40Uk_1] += busy_adjustment[5]; | |
1133 | if (ACC40Uk_2 >= 0) | |
1134 | acc[ACC40Uk_2] += busy_adjustment[6]; | |
1135 | if (ACC40Uk_3 >= 0) | |
1136 | acc[ACC40Uk_3] += busy_adjustment[7]; | |
1137 | } | |
1138 | ||
1139 | /* The latency of the output register will be at least the latency of the | |
1140 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1141 | if (out_ACC40Sk >= 0) | |
1142 | { | |
1143 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1144 | ||
1145 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1146 | if (ACC40Sk_1 >= 0) | |
1147 | { | |
1148 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1149 | ||
1150 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1151 | } | |
1152 | if (ACC40Sk_2 >= 0) | |
1153 | { | |
1154 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
1155 | ||
1156 | set_acc_use_is_media_p2 (cpu, ACC40Sk_2); | |
1157 | } | |
1158 | if (ACC40Sk_3 >= 0) | |
1159 | { | |
1160 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
1161 | ||
1162 | set_acc_use_is_media_p2 (cpu, ACC40Sk_3); | |
1163 | } | |
1164 | } | |
1165 | else if (out_ACC40Uk >= 0) | |
1166 | { | |
1167 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
1168 | ||
1169 | set_acc_use_is_media_p2 (cpu, out_ACC40Uk); | |
1170 | if (ACC40Uk_1 >= 0) | |
1171 | { | |
1172 | update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); | |
1173 | ||
1174 | set_acc_use_is_media_p2 (cpu, ACC40Uk_1); | |
1175 | } | |
1176 | if (ACC40Uk_2 >= 0) | |
1177 | { | |
1178 | update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); | |
1179 | ||
1180 | set_acc_use_is_media_p2 (cpu, ACC40Uk_2); | |
1181 | } | |
1182 | if (ACC40Uk_3 >= 0) | |
1183 | { | |
1184 | update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); | |
1185 | ||
1186 | set_acc_use_is_media_p2 (cpu, ACC40Uk_3); | |
1187 | } | |
1188 | } | |
1189 | ||
1190 | return cycles; | |
1191 | } | |
1192 | ||
1193 | int | |
1194 | frvbf_model_fr400_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, | |
1195 | int unit_num, int referenced, | |
1196 | INT in_ACC40Si, INT out_ACC40Sk) | |
1197 | { | |
1198 | int cycles; | |
1199 | INT ACC40Si_1; | |
1200 | FRV_PROFILE_STATE *ps; | |
1201 | int busy_adjustment[] = {0, 0, 0}; | |
1202 | int *acc; | |
1203 | ||
1204 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1205 | return 0; | |
1206 | ||
1207 | /* The preprocessing can execute right away. */ | |
1208 | cycles = idesc->timing->units[unit_num].done; | |
1209 | ||
1210 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1211 | ||
1212 | ps = CPU_PROFILE_STATE (cpu); | |
1213 | /* The latency of the registers may be less than previously recorded, | |
1214 | depending on how they were used previously. | |
1215 | See Table 13-8 in the LSI. */ | |
1216 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1217 | { | |
1218 | busy_adjustment[0] = 1; | |
1219 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1220 | } | |
1221 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1222 | { | |
1223 | busy_adjustment[1] = 1; | |
1224 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1225 | } | |
1226 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1227 | && acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1228 | { | |
1229 | busy_adjustment[2] = 1; | |
1230 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
1231 | } | |
1232 | ||
1233 | /* The post processing must wait if there is a dependency on a register | |
1234 | which is not ready yet. */ | |
1235 | ps->post_wait = cycles; | |
1236 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1237 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1238 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1239 | ||
1240 | /* Restore the busy cycles of the registers we used. */ | |
1241 | acc = ps->acc_busy; | |
1242 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1243 | if (ACC40Si_1 >= 0) | |
1244 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1245 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
1246 | ||
1247 | /* The latency of the output register will be at least the latency of the | |
1248 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1249 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1250 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1251 | ||
1252 | return cycles; | |
1253 | } | |
1254 | ||
1255 | int | |
1256 | frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1257 | int unit_num, int referenced, | |
1258 | INT in_ACC40Si, INT out_ACC40Sk) | |
1259 | { | |
1260 | int cycles; | |
1261 | INT ACC40Si_1; | |
1262 | INT ACC40Si_2; | |
1263 | INT ACC40Si_3; | |
1264 | INT ACC40Sk_1; | |
1265 | FRV_PROFILE_STATE *ps; | |
1266 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
1267 | int *acc; | |
1268 | ||
1269 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1270 | return 0; | |
1271 | ||
1272 | /* The preprocessing can execute right away. */ | |
1273 | cycles = idesc->timing->units[unit_num].done; | |
1274 | ||
1275 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1276 | ACC40Si_2 = DUAL_REG (ACC40Si_1); | |
1277 | ACC40Si_3 = DUAL_REG (ACC40Si_2); | |
1278 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1279 | ||
1280 | ps = CPU_PROFILE_STATE (cpu); | |
1281 | /* The latency of the registers may be less than previously recorded, | |
1282 | depending on how they were used previously. | |
1283 | See Table 13-8 in the LSI. */ | |
1284 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1285 | { | |
1286 | busy_adjustment[0] = 1; | |
1287 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1288 | } | |
1289 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1290 | { | |
1291 | busy_adjustment[1] = 1; | |
1292 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1293 | } | |
1294 | if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) | |
1295 | { | |
1296 | busy_adjustment[2] = 1; | |
1297 | decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); | |
1298 | } | |
1299 | if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) | |
1300 | { | |
1301 | busy_adjustment[3] = 1; | |
1302 | decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); | |
1303 | } | |
1304 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1305 | && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) | |
1306 | { | |
1307 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1308 | { | |
1309 | busy_adjustment[4] = 1; | |
1310 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1311 | } | |
1312 | } | |
1313 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 | |
1314 | && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) | |
1315 | { | |
1316 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1317 | { | |
1318 | busy_adjustment[5] = 1; | |
1319 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1320 | } | |
1321 | } | |
1322 | ||
1323 | /* The post processing must wait if there is a dependency on a register | |
1324 | which is not ready yet. */ | |
1325 | ps->post_wait = cycles; | |
1326 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1327 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1328 | post_wait_for_ACC (cpu, ACC40Si_2); | |
1329 | post_wait_for_ACC (cpu, ACC40Si_3); | |
1330 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1331 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1332 | ||
1333 | /* Restore the busy cycles of the registers we used. */ | |
1334 | acc = ps->acc_busy; | |
1335 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1336 | if (ACC40Si_1 >= 0) | |
1337 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1338 | if (ACC40Si_2 >= 0) | |
1339 | acc[ACC40Si_2] += busy_adjustment[2]; | |
1340 | if (ACC40Si_3 >= 0) | |
1341 | acc[ACC40Si_3] += busy_adjustment[3]; | |
1342 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1343 | if (ACC40Sk_1 >= 0) | |
1344 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1345 | ||
1346 | /* The latency of the output register will be at least the latency of the | |
1347 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1348 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1349 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1350 | if (ACC40Sk_1 >= 0) | |
1351 | { | |
1352 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1353 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1354 | } | |
1355 | ||
1356 | return cycles; | |
1357 | } | |
1358 | ||
1359 | int | |
1360 | frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, | |
1361 | int unit_num, int referenced, | |
1362 | INT in_ACC40Si, INT out_ACC40Sk) | |
1363 | { | |
1364 | int cycles; | |
1365 | INT ACC40Si_1; | |
1366 | INT ACC40Sk_1; | |
1367 | FRV_PROFILE_STATE *ps; | |
1368 | int busy_adjustment[] = {0, 0, 0, 0}; | |
1369 | int *acc; | |
1370 | ||
1371 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1372 | return 0; | |
1373 | ||
1374 | /* The preprocessing can execute right away. */ | |
1375 | cycles = idesc->timing->units[unit_num].done; | |
1376 | ||
1377 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1378 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1379 | ||
1380 | ps = CPU_PROFILE_STATE (cpu); | |
1381 | /* The latency of the registers may be less than previously recorded, | |
1382 | depending on how they were used previously. | |
1383 | See Table 13-8 in the LSI. */ | |
1384 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1385 | { | |
1386 | busy_adjustment[0] = 1; | |
1387 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1388 | } | |
1389 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1390 | { | |
1391 | busy_adjustment[1] = 1; | |
1392 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1393 | } | |
1394 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1) | |
1395 | { | |
1396 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1397 | { | |
1398 | busy_adjustment[2] = 1; | |
1399 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
1400 | } | |
1401 | } | |
1402 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1) | |
1403 | { | |
1404 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1405 | { | |
1406 | busy_adjustment[3] = 1; | |
1407 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[3]); | |
1408 | } | |
1409 | } | |
1410 | ||
1411 | /* The post processing must wait if there is a dependency on a register | |
1412 | which is not ready yet. */ | |
1413 | ps->post_wait = cycles; | |
1414 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1415 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1416 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1417 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1418 | ||
1419 | /* Restore the busy cycles of the registers we used. */ | |
1420 | acc = ps->acc_busy; | |
1421 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1422 | if (ACC40Si_1 >= 0) | |
1423 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1424 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
1425 | if (ACC40Sk_1 >= 0) | |
1426 | acc[ACC40Sk_1] += busy_adjustment[3]; | |
1427 | ||
1428 | /* The latency of the output register will be at least the latency of the | |
1429 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1430 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1431 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1432 | if (ACC40Sk_1 >= 0) | |
1433 | { | |
1434 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1435 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1436 | } | |
1437 | ||
1438 | return cycles; | |
1439 | } | |
1440 | ||
1441 | int | |
1442 | frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1443 | int unit_num, int referenced, | |
1444 | INT in_ACC40Si, INT out_ACC40Sk) | |
1445 | { | |
1446 | int cycles; | |
1447 | INT ACC40Si_1; | |
1448 | INT ACC40Si_2; | |
1449 | INT ACC40Si_3; | |
1450 | INT ACC40Sk_1; | |
1451 | INT ACC40Sk_2; | |
1452 | INT ACC40Sk_3; | |
1453 | FRV_PROFILE_STATE *ps; | |
1454 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0, 0}; | |
1455 | int *acc; | |
1456 | ||
1457 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1458 | return 0; | |
1459 | ||
1460 | /* The preprocessing can execute right away. */ | |
1461 | cycles = idesc->timing->units[unit_num].done; | |
1462 | ||
1463 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1464 | ACC40Si_2 = DUAL_REG (ACC40Si_1); | |
1465 | ACC40Si_3 = DUAL_REG (ACC40Si_2); | |
1466 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1467 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
1468 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
1469 | ||
1470 | ps = CPU_PROFILE_STATE (cpu); | |
1471 | /* The latency of the registers may be less than previously recorded, | |
1472 | depending on how they were used previously. | |
1473 | See Table 13-8 in the LSI. */ | |
1474 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1475 | { | |
1476 | busy_adjustment[0] = 1; | |
1477 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1478 | } | |
1479 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1480 | { | |
1481 | busy_adjustment[1] = 1; | |
1482 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1483 | } | |
1484 | if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) | |
1485 | { | |
1486 | busy_adjustment[2] = 1; | |
1487 | decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); | |
1488 | } | |
1489 | if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) | |
1490 | { | |
1491 | busy_adjustment[3] = 1; | |
1492 | decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); | |
1493 | } | |
1494 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1495 | && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) | |
1496 | { | |
1497 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1498 | { | |
1499 | busy_adjustment[4] = 1; | |
1500 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1501 | } | |
1502 | } | |
1503 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 | |
1504 | && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) | |
1505 | { | |
1506 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1507 | { | |
1508 | busy_adjustment[5] = 1; | |
1509 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1510 | } | |
1511 | } | |
1512 | if (ACC40Sk_2 != in_ACC40Si && ACC40Sk_2 != ACC40Si_1 | |
1513 | && ACC40Sk_2 != ACC40Si_2 && ACC40Sk_2 != ACC40Si_3) | |
1514 | { | |
1515 | if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) | |
1516 | { | |
1517 | busy_adjustment[6] = 1; | |
1518 | decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); | |
1519 | } | |
1520 | } | |
1521 | if (ACC40Sk_3 != in_ACC40Si && ACC40Sk_3 != ACC40Si_1 | |
1522 | && ACC40Sk_3 != ACC40Si_2 && ACC40Sk_3 != ACC40Si_3) | |
1523 | { | |
1524 | if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) | |
1525 | { | |
1526 | busy_adjustment[7] = 1; | |
1527 | decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | /* The post processing must wait if there is a dependency on a register | |
1532 | which is not ready yet. */ | |
1533 | ps->post_wait = cycles; | |
1534 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1535 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1536 | post_wait_for_ACC (cpu, ACC40Si_2); | |
1537 | post_wait_for_ACC (cpu, ACC40Si_3); | |
1538 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1539 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1540 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
1541 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
1542 | ||
1543 | /* Restore the busy cycles of the registers we used. */ | |
1544 | acc = ps->acc_busy; | |
1545 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1546 | if (ACC40Si_1 >= 0) | |
1547 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1548 | if (ACC40Si_2 >= 0) | |
1549 | acc[ACC40Si_2] += busy_adjustment[2]; | |
1550 | if (ACC40Si_3 >= 0) | |
1551 | acc[ACC40Si_3] += busy_adjustment[3]; | |
1552 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1553 | if (ACC40Sk_1 >= 0) | |
1554 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1555 | if (ACC40Sk_2 >= 0) | |
1556 | acc[ACC40Sk_2] += busy_adjustment[6]; | |
1557 | if (ACC40Sk_3 >= 0) | |
1558 | acc[ACC40Sk_3] += busy_adjustment[7]; | |
1559 | ||
1560 | /* The latency of the output register will be at least the latency of the | |
1561 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1562 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1563 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1564 | if (ACC40Sk_1 >= 0) | |
1565 | { | |
1566 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1567 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1568 | } | |
1569 | if (ACC40Sk_2 >= 0) | |
1570 | { | |
1571 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
1572 | set_acc_use_is_media_p2 (cpu, ACC40Sk_2); | |
1573 | } | |
1574 | if (ACC40Sk_3 >= 0) | |
1575 | { | |
1576 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
1577 | set_acc_use_is_media_p2 (cpu, ACC40Sk_3); | |
1578 | } | |
1579 | ||
1580 | return cycles; | |
1581 | } | |
1582 | ||
1583 | int | |
1584 | frvbf_model_fr400_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, | |
1585 | int unit_num, int referenced, | |
1586 | INT in_FRi, INT in_FRj, | |
1587 | INT out_FRk) | |
1588 | { | |
1589 | /* Modelling is the same as media unit 1. */ | |
1590 | return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced, | |
1591 | in_FRi, in_FRj, out_FRk); | |
1592 | } | |
1593 | ||
1594 | int | |
1595 | frvbf_model_fr400_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1596 | int unit_num, int referenced, | |
1597 | INT in_FRi, INT out_FRk) | |
1598 | { | |
1599 | int cycles; | |
1600 | INT dual_FRi; | |
1601 | FRV_PROFILE_STATE *ps; | |
1602 | int busy_adjustment[] = {0, 0}; | |
1603 | int *fr; | |
1604 | ||
1605 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1606 | return 0; | |
1607 | ||
1608 | /* The preprocessing can execute right away. */ | |
1609 | cycles = idesc->timing->units[unit_num].done; | |
1610 | ||
1611 | ps = CPU_PROFILE_STATE (cpu); | |
1612 | dual_FRi = DUAL_REG (in_FRi); | |
1613 | ||
1614 | /* The latency of the registers may be less than previously recorded, | |
1615 | depending on how they were used previously. | |
1616 | See Table 13-8 in the LSI. */ | |
1617 | if (use_is_fp_load (cpu, in_FRi)) | |
1618 | { | |
1619 | busy_adjustment[0] = 1; | |
1620 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1621 | } | |
1622 | else | |
1623 | enforce_full_fr_latency (cpu, in_FRi); | |
1624 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
1625 | { | |
1626 | busy_adjustment[1] = 1; | |
1627 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
1628 | } | |
1629 | else | |
1630 | enforce_full_fr_latency (cpu, dual_FRi); | |
1631 | ||
1632 | /* The post processing must wait if there is a dependency on a FR | |
1633 | which is not ready yet. */ | |
1634 | ps->post_wait = cycles; | |
1635 | post_wait_for_FR (cpu, in_FRi); | |
1636 | post_wait_for_FR (cpu, dual_FRi); | |
1637 | post_wait_for_FR (cpu, out_FRk); | |
1638 | ||
1639 | /* Restore the busy cycles of the registers we used. */ | |
1640 | fr = ps->fr_busy; | |
1641 | fr[in_FRi] += busy_adjustment[0]; | |
1642 | if (dual_FRi >= 0) | |
1643 | fr[dual_FRi] += busy_adjustment[1]; | |
1644 | ||
1645 | /* The latency of the output register will be at least the latency of the | |
1646 | other inputs. */ | |
1647 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1648 | ||
1649 | /* Once initiated, post-processing has no latency. */ | |
1650 | update_FR_ptime (cpu, out_FRk, 0); | |
1651 | ||
1652 | return cycles; | |
1653 | } | |
1654 | ||
1655 | int | |
1656 | frvbf_model_fr400_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, | |
1657 | int unit_num, int referenced, | |
1658 | INT in_FRi, INT in_FRj, | |
1659 | INT out_FRk) | |
1660 | { | |
1661 | /* Modelling is the same as media unit 1. */ | |
1662 | return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced, | |
1663 | in_FRi, in_FRj, out_FRk); | |
1664 | } | |
1665 | ||
1666 | int | |
1667 | frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, | |
1668 | int unit_num, int referenced, | |
1669 | INT in_ACC40Si, INT in_FRj, | |
1670 | INT out_ACC40Sk, INT out_FRk) | |
1671 | { | |
1672 | int cycles; | |
1673 | FRV_PROFILE_STATE *ps; | |
b34f6357 | 1674 | int busy_adjustment[] = {0}; |
b34f6357 DB |
1675 | |
1676 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1677 | return 0; | |
1678 | ||
1679 | /* The preprocessing can execute right away. */ | |
1680 | cycles = idesc->timing->units[unit_num].done; | |
1681 | ||
1682 | ps = CPU_PROFILE_STATE (cpu); | |
b34f6357 DB |
1683 | |
1684 | /* The latency of the registers may be less than previously recorded, | |
1685 | depending on how they were used previously. | |
1686 | See Table 13-8 in the LSI. */ | |
1687 | if (in_FRj >= 0) | |
1688 | { | |
1689 | if (use_is_fp_load (cpu, in_FRj)) | |
1690 | { | |
1691 | busy_adjustment[0] = 1; | |
1692 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); | |
1693 | } | |
1694 | else | |
1695 | enforce_full_fr_latency (cpu, in_FRj); | |
1696 | } | |
1697 | ||
1698 | /* The post processing must wait if there is a dependency on a FR | |
1699 | which is not ready yet. */ | |
1700 | ps->post_wait = cycles; | |
1701 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1702 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1703 | post_wait_for_FR (cpu, in_FRj); | |
1704 | post_wait_for_FR (cpu, out_FRk); | |
1705 | ||
1706 | /* Restore the busy cycles of the registers we used. */ | |
b34f6357 DB |
1707 | |
1708 | /* The latency of the output register will be at least the latency of the | |
1709 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1710 | if (out_FRk >= 0) | |
1711 | { | |
1712 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1713 | update_FR_ptime (cpu, out_FRk, 1); | |
1714 | /* Mark this use of the register as media unit 4. */ | |
1715 | set_use_is_media_p4 (cpu, out_FRk); | |
1716 | } | |
1717 | else if (out_ACC40Sk >= 0) | |
1718 | { | |
1719 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait); | |
1720 | update_ACC_ptime (cpu, out_ACC40Sk, 1); | |
1721 | /* Mark this use of the register as media unit 4. */ | |
1722 | set_acc_use_is_media_p4 (cpu, out_ACC40Sk); | |
1723 | } | |
1724 | ||
1725 | return cycles; | |
1726 | } | |
1727 | ||
1728 | int | |
1729 | frvbf_model_fr400_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, | |
1730 | int unit_num, int referenced, | |
1731 | INT in_ACCGi, INT in_FRinti, | |
1732 | INT out_ACCGk, INT out_FRintk) | |
1733 | { | |
1734 | /* Modelling is the same as media-4 unit except use accumulator guards | |
1735 | as input instead of accumulators. */ | |
1736 | return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, | |
1737 | in_ACCGi, in_FRinti, | |
1738 | out_ACCGk, out_FRintk); | |
1739 | } | |
1740 | ||
1741 | int | |
1742 | frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1743 | int unit_num, int referenced, | |
1744 | INT in_ACC40Si, INT out_FRk) | |
1745 | { | |
1746 | int cycles; | |
1747 | FRV_PROFILE_STATE *ps; | |
b34f6357 DB |
1748 | INT ACC40Si_1; |
1749 | INT FRk_1; | |
1750 | ||
1751 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1752 | return 0; | |
1753 | ||
1754 | /* The preprocessing can execute right away. */ | |
1755 | cycles = idesc->timing->units[unit_num].done; | |
1756 | ||
1757 | ps = CPU_PROFILE_STATE (cpu); | |
1758 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1759 | FRk_1 = DUAL_REG (out_FRk); | |
1760 | ||
b34f6357 DB |
1761 | /* The post processing must wait if there is a dependency on a FR |
1762 | which is not ready yet. */ | |
1763 | ps->post_wait = cycles; | |
1764 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1765 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1766 | post_wait_for_FR (cpu, out_FRk); | |
1767 | post_wait_for_FR (cpu, FRk_1); | |
1768 | ||
1769 | /* The latency of the output register will be at least the latency of the | |
1770 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1771 | if (out_FRk >= 0) | |
1772 | { | |
1773 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1774 | update_FR_ptime (cpu, out_FRk, 1); | |
1775 | /* Mark this use of the register as media unit 4. */ | |
1776 | set_use_is_media_p4 (cpu, out_FRk); | |
1777 | } | |
1778 | if (FRk_1 >= 0) | |
1779 | { | |
1780 | update_FR_latency (cpu, FRk_1, ps->post_wait); | |
1781 | update_FR_ptime (cpu, FRk_1, 1); | |
1782 | /* Mark this use of the register as media unit 4. */ | |
1783 | set_use_is_media_p4 (cpu, FRk_1); | |
1784 | } | |
1785 | ||
1786 | return cycles; | |
1787 | } | |
1788 | ||
1789 | int | |
1790 | frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, | |
1791 | int unit_num, int referenced, | |
1792 | INT in_FRi, INT out_FRk) | |
1793 | { | |
1794 | int cycles; | |
1795 | FRV_PROFILE_STATE *ps; | |
b34f6357 DB |
1796 | int busy_adjustment[] = {0}; |
1797 | int *fr; | |
1798 | ||
1799 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1800 | return 0; | |
1801 | ||
1802 | /* The preprocessing can execute right away. */ | |
1803 | cycles = idesc->timing->units[unit_num].done; | |
1804 | ||
1805 | ps = CPU_PROFILE_STATE (cpu); | |
b34f6357 DB |
1806 | |
1807 | /* The latency of the registers may be less than previously recorded, | |
1808 | depending on how they were used previously. | |
1809 | See Table 13-8 in the LSI. */ | |
1810 | if (in_FRi >= 0) | |
1811 | { | |
1812 | if (use_is_fp_load (cpu, in_FRi)) | |
1813 | { | |
1814 | busy_adjustment[0] = 1; | |
1815 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1816 | } | |
1817 | else | |
1818 | enforce_full_fr_latency (cpu, in_FRi); | |
1819 | } | |
1820 | ||
1821 | /* The post processing must wait if there is a dependency on a FR | |
1822 | which is not ready yet. */ | |
1823 | ps->post_wait = cycles; | |
1824 | post_wait_for_FR (cpu, in_FRi); | |
1825 | post_wait_for_FR (cpu, out_FRk); | |
1826 | ||
1827 | /* Restore the busy cycles of the registers we used. */ | |
1828 | fr = ps->fr_busy; | |
1829 | if (in_FRi >= 0) | |
1830 | fr[in_FRi] += busy_adjustment[0]; | |
1831 | ||
1832 | /* The latency of the output register will be at least the latency of the | |
1833 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1834 | if (out_FRk >= 0) | |
1835 | { | |
1836 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1837 | update_FR_ptime (cpu, out_FRk, 1); | |
1838 | ||
1839 | /* Mark this use of the register as media unit 1. */ | |
1840 | set_use_is_media_p6 (cpu, out_FRk); | |
1841 | } | |
1842 | ||
1843 | return cycles; | |
1844 | } | |
1845 | ||
1846 | int | |
1847 | frvbf_model_fr400_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, | |
1848 | int unit_num, int referenced, | |
1849 | INT in_FRinti, INT in_FRintj, | |
1850 | INT out_FCCk) | |
1851 | { | |
1852 | int cycles; | |
1853 | FRV_PROFILE_STATE *ps; | |
1854 | int busy_adjustment[] = {0, 0}; | |
1855 | int *fr; | |
1856 | ||
1857 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1858 | return 0; | |
1859 | ||
1860 | /* The preprocessing can execute right away. */ | |
1861 | cycles = idesc->timing->units[unit_num].done; | |
1862 | ||
1863 | /* The post processing must wait if there is a dependency on a FR | |
1864 | which is not ready yet. */ | |
1865 | ps = CPU_PROFILE_STATE (cpu); | |
1866 | ||
1867 | /* The latency of the registers may be less than previously recorded, | |
1868 | depending on how they were used previously. | |
1869 | See Table 13-8 in the LSI. */ | |
1870 | if (in_FRinti >= 0) | |
1871 | { | |
1872 | if (use_is_fp_load (cpu, in_FRinti)) | |
1873 | { | |
1874 | busy_adjustment[0] = 1; | |
1875 | decrease_FR_busy (cpu, in_FRinti, busy_adjustment[0]); | |
1876 | } | |
1877 | else | |
1878 | enforce_full_fr_latency (cpu, in_FRinti); | |
1879 | } | |
1880 | if (in_FRintj >= 0 && in_FRintj != in_FRinti) | |
1881 | { | |
1882 | if (use_is_fp_load (cpu, in_FRintj)) | |
1883 | { | |
1884 | busy_adjustment[1] = 1; | |
1885 | decrease_FR_busy (cpu, in_FRintj, busy_adjustment[1]); | |
1886 | } | |
1887 | else | |
1888 | enforce_full_fr_latency (cpu, in_FRintj); | |
1889 | } | |
1890 | ||
1891 | ps->post_wait = cycles; | |
1892 | post_wait_for_FR (cpu, in_FRinti); | |
1893 | post_wait_for_FR (cpu, in_FRintj); | |
1894 | post_wait_for_CCR (cpu, out_FCCk); | |
1895 | ||
1896 | /* Restore the busy cycles of the registers we used. */ | |
1897 | fr = ps->fr_busy; | |
1898 | if (in_FRinti >= 0) | |
1899 | fr[in_FRinti] += busy_adjustment[0]; | |
1900 | if (in_FRintj >= 0) | |
1901 | fr[in_FRintj] += busy_adjustment[1]; | |
1902 | ||
1903 | /* The latency of FCCi_2 will be the latency of the other inputs plus 1 | |
1904 | cycle. */ | |
1905 | update_CCR_latency (cpu, out_FCCk, ps->post_wait + 1); | |
1906 | ||
1907 | return cycles; | |
1908 | } | |
1909 | ||
1910 | int | |
1911 | frvbf_model_fr400_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, | |
1912 | int unit_num, int referenced, | |
1913 | INT in_FRi, | |
1914 | INT out_FRk) | |
1915 | { | |
1916 | /* Insns using this unit are media-3 class insns, with a dual FRk output. */ | |
1917 | int cycles; | |
1918 | INT dual_FRk; | |
1919 | FRV_PROFILE_STATE *ps; | |
1920 | int busy_adjustment[] = {0}; | |
1921 | int *fr; | |
1922 | ||
1923 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1924 | return 0; | |
1925 | ||
1926 | /* The preprocessing can execute right away. */ | |
1927 | cycles = idesc->timing->units[unit_num].done; | |
1928 | ||
1929 | /* If the previous use of the registers was a media op, | |
1930 | then their latency will be less than previously recorded. | |
1931 | See Table 13-13 in the LSI. */ | |
1932 | dual_FRk = DUAL_REG (out_FRk); | |
1933 | ps = CPU_PROFILE_STATE (cpu); | |
1934 | if (use_is_fp_load (cpu, in_FRi)) | |
1935 | { | |
1936 | busy_adjustment[0] = 1; | |
1937 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1938 | } | |
1939 | else | |
1940 | enforce_full_fr_latency (cpu, in_FRi); | |
1941 | ||
1942 | /* The post processing must wait if there is a dependency on a FR | |
1943 | which is not ready yet. */ | |
1944 | ps->post_wait = cycles; | |
1945 | post_wait_for_FR (cpu, in_FRi); | |
1946 | post_wait_for_FR (cpu, out_FRk); | |
1947 | post_wait_for_FR (cpu, dual_FRk); | |
1948 | ||
1949 | /* Restore the busy cycles of the registers we used. */ | |
1950 | fr = ps->fr_busy; | |
1951 | fr[in_FRi] += busy_adjustment[0]; | |
1952 | ||
1953 | /* The latency of the output register will be at least the latency of the | |
1954 | other inputs. Once initiated, post-processing has no latency. */ | |
1955 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1956 | update_FR_ptime (cpu, out_FRk, 0); | |
1957 | ||
1958 | if (dual_FRk >= 0) | |
1959 | { | |
1960 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
1961 | update_FR_ptime (cpu, dual_FRk, 0); | |
1962 | } | |
1963 | ||
1964 | return cycles; | |
1965 | } | |
1966 | ||
1967 | int | |
1968 | frvbf_model_fr400_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, | |
1969 | int unit_num, int referenced, | |
1970 | INT in_FRj, | |
1971 | INT out_FRk) | |
1972 | { | |
1973 | /* Insns using this unit are media-3 class insns, with a dual FRj input. */ | |
1974 | int cycles; | |
1975 | INT dual_FRj; | |
1976 | FRV_PROFILE_STATE *ps; | |
1977 | int busy_adjustment[] = {0, 0}; | |
1978 | int *fr; | |
1979 | ||
1980 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1981 | return 0; | |
1982 | ||
1983 | /* The preprocessing can execute right away. */ | |
1984 | cycles = idesc->timing->units[unit_num].done; | |
1985 | ||
1986 | /* If the previous use of the registers was a media op, | |
1987 | then their latency will be less than previously recorded. | |
1988 | See Table 13-13 in the LSI. */ | |
1989 | dual_FRj = DUAL_REG (in_FRj); | |
1990 | ps = CPU_PROFILE_STATE (cpu); | |
1991 | if (use_is_fp_load (cpu, in_FRj)) | |
1992 | { | |
1993 | busy_adjustment[0] = 1; | |
1994 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); | |
1995 | } | |
1996 | else | |
1997 | enforce_full_fr_latency (cpu, in_FRj); | |
1998 | if (dual_FRj >= 0) | |
1999 | { | |
2000 | if (use_is_fp_load (cpu, dual_FRj)) | |
2001 | { | |
2002 | busy_adjustment[1] = 1; | |
2003 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]); | |
2004 | } | |
2005 | else | |
2006 | enforce_full_fr_latency (cpu, dual_FRj); | |
2007 | } | |
2008 | ||
2009 | /* The post processing must wait if there is a dependency on a FR | |
2010 | which is not ready yet. */ | |
2011 | ps->post_wait = cycles; | |
2012 | post_wait_for_FR (cpu, in_FRj); | |
2013 | post_wait_for_FR (cpu, dual_FRj); | |
2014 | post_wait_for_FR (cpu, out_FRk); | |
2015 | ||
2016 | /* Restore the busy cycles of the registers we used. */ | |
2017 | fr = ps->fr_busy; | |
2018 | fr[in_FRj] += busy_adjustment[0]; | |
2019 | if (dual_FRj >= 0) | |
2020 | fr[dual_FRj] += busy_adjustment[1]; | |
2021 | ||
2022 | /* The latency of the output register will be at least the latency of the | |
2023 | other inputs. */ | |
2024 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2025 | ||
2026 | /* Once initiated, post-processing has no latency. */ | |
2027 | update_FR_ptime (cpu, out_FRk, 0); | |
2028 | ||
2029 | return cycles; | |
2030 | } | |
2031 | ||
2032 | int | |
2033 | frvbf_model_fr400_u_ici (SIM_CPU *cpu, const IDESC *idesc, | |
2034 | int unit_num, int referenced, | |
2035 | INT in_GRi, INT in_GRj) | |
2036 | { | |
2037 | /* Modelling for this unit is the same as for fr500. */ | |
2038 | return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, | |
2039 | in_GRi, in_GRj); | |
2040 | } | |
2041 | ||
2042 | int | |
2043 | frvbf_model_fr400_u_dci (SIM_CPU *cpu, const IDESC *idesc, | |
2044 | int unit_num, int referenced, | |
2045 | INT in_GRi, INT in_GRj) | |
2046 | { | |
2047 | /* Modelling for this unit is the same as for fr500. */ | |
2048 | return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, | |
2049 | in_GRi, in_GRj); | |
2050 | } | |
2051 | ||
2052 | int | |
2053 | frvbf_model_fr400_u_dcf (SIM_CPU *cpu, const IDESC *idesc, | |
2054 | int unit_num, int referenced, | |
2055 | INT in_GRi, INT in_GRj) | |
2056 | { | |
2057 | /* Modelling for this unit is the same as for fr500. */ | |
2058 | return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, | |
2059 | in_GRi, in_GRj); | |
2060 | } | |
2061 | ||
2062 | int | |
2063 | frvbf_model_fr400_u_icpl (SIM_CPU *cpu, const IDESC *idesc, | |
2064 | int unit_num, int referenced, | |
2065 | INT in_GRi, INT in_GRj) | |
2066 | { | |
2067 | /* Modelling for this unit is the same as for fr500. */ | |
2068 | return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, | |
2069 | in_GRi, in_GRj); | |
2070 | } | |
2071 | ||
2072 | int | |
2073 | frvbf_model_fr400_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, | |
2074 | int unit_num, int referenced, | |
2075 | INT in_GRi, INT in_GRj) | |
2076 | { | |
2077 | /* Modelling for this unit is the same as for fr500. */ | |
2078 | return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, | |
2079 | in_GRi, in_GRj); | |
2080 | } | |
2081 | ||
2082 | int | |
2083 | frvbf_model_fr400_u_icul (SIM_CPU *cpu, const IDESC *idesc, | |
2084 | int unit_num, int referenced, | |
2085 | INT in_GRi, INT in_GRj) | |
2086 | { | |
2087 | /* Modelling for this unit is the same as for fr500. */ | |
2088 | return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, | |
2089 | in_GRi, in_GRj); | |
2090 | } | |
2091 | ||
2092 | int | |
2093 | frvbf_model_fr400_u_dcul (SIM_CPU *cpu, const IDESC *idesc, | |
2094 | int unit_num, int referenced, | |
2095 | INT in_GRi, INT in_GRj) | |
2096 | { | |
2097 | /* Modelling for this unit is the same as for fr500. */ | |
2098 | return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, | |
2099 | in_GRi, in_GRj); | |
2100 | } | |
2101 | ||
2102 | int | |
2103 | frvbf_model_fr400_u_barrier (SIM_CPU *cpu, const IDESC *idesc, | |
2104 | int unit_num, int referenced) | |
2105 | { | |
2106 | /* Modelling for this unit is the same as for fr500. */ | |
2107 | return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced); | |
2108 | } | |
2109 | ||
2110 | int | |
2111 | frvbf_model_fr400_u_membar (SIM_CPU *cpu, const IDESC *idesc, | |
2112 | int unit_num, int referenced) | |
2113 | { | |
2114 | /* Modelling for this unit is the same as for fr500. */ | |
2115 | return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced); | |
2116 | } | |
2117 | ||
2118 | #endif /* WITH_PROFILE_MODEL_P */ |