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New simulator for Fujitsu frv contributed by Red Hat.
[thirdparty/binutils-gdb.git] / sim / frv / profile-fr500.c
CommitLineData
b34f6357
DB		 1/* frv simulator fr500 dependent profiling code.
2
3 Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Red Hat
5
6This file is part of the GNU simulators.
7
8This program is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 2, or (at your option)
11any later version.
12
13This program is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License along
19with this program; if not, write to the Free Software Foundation, Inc.,
2059 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21
22*/
23#define WANT_CPU
24#define WANT_CPU_FRVBF
25
26#include "sim-main.h"
27#include "bfd.h"
28
29#if WITH_PROFILE_MODEL_P
30
31#include "profile.h"
32#include "profile-fr500.h"
33
34/* Initialize cycle counting for an insn.
35 FIRST_P is non-zero if this is the first insn in a set of parallel
36 insns. */
37void
38fr500_model_insn_before (SIM_CPU *cpu, int first_p)
39{
40 if (first_p)
41 {
42 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
43 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
44 ps->cur_gr_complex = ps->prev_gr_complex;
45 d->cur_fpop = d->prev_fpop;
46 d->cur_media = d->prev_media;
47 d->cur_cc_complex = d->prev_cc_complex;
48 }
49}
50
51/* Record the cycles computed for an insn.
52 LAST_P is non-zero if this is the last insn in a set of parallel insns,
53 and we update the total cycle count.
54 CYCLES is the cycle count of the insn. */
55void
56fr500_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
57{
58 if (last_p)
59 {
60 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
61 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
62 ps->prev_gr_complex = ps->cur_gr_complex;
63 d->prev_fpop = d->cur_fpop;
64 d->prev_media = d->cur_media;
65 d->prev_cc_complex = d->cur_cc_complex;
66 }
67}
68
69static void
70set_use_is_fpop (SIM_CPU *cpu, INT fr)
71{
72 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
73 fr500_reset_fr_flags (cpu, (fr));
74 d->cur_fpop |= (((DI)1) << (fr));
75}
76
77static void
78set_use_not_fpop (SIM_CPU *cpu, INT fr)
79{
80 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
81 d->cur_fpop &= ~(((DI)1) << (fr));
82}
83
84static int
85use_is_fpop (SIM_CPU *cpu, INT fr)
86{
87 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
88 return d->prev_fpop & (((DI)1) << (fr));
89}
90
91static void
92set_use_is_media ( SIM_CPU *cpu, INT fr)
93{
94 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
95 fr500_reset_fr_flags (cpu, (fr));
96 d->cur_media |= (((DI)1) << (fr));
97}
98
99static void
100set_use_not_media (SIM_CPU *cpu, INT fr)
101{
102 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
103 d->cur_media &= ~(((DI)1) << (fr));
104}
105
106static int
107use_is_media (SIM_CPU *cpu, INT fr)
108{
109 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
110 return d->prev_media & (((DI)1) << (fr));
111}
112
113static void
114set_use_is_cc_complex (SIM_CPU *cpu, INT cc)
115{
116 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
117 fr500_reset_cc_flags (cpu, cc);
118 d->cur_cc_complex |= (((DI)1) << (cc));
119}
120
121static void
122set_use_not_cc_complex (SIM_CPU *cpu, INT cc)
123{
124 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
125 d->cur_cc_complex &= ~(((DI)1) << (cc));
126}
127
128static int
129use_is_cc_complex (SIM_CPU *cpu, INT cc)
130{
131 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
132 return d->prev_cc_complex & (((DI)1) << (cc));
133}
134
135void
136fr500_reset_fr_flags (SIM_CPU *cpu, INT fr)
137{
138 set_use_not_fpop (cpu, fr);
139 set_use_not_media (cpu, fr);
140}
141
142void
143fr500_reset_cc_flags (SIM_CPU *cpu, INT cc)
144{
145 set_use_not_cc_complex (cpu, cc);
146}
147
148/* Latency of floating point registers may be less than recorded when followed
149 by another floating point insn. */
150static void
151adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
152 int cycles)
153{
154 /* If the registers were previously used in a floating point op,
155 then their latency will be less than previously recorded.
156 See Table 13-13 in the LSI. */
157 if (in_FRi >= 0)
158 if (use_is_fpop (cpu, in_FRi))
159 decrease_FR_busy (cpu, in_FRi, cycles);
160 else
161 enforce_full_fr_latency (cpu, in_FRi);
162
163 if (in_FRj >= 0 && in_FRj != in_FRi)
164 if (use_is_fpop (cpu, in_FRj))
165 decrease_FR_busy (cpu, in_FRj, cycles);
166 else
167 enforce_full_fr_latency (cpu, in_FRj);
168
169 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
170 if (use_is_fpop (cpu, out_FRk))
171 decrease_FR_busy (cpu, out_FRk, cycles);
172 else
173 enforce_full_fr_latency (cpu, out_FRk);
174}
175
176/* Latency of floating point registers may be less than recorded when followed
177 by another floating point insn. */
178static void
179adjust_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
180 int cycles)
181{
182 /* If the registers were previously used in a floating point op,
183 then their latency will be less than previously recorded.
184 See Table 13-13 in the LSI. */
185 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
186 if (in_FRi >= 0) ++in_FRi;
187 if (in_FRj >= 0) ++in_FRj;
188 if (out_FRk >= 0) ++out_FRk;
189 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
190}
191
192/* Latency of floating point registers is less than recorded when followed
193 by another floating point insn. */
194static void
195restore_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
196 int cycles)
197{
198 /* If the registers were previously used in a floating point op,
199 then their latency will be less than previously recorded.
200 See Table 13-13 in the LSI. */
201 if (in_FRi >= 0 && use_is_fpop (cpu, in_FRi))
202 increase_FR_busy (cpu, in_FRi, cycles);
203 if (in_FRj != in_FRi && use_is_fpop (cpu, in_FRj))
204 increase_FR_busy (cpu, in_FRj, cycles);
205 if (out_FRk != in_FRi && out_FRk != in_FRj && use_is_fpop (cpu, out_FRk))
206 increase_FR_busy (cpu, out_FRk, cycles);
207}
208
209/* Latency of floating point registers is less than recorded when followed
210 by another floating point insn. */
211static void
212restore_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
213 int cycles)
214{
215 /* If the registers were previously used in a floating point op,
216 then their latency will be less than previously recorded.
217 See Table 13-13 in the LSI. */
218 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
219 if (in_FRi >= 0) ++in_FRi;
220 if (in_FRj >= 0) ++in_FRj;
221 if (out_FRk >= 0) ++out_FRk;
222 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
223}
224
225int
226frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc,
227 int unit_num, int referenced)
228{
229 return idesc->timing->units[unit_num].done;
230}
231
232int
233frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc,
234 int unit_num, int referenced,
235 INT in_GRi, INT in_GRj, INT out_GRk,
236 INT out_ICCi_1)
237{
238 int cycles;
239
240 if (model_insn == FRV_INSN_MODEL_PASS_1)
241 {
242 /* icc0-icc4 are the upper 4 fields of the CCR. */
243 if (out_ICCi_1 >= 0)
244 out_ICCi_1 += 4;
245
246 /* The entire VLIW insn must wait if there is a dependency on a register
247 which is not ready yet.
248 The latency of the registers may be less than previously recorded,
249 depending on how they were used previously.
250 See Table 13-8 in the LSI. */
251 if (in_GRi != out_GRk && in_GRi >= 0)
252 {
253 if (use_is_gr_complex (cpu, in_GRi))
254 decrease_GR_busy (cpu, in_GRi, 1);
255 }
256 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
257 {
258 if (use_is_gr_complex (cpu, in_GRj))
259 decrease_GR_busy (cpu, in_GRj, 1);
260 }
261 vliw_wait_for_GR (cpu, in_GRi);
262 vliw_wait_for_GR (cpu, in_GRj);
263 vliw_wait_for_GR (cpu, out_GRk);
264 vliw_wait_for_CCR (cpu, out_ICCi_1);
265 handle_resource_wait (cpu);
266 load_wait_for_GR (cpu, in_GRi);
267 load_wait_for_GR (cpu, in_GRj);
268 load_wait_for_GR (cpu, out_GRk);
269 trace_vliw_wait_cycles (cpu);
270 return 0;
271 }
272
273 /* GRk is available immediately to the next VLIW insn as is ICCi_1. */
274 cycles = idesc->timing->units[unit_num].done;
275 return cycles;
276}
277
278int
279frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc,
280 int unit_num, int referenced,
281 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
282{
283 int cycles;
284 /* icc0-icc4 are the upper 4 fields of the CCR. */
285 if (out_ICCi_1 >= 0)
286 out_ICCi_1 += 4;
287
288 if (model_insn == FRV_INSN_MODEL_PASS_1)
289 {
290 /* The entire VLIW insn must wait if there is a dependency on a register
291 which is not ready yet.
292 The latency of the registers may be less than previously recorded,
293 depending on how they were used previously.
294 See Table 13-8 in the LSI. */
295 if (in_GRi != out_GRk && in_GRi >= 0)
296 {
297 if (use_is_gr_complex (cpu, in_GRi))
298 decrease_GR_busy (cpu, in_GRi, 1);
299 }
300 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
301 {
302 if (use_is_gr_complex (cpu, in_GRj))
303 decrease_GR_busy (cpu, in_GRj, 1);
304 }
305 vliw_wait_for_GR (cpu, in_GRi);
306 vliw_wait_for_GR (cpu, in_GRj);
307 vliw_wait_for_GRdouble (cpu, out_GRk);
308 vliw_wait_for_CCR (cpu, out_ICCi_1);
309 handle_resource_wait (cpu);
310 load_wait_for_GR (cpu, in_GRi);
311 load_wait_for_GR (cpu, in_GRj);
312 load_wait_for_GRdouble (cpu, out_GRk);
313 trace_vliw_wait_cycles (cpu);
314 return 0;
315 }
316
317 /* GRk has a latency of 2 cycles. */
318 cycles = idesc->timing->units[unit_num].done;
319 update_GRdouble_latency (cpu, out_GRk, cycles + 2);
320 set_use_is_gr_complex (cpu, out_GRk);
321 set_use_is_gr_complex (cpu, out_GRk + 1);
322
323 /* ICCi_1 has a latency of 1 cycle. */
324 update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
325
326 return cycles;
327}
328
329int
330frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
331 int unit_num, int referenced,
332 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
333{
334 int cycles;
335 FRV_VLIW *vliw;
336 int slot;
337
338 /* icc0-icc4 are the upper 4 fields of the CCR. */
339 if (out_ICCi_1 >= 0)
340 out_ICCi_1 += 4;
341
342 vliw = CPU_VLIW (cpu);
343 slot = vliw->next_slot - 1;
344 slot = (*vliw->current_vliw)[slot] - UNIT_I0;
345
346 if (model_insn == FRV_INSN_MODEL_PASS_1)
347 {
348 /* The entire VLIW insn must wait if there is a dependency on a register
349 which is not ready yet.
350 The latency of the registers may be less than previously recorded,
351 depending on how they were used previously.
352 See Table 13-8 in the LSI. */
353 if (in_GRi != out_GRk && in_GRi >= 0)
354 {
355 if (use_is_gr_complex (cpu, in_GRi))
356 decrease_GR_busy (cpu, in_GRi, 1);
357 }
358 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
359 {
360 if (use_is_gr_complex (cpu, in_GRj))
361 decrease_GR_busy (cpu, in_GRj, 1);
362 }
363 vliw_wait_for_GR (cpu, in_GRi);
364 vliw_wait_for_GR (cpu, in_GRj);
365 vliw_wait_for_GR (cpu, out_GRk);
366 vliw_wait_for_CCR (cpu, out_ICCi_1);
367 vliw_wait_for_idiv_resource (cpu, slot);
368 handle_resource_wait (cpu);
369 load_wait_for_GR (cpu, in_GRi);
370 load_wait_for_GR (cpu, in_GRj);
371 load_wait_for_GR (cpu, out_GRk);
372 trace_vliw_wait_cycles (cpu);
373 return 0;
374 }
375
376 /* GRk has a latency of 19 cycles! */
377 cycles = idesc->timing->units[unit_num].done;
378 update_GR_latency (cpu, out_GRk, cycles + 19);
379 set_use_is_gr_complex (cpu, out_GRk);
380
381 /* ICCi_1 has a latency of 19 cycles. */
382 update_CCR_latency (cpu, out_ICCi_1, cycles + 19);
383 set_use_is_cc_complex (cpu, out_ICCi_1);
384
385 /* the idiv resource has a latency of 18 cycles! */
386 update_idiv_resource_latency (cpu, slot, cycles + 18);
387
388 return cycles;
389}
390
391int
392frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc,
393 int unit_num, int referenced,
394 INT in_GRi, INT in_GRj,
395 INT in_ICCi_2, INT in_FCCi_2)
396{
397 int cycles;
398 FRV_PROFILE_STATE *ps;
399
400 if (model_insn == FRV_INSN_MODEL_PASS_1)
401 {
402 /* icc0-icc4 are the upper 4 fields of the CCR. */
403 if (in_ICCi_2 >= 0)
404 in_ICCi_2 += 4;
405
406 /* The entire VLIW insn must wait if there is a dependency on a register
407 which is not ready yet.
408 The latency of the registers may be less than previously recorded,
409 depending on how they were used previously.
410 See Table 13-8 in the LSI. */
411 if (in_GRi >= 0)
412 {
413 if (use_is_gr_complex (cpu, in_GRi))
414 decrease_GR_busy (cpu, in_GRi, 1);
415 }
416 if (in_GRj != in_GRi && in_GRj >= 0)
417 {
418 if (use_is_gr_complex (cpu, in_GRj))
419 decrease_GR_busy (cpu, in_GRj, 1);
420 }
421 vliw_wait_for_GR (cpu, in_GRi);
422 vliw_wait_for_GR (cpu, in_GRj);
423 vliw_wait_for_CCR (cpu, in_ICCi_2);
424 vliw_wait_for_CCR (cpu, in_FCCi_2);
425 handle_resource_wait (cpu);
426 load_wait_for_GR (cpu, in_GRi);
427 load_wait_for_GR (cpu, in_GRj);
428 trace_vliw_wait_cycles (cpu);
429 return 0;
430 }
431
432 /* When counting branches taken or not taken, don't consider branches after
433 the first taken branch in a vliw insn. */
434 ps = CPU_PROFILE_STATE (cpu);
435 if (! ps->vliw_branch_taken)
436 {
437 /* (1 << 4): The pc is the 5th element in inputs, outputs.
438 ??? can be cleaned up */
439 PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
440 int taken = (referenced & (1 << 4)) != 0;
441 if (taken)
442 {
443 ++PROFILE_MODEL_TAKEN_COUNT (p);
444 ps->vliw_branch_taken = 1;
445 }
446 else
447 ++PROFILE_MODEL_UNTAKEN_COUNT (p);
448 }
449
450 cycles = idesc->timing->units[unit_num].done;
451 return cycles;
452}
453
454int
455frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc,
456 int unit_num, int referenced,
457 INT in_GRi, INT in_GRj,
458 INT in_ICCi_2, INT in_FCCi_2)
459{
460 int cycles;
461 FRV_PROFILE_STATE *ps;
462
463 if (model_insn == FRV_INSN_MODEL_PASS_1)
464 {
465 /* icc0-icc4 are the upper 4 fields of the CCR. */
466 if (in_ICCi_2 >= 0)
467 in_ICCi_2 += 4;
468
469 /* The entire VLIW insn must wait if there is a dependency on a register
470 which is not ready yet.
471 The latency of the registers may be less than previously recorded,
472 depending on how they were used previously.
473 See Table 13-8 in the LSI. */
474 if (in_GRi >= 0)
475 {
476 if (use_is_gr_complex (cpu, in_GRi))
477 decrease_GR_busy (cpu, in_GRi, 1);
478 }
479 if (in_GRj != in_GRi && in_GRj >= 0)
480 {
481 if (use_is_gr_complex (cpu, in_GRj))
482 decrease_GR_busy (cpu, in_GRj, 1);
483 }
484 vliw_wait_for_GR (cpu, in_GRi);
485 vliw_wait_for_GR (cpu, in_GRj);
486 vliw_wait_for_CCR (cpu, in_ICCi_2);
487 vliw_wait_for_CCR (cpu, in_FCCi_2);
488 handle_resource_wait (cpu);
489 load_wait_for_GR (cpu, in_GRi);
490 load_wait_for_GR (cpu, in_GRj);
491 trace_vliw_wait_cycles (cpu);
492 return 0;
493 }
494
495 cycles = idesc->timing->units[unit_num].done;
496 return cycles;
497}
498
499int
500frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc,
501 int unit_num, int referenced,
502 INT in_ICCi_3, INT in_FCCi_3)
503{
504 int cycles;
505 FRV_PROFILE_STATE *ps;
506
507 if (model_insn == FRV_INSN_MODEL_PASS_1)
508 {
509 /* icc0-icc4 are the upper 4 fields of the CCR. */
510 if (in_ICCi_3 >= 0)
511 in_ICCi_3 += 4;
512
513 /* The entire VLIW insn must wait if there is a dependency on a register
514 which is not ready yet. */
515 vliw_wait_for_CCR (cpu, in_ICCi_3);
516 vliw_wait_for_CCR (cpu, in_FCCi_3);
517 handle_resource_wait (cpu);
518 trace_vliw_wait_cycles (cpu);
519 return 0;
520 }
521
522 cycles = idesc->timing->units[unit_num].done;
523 return cycles;
524}
525
526int
527frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
528 int unit_num, int referenced,
529 INT out_GRkhi, INT out_GRklo)
530{
531 int cycles;
532
533 if (model_insn == FRV_INSN_MODEL_PASS_1)
534 {
535 /* The entire VLIW insn must wait if there is a dependency on a GR
536 which is not ready yet. */
537 vliw_wait_for_GR (cpu, out_GRkhi);
538 vliw_wait_for_GR (cpu, out_GRklo);
539 handle_resource_wait (cpu);
540 load_wait_for_GR (cpu, out_GRkhi);
541 load_wait_for_GR (cpu, out_GRklo);
542 trace_vliw_wait_cycles (cpu);
543 return 0;
544 }
545
546 /* GRk is available immediately to the next VLIW insn. */
547 cycles = idesc->timing->units[unit_num].done;
548
549 set_use_not_gr_complex (cpu, out_GRkhi);
550 set_use_not_gr_complex (cpu, out_GRklo);
551
552 return cycles;
553}
554
555int
556frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
557 int unit_num, int referenced,
558 INT in_GRi, INT in_GRj,
559 INT out_GRk, INT out_GRdoublek)
560{
561 int cycles;
562
563 if (model_insn == FRV_INSN_MODEL_PASS_1)
564 {
565 /* The entire VLIW insn must wait if there is a dependency on a register
566 which is not ready yet.
567 The latency of the registers may be less than previously recorded,
568 depending on how they were used previously.
569 See Table 13-8 in the LSI. */
570 if (in_GRi != out_GRk && in_GRi != out_GRdoublek
571 && in_GRi != out_GRdoublek + 1 && in_GRi >= 0)
572 {
573 if (use_is_gr_complex (cpu, in_GRi))
574 decrease_GR_busy (cpu, in_GRi, 1);
575 }
576 if (in_GRj != in_GRi && in_GRj != out_GRk && in_GRj != out_GRdoublek
577 && in_GRj != out_GRdoublek + 1 && in_GRj >= 0)
578
579 {
580 if (use_is_gr_complex (cpu, in_GRj))
581 decrease_GR_busy (cpu, in_GRj, 1);
582 }
583 vliw_wait_for_GR (cpu, in_GRi);
584 vliw_wait_for_GR (cpu, in_GRj);
585 vliw_wait_for_GR (cpu, out_GRk);
586 vliw_wait_for_GRdouble (cpu, out_GRdoublek);
587 handle_resource_wait (cpu);
588 load_wait_for_GR (cpu, in_GRi);
589 load_wait_for_GR (cpu, in_GRj);
590 load_wait_for_GR (cpu, out_GRk);
591 load_wait_for_GRdouble (cpu, out_GRdoublek);
592 trace_vliw_wait_cycles (cpu);
593 return 0;
594 }
595
596 cycles = idesc->timing->units[unit_num].done;
597
598 /* The latency of GRk for a load will depend on how long it takes to retrieve
599 the the data from the cache or memory. */
600 update_GR_latency_for_load (cpu, out_GRk, cycles);
601 update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
602
603 set_use_is_gr_complex (cpu, out_GRk);
604 set_use_is_gr_complex (cpu, out_GRdoublek);
605 set_use_is_gr_complex (cpu, out_GRdoublek + 1);
606
607 return cycles;
608}
609
610int
611frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
612 int unit_num, int referenced,
613 INT in_GRi, INT in_GRj,
614 INT in_GRk, INT in_GRdoublek)
615{
616 int cycles;
617
618 if (model_insn == FRV_INSN_MODEL_PASS_1)
619 {
620 /* The entire VLIW insn must wait if there is a dependency on a register
621 which is not ready yet.
622 The latency of the registers may be less than previously recorded,
623 depending on how they were used previously.
624 See Table 13-8 in the LSI. */
625 if (in_GRi >= 0)
626 {
627 if (use_is_gr_complex (cpu, in_GRi))
628 decrease_GR_busy (cpu, in_GRi, 1);
629 }
630 if (in_GRj != in_GRi && in_GRj >= 0)
631 {
632 if (use_is_gr_complex (cpu, in_GRj))
633 decrease_GR_busy (cpu, in_GRj, 1);
634 }
635 if (in_GRk != in_GRi && in_GRk != in_GRj && in_GRk >= 0)
636 {
637 if (use_is_gr_complex (cpu, in_GRk))
638 decrease_GR_busy (cpu, in_GRk, 1);
639 }
640 if (in_GRdoublek != in_GRi && in_GRdoublek != in_GRj
641 && in_GRdoublek + 1 != in_GRi && in_GRdoublek + 1 != in_GRj
642 && in_GRdoublek >= 0)
643 {
644 if (use_is_gr_complex (cpu, in_GRdoublek))
645 decrease_GR_busy (cpu, in_GRdoublek, 1);
646 if (use_is_gr_complex (cpu, in_GRdoublek + 1))
647 decrease_GR_busy (cpu, in_GRdoublek + 1, 1);
648 }
649 vliw_wait_for_GR (cpu, in_GRi);
650 vliw_wait_for_GR (cpu, in_GRj);
651 vliw_wait_for_GR (cpu, in_GRk);
652 vliw_wait_for_GRdouble (cpu, in_GRdoublek);
653 handle_resource_wait (cpu);
654 load_wait_for_GR (cpu, in_GRi);
655 load_wait_for_GR (cpu, in_GRj);
656 load_wait_for_GR (cpu, in_GRk);
657 load_wait_for_GRdouble (cpu, in_GRdoublek);
658 trace_vliw_wait_cycles (cpu);
659 return 0;
660 }
661
662 cycles = idesc->timing->units[unit_num].done;
663
664 return cycles;
665}
666
667int
668frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc,
669 int unit_num, int referenced,
670 INT in_GRi, INT in_GRj,
671 INT in_GRk, INT in_GRdoublek)
672{
673 int cycles = frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
674 in_GRi, in_GRj, in_GRk,
675 in_GRdoublek);
676
677 if (model_insn == FRV_INSN_MODEL_PASS_2)
678 {
679 if (CPU_RSTR_INVALIDATE(cpu))
680 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
681 }
682
683 return cycles;
684}
685
686int
687frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
688 int unit_num, int referenced,
689 INT in_GRi, INT in_GRj,
690 INT out_FRk, INT out_FRdoublek)
691{
692 int cycles;
693
694 if (model_insn == FRV_INSN_MODEL_PASS_1)
695 {
696 /* The entire VLIW insn must wait if there is a dependency on a register
697 which is not ready yet.
698 The latency of the registers may be less than previously recorded,
699 depending on how they were used previously.
700 See Table 13-8 in the LSI. */
701 if (in_GRi >= 0)
702 {
703 if (use_is_gr_complex (cpu, in_GRi))
704 decrease_GR_busy (cpu, in_GRi, 1);
705 }
706 if (in_GRj != in_GRi && in_GRj >= 0)
707 {
708 if (use_is_gr_complex (cpu, in_GRj))
709 decrease_GR_busy (cpu, in_GRj, 1);
710 }
711 if (out_FRk >= 0)
712 {
713 if (use_is_media (cpu, out_FRk))
714 decrease_FR_busy (cpu, out_FRk, 1);
715 else
716 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
717 }
718 if (out_FRdoublek >= 0)
719 {
720 if (use_is_media (cpu, out_FRdoublek))
721 decrease_FR_busy (cpu, out_FRdoublek, 1);
722 else
723 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek, 1);
724 if (use_is_media (cpu, out_FRdoublek + 1))
725 decrease_FR_busy (cpu, out_FRdoublek + 1, 1);
726 else
727 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek + 1, 1);
728 }
729 vliw_wait_for_GR (cpu, in_GRi);
730 vliw_wait_for_GR (cpu, in_GRj);
731 vliw_wait_for_FR (cpu, out_FRk);
732 vliw_wait_for_FRdouble (cpu, out_FRdoublek);
733 handle_resource_wait (cpu);
734 load_wait_for_GR (cpu, in_GRi);
735 load_wait_for_GR (cpu, in_GRj);
736 load_wait_for_FR (cpu, out_FRk);
737 load_wait_for_FRdouble (cpu, out_FRdoublek);
738 trace_vliw_wait_cycles (cpu);
739 return 0;
740 }
741
742 cycles = idesc->timing->units[unit_num].done;
743
744 /* The latency of FRk for a load will depend on how long it takes to retrieve
745 the the data from the cache or memory. */
746 update_FR_latency_for_load (cpu, out_FRk, cycles);
747 update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles);
748
749 fr500_reset_fr_flags (cpu, out_FRk);
750
751 return cycles;
752}
753
754int
755frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
756 int unit_num, int referenced,
757 INT in_GRi, INT in_GRj,
758 INT in_FRk, INT in_FRdoublek)
759{
760 int cycles;
761
762 if (model_insn == FRV_INSN_MODEL_PASS_1)
763 {
764 /* The entire VLIW insn must wait if there is a dependency on a register
765 which is not ready yet.
766 The latency of the registers may be less than previously recorded,
767 depending on how they were used previously.
768 See Table 13-8 in the LSI. */
769 if (in_GRi >= 0)
770 {
771 if (use_is_gr_complex (cpu, in_GRi))
772 decrease_GR_busy (cpu, in_GRi, 1);
773 }
774 if (in_GRj != in_GRi && in_GRj >= 0)
775 {
776 if (use_is_gr_complex (cpu, in_GRj))
777 decrease_GR_busy (cpu, in_GRj, 1);
778 }
779 if (in_FRk >= 0)
780 {
781 if (use_is_media (cpu, in_FRk))
782 decrease_FR_busy (cpu, in_FRk, 1);
783 else
784 adjust_float_register_busy (cpu, -1, -1, in_FRk, 1);
785 }
786 if (in_FRdoublek >= 0)
787 {
788 if (use_is_media (cpu, in_FRdoublek))
789 decrease_FR_busy (cpu, in_FRdoublek, 1);
790 else
791 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek, 1);
792 if (use_is_media (cpu, in_FRdoublek + 1))
793 decrease_FR_busy (cpu, in_FRdoublek + 1, 1);
794 else
795 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek + 1, 1);
796 }
797 vliw_wait_for_GR (cpu, in_GRi);
798 vliw_wait_for_GR (cpu, in_GRj);
799 vliw_wait_for_FR (cpu, in_FRk);
800 vliw_wait_for_FRdouble (cpu, in_FRdoublek);
801 handle_resource_wait (cpu);
802 load_wait_for_GR (cpu, in_GRi);
803 load_wait_for_GR (cpu, in_GRj);
804 load_wait_for_FR (cpu, in_FRk);
805 load_wait_for_FRdouble (cpu, in_FRdoublek);
806 trace_vliw_wait_cycles (cpu);
807 return 0;
808 }
809
810 cycles = idesc->timing->units[unit_num].done;
811
812 return cycles;
813}
814
815int
816frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc,
817 int unit_num, int referenced,
818 INT in_GRi, INT in_GRj,
819 INT in_FRk, INT in_FRdoublek)
820{
821 int cycles = frvbf_model_fr500_u_fr_store (cpu, idesc, unit_num, referenced,
822 in_GRi, in_GRj, in_FRk,
823 in_FRdoublek);
824
825 if (model_insn == FRV_INSN_MODEL_PASS_2)
826 {
827 if (CPU_RSTR_INVALIDATE(cpu))
828 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
829 }
830
831 return cycles;
832}
833
834int
835frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc,
836 int unit_num, int referenced,
837 INT in_GRi, INT in_GRj, INT out_GRk)
838{
839 int cycles;
840
841 if (model_insn == FRV_INSN_MODEL_PASS_1)
842 {
843 /* The entire VLIW insn must wait if there is a dependency on a register
844 which is not ready yet.
845 The latency of the registers may be less than previously recorded,
846 depending on how they were used previously.
847 See Table 13-8 in the LSI. */
848 if (in_GRi != out_GRk && in_GRi >= 0)
849 {
850 if (use_is_gr_complex (cpu, in_GRi))
851 decrease_GR_busy (cpu, in_GRi, 1);
852 }
853 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
854 {
855 if (use_is_gr_complex (cpu, in_GRj))
856 decrease_GR_busy (cpu, in_GRj, 1);
857 }
858 vliw_wait_for_GR (cpu, in_GRi);
859 vliw_wait_for_GR (cpu, in_GRj);
860 vliw_wait_for_GR (cpu, out_GRk);
861 handle_resource_wait (cpu);
862 load_wait_for_GR (cpu, in_GRi);
863 load_wait_for_GR (cpu, in_GRj);
864 load_wait_for_GR (cpu, out_GRk);
865 trace_vliw_wait_cycles (cpu);
866 return 0;
867 }
868
869 cycles = idesc->timing->units[unit_num].done;
870
871 /* The latency of GRk will depend on how long it takes to swap
872 the the data from the cache or memory. */
873 update_GR_latency_for_swap (cpu, out_GRk, cycles);
874 set_use_is_gr_complex (cpu, out_GRk);
875
876 return cycles;
877}
878
879int
880frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc,
881 int unit_num, int referenced,
882 INT in_FRj, INT out_FRk)
883{
884 int cycles;
885
886 if (model_insn == FRV_INSN_MODEL_PASS_1)
887 {
888 /* The entire VLIW insn must wait if there is a dependency on a register
889 which is not ready yet. */
890 if (in_FRj >= 0)
891 {
892 if (use_is_media (cpu, in_FRj))
893 decrease_FR_busy (cpu, in_FRj, 1);
894 else
895 adjust_float_register_busy (cpu, -1, in_FRj, -1, 1);
896 }
897 if (out_FRk >= 0 && out_FRk != in_FRj)
898 {
899 if (use_is_media (cpu, out_FRk))
900 decrease_FR_busy (cpu, out_FRk, 1);
901 else
902 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
903 }
904 vliw_wait_for_FR (cpu, in_FRj);
905 vliw_wait_for_FR (cpu, out_FRk);
906 handle_resource_wait (cpu);
907 load_wait_for_FR (cpu, in_FRj);
908 load_wait_for_FR (cpu, out_FRk);
909 trace_vliw_wait_cycles (cpu);
910 return 0;
911 }
912
913 /* The latency of FRj is 3 cycles. */
914 cycles = idesc->timing->units[unit_num].done;
915 update_FR_latency (cpu, out_FRk, cycles + 3);
916
917 return cycles;
918}
919
920int
921frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
922 int unit_num, int referenced,
923 INT in_FRk, INT out_GRj)
924{
925 int cycles;
926
927 if (model_insn == FRV_INSN_MODEL_PASS_1)
928 {
929 /* The entire VLIW insn must wait if there is a dependency on a register
930 which is not ready yet. */
931 if (in_FRk >= 0)
932 {
933 if (use_is_media (cpu, in_FRk))
934 decrease_FR_busy (cpu, in_FRk, 1);
935 else
936 adjust_float_register_busy (cpu, -1, in_FRk, -1, 1);
937 }
938 vliw_wait_for_FR (cpu, in_FRk);
939 vliw_wait_for_GR (cpu, out_GRj);
940 handle_resource_wait (cpu);
941 load_wait_for_FR (cpu, in_FRk);
942 load_wait_for_GR (cpu, out_GRj);
943 trace_vliw_wait_cycles (cpu);
944 return 0;
945 }
946
947 /* The latency of GRj is 2 cycles. */
948 cycles = idesc->timing->units[unit_num].done;
949 update_GR_latency (cpu, out_GRj, cycles + 2);
950 set_use_is_gr_complex (cpu, out_GRj);
951
952 return cycles;
953}
954
955int
956frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
957 int unit_num, int referenced,
958 INT in_spr, INT out_GRj)
959{
960 int cycles;
961
962 if (model_insn == FRV_INSN_MODEL_PASS_1)
963 {
964 /* The entire VLIW insn must wait if there is a dependency on a register
965 which is not ready yet.
966 SPR registers appear to have no latency effects. */
967 vliw_wait_for_GR (cpu, out_GRj);
968 handle_resource_wait (cpu);
969 load_wait_for_GR (cpu, out_GRj);
970 trace_vliw_wait_cycles (cpu);
971 return 0;
972 }
973
974 cycles = idesc->timing->units[unit_num].done;
975
976#if 0 /* no latency? */
977 /* The latency of GRj is 2 cycles. */
978 update_GR_latency (cpu, out_GRj, cycles + 2);
979#endif
980
981 return cycles;
982}
983
984int
985frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
986 int unit_num, int referenced,
987 INT in_GRj, INT out_FRk)
988{
989 int cycles;
990
991 if (model_insn == FRV_INSN_MODEL_PASS_1)
992 {
993 /* The entire VLIW insn must wait if there is a dependency on a register
994 which is not ready yet.
995 The latency of the registers may be less than previously recorded,
996 depending on how they were used previously.
997 See Table 13-8 in the LSI. */
998 if (in_GRj >= 0)
999 {
1000 if (use_is_gr_complex (cpu, in_GRj))
1001 decrease_GR_busy (cpu, in_GRj, 1);
1002 }
1003 if (out_FRk >= 0)
1004 {
1005 if (use_is_media (cpu, out_FRk))
1006 decrease_FR_busy (cpu, out_FRk, 1);
1007 else
1008 adjust_float_register_busy (cpu, -1, out_FRk, -1, 1);
1009 }
1010 vliw_wait_for_GR (cpu, in_GRj);
1011 vliw_wait_for_FR (cpu, out_FRk);
1012 handle_resource_wait (cpu);
1013 load_wait_for_GR (cpu, in_GRj);
1014 load_wait_for_FR (cpu, out_FRk);
1015 trace_vliw_wait_cycles (cpu);
1016 return 0;
1017 }
1018
1019 /* The latency of FRk is 2 cycles. */
1020 cycles = idesc->timing->units[unit_num].done;
1021 update_FR_latency (cpu, out_FRk, cycles + 2);
1022
1023 /* Mark this use of the register as NOT a floating point op. */
1024 fr500_reset_fr_flags (cpu, out_FRk);
1025
1026 return cycles;
1027}
1028
1029int
1030frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
1031 int unit_num, int referenced,
1032 INT in_GRj, INT out_spr)
1033{
1034 int cycles;
1035
1036 if (model_insn == FRV_INSN_MODEL_PASS_1)
1037 {
1038 /* The entire VLIW insn must wait if there is a dependency on a register
1039 which is not ready yet.
1040 The latency of the registers may be less than previously recorded,
1041 depending on how they were used previously.
1042 See Table 13-8 in the LSI. */
1043 if (in_GRj >= 0)
1044 {
1045 if (use_is_gr_complex (cpu, in_GRj))
1046 decrease_GR_busy (cpu, in_GRj, 1);
1047 }
1048 vliw_wait_for_GR (cpu, in_GRj);
1049 handle_resource_wait (cpu);
1050 load_wait_for_GR (cpu, in_GRj);
1051 trace_vliw_wait_cycles (cpu);
1052 return 0;
1053 }
1054
1055 cycles = idesc->timing->units[unit_num].done;
1056
1057#if 0
1058 /* The latency of spr is ? cycles. */
1059 update_SPR_latency (cpu, out_spr, cycles + ?);
1060#endif
1061
1062 return cycles;
1063}
1064
1065int
1066frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc,
1067 int unit_num, int referenced,
1068 INT in_GRi, INT in_GRj)
1069{
1070 int cycles;
1071
1072 if (model_insn == FRV_INSN_MODEL_PASS_1)
1073 {
1074 /* The entire VLIW insn must wait if there is a dependency on a register
1075 which is not ready yet.
1076 The latency of the registers may be less than previously recorded,
1077 depending on how they were used previously.
1078 See Table 13-8 in the LSI. */
1079 if (in_GRi >= 0)
1080 {
1081 if (use_is_gr_complex (cpu, in_GRi))
1082 decrease_GR_busy (cpu, in_GRi, 1);
1083 }
1084 if (in_GRj != in_GRi && in_GRj >= 0)
1085 {
1086 if (use_is_gr_complex (cpu, in_GRj))
1087 decrease_GR_busy (cpu, in_GRj, 1);
1088 }
1089 vliw_wait_for_GR (cpu, in_GRi);
1090 vliw_wait_for_GR (cpu, in_GRj);
1091 handle_resource_wait (cpu);
1092 load_wait_for_GR (cpu, in_GRi);
1093 load_wait_for_GR (cpu, in_GRj);
1094 trace_vliw_wait_cycles (cpu);
1095 return 0;
1096 }
1097
1098 cycles = idesc->timing->units[unit_num].done;
1099 request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles);
1100 return cycles;
1101}
1102
1103int
1104frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc,
1105 int unit_num, int referenced,
1106 INT in_GRi, INT in_GRj)
1107{
1108 int cycles;
1109
1110 if (model_insn == FRV_INSN_MODEL_PASS_1)
1111 {
1112 /* The entire VLIW insn must wait if there is a dependency on a register
1113 which is not ready yet.
1114 The latency of the registers may be less than previously recorded,
1115 depending on how they were used previously.
1116 See Table 13-8 in the LSI. */
1117 if (in_GRi >= 0)
1118 {
1119 if (use_is_gr_complex (cpu, in_GRi))
1120 decrease_GR_busy (cpu, in_GRi, 1);
1121 }
1122 if (in_GRj != in_GRi && in_GRj >= 0)
1123 {
1124 if (use_is_gr_complex (cpu, in_GRj))
1125 decrease_GR_busy (cpu, in_GRj, 1);
1126 }
1127 vliw_wait_for_GR (cpu, in_GRi);
1128 vliw_wait_for_GR (cpu, in_GRj);
1129 handle_resource_wait (cpu);
1130 load_wait_for_GR (cpu, in_GRi);
1131 load_wait_for_GR (cpu, in_GRj);
1132 trace_vliw_wait_cycles (cpu);
1133 return 0;
1134 }
1135
1136 cycles = idesc->timing->units[unit_num].done;
1137 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
1138 return cycles;
1139}
1140
1141int
1142frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
1143 int unit_num, int referenced,
1144 INT in_GRi, INT in_GRj)
1145{
1146 int cycles;
1147
1148 if (model_insn == FRV_INSN_MODEL_PASS_1)
1149 {
1150 /* The entire VLIW insn must wait if there is a dependency on a register
1151 which is not ready yet.
1152 The latency of the registers may be less than previously recorded,
1153 depending on how they were used previously.
1154 See Table 13-8 in the LSI. */
1155 if (in_GRi >= 0)
1156 {
1157 if (use_is_gr_complex (cpu, in_GRi))
1158 decrease_GR_busy (cpu, in_GRi, 1);
1159 }
1160 if (in_GRj != in_GRi && in_GRj >= 0)
1161 {
1162 if (use_is_gr_complex (cpu, in_GRj))
1163 decrease_GR_busy (cpu, in_GRj, 1);
1164 }
1165 vliw_wait_for_GR (cpu, in_GRi);
1166 vliw_wait_for_GR (cpu, in_GRj);
1167 handle_resource_wait (cpu);
1168 load_wait_for_GR (cpu, in_GRi);
1169 load_wait_for_GR (cpu, in_GRj);
1170 trace_vliw_wait_cycles (cpu);
1171 return 0;
1172 }
1173
1174 cycles = idesc->timing->units[unit_num].done;
1175 request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles);
1176 return cycles;
1177}
1178
1179int
1180frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
1181 int unit_num, int referenced,
1182 INT in_GRi, INT in_GRj)
1183{
1184 int cycles;
1185
1186 if (model_insn == FRV_INSN_MODEL_PASS_1)
1187 {
1188 /* The entire VLIW insn must wait if there is a dependency on a register
1189 which is not ready yet.
1190 The latency of the registers may be less than previously recorded,
1191 depending on how they were used previously.
1192 See Table 13-8 in the LSI. */
1193 if (in_GRi >= 0)
1194 {
1195 if (use_is_gr_complex (cpu, in_GRi))
1196 decrease_GR_busy (cpu, in_GRi, 1);
1197 }
1198 if (in_GRj != in_GRi && in_GRj >= 0)
1199 {
1200 if (use_is_gr_complex (cpu, in_GRj))
1201 decrease_GR_busy (cpu, in_GRj, 1);
1202 }
1203 vliw_wait_for_GR (cpu, in_GRi);
1204 vliw_wait_for_GR (cpu, in_GRj);
1205 handle_resource_wait (cpu);
1206 load_wait_for_GR (cpu, in_GRi);
1207 load_wait_for_GR (cpu, in_GRj);
1208 trace_vliw_wait_cycles (cpu);
1209 return 0;
1210 }
1211
1212 cycles = idesc->timing->units[unit_num].done;
1213 request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles);
1214 return cycles;
1215}
1216
1217int
1218frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
1219 int unit_num, int referenced,
1220 INT in_GRi, INT in_GRj)
1221{
1222 int cycles;
1223
1224 if (model_insn == FRV_INSN_MODEL_PASS_1)
1225 {
1226 /* The entire VLIW insn must wait if there is a dependency on a register
1227 which is not ready yet.
1228 The latency of the registers may be less than previously recorded,
1229 depending on how they were used previously.
1230 See Table 13-8 in the LSI. */
1231 if (in_GRi >= 0)
1232 {
1233 if (use_is_gr_complex (cpu, in_GRi))
1234 decrease_GR_busy (cpu, in_GRi, 1);
1235 }
1236 if (in_GRj != in_GRi && in_GRj >= 0)
1237 {
1238 if (use_is_gr_complex (cpu, in_GRj))
1239 decrease_GR_busy (cpu, in_GRj, 1);
1240 }
1241 vliw_wait_for_GR (cpu, in_GRi);
1242 vliw_wait_for_GR (cpu, in_GRj);
1243 handle_resource_wait (cpu);
1244 load_wait_for_GR (cpu, in_GRi);
1245 load_wait_for_GR (cpu, in_GRj);
1246 trace_vliw_wait_cycles (cpu);
1247 return 0;
1248 }
1249
1250 cycles = idesc->timing->units[unit_num].done;
1251 request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles);
1252 return cycles;
1253}
1254
1255int
1256frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc,
1257 int unit_num, int referenced,
1258 INT in_GRi, INT in_GRj)
1259{
1260 int cycles;
1261
1262 if (model_insn == FRV_INSN_MODEL_PASS_1)
1263 {
1264 /* The entire VLIW insn must wait if there is a dependency on a register
1265 which is not ready yet.
1266 The latency of the registers may be less than previously recorded,
1267 depending on how they were used previously.
1268 See Table 13-8 in the LSI. */
1269 if (in_GRi >= 0)
1270 {
1271 if (use_is_gr_complex (cpu, in_GRi))
1272 decrease_GR_busy (cpu, in_GRi, 1);
1273 }
1274 if (in_GRj != in_GRi && in_GRj >= 0)
1275 {
1276 if (use_is_gr_complex (cpu, in_GRj))
1277 decrease_GR_busy (cpu, in_GRj, 1);
1278 }
1279 vliw_wait_for_GR (cpu, in_GRi);
1280 vliw_wait_for_GR (cpu, in_GRj);
1281 handle_resource_wait (cpu);
1282 load_wait_for_GR (cpu, in_GRi);
1283 load_wait_for_GR (cpu, in_GRj);
1284 trace_vliw_wait_cycles (cpu);
1285 return 0;
1286 }
1287
1288 cycles = idesc->timing->units[unit_num].done;
1289 request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles);
1290 return cycles;
1291}
1292
1293int
1294frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
1295 int unit_num, int referenced,
1296 INT in_GRi, INT in_GRj)
1297{
1298 int cycles;
1299
1300 if (model_insn == FRV_INSN_MODEL_PASS_1)
1301 {
1302 /* The entire VLIW insn must wait if there is a dependency on a register
1303 which is not ready yet.
1304 The latency of the registers may be less than previously recorded,
1305 depending on how they were used previously.
1306 See Table 13-8 in the LSI. */
1307 if (in_GRi >= 0)
1308 {
1309 if (use_is_gr_complex (cpu, in_GRi))
1310 decrease_GR_busy (cpu, in_GRi, 1);
1311 }
1312 if (in_GRj != in_GRi && in_GRj >= 0)
1313 {
1314 if (use_is_gr_complex (cpu, in_GRj))
1315 decrease_GR_busy (cpu, in_GRj, 1);
1316 }
1317 vliw_wait_for_GR (cpu, in_GRi);
1318 vliw_wait_for_GR (cpu, in_GRj);
1319 handle_resource_wait (cpu);
1320 load_wait_for_GR (cpu, in_GRi);
1321 load_wait_for_GR (cpu, in_GRj);
1322 trace_vliw_wait_cycles (cpu);
1323 return 0;
1324 }
1325
1326 cycles = idesc->timing->units[unit_num].done;
1327 request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles);
1328 return cycles;
1329}
1330
1331/* Top up the post-processing time of the given FR by the given number of
1332 cycles. */
1333static void
1334update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
1335{
1336 if (out_FR >= 0)
1337 {
1338 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
1339 /* If a load is pending on this register, then add the cycles to
1340 the post processing time for this register. Otherwise apply it
1341 directly to the latency of the register. */
1342 if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
1343 {
1344 int *fr = ps->fr_latency;
1345 fr[out_FR] += cycles;
1346 }
1347 else
1348 ps->fr_ptime[out_FR] += cycles;
1349 }
1350}
1351
1352static void
1353update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
1354{
1355 if (out_FR >= 0)
1356 {
1357 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
1358 /* If a load is pending on this register, then add the cycles to
1359 the post processing time for this register. Otherwise apply it
1360 directly to the latency of the register. */
1361 if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
1362 {
1363 int *fr = ps->fr_latency;
1364 fr[out_FR] += cycles;
1365 if (out_FR < 63)
1366 fr[out_FR + 1] += cycles;
1367 }
1368 else
1369 {
1370 ps->fr_ptime[out_FR] += cycles;
1371 if (out_FR < 63)
1372 ps->fr_ptime[out_FR + 1] += cycles;
1373 }
1374 }
1375}
1376
1377int
1378frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc,
1379 int unit_num, int referenced,
1380 INT in_FRi, INT in_FRj,
1381 INT in_FRdoublei, INT in_FRdoublej,
1382 INT out_FRk, INT out_FRdoublek)
1383{
1384 int cycles;
1385 FRV_PROFILE_STATE *ps;
1386
1387 if (model_insn == FRV_INSN_MODEL_PASS_1)
1388 return 0;
1389
1390 /* The preprocessing can execute right away. */
1391 cycles = idesc->timing->units[unit_num].done;
1392
1393 /* The post processing must wait if there is a dependency on a FR
1394 which is not ready yet. */
1395 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1396 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1397 1);
1398 ps = CPU_PROFILE_STATE (cpu);
1399 ps->post_wait = cycles;
1400 post_wait_for_FR (cpu, in_FRi);
1401 post_wait_for_FR (cpu, in_FRj);
1402 post_wait_for_FR (cpu, out_FRk);
1403 post_wait_for_FRdouble (cpu, in_FRdoublei);
1404 post_wait_for_FRdouble (cpu, in_FRdoublej);
1405 post_wait_for_FRdouble (cpu, out_FRdoublek);
1406 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1407 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1408 1);
1409
1410 /* The latency of FRk will be at least the latency of the other inputs. */
1411 update_FR_latency (cpu, out_FRk, ps->post_wait);
1412 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1413
1414 /* Once initiated, post-processing will take 3 cycles. */
1415 update_FR_ptime (cpu, out_FRk, 3);
1416 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1417
1418 /* Mark this use of the register as a floating point op. */
1419 if (out_FRk >= 0)
1420 set_use_is_fpop (cpu, out_FRk);
1421 if (out_FRdoublek >= 0)
1422 {
1423 set_use_is_fpop (cpu, out_FRdoublek);
1424 if (out_FRdoublek < 63)
1425 set_use_is_fpop (cpu, out_FRdoublek + 1);
1426 }
1427
1428 return cycles;
1429}
1430
1431int
1432frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc,
1433 int unit_num, int referenced,
1434 INT in_FRi, INT in_FRj,
1435 INT in_FRdoublei, INT in_FRdoublej,
1436 INT out_FRk, INT out_FRdoublek)
1437{
1438 int cycles;
1439 INT dual_FRi;
1440 INT dual_FRj;
1441 INT dual_FRk;
1442 INT dual_FRdoublei;
1443 INT dual_FRdoublej;
1444 INT dual_FRdoublek;
1445 FRV_PROFILE_STATE *ps;
1446
1447 if (model_insn == FRV_INSN_MODEL_PASS_1)
1448 return 0;
1449
1450 /* The preprocessing can execute right away. */
1451 cycles = idesc->timing->units[unit_num].done;
1452
1453 /* The post processing must wait if there is a dependency on a FR
1454 which is not ready yet. */
1455 dual_FRi = DUAL_REG (in_FRi);
1456 dual_FRj = DUAL_REG (in_FRj);
1457 dual_FRk = DUAL_REG (out_FRk);
1458 dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei);
1459 dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej);
1460 dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek);
1461
1462 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1463 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
1464 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1465 1);
1466 adjust_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
1467 dual_FRdoublek, 1);
1468 ps = CPU_PROFILE_STATE (cpu);
1469 ps->post_wait = cycles;
1470 post_wait_for_FR (cpu, in_FRi);
1471 post_wait_for_FR (cpu, in_FRj);
1472 post_wait_for_FR (cpu, out_FRk);
1473 post_wait_for_FR (cpu, dual_FRi);
1474 post_wait_for_FR (cpu, dual_FRj);
1475 post_wait_for_FR (cpu, dual_FRk);
1476 post_wait_for_FRdouble (cpu, in_FRdoublei);
1477 post_wait_for_FRdouble (cpu, in_FRdoublej);
1478 post_wait_for_FRdouble (cpu, out_FRdoublek);
1479 post_wait_for_FRdouble (cpu, dual_FRdoublei);
1480 post_wait_for_FRdouble (cpu, dual_FRdoublej);
1481 post_wait_for_FRdouble (cpu, dual_FRdoublek);
1482 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1483 restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
1484 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1485 1);
1486 restore_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
1487 dual_FRdoublek, 1);
1488
1489 /* The latency of FRk will be at least the latency of the other inputs. */
1490 update_FR_latency (cpu, out_FRk, ps->post_wait);
1491 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1492 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1493 update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait);
1494
1495 /* Once initiated, post-processing will take 3 cycles. */
1496 update_FR_ptime (cpu, out_FRk, 3);
1497 update_FR_ptime (cpu, dual_FRk, 3);
1498 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1499 update_FRdouble_ptime (cpu, dual_FRdoublek, 3);
1500
1501 /* Mark this use of the register as a floating point op. */
1502 if (out_FRk >= 0)
1503 set_use_is_fpop (cpu, out_FRk);
1504 if (dual_FRk >= 0)
1505 set_use_is_fpop (cpu, dual_FRk);
1506 if (out_FRdoublek >= 0)
1507 {
1508 set_use_is_fpop (cpu, out_FRdoublek);
1509 if (out_FRdoublek < 63)
1510 set_use_is_fpop (cpu, out_FRdoublek + 1);
1511 }
1512 if (dual_FRdoublek >= 0)
1513 {
1514 set_use_is_fpop (cpu, dual_FRdoublek);
1515 if (dual_FRdoublek < 63)
1516 set_use_is_fpop (cpu, dual_FRdoublek + 1);
1517 }
1518
1519 return cycles;
1520}
1521
1522int
1523frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc,
1524 int unit_num, int referenced,
1525 INT in_FRi, INT in_FRj, INT out_FRk)
1526{
1527 int cycles;
1528 FRV_VLIW *vliw;
1529 int slot;
1530 FRV_PROFILE_STATE *ps;
1531
1532 if (model_insn == FRV_INSN_MODEL_PASS_1)
1533 return 0;
1534
1535 cycles = idesc->timing->units[unit_num].done;
1536
1537 /* The post processing must wait if there is a dependency on a FR
1538 which is not ready yet. */
1539 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1540 ps = CPU_PROFILE_STATE (cpu);
1541 ps->post_wait = cycles;
1542 post_wait_for_FR (cpu, in_FRi);
1543 post_wait_for_FR (cpu, in_FRj);
1544 post_wait_for_FR (cpu, out_FRk);
1545 vliw = CPU_VLIW (cpu);
1546 slot = vliw->next_slot - 1;
1547 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1548 post_wait_for_fdiv (cpu, slot);
1549 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1550
1551 /* The latency of FRk will be at least the latency of the other inputs. */
1552 /* Once initiated, post-processing will take 10 cycles. */
1553 update_FR_latency (cpu, out_FRk, ps->post_wait);
1554 update_FR_ptime (cpu, out_FRk, 10);
1555
1556 /* The latency of the fdiv unit will be at least the latency of the other
1557 inputs. Once initiated, post-processing will take 9 cycles. */
1558 update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9);
1559
1560 /* Mark this use of the register as a floating point op. */
1561 set_use_is_fpop (cpu, out_FRk);
1562
1563 return cycles;
1564}
1565
1566int
1567frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1568 int unit_num, int referenced,
1569 INT in_FRj, INT in_FRdoublej,
1570 INT out_FRk, INT out_FRdoublek)
1571{
1572 int cycles;
1573 FRV_VLIW *vliw;
1574 int slot;
1575 FRV_PROFILE_STATE *ps;
1576
1577 if (model_insn == FRV_INSN_MODEL_PASS_1)
1578 return 0;
1579
1580 cycles = idesc->timing->units[unit_num].done;
1581
1582 /* The post processing must wait if there is a dependency on a FR
1583 which is not ready yet. */
1584 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1585 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1586 ps = CPU_PROFILE_STATE (cpu);
1587 ps->post_wait = cycles;
1588 post_wait_for_FR (cpu, in_FRj);
1589 post_wait_for_FR (cpu, out_FRk);
1590 post_wait_for_FRdouble (cpu, in_FRdoublej);
1591 post_wait_for_FRdouble (cpu, out_FRdoublek);
1592 vliw = CPU_VLIW (cpu);
1593 slot = vliw->next_slot - 1;
1594 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1595 post_wait_for_fsqrt (cpu, slot);
1596 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1597 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1598
1599 /* The latency of FRk will be at least the latency of the other inputs. */
1600 update_FR_latency (cpu, out_FRk, ps->post_wait);
1601 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1602
1603 /* Once initiated, post-processing will take 15 cycles. */
1604 update_FR_ptime (cpu, out_FRk, 15);
1605 update_FRdouble_ptime (cpu, out_FRdoublek, 15);
1606
1607 /* The latency of the sqrt unit will be the latency of the other
1608 inputs plus 14 cycles. */
1609 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
1610
1611 /* Mark this use of the register as a floating point op. */
1612 if (out_FRk >= 0)
1613 set_use_is_fpop (cpu, out_FRk);
1614 if (out_FRdoublek >= 0)
1615 {
1616 set_use_is_fpop (cpu, out_FRdoublek);
1617 if (out_FRdoublek < 63)
1618 set_use_is_fpop (cpu, out_FRdoublek + 1);
1619 }
1620
1621 return cycles;
1622}
1623
1624int
1625frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1626 int unit_num, int referenced,
1627 INT in_FRj, INT out_FRk)
1628{
1629 int cycles;
1630 FRV_VLIW *vliw;
1631 int slot;
1632 INT dual_FRj;
1633 INT dual_FRk;
1634 FRV_PROFILE_STATE *ps;
1635
1636 if (model_insn == FRV_INSN_MODEL_PASS_1)
1637 return 0;
1638
1639 cycles = idesc->timing->units[unit_num].done;
1640
1641 /* The post processing must wait if there is a dependency on a FR
1642 which is not ready yet. */
1643 dual_FRj = DUAL_REG (in_FRj);
1644 dual_FRk = DUAL_REG (out_FRk);
1645 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1646 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1647 ps = CPU_PROFILE_STATE (cpu);
1648 ps->post_wait = cycles;
1649 post_wait_for_FR (cpu, in_FRj);
1650 post_wait_for_FR (cpu, out_FRk);
1651 post_wait_for_FR (cpu, dual_FRj);
1652 post_wait_for_FR (cpu, dual_FRk);
1653
1654 vliw = CPU_VLIW (cpu);
1655 slot = vliw->next_slot - 1;
1656 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1657 post_wait_for_fsqrt (cpu, slot);
1658 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1659 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1660
1661 /* The latency of FRk will be at least the latency of the other inputs. */
1662 update_FR_latency (cpu, out_FRk, ps->post_wait);
1663 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1664
1665 /* Once initiated, post-processing will take 15 cycles. */
1666 update_FR_ptime (cpu, out_FRk, 15);
1667 update_FR_ptime (cpu, dual_FRk, 15);
1668
1669 /* The latency of the sqrt unit will be at least the latency of the other
1670 inputs. */
1671 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
1672
1673 /* Mark this use of the register as a floating point op. */
1674 if (out_FRk >= 0)
1675 set_use_is_fpop (cpu, out_FRk);
1676 if (dual_FRk >= 0)
1677 set_use_is_fpop (cpu, dual_FRk);
1678
1679 return cycles;
1680}
1681
1682int
1683frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc,
1684 int unit_num, int referenced,
1685 INT in_FRi, INT in_FRj,
1686 INT in_FRdoublei, INT in_FRdoublej,
1687 INT out_FCCi_2)
1688{
1689 int cycles;
1690 FRV_PROFILE_STATE *ps;
1691
1692 if (model_insn == FRV_INSN_MODEL_PASS_1)
1693 return 0;
1694
1695 /* The preprocessing can execute right away. */
1696 cycles = idesc->timing->units[unit_num].done;
1697
1698 /* The post processing must wait if there is a dependency on a FR
1699 which is not ready yet. */
1700 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
1701 ps = CPU_PROFILE_STATE (cpu);
1702 ps->post_wait = cycles;
1703 post_wait_for_FR (cpu, in_FRi);
1704 post_wait_for_FR (cpu, in_FRj);
1705 post_wait_for_FRdouble (cpu, in_FRdoublei);
1706 post_wait_for_FRdouble (cpu, in_FRdoublej);
1707 post_wait_for_CCR (cpu, out_FCCi_2);
1708 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
1709
1710 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1711 cycles. */
1712 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
1713
1714 return cycles;
1715}
1716
1717int
1718frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc,
1719 int unit_num, int referenced,
1720 INT in_FRi, INT in_FRj,
1721 INT out_FCCi_2)
1722{
1723 int cycles;
1724 INT dual_FRi;
1725 INT dual_FRj;
1726 INT dual_FCCi_2;
1727 FRV_PROFILE_STATE *ps;
1728
1729 if (model_insn == FRV_INSN_MODEL_PASS_1)
1730 return 0;
1731
1732 /* The preprocessing can execute right away. */
1733 cycles = idesc->timing->units[unit_num].done;
1734
1735 /* The post processing must wait if there is a dependency on a FR
1736 which is not ready yet. */
1737 ps = CPU_PROFILE_STATE (cpu);
1738 ps->post_wait = cycles;
1739 dual_FRi = DUAL_REG (in_FRi);
1740 dual_FRj = DUAL_REG (in_FRj);
1741 dual_FCCi_2 = out_FCCi_2 + 1;
1742 adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
1743 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
1744 post_wait_for_FR (cpu, in_FRi);
1745 post_wait_for_FR (cpu, in_FRj);
1746 post_wait_for_FR (cpu, dual_FRi);
1747 post_wait_for_FR (cpu, dual_FRj);
1748 post_wait_for_CCR (cpu, out_FCCi_2);
1749 post_wait_for_CCR (cpu, dual_FCCi_2);
1750 restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
1751 restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
1752
1753 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1754 cycles. */
1755 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
1756 update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3);
1757
1758 return cycles;
1759}
1760
1761int
1762frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc,
1763 int unit_num, int referenced,
1764 INT in_FRj, INT in_FRintj, INT in_FRdoublej,
1765 INT out_FRk, INT out_FRintk,
1766 INT out_FRdoublek)
1767{
1768 int cycles;
1769 FRV_PROFILE_STATE *ps;
1770
1771 if (model_insn == FRV_INSN_MODEL_PASS_1)
1772 return 0;
1773
1774 /* The preprocessing can execute right away. */
1775 cycles = idesc->timing->units[unit_num].done;
1776
1777 /* The post processing must wait if there is a dependency on a FR
1778 which is not ready yet. */
1779 ps = CPU_PROFILE_STATE (cpu);
1780 ps->post_wait = cycles;
1781 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1782 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1783 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1784 post_wait_for_FR (cpu, in_FRj);
1785 post_wait_for_FR (cpu, in_FRintj);
1786 post_wait_for_FRdouble (cpu, in_FRdoublej);
1787 post_wait_for_FR (cpu, out_FRk);
1788 post_wait_for_FR (cpu, out_FRintk);
1789 post_wait_for_FRdouble (cpu, out_FRdoublek);
1790 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1791 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1792 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1793
1794 /* The latency of FRk will be at least the latency of the other inputs. */
1795 update_FR_latency (cpu, out_FRk, ps->post_wait);
1796 update_FR_latency (cpu, out_FRintk, ps->post_wait);
1797 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1798
1799 /* Once initiated, post-processing will take 3 cycles. */
1800 update_FR_ptime (cpu, out_FRk, 3);
1801 update_FR_ptime (cpu, out_FRintk, 3);
1802 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1803
1804 /* Mark this use of the register as a floating point op. */
1805 if (out_FRk >= 0)
1806 set_use_is_fpop (cpu, out_FRk);
1807 if (out_FRintk >= 0)
1808 set_use_is_fpop (cpu, out_FRintk);
1809 if (out_FRdoublek >= 0)
1810 {
1811 set_use_is_fpop (cpu, out_FRdoublek);
1812 set_use_is_fpop (cpu, out_FRdoublek + 1);
1813 }
1814
1815 return cycles;
1816}
1817
1818int
1819frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc,
1820 int unit_num, int referenced,
1821 INT in_FRj, INT in_FRintj,
1822 INT out_FRk, INT out_FRintk)
1823{
1824 int cycles;
1825 INT dual_FRj;
1826 INT dual_FRintj;
1827 INT dual_FRk;
1828 INT dual_FRintk;
1829 FRV_PROFILE_STATE *ps;
1830
1831 if (model_insn == FRV_INSN_MODEL_PASS_1)
1832 return 0;
1833
1834 /* The preprocessing can execute right away. */
1835 cycles = idesc->timing->units[unit_num].done;
1836
1837 /* The post processing must wait if there is a dependency on a FR
1838 which is not ready yet. */
1839 ps = CPU_PROFILE_STATE (cpu);
1840 ps->post_wait = cycles;
1841 dual_FRj = DUAL_REG (in_FRj);
1842 dual_FRintj = DUAL_REG (in_FRintj);
1843 dual_FRk = DUAL_REG (out_FRk);
1844 dual_FRintk = DUAL_REG (out_FRintk);
1845 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1846 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1847 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1848 adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
1849 post_wait_for_FR (cpu, in_FRj);
1850 post_wait_for_FR (cpu, in_FRintj);
1851 post_wait_for_FR (cpu, out_FRk);
1852 post_wait_for_FR (cpu, out_FRintk);
1853 post_wait_for_FR (cpu, dual_FRj);
1854 post_wait_for_FR (cpu, dual_FRintj);
1855 post_wait_for_FR (cpu, dual_FRk);
1856 post_wait_for_FR (cpu, dual_FRintk);
1857 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1858 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1859 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1860 restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
1861
1862 /* The latency of FRk will be at least the latency of the other inputs. */
1863 update_FR_latency (cpu, out_FRk, ps->post_wait);
1864 update_FR_latency (cpu, out_FRintk, ps->post_wait);
1865 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1866 update_FR_latency (cpu, dual_FRintk, ps->post_wait);
1867
1868 /* Once initiated, post-processing will take 3 cycles. */
1869 update_FR_ptime (cpu, out_FRk, 3);
1870 update_FR_ptime (cpu, out_FRintk, 3);
1871 update_FR_ptime (cpu, dual_FRk, 3);
1872 update_FR_ptime (cpu, dual_FRintk, 3);
1873
1874 /* Mark this use of the register as a floating point op. */
1875 if (out_FRk >= 0)
1876 set_use_is_fpop (cpu, out_FRk);
1877 if (out_FRintk >= 0)
1878 set_use_is_fpop (cpu, out_FRintk);
1879
1880 return cycles;
1881}
1882
1883int
1884frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
1885 int unit_num, int referenced,
1886 INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi,
1887 INT out_FRk,
1888 INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk)
1889{
1890 int cycles;
1891 FRV_PROFILE_STATE *ps;
1892 const CGEN_INSN *insn;
1893 int is_media_s1;
1894 int is_media_s2;
1895 int busy_adjustment[] = {0, 0, 0};
1896 int *fr;
1897 int *acc;
1898
1899 if (model_insn == FRV_INSN_MODEL_PASS_1)
1900 return 0;
1901
1902 /* The preprocessing can execute right away. */
1903 cycles = idesc->timing->units[unit_num].done;
1904
1905 ps = CPU_PROFILE_STATE (cpu);
1906 insn = idesc->idata;
1907
1908 /* If the previous use of the registers was a media op,
1909 then their latency will be less than previously recorded.
1910 See Table 13-13 in the LSI. */
1911 if (in_FRi >= 0)
1912 {
1913 if (use_is_media (cpu, in_FRi))
1914 {
1915 busy_adjustment[0] = 2;
1916 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
1917 }
1918 else
1919 enforce_full_fr_latency (cpu, in_FRi);
1920 }
1921 if (in_FRj >= 0 && in_FRj != in_FRi)
1922 {
1923 if (use_is_media (cpu, in_FRj))
1924 {
1925 busy_adjustment[1] = 2;
1926 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
1927 }
1928 else
1929 enforce_full_fr_latency (cpu, in_FRj);
1930 }
1931 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
1932 {
1933 if (use_is_media (cpu, out_FRk))
1934 {
1935 busy_adjustment[2] = 2;
1936 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
1937 }
1938 else
1939 enforce_full_fr_latency (cpu, out_FRk);
1940 }
1941
1942 /* The post processing must wait if there is a dependency on a FR
1943 which is not ready yet. */
1944 ps->post_wait = cycles;
1945 post_wait_for_FR (cpu, in_FRi);
1946 post_wait_for_FR (cpu, in_FRj);
1947 post_wait_for_FR (cpu, out_FRk);
1948 post_wait_for_ACC (cpu, in_ACC40Si);
1949 post_wait_for_ACC (cpu, in_ACCGi);
1950 post_wait_for_ACC (cpu, out_ACC40Sk);
1951 post_wait_for_ACC (cpu, out_ACC40Uk);
1952 post_wait_for_ACC (cpu, out_ACCGk);
1953
1954 /* Restore the busy cycles of the registers we used. */
1955 fr = ps->fr_busy;
1956 if (in_FRi >= 0)
1957 fr[in_FRi] += busy_adjustment[0];
1958 if (in_FRj >= 0)
1959 fr[in_FRj] += busy_adjustment[1];
1960 if (out_FRk >= 0)
1961 fr[out_FRk] += busy_adjustment[2];
1962
1963 /* The latency of tht output register will be at least the latency of the
1964 other inputs. Once initiated, post-processing will take 3 cycles. */
1965 if (out_FRk >= 0)
1966 {
1967 update_FR_latency (cpu, out_FRk, ps->post_wait);
1968 update_FR_ptime (cpu, out_FRk, 3);
1969 /* Mark this use of the register as a media op. */
1970 set_use_is_media (cpu, out_FRk);
1971 }
1972 /* The latency of tht output accumulator will be at least the latency of the
1973 other inputs. Once initiated, post-processing will take 1 cycle. */
1974 if (out_ACC40Sk >= 0)
1975 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
1976 if (out_ACC40Uk >= 0)
1977 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
1978 if (out_ACCGk >= 0)
1979 update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1);
1980
1981 return cycles;
1982}
1983
1984int
1985frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc,
1986 int unit_num, int referenced,
1987 INT in_FRi, INT in_FRj,
1988 INT out_FRk)
1989{
1990 int cycles;
1991 INT dual_FRi;
1992 INT dual_FRj;
1993 INT dual_FRk;
1994 FRV_PROFILE_STATE *ps;
1995 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
1996 int *fr;
1997
1998 if (model_insn == FRV_INSN_MODEL_PASS_1)
1999 return 0;
2000
2001 /* The preprocessing can execute right away. */
2002 cycles = idesc->timing->units[unit_num].done;
2003
2004 ps = CPU_PROFILE_STATE (cpu);
2005 dual_FRi = DUAL_REG (in_FRi);
2006 dual_FRj = DUAL_REG (in_FRj);
2007 dual_FRk = DUAL_REG (out_FRk);
2008
2009 /* If the previous use of the registers was a media op,
2010 then their latency will be less than previously recorded.
2011 See Table 13-13 in the LSI. */
2012 if (use_is_media (cpu, in_FRi))
2013 {
2014 busy_adjustment[0] = 2;
2015 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2016 }
2017 else
2018 enforce_full_fr_latency (cpu, in_FRi);
2019 if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi))
2020 {
2021 busy_adjustment[1] = 2;
2022 decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
2023 }
2024 else
2025 enforce_full_fr_latency (cpu, dual_FRi);
2026 if (in_FRj != in_FRi)
2027 {
2028 if (use_is_media (cpu, in_FRj))
2029 {
2030 busy_adjustment[2] = 2;
2031 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2032 }
2033 else
2034 enforce_full_fr_latency (cpu, in_FRj);
2035 if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj))
2036 {
2037 busy_adjustment[3] = 2;
2038 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]);
2039 }
2040 else
2041 enforce_full_fr_latency (cpu, dual_FRj + 1);
2042 }
2043 if (out_FRk != in_FRi && out_FRk != in_FRj)
2044 {
2045 if (use_is_media (cpu, out_FRk))
2046 {
2047 busy_adjustment[4] = 2;
2048 decrease_FR_busy (cpu, out_FRk, busy_adjustment[4]);
2049 }
2050 else
2051 enforce_full_fr_latency (cpu, out_FRk);
2052 if (dual_FRk >= 0 && use_is_media (cpu, dual_FRk))
2053 {
2054 busy_adjustment[5] = 2;
2055 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[5]);
2056 }
2057 else
2058 enforce_full_fr_latency (cpu, dual_FRk);
2059 }
2060
2061 /* The post processing must wait if there is a dependency on a FR
2062 which is not ready yet. */
2063 ps->post_wait = cycles;
2064 post_wait_for_FR (cpu, in_FRi);
2065 post_wait_for_FR (cpu, dual_FRi);
2066 post_wait_for_FR (cpu, in_FRj);
2067 post_wait_for_FR (cpu, dual_FRj);
2068 post_wait_for_FR (cpu, out_FRk);
2069 post_wait_for_FR (cpu, dual_FRk);
2070
2071 /* Restore the busy cycles of the registers we used. */
2072 fr = ps->fr_busy;
2073 fr[in_FRi] += busy_adjustment[0];
2074 if (dual_FRi >= 0)
2075 fr[dual_FRi] += busy_adjustment[1];
2076 fr[in_FRj] += busy_adjustment[2];
2077 if (dual_FRj >= 0)
2078 fr[dual_FRj] += busy_adjustment[3];
2079 fr[out_FRk] += busy_adjustment[4];
2080 if (dual_FRk >= 0)
2081 fr[dual_FRk] += busy_adjustment[5];
2082
2083 /* The latency of tht output register will be at least the latency of the
2084 other inputs. */
2085 update_FR_latency (cpu, out_FRk, ps->post_wait);
2086
2087 /* Once initiated, post-processing will take 3 cycles. */
2088 update_FR_ptime (cpu, out_FRk, 3);
2089
2090 /* Mark this use of the register as a media op. */
2091 set_use_is_media (cpu, out_FRk);
2092 if (dual_FRk >= 0)
2093 {
2094 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2095 update_FR_ptime (cpu, dual_FRk, 3);
2096 /* Mark this use of the register as a media op. */
2097 set_use_is_media (cpu, dual_FRk);
2098 }
2099
2100 return cycles;
2101}
2102
2103int
2104frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc,
2105 int unit_num, int referenced,
2106 INT in_FRi, INT in_FRj,
2107 INT out_ACC40Sk, INT out_ACC40Uk)
2108{
2109 int cycles;
2110 INT dual_ACC40Sk;
2111 INT dual_ACC40Uk;
2112 FRV_PROFILE_STATE *ps;
2113 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2114 int *fr;
2115 int *acc;
2116
2117 if (model_insn == FRV_INSN_MODEL_PASS_1)
2118 return 0;
2119
2120 /* The preprocessing can execute right away. */
2121 cycles = idesc->timing->units[unit_num].done;
2122
2123 ps = CPU_PROFILE_STATE (cpu);
2124 dual_ACC40Sk = DUAL_REG (out_ACC40Sk);
2125 dual_ACC40Uk = DUAL_REG (out_ACC40Uk);
2126
2127 /* If the previous use of the registers was a media op,
2128 then their latency will be less than previously recorded.
2129 See Table 13-13 in the LSI. */
2130 if (use_is_media (cpu, in_FRi))
2131 {
2132 busy_adjustment[0] = 2;
2133 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2134 }
2135 else
2136 enforce_full_fr_latency (cpu, in_FRi);
2137 if (in_FRj != in_FRi)
2138 {
2139 if (use_is_media (cpu, in_FRj))
2140 {
2141 busy_adjustment[1] = 2;
2142 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
2143 }
2144 else
2145 enforce_full_fr_latency (cpu, in_FRj);
2146 }
2147 if (out_ACC40Sk >= 0)
2148 {
2149 busy_adjustment[2] = 1;
2150 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
2151 }
2152 if (dual_ACC40Sk >= 0)
2153 {
2154 busy_adjustment[3] = 1;
2155 decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]);
2156 }
2157 if (out_ACC40Uk >= 0)
2158 {
2159 busy_adjustment[4] = 1;
2160 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
2161 }
2162 if (dual_ACC40Uk >= 0)
2163 {
2164 busy_adjustment[5] = 1;
2165 decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]);
2166 }
2167
2168 /* The post processing must wait if there is a dependency on a FR
2169 which is not ready yet. */
2170 ps->post_wait = cycles;
2171 post_wait_for_FR (cpu, in_FRi);
2172 post_wait_for_FR (cpu, in_FRj);
2173 post_wait_for_ACC (cpu, out_ACC40Sk);
2174 post_wait_for_ACC (cpu, dual_ACC40Sk);
2175 post_wait_for_ACC (cpu, out_ACC40Uk);
2176 post_wait_for_ACC (cpu, dual_ACC40Uk);
2177
2178 /* Restore the busy cycles of the registers we used. */
2179 fr = ps->fr_busy;
2180 acc = ps->acc_busy;
2181 fr[in_FRi] += busy_adjustment[0];
2182 fr[in_FRj] += busy_adjustment[1];
2183 if (out_ACC40Sk >= 0)
2184 acc[out_ACC40Sk] += busy_adjustment[2];
2185 if (dual_ACC40Sk >= 0)
2186 acc[dual_ACC40Sk] += busy_adjustment[3];
2187 if (out_ACC40Uk >= 0)
2188 acc[out_ACC40Uk] += busy_adjustment[4];
2189 if (dual_ACC40Uk >= 0)
2190 acc[dual_ACC40Uk] += busy_adjustment[5];
2191
2192 /* The latency of tht output register will be at least the latency of the
2193 other inputs. Once initiated, post-processing will take 1 cycle. */
2194 if (out_ACC40Sk >= 0)
2195 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2196 if (dual_ACC40Sk >= 0)
2197 update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1);
2198 if (out_ACC40Uk >= 0)
2199 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2200 if (dual_ACC40Uk >= 0)
2201 update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1);
2202
2203 return cycles;
2204}
2205
2206int
2207frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc,
2208 int unit_num, int referenced,
2209 INT in_FRi, INT in_FRj,
2210 INT out_ACC40Sk, INT out_ACC40Uk)
2211{
2212 int cycles;
2213 INT FRi_1;
2214 INT FRj_1;
2215 INT ACC40Sk_1;
2216 INT ACC40Sk_2;
2217 INT ACC40Sk_3;
2218 INT ACC40Uk_1;
2219 INT ACC40Uk_2;
2220 INT ACC40Uk_3;
2221 FRV_PROFILE_STATE *ps;
2222 int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0};
2223 int *fr;
2224 int *acc;
2225
2226 if (model_insn == FRV_INSN_MODEL_PASS_1)
2227 return 0;
2228
2229 /* The preprocessing can execute right away. */
2230 cycles = idesc->timing->units[unit_num].done;
2231
2232 FRi_1 = DUAL_REG (in_FRi);
2233 FRj_1 = DUAL_REG (in_FRj);
2234 ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
2235 ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
2236 ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
2237 ACC40Uk_1 = DUAL_REG (out_ACC40Uk);
2238 ACC40Uk_2 = DUAL_REG (ACC40Uk_1);
2239 ACC40Uk_3 = DUAL_REG (ACC40Uk_2);
2240
2241 /* If the previous use of the registers was a media op,
2242 then their latency will be less than previously recorded.
2243 See Table 13-13 in the LSI. */
2244 ps = CPU_PROFILE_STATE (cpu);
2245 if (use_is_media (cpu, in_FRi))
2246 {
2247 busy_adjustment[0] = 2;
2248 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2249 }
2250 else
2251 enforce_full_fr_latency (cpu, in_FRi);
2252 if (FRi_1 >= 0)
2253 {
2254 if (use_is_media (cpu, FRi_1))
2255 {
2256 busy_adjustment[1] = 2;
2257 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2258 }
2259 else
2260 enforce_full_fr_latency (cpu, FRi_1);
2261 }
2262 if (in_FRj != in_FRi)
2263 {
2264 if (use_is_media (cpu, in_FRj))
2265 {
2266 busy_adjustment[2] = 2;
2267 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2268 }
2269 else
2270 enforce_full_fr_latency (cpu, in_FRj);
2271 if (FRj_1 >= 0)
2272 {
2273 if (use_is_media (cpu, FRj_1))
2274 {
2275 busy_adjustment[3] = 2;
2276 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
2277 }
2278 else
2279 enforce_full_fr_latency (cpu, FRj_1);
2280 }
2281 }
2282 if (out_ACC40Sk >= 0)
2283 {
2284 busy_adjustment[4] = 1;
2285 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
2286
2287 if (ACC40Sk_1 >= 0)
2288 {
2289 busy_adjustment[5] = 1;
2290 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
2291 }
2292 if (ACC40Sk_2 >= 0)
2293 {
2294 busy_adjustment[6] = 1;
2295 decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]);
2296 }
2297 if (ACC40Sk_3 >= 0)
2298 {
2299 busy_adjustment[7] = 1;
2300 decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]);
2301 }
2302 }
2303 else if (out_ACC40Uk >= 0)
2304 {
2305 busy_adjustment[4] = 1;
2306 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
2307
2308 if (ACC40Uk_1 >= 0)
2309 {
2310 busy_adjustment[5] = 1;
2311 decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]);
2312 }
2313 if (ACC40Uk_2 >= 0)
2314 {
2315 busy_adjustment[6] = 1;
2316 decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]);
2317 }
2318 if (ACC40Uk_3 >= 0)
2319 {
2320 busy_adjustment[7] = 1;
2321 decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]);
2322 }
2323 }
2324
2325 /* The post processing must wait if there is a dependency on a FR
2326 which is not ready yet. */
2327 ps->post_wait = cycles;
2328 post_wait_for_FR (cpu, in_FRi);
2329 post_wait_for_FR (cpu, FRi_1);
2330 post_wait_for_FR (cpu, in_FRj);
2331 post_wait_for_FR (cpu, FRj_1);
2332 post_wait_for_ACC (cpu, out_ACC40Sk);
2333 post_wait_for_ACC (cpu, ACC40Sk_1);
2334 post_wait_for_ACC (cpu, ACC40Sk_2);
2335 post_wait_for_ACC (cpu, ACC40Sk_3);
2336 post_wait_for_ACC (cpu, out_ACC40Uk);
2337 post_wait_for_ACC (cpu, ACC40Uk_1);
2338 post_wait_for_ACC (cpu, ACC40Uk_2);
2339 post_wait_for_ACC (cpu, ACC40Uk_3);
2340
2341 /* Restore the busy cycles of the registers we used. */
2342 fr = ps->fr_busy;
2343 acc = ps->acc_busy;
2344 fr[in_FRi] += busy_adjustment[0];
2345 if (FRi_1 >= 0)
2346 fr[FRi_1] += busy_adjustment[1];
2347 fr[in_FRj] += busy_adjustment[2];
2348 if (FRj_1 > 0)
2349 fr[FRj_1] += busy_adjustment[3];
2350 if (out_ACC40Sk >= 0)
2351 {
2352 acc[out_ACC40Sk] += busy_adjustment[4];
2353 if (ACC40Sk_1 >= 0)
2354 acc[ACC40Sk_1] += busy_adjustment[5];
2355 if (ACC40Sk_2 >= 0)
2356 acc[ACC40Sk_2] += busy_adjustment[6];
2357 if (ACC40Sk_3 >= 0)
2358 acc[ACC40Sk_3] += busy_adjustment[7];
2359 }
2360 else if (out_ACC40Uk >= 0)
2361 {
2362 acc[out_ACC40Uk] += busy_adjustment[4];
2363 if (ACC40Uk_1 >= 0)
2364 acc[ACC40Uk_1] += busy_adjustment[5];
2365 if (ACC40Uk_2 >= 0)
2366 acc[ACC40Uk_2] += busy_adjustment[6];
2367 if (ACC40Uk_3 >= 0)
2368 acc[ACC40Uk_3] += busy_adjustment[7];
2369 }
2370
2371 /* The latency of tht output register will be at least the latency of the
2372 other inputs. Once initiated, post-processing will take 1 cycle. */
2373 if (out_ACC40Sk >= 0)
2374 {
2375 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2376 if (ACC40Sk_1 >= 0)
2377 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
2378 if (ACC40Sk_2 >= 0)
2379 update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
2380 if (ACC40Sk_3 >= 0)
2381 update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
2382 }
2383 else if (out_ACC40Uk >= 0)
2384 {
2385 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2386 if (ACC40Uk_1 >= 0)
2387 update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1);
2388 if (ACC40Uk_2 >= 0)
2389 update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1);
2390 if (ACC40Uk_3 >= 0)
2391 update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1);
2392 }
2393
2394 return cycles;
2395}
2396
2397int
2398frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc,
2399 int unit_num, int referenced,
2400 INT in_FRi, INT in_FRj,
2401 INT out_ACC40Sk)
2402{
2403 int cycles;
2404 INT FRi_1;
2405 INT FRj_1;
2406 INT ACC40Sk_1;
2407 FRV_PROFILE_STATE *ps;
2408 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2409 int *fr;
2410 int *acc;
2411
2412 if (model_insn == FRV_INSN_MODEL_PASS_1)
2413 return 0;
2414
2415 /* The preprocessing can execute right away. */
2416 cycles = idesc->timing->units[unit_num].done;
2417
2418 FRi_1 = DUAL_REG (in_FRi);
2419 FRj_1 = DUAL_REG (in_FRj);
2420 ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
2421
2422 /* If the previous use of the registers was a media op,
2423 then their latency will be less than previously recorded.
2424 See Table 13-13 in the LSI. */
2425 ps = CPU_PROFILE_STATE (cpu);
2426 if (use_is_media (cpu, in_FRi))
2427 {
2428 busy_adjustment[0] = 2;
2429 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2430 }
2431 else
2432 enforce_full_fr_latency (cpu, in_FRi);
2433 if (FRi_1 >= 0)
2434 {
2435 if (use_is_media (cpu, FRi_1))
2436 {
2437 busy_adjustment[1] = 2;
2438 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2439 }
2440 else
2441 enforce_full_fr_latency (cpu, FRi_1);
2442 }
2443 if (in_FRj != in_FRi)
2444 {
2445 if (use_is_media (cpu, in_FRj))
2446 {
2447 busy_adjustment[2] = 2;
2448 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2449 }
2450 else
2451 enforce_full_fr_latency (cpu, in_FRj);
2452 if (FRj_1 >= 0)
2453 {
2454 if (use_is_media (cpu, FRj_1))
2455 {
2456 busy_adjustment[3] = 2;
2457 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
2458 }
2459 else
2460 enforce_full_fr_latency (cpu, FRj_1);
2461 }
2462 }
2463 if (out_ACC40Sk >= 0)
2464 {
2465 busy_adjustment[4] = 1;
2466 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
2467
2468 if (ACC40Sk_1 >= 0)
2469 {
2470 busy_adjustment[5] = 1;
2471 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
2472 }
2473 }
2474
2475 /* The post processing must wait if there is a dependency on a FR
2476 which is not ready yet. */
2477 ps->post_wait = cycles;
2478 post_wait_for_FR (cpu, in_FRi);
2479 post_wait_for_FR (cpu, FRi_1);
2480 post_wait_for_FR (cpu, in_FRj);
2481 post_wait_for_FR (cpu, FRj_1);
2482 post_wait_for_ACC (cpu, out_ACC40Sk);
2483 post_wait_for_ACC (cpu, ACC40Sk_1);
2484
2485 /* Restore the busy cycles of the registers we used. */
2486 fr = ps->fr_busy;
2487 acc = ps->acc_busy;
2488 fr[in_FRi] += busy_adjustment[0];
2489 if (FRi_1 >= 0)
2490 fr[FRi_1] += busy_adjustment[1];
2491 fr[in_FRj] += busy_adjustment[2];
2492 if (FRj_1 > 0)
2493 fr[FRj_1] += busy_adjustment[3];
2494 if (out_ACC40Sk >= 0)
2495 {
2496 acc[out_ACC40Sk] += busy_adjustment[4];
2497 if (ACC40Sk_1 >= 0)
2498 acc[ACC40Sk_1] += busy_adjustment[5];
2499 }
2500
2501 /* The latency of tht output register will be at least the latency of the
2502 other inputs. Once initiated, post-processing will take 1 cycle. */
2503 if (out_ACC40Sk >= 0)
2504 {
2505 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2506 if (ACC40Sk_1 >= 0)
2507 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
2508 }
2509
2510 return cycles;
2511}
2512
2513int
2514frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
2515 int unit_num, int referenced,
2516 INT in_FRi,
2517 INT out_FRk)
2518{
2519 int cycles;
2520 INT dual_FRk;
2521 FRV_PROFILE_STATE *ps;
2522 int busy_adjustment[] = {0, 0, 0};
2523 int *fr;
2524
2525 if (model_insn == FRV_INSN_MODEL_PASS_1)
2526 return 0;
2527
2528 /* The preprocessing can execute right away. */
2529 cycles = idesc->timing->units[unit_num].done;
2530
2531 /* If the previous use of the registers was a media op,
2532 then their latency will be less than previously recorded.
2533 See Table 13-13 in the LSI. */
2534 dual_FRk = DUAL_REG (out_FRk);
2535 ps = CPU_PROFILE_STATE (cpu);
2536 if (use_is_media (cpu, in_FRi))
2537 {
2538 busy_adjustment[0] = 2;
2539 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2540 }
2541 else
2542 enforce_full_fr_latency (cpu, in_FRi);
2543 if (out_FRk != in_FRi)
2544 {
2545 if (use_is_media (cpu, out_FRk))
2546 {
2547 busy_adjustment[1] = 2;
2548 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
2549 }
2550 else
2551 enforce_full_fr_latency (cpu, out_FRk);
2552 }
2553 if (dual_FRk >= 0 && dual_FRk != in_FRi)
2554 {
2555 if (use_is_media (cpu, dual_FRk))
2556 {
2557 busy_adjustment[2] = 2;
2558 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[2]);
2559 }
2560 else
2561 enforce_full_fr_latency (cpu, dual_FRk);
2562 }
2563
2564 /* The post processing must wait if there is a dependency on a FR
2565 which is not ready yet. */
2566 ps->post_wait = cycles;
2567 post_wait_for_FR (cpu, in_FRi);
2568 post_wait_for_FR (cpu, out_FRk);
2569 post_wait_for_FR (cpu, dual_FRk);
2570
2571 /* Restore the busy cycles of the registers we used. */
2572 fr = ps->fr_busy;
2573 fr[in_FRi] += busy_adjustment[0];
2574 fr[out_FRk] += busy_adjustment[1];
2575 if (dual_FRk >= 0)
2576 fr[dual_FRk] += busy_adjustment[2];
2577
2578 /* The latency of tht output register will be at least the latency of the
2579 other inputs. Once initiated, post-processing will take 3 cycles. */
2580 update_FR_latency (cpu, out_FRk, ps->post_wait);
2581 update_FR_ptime (cpu, out_FRk, 3);
2582
2583 /* Mark this use of the register as a media op. */
2584 set_use_is_media (cpu, out_FRk);
2585 if (dual_FRk >= 0)
2586 {
2587 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2588 update_FR_ptime (cpu, dual_FRk, 3);
2589
2590 /* Mark this use of the register as a media op. */
2591 set_use_is_media (cpu, dual_FRk);
2592 }
2593
2594 return cycles;
2595}
2596
2597int
2598frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc,
2599 int unit_num, int referenced,
2600 INT in_FRi,
2601 INT out_FRk)
2602{
2603 int cycles;
2604 INT FRi_1;
2605 INT FRk_1;
2606 INT FRk_2;
2607 INT FRk_3;
2608 FRV_PROFILE_STATE *ps;
2609 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2610 int *fr;
2611
2612 if (model_insn == FRV_INSN_MODEL_PASS_1)
2613 return 0;
2614
2615 /* The preprocessing can execute right away. */
2616 cycles = idesc->timing->units[unit_num].done;
2617
2618 FRi_1 = DUAL_REG (in_FRi);
2619 FRk_1 = DUAL_REG (out_FRk);
2620 FRk_2 = DUAL_REG (FRk_1);
2621 FRk_3 = DUAL_REG (FRk_2);
2622
2623 /* If the previous use of the registers was a media op,
2624 then their latency will be less than previously recorded.
2625 See Table 13-13 in the LSI. */
2626 ps = CPU_PROFILE_STATE (cpu);
2627 if (use_is_media (cpu, in_FRi))
2628 {
2629 busy_adjustment[0] = 2;
2630 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2631 }
2632 else
2633 enforce_full_fr_latency (cpu, in_FRi);
2634 if (FRi_1 >= 0 && use_is_media (cpu, FRi_1))
2635 {
2636 busy_adjustment[1] = 2;
2637 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2638 }
2639 else
2640 enforce_full_fr_latency (cpu, FRi_1);
2641 if (out_FRk != in_FRi)
2642 {
2643 if (use_is_media (cpu, out_FRk))
2644 {
2645 busy_adjustment[2] = 2;
2646 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2647 }
2648 else
2649 enforce_full_fr_latency (cpu, out_FRk);
2650 if (FRk_1 >= 0 && FRk_1 != in_FRi)
2651 {
2652 if (use_is_media (cpu, FRk_1))
2653 {
2654 busy_adjustment[3] = 2;
2655 decrease_FR_busy (cpu, FRk_1, busy_adjustment[3]);
2656 }
2657 else
2658 enforce_full_fr_latency (cpu, FRk_1);
2659 }
2660 if (FRk_2 >= 0 && FRk_2 != in_FRi)
2661 {
2662 if (use_is_media (cpu, FRk_2))
2663 {
2664 busy_adjustment[4] = 2;
2665 decrease_FR_busy (cpu, FRk_2, busy_adjustment[4]);
2666 }
2667 else
2668 enforce_full_fr_latency (cpu, FRk_2);
2669 }
2670 if (FRk_3 >= 0 && FRk_3 != in_FRi)
2671 {
2672 if (use_is_media (cpu, FRk_3))
2673 {
2674 busy_adjustment[5] = 2;
2675 decrease_FR_busy (cpu, FRk_3, busy_adjustment[5]);
2676 }
2677 else
2678 enforce_full_fr_latency (cpu, FRk_3);
2679 }
2680 }
2681
2682 /* The post processing must wait if there is a dependency on a FR
2683 which is not ready yet. */
2684 ps->post_wait = cycles;
2685 post_wait_for_FR (cpu, in_FRi);
2686 post_wait_for_FR (cpu, FRi_1);
2687 post_wait_for_FR (cpu, out_FRk);
2688 post_wait_for_FR (cpu, FRk_1);
2689 post_wait_for_FR (cpu, FRk_2);
2690 post_wait_for_FR (cpu, FRk_3);
2691
2692 /* Restore the busy cycles of the registers we used. */
2693 fr = ps->fr_busy;
2694 fr[in_FRi] += busy_adjustment[0];
2695 if (FRi_1 >= 0)
2696 fr[FRi_1] += busy_adjustment[1];
2697 fr[out_FRk] += busy_adjustment[2];
2698 if (FRk_1 >= 0)
2699 fr[FRk_1] += busy_adjustment[3];
2700 if (FRk_2 >= 0)
2701 fr[FRk_2] += busy_adjustment[4];
2702 if (FRk_3 >= 0)
2703 fr[FRk_3] += busy_adjustment[5];
2704
2705 /* The latency of tht output register will be at least the latency of the
2706 other inputs. Once initiated, post-processing will take 3 cycles. */
2707 update_FR_latency (cpu, out_FRk, ps->post_wait);
2708 update_FR_ptime (cpu, out_FRk, 3);
2709
2710 /* Mark this use of the register as a media op. */
2711 set_use_is_media (cpu, out_FRk);
2712 if (FRk_1 >= 0)
2713 {
2714 update_FR_latency (cpu, FRk_1, ps->post_wait);
2715 update_FR_ptime (cpu, FRk_1, 3);
2716
2717 /* Mark this use of the register as a media op. */
2718 set_use_is_media (cpu, FRk_1);
2719 }
2720 if (FRk_2 >= 0)
2721 {
2722 update_FR_latency (cpu, FRk_2, ps->post_wait);
2723 update_FR_ptime (cpu, FRk_2, 3);
2724
2725 /* Mark this use of the register as a media op. */
2726 set_use_is_media (cpu, FRk_2);
2727 }
2728 if (FRk_3 >= 0)
2729 {
2730 update_FR_latency (cpu, FRk_3, ps->post_wait);
2731 update_FR_ptime (cpu, FRk_3, 3);
2732
2733 /* Mark this use of the register as a media op. */
2734 set_use_is_media (cpu, FRk_3);
2735 }
2736
2737 return cycles;
2738}
2739
2740int
2741frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc,
2742 int unit_num, int referenced,
2743 INT in_FRj,
2744 INT out_FRk)
2745{
2746 return frvbf_model_fr500_u_media_dual_expand (cpu, idesc, unit_num,
2747 referenced, in_FRj, out_FRk);
2748}
2749
2750int
2751frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
2752 int unit_num, int referenced,
2753 INT in_FRj,
2754 INT out_FRk)
2755{
2756 int cycles;
2757 INT dual_FRj;
2758 FRV_PROFILE_STATE *ps;
2759 int busy_adjustment[] = {0, 0, 0};
2760 int *fr;
2761
2762 if (model_insn == FRV_INSN_MODEL_PASS_1)
2763 return 0;
2764
2765 /* The preprocessing can execute right away. */
2766 cycles = idesc->timing->units[unit_num].done;
2767
2768 /* If the previous use of the registers was a media op,
2769 then their latency will be less than previously recorded.
2770 See Table 13-13 in the LSI. */
2771 dual_FRj = DUAL_REG (in_FRj);
2772 ps = CPU_PROFILE_STATE (cpu);
2773 if (use_is_media (cpu, in_FRj))
2774 {
2775 busy_adjustment[0] = 2;
2776 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
2777 }
2778 else
2779 enforce_full_fr_latency (cpu, in_FRj);
2780 if (dual_FRj >= 0)
2781 {
2782 if (use_is_media (cpu, dual_FRj))
2783 {
2784 busy_adjustment[1] = 2;
2785 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]);
2786 }
2787 else
2788 enforce_full_fr_latency (cpu, dual_FRj);
2789 }
2790 if (out_FRk != in_FRj)
2791 {
2792 if (use_is_media (cpu, out_FRk))
2793 {
2794 busy_adjustment[2] = 2;
2795 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2796 }
2797 else
2798 enforce_full_fr_latency (cpu, out_FRk);
2799 }
2800
2801 /* The post processing must wait if there is a dependency on a FR
2802 which is not ready yet. */
2803 ps->post_wait = cycles;
2804 post_wait_for_FR (cpu, in_FRj);
2805 post_wait_for_FR (cpu, dual_FRj);
2806 post_wait_for_FR (cpu, out_FRk);
2807
2808 /* Restore the busy cycles of the registers we used. */
2809 fr = ps->fr_busy;
2810 fr[in_FRj] += busy_adjustment[0];
2811 if (dual_FRj >= 0)
2812 fr[dual_FRj] += busy_adjustment[1];
2813 fr[out_FRk] += busy_adjustment[2];
2814
2815 /* The latency of tht output register will be at least the latency of the
2816 other inputs. */
2817 update_FR_latency (cpu, out_FRk, ps->post_wait);
2818
2819 /* Once initiated, post-processing will take 3 cycles. */
2820 update_FR_ptime (cpu, out_FRk, 3);
2821
2822 /* Mark this use of the register as a media op. */
2823 set_use_is_media (cpu, out_FRk);
2824
2825 return cycles;
2826}
2827
2828int
2829frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc,
2830 int unit_num, int referenced,
2831 INT in_FRj,
2832 INT out_FRk)
2833{
2834 int cycles;
2835 INT FRk_1;
2836 INT FRk_2;
2837 INT FRk_3;
2838 FRV_PROFILE_STATE *ps;
2839 int busy_adjustment[] = {0, 0, 0, 0, 0};
2840 int *fr;
2841
2842 if (model_insn == FRV_INSN_MODEL_PASS_1)
2843 return 0;
2844
2845 /* The preprocessing can execute right away. */
2846 cycles = idesc->timing->units[unit_num].done;
2847
2848 FRk_1 = DUAL_REG (out_FRk);
2849 FRk_2 = DUAL_REG (FRk_1);
2850 FRk_3 = DUAL_REG (FRk_2);
2851
2852 /* If the previous use of the registers was a media op,
2853 then their latency will be less than previously recorded.
2854 See Table 13-13 in the LSI. */
2855 ps = CPU_PROFILE_STATE (cpu);
2856 if (use_is_media (cpu, in_FRj))
2857 {
2858 busy_adjustment[0] = 2;
2859 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
2860 }
2861 else
2862 enforce_full_fr_latency (cpu, in_FRj);
2863 if (out_FRk != in_FRj)
2864 {
2865 if (use_is_media (cpu, out_FRk))
2866 {
2867 busy_adjustment[1] = 2;
2868 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
2869 }
2870 else
2871 enforce_full_fr_latency (cpu, out_FRk);
2872 if (FRk_1 >= 0 && FRk_1 != in_FRj)
2873 {
2874 if (use_is_media (cpu, FRk_1))
2875 {
2876 busy_adjustment[2] = 2;
2877 decrease_FR_busy (cpu, FRk_1, busy_adjustment[2]);
2878 }
2879 else
2880 enforce_full_fr_latency (cpu, FRk_1);
2881 }
2882 if (FRk_2 >= 0 && FRk_2 != in_FRj)
2883 {
2884 if (use_is_media (cpu, FRk_2))
2885 {
2886 busy_adjustment[3] = 2;
2887 decrease_FR_busy (cpu, FRk_2, busy_adjustment[3]);
2888 }
2889 else
2890 enforce_full_fr_latency (cpu, FRk_2);
2891 }
2892 if (FRk_3 >= 0 && FRk_3 != in_FRj)
2893 {
2894 if (use_is_media (cpu, FRk_3))
2895 {
2896 busy_adjustment[4] = 2;
2897 decrease_FR_busy (cpu, FRk_3, busy_adjustment[4]);
2898 }
2899 else
2900 enforce_full_fr_latency (cpu, FRk_3);
2901 }
2902 }
2903
2904 /* The post processing must wait if there is a dependency on a FR
2905 which is not ready yet. */
2906 ps->post_wait = cycles;
2907 post_wait_for_FR (cpu, in_FRj);
2908 post_wait_for_FR (cpu, out_FRk);
2909 post_wait_for_FR (cpu, FRk_1);
2910 post_wait_for_FR (cpu, FRk_2);
2911 post_wait_for_FR (cpu, FRk_3);
2912
2913 /* Restore the busy cycles of the registers we used. */
2914 fr = ps->fr_busy;
2915 fr[in_FRj] += busy_adjustment[0];
2916 fr[out_FRk] += busy_adjustment[1];
2917 if (FRk_1 >= 0)
2918 fr[FRk_1] += busy_adjustment[2];
2919 if (FRk_2 >= 0)
2920 fr[FRk_2] += busy_adjustment[3];
2921 if (FRk_3 >= 0)
2922 fr[FRk_3] += busy_adjustment[4];
2923
2924 /* The latency of tht output register will be at least the latency of the
2925 other inputs. Once initiated, post-processing will take 3 cycles. */
2926 update_FR_latency (cpu, out_FRk, ps->post_wait);
2927 update_FR_ptime (cpu, out_FRk, 3);
2928
2929 /* Mark this use of the register as a media op. */
2930 set_use_is_media (cpu, out_FRk);
2931 if (FRk_1 >= 0)
2932 {
2933 update_FR_latency (cpu, FRk_1, ps->post_wait);
2934 update_FR_ptime (cpu, FRk_1, 3);
2935
2936 /* Mark this use of the register as a media op. */
2937 set_use_is_media (cpu, FRk_1);
2938 }
2939 if (FRk_2 >= 0)
2940 {
2941 update_FR_latency (cpu, FRk_2, ps->post_wait);
2942 update_FR_ptime (cpu, FRk_2, 3);
2943
2944 /* Mark this use of the register as a media op. */
2945 set_use_is_media (cpu, FRk_2);
2946 }
2947 if (FRk_3 >= 0)
2948 {
2949 update_FR_latency (cpu, FRk_3, ps->post_wait);
2950 update_FR_ptime (cpu, FRk_3, 3);
2951
2952 /* Mark this use of the register as a media op. */
2953 set_use_is_media (cpu, FRk_3);
2954 }
2955
2956 return cycles;
2957}
2958
2959int
2960frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
2961 int unit_num, int referenced)
2962{
2963 int cycles;
2964 if (model_insn == FRV_INSN_MODEL_PASS_1)
2965 {
2966 int i;
2967 /* Wait for ALL resources. */
2968 for (i = 0; i < 64; ++i)
2969 {
2970 enforce_full_fr_latency (cpu, i);
2971 vliw_wait_for_GR (cpu, i);
2972 vliw_wait_for_FR (cpu, i);
2973 vliw_wait_for_ACC (cpu, i);
2974 }
2975 for (i = 0; i < 8; ++i)
2976 vliw_wait_for_CCR (cpu, i);
2977 for (i = 0; i < 2; ++i)
2978 {
2979 vliw_wait_for_idiv_resource (cpu, i);
2980 vliw_wait_for_fdiv_resource (cpu, i);
2981 vliw_wait_for_fsqrt_resource (cpu, i);
2982 }
2983 handle_resource_wait (cpu);
2984 for (i = 0; i < 64; ++i)
2985 {
2986 load_wait_for_GR (cpu, i);
2987 load_wait_for_FR (cpu, i);
2988 }
2989 trace_vliw_wait_cycles (cpu);
2990 return 0;
2991 }
2992
2993 cycles = idesc->timing->units[unit_num].done;
2994 return cycles;
2995}
2996
2997int
2998frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc,
2999 int unit_num, int referenced)
3000{
3001 int cycles;
3002 if (model_insn == FRV_INSN_MODEL_PASS_1)
3003 {
3004 int i;
3005 /* Wait for ALL resources, except GR and ICC. */
3006 for (i = 0; i < 64; ++i)
3007 {
3008 enforce_full_fr_latency (cpu, i);
3009 vliw_wait_for_FR (cpu, i);
3010 vliw_wait_for_ACC (cpu, i);
3011 }
3012 for (i = 0; i < 4; ++i)
3013 vliw_wait_for_CCR (cpu, i);
3014 for (i = 0; i < 2; ++i)
3015 {
3016 vliw_wait_for_idiv_resource (cpu, i);
3017 vliw_wait_for_fdiv_resource (cpu, i);
3018 vliw_wait_for_fsqrt_resource (cpu, i);
3019 }
3020 handle_resource_wait (cpu);
3021 for (i = 0; i < 64; ++i)
3022 {
3023 load_wait_for_FR (cpu, i);
3024 }
3025 trace_vliw_wait_cycles (cpu);
3026 return 0;
3027 }
3028
3029 cycles = idesc->timing->units[unit_num].done;
3030 return cycles;
3031}
3032
3033/* The frv machine is a fictional implementation of the fr500 which implements
3034 all frv architectural features. */
3035int
3036frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3037 int unit_num, int referenced)
3038{
3039 return idesc->timing->units[unit_num].done;
3040}
3041
3042/* The simple machine is a fictional implementation of the fr500 which
3043 implements limited frv architectural features. */
3044int
3045frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3046 int unit_num, int referenced)
3047{
3048 return idesc->timing->units[unit_num].done;
3049}
3050
3051/* The tomcat machine is models a prototype fr500 machine which had a few
3052 bugs and restrictions to work around. */
3053int
3054frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3055 int unit_num, int referenced)
3056{
3057 return idesc->timing->units[unit_num].done;
3058}
3059
3060#endif /* WITH_PROFILE_MODEL_P */
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