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e930b1f5 DB |
1 | /* frv simulator fr550 dependent profiling code. |
2 | ||
1d506c26 | 3 | Copyright (C) 2003-2024 Free Software Foundation, Inc. |
e930b1f5 DB |
4 | Contributed by Red Hat |
5 | ||
6 | This file is part of the GNU simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
10 | the Free Software Foundation; either version 3 of the License, or |
11 | (at your option) any later version. | |
e930b1f5 DB |
12 | |
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
4744ac1b | 18 | You should have received a copy of the GNU General Public License |
6df01ab8 MF |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
20 | ||
21 | /* This must come before any other includes. */ | |
22 | #include "defs.h" | |
e930b1f5 | 23 | |
e930b1f5 DB |
24 | #define WANT_CPU |
25 | #define WANT_CPU_FRVBF | |
26 | ||
27 | #include "sim-main.h" | |
28 | #include "bfd.h" | |
29 | ||
30 | #if WITH_PROFILE_MODEL_P | |
31 | ||
32 | #include "profile.h" | |
33 | #include "profile-fr550.h" | |
34 | ||
35 | /* Initialize cycle counting for an insn. | |
36 | FIRST_P is non-zero if this is the first insn in a set of parallel | |
37 | insns. */ | |
38 | void | |
39 | fr550_model_insn_before (SIM_CPU *cpu, int first_p) | |
40 | { | |
41 | if (first_p) | |
42 | { | |
43 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
44 | d->cur_fr_load = d->prev_fr_load; | |
45 | d->cur_fr_complex_1 = d->prev_fr_complex_1; | |
46 | d->cur_fr_complex_2 = d->prev_fr_complex_2; | |
47 | d->cur_ccr_complex = d->prev_ccr_complex; | |
48 | d->cur_acc_mmac = d->prev_acc_mmac; | |
49 | } | |
50 | } | |
51 | ||
52 | /* Record the cycles computed for an insn. | |
53 | LAST_P is non-zero if this is the last insn in a set of parallel insns, | |
54 | and we update the total cycle count. | |
55 | CYCLES is the cycle count of the insn. */ | |
56 | void | |
57 | fr550_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) | |
58 | { | |
59 | if (last_p) | |
60 | { | |
61 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
62 | d->prev_fr_load = d->cur_fr_load; | |
63 | d->prev_fr_complex_1 = d->cur_fr_complex_1; | |
64 | d->prev_fr_complex_2 = d->cur_fr_complex_2; | |
65 | d->prev_ccr_complex = d->cur_ccr_complex; | |
66 | d->prev_acc_mmac = d->cur_acc_mmac; | |
67 | } | |
68 | } | |
69 | ||
70 | static void fr550_reset_fr_flags (SIM_CPU *cpu, INT fr); | |
71 | static void fr550_reset_ccr_flags (SIM_CPU *cpu, INT ccr); | |
72 | static void fr550_reset_acc_flags (SIM_CPU *cpu, INT acc); | |
73 | ||
74 | static void | |
75 | set_use_is_fr_load (SIM_CPU *cpu, INT fr) | |
76 | { | |
77 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
78 | fr550_reset_fr_flags (cpu, (fr)); | |
79 | d->cur_fr_load |= (((DI)1) << (fr)); | |
80 | } | |
81 | ||
82 | static void | |
83 | set_use_not_fr_load (SIM_CPU *cpu, INT fr) | |
84 | { | |
85 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
86 | d->cur_fr_load &= ~(((DI)1) << (fr)); | |
87 | } | |
88 | ||
89 | static int | |
90 | use_is_fr_load (SIM_CPU *cpu, INT fr) | |
91 | { | |
92 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
93 | return d->prev_fr_load & (((DI)1) << (fr)); | |
94 | } | |
95 | ||
96 | static void | |
97 | set_use_is_fr_complex_1 (SIM_CPU *cpu, INT fr) | |
98 | { | |
99 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
100 | fr550_reset_fr_flags (cpu, (fr)); | |
101 | d->cur_fr_complex_1 |= (((DI)1) << (fr)); | |
102 | } | |
103 | ||
104 | static void | |
105 | set_use_not_fr_complex_1 (SIM_CPU *cpu, INT fr) | |
106 | { | |
107 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
108 | d->cur_fr_complex_1 &= ~(((DI)1) << (fr)); | |
109 | } | |
110 | ||
111 | static int | |
112 | use_is_fr_complex_1 (SIM_CPU *cpu, INT fr) | |
113 | { | |
114 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
115 | return d->prev_fr_complex_1 & (((DI)1) << (fr)); | |
116 | } | |
117 | ||
118 | static void | |
119 | set_use_is_fr_complex_2 (SIM_CPU *cpu, INT fr) | |
120 | { | |
121 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
122 | fr550_reset_fr_flags (cpu, (fr)); | |
123 | d->cur_fr_complex_2 |= (((DI)1) << (fr)); | |
124 | } | |
125 | ||
126 | static void | |
127 | set_use_not_fr_complex_2 (SIM_CPU *cpu, INT fr) | |
128 | { | |
129 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
130 | d->cur_fr_complex_2 &= ~(((DI)1) << (fr)); | |
131 | } | |
132 | ||
133 | static int | |
134 | use_is_fr_complex_2 (SIM_CPU *cpu, INT fr) | |
135 | { | |
136 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
137 | return d->prev_fr_complex_2 & (((DI)1) << (fr)); | |
138 | } | |
139 | ||
140 | static void | |
141 | set_use_is_ccr_complex (SIM_CPU *cpu, INT ccr) | |
142 | { | |
143 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
144 | fr550_reset_ccr_flags (cpu, (ccr)); | |
145 | d->cur_ccr_complex |= (((SI)1) << (ccr)); | |
146 | } | |
147 | ||
148 | static void | |
149 | set_use_not_ccr_complex (SIM_CPU *cpu, INT ccr) | |
150 | { | |
151 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
152 | d->cur_ccr_complex &= ~(((SI)1) << (ccr)); | |
153 | } | |
154 | ||
67514280 | 155 | #if 0 |
e930b1f5 DB |
156 | static int |
157 | use_is_ccr_complex (SIM_CPU *cpu, INT ccr) | |
158 | { | |
159 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
160 | return d->prev_ccr_complex & (((SI)1) << (ccr)); | |
161 | } | |
67514280 | 162 | #endif |
e930b1f5 DB |
163 | |
164 | static void | |
165 | set_use_is_acc_mmac (SIM_CPU *cpu, INT acc) | |
166 | { | |
167 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
168 | fr550_reset_acc_flags (cpu, (acc)); | |
169 | d->cur_acc_mmac |= (((DI)1) << (acc)); | |
170 | } | |
171 | ||
172 | static void | |
173 | set_use_not_acc_mmac (SIM_CPU *cpu, INT acc) | |
174 | { | |
175 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
176 | d->cur_acc_mmac &= ~(((DI)1) << (acc)); | |
177 | } | |
178 | ||
179 | static int | |
180 | use_is_acc_mmac (SIM_CPU *cpu, INT acc) | |
181 | { | |
182 | MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); | |
183 | return d->prev_acc_mmac & (((DI)1) << (acc)); | |
184 | } | |
185 | ||
186 | static void | |
187 | fr550_reset_fr_flags (SIM_CPU *cpu, INT fr) | |
188 | { | |
189 | set_use_not_fr_load (cpu, fr); | |
190 | set_use_not_fr_complex_1 (cpu, fr); | |
191 | set_use_not_fr_complex_2 (cpu, fr); | |
192 | } | |
193 | ||
194 | static void | |
195 | fr550_reset_ccr_flags (SIM_CPU *cpu, INT ccr) | |
196 | { | |
197 | set_use_not_ccr_complex (cpu, ccr); | |
198 | } | |
199 | ||
200 | static void | |
201 | fr550_reset_acc_flags (SIM_CPU *cpu, INT acc) | |
202 | { | |
203 | set_use_not_acc_mmac (cpu, acc); | |
204 | } | |
205 | ||
206 | /* Detect overlap between two register ranges. Works if one of the registers | |
207 | is -1 with width 1 (i.e. undefined), but not both. */ | |
208 | #define REG_OVERLAP(r1, w1, r2, w2) ( \ | |
209 | (r1) + (w1) - 1 >= (r2) && (r2) + (w2) - 1 >= (r1) \ | |
210 | ) | |
211 | ||
212 | /* Latency of floating point registers may be less than recorded when followed | |
213 | by another floating point insn. */ | |
214 | static void | |
215 | adjust_float_register_busy (SIM_CPU *cpu, | |
216 | INT in_FRi, int iwidth, | |
217 | INT in_FRj, int jwidth, | |
218 | INT out_FRk, int kwidth) | |
219 | { | |
220 | int i; | |
221 | /* The latency of FRk may be less than previously recorded. | |
222 | See Table 14-15 in the LSI. */ | |
223 | if (in_FRi >= 0) | |
224 | { | |
225 | for (i = 0; i < iwidth; ++i) | |
226 | { | |
227 | if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth)) | |
ff68b4b5 MF |
228 | { |
229 | if (use_is_fr_load (cpu, in_FRi + i)) | |
230 | decrease_FR_busy (cpu, in_FRi + i, 1); | |
231 | else | |
232 | enforce_full_fr_latency (cpu, in_FRi + i); | |
233 | } | |
e930b1f5 DB |
234 | } |
235 | } | |
236 | ||
237 | if (in_FRj >= 0) | |
238 | { | |
239 | for (i = 0; i < jwidth; ++i) | |
240 | { | |
241 | if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth) | |
242 | && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth)) | |
ff68b4b5 MF |
243 | { |
244 | if (use_is_fr_load (cpu, in_FRj + i)) | |
245 | decrease_FR_busy (cpu, in_FRj + i, 1); | |
246 | else | |
247 | enforce_full_fr_latency (cpu, in_FRj + i); | |
248 | } | |
e930b1f5 DB |
249 | } |
250 | } | |
251 | ||
252 | if (out_FRk >= 0) | |
253 | { | |
254 | for (i = 0; i < kwidth; ++i) | |
255 | { | |
256 | if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth) | |
257 | && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth)) | |
258 | { | |
259 | if (use_is_fr_complex_1 (cpu, out_FRk + i)) | |
260 | decrease_FR_busy (cpu, out_FRk + i, 1); | |
261 | else if (use_is_fr_complex_2 (cpu, out_FRk + i)) | |
262 | decrease_FR_busy (cpu, out_FRk + i, 2); | |
263 | else | |
264 | enforce_full_fr_latency (cpu, out_FRk + i); | |
265 | } | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
270 | static void | |
271 | restore_float_register_busy (SIM_CPU *cpu, | |
272 | INT in_FRi, int iwidth, | |
273 | INT in_FRj, int jwidth, | |
274 | INT out_FRk, int kwidth) | |
275 | { | |
276 | int i; | |
277 | /* The latency of FRk may be less than previously recorded. | |
278 | See Table 14-15 in the LSI. */ | |
279 | if (in_FRi >= 0) | |
280 | { | |
281 | for (i = 0; i < iwidth; ++i) | |
282 | { | |
283 | if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth)) | |
284 | if (use_is_fr_load (cpu, in_FRi + i)) | |
285 | increase_FR_busy (cpu, in_FRi + i, 1); | |
286 | } | |
287 | } | |
288 | ||
289 | if (in_FRj >= 0) | |
290 | { | |
291 | for (i = 0; i < jwidth; ++i) | |
292 | { | |
293 | if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth) | |
294 | && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth)) | |
295 | if (use_is_fr_load (cpu, in_FRj + i)) | |
296 | increase_FR_busy (cpu, in_FRj + i, 1); | |
297 | } | |
298 | } | |
299 | ||
300 | if (out_FRk >= 0) | |
301 | { | |
302 | for (i = 0; i < kwidth; ++i) | |
303 | { | |
304 | if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth) | |
305 | && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth)) | |
306 | { | |
307 | if (use_is_fr_complex_1 (cpu, out_FRk + i)) | |
308 | increase_FR_busy (cpu, out_FRk + i, 1); | |
309 | else if (use_is_fr_complex_2 (cpu, out_FRk + i)) | |
310 | increase_FR_busy (cpu, out_FRk + i, 2); | |
311 | } | |
312 | } | |
313 | } | |
314 | } | |
315 | ||
316 | /* Latency of floating point registers may be less than recorded when used in a | |
317 | media insns and followed by another media insn. */ | |
318 | static void | |
319 | adjust_float_register_busy_for_media (SIM_CPU *cpu, | |
320 | INT in_FRi, int iwidth, | |
321 | INT in_FRj, int jwidth, | |
322 | INT out_FRk, int kwidth) | |
323 | { | |
324 | int i; | |
325 | /* The latency of FRk may be less than previously recorded. | |
326 | See Table 14-15 in the LSI. */ | |
327 | if (out_FRk >= 0) | |
328 | { | |
329 | for (i = 0; i < kwidth; ++i) | |
330 | { | |
331 | if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth) | |
332 | && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth)) | |
333 | { | |
334 | if (use_is_fr_complex_1 (cpu, out_FRk + i)) | |
335 | decrease_FR_busy (cpu, out_FRk + i, 1); | |
336 | else | |
337 | enforce_full_fr_latency (cpu, out_FRk + i); | |
338 | } | |
339 | } | |
340 | } | |
341 | } | |
342 | ||
343 | static void | |
344 | restore_float_register_busy_for_media (SIM_CPU *cpu, | |
345 | INT in_FRi, int iwidth, | |
346 | INT in_FRj, int jwidth, | |
347 | INT out_FRk, int kwidth) | |
348 | { | |
349 | int i; | |
350 | if (out_FRk >= 0) | |
351 | { | |
352 | for (i = 0; i < kwidth; ++i) | |
353 | { | |
354 | if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth) | |
355 | && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth)) | |
356 | { | |
357 | if (use_is_fr_complex_1 (cpu, out_FRk + i)) | |
358 | increase_FR_busy (cpu, out_FRk + i, 1); | |
359 | } | |
360 | } | |
361 | } | |
362 | } | |
363 | ||
364 | /* Latency of accumulator registers may be less than recorded when used in a | |
365 | media insns and followed by another media insn. */ | |
366 | static void | |
367 | adjust_acc_busy_for_mmac (SIM_CPU *cpu, | |
368 | INT in_ACC, int inwidth, | |
369 | INT out_ACC, int outwidth) | |
370 | { | |
371 | int i; | |
372 | /* The latency of an accumulator may be less than previously recorded. | |
373 | See Table 14-15 in the LSI. */ | |
374 | if (in_ACC >= 0) | |
375 | { | |
376 | for (i = 0; i < inwidth; ++i) | |
377 | { | |
378 | if (use_is_acc_mmac (cpu, in_ACC + i)) | |
379 | decrease_ACC_busy (cpu, in_ACC + i, 1); | |
380 | else | |
381 | enforce_full_acc_latency (cpu, in_ACC + i); | |
382 | } | |
383 | } | |
384 | if (out_ACC >= 0) | |
385 | { | |
386 | for (i = 0; i < outwidth; ++i) | |
387 | { | |
388 | if (! REG_OVERLAP (out_ACC + i, 1, in_ACC, inwidth)) | |
389 | { | |
390 | if (use_is_acc_mmac (cpu, out_ACC + i)) | |
391 | decrease_ACC_busy (cpu, out_ACC + i, 1); | |
392 | else | |
393 | enforce_full_acc_latency (cpu, out_ACC + i); | |
394 | } | |
395 | } | |
396 | } | |
397 | } | |
398 | ||
399 | static void | |
400 | restore_acc_busy_for_mmac (SIM_CPU *cpu, | |
401 | INT in_ACC, int inwidth, | |
402 | INT out_ACC, int outwidth) | |
403 | { | |
404 | int i; | |
405 | if (in_ACC >= 0) | |
406 | { | |
407 | for (i = 0; i < inwidth; ++i) | |
408 | { | |
409 | if (use_is_acc_mmac (cpu, in_ACC + i)) | |
410 | increase_ACC_busy (cpu, in_ACC + i, 1); | |
411 | } | |
412 | } | |
413 | if (out_ACC >= 0) | |
414 | { | |
415 | for (i = 0; i < outwidth; ++i) | |
416 | { | |
417 | if (! REG_OVERLAP (out_ACC + i, 1, in_ACC, inwidth)) | |
418 | { | |
419 | if (use_is_acc_mmac (cpu, out_ACC + i)) | |
420 | increase_ACC_busy (cpu, out_ACC + i, 1); | |
421 | } | |
422 | } | |
423 | } | |
424 | } | |
425 | ||
426 | int | |
427 | frvbf_model_fr550_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
428 | int unit_num, int referenced) | |
429 | { | |
430 | return idesc->timing->units[unit_num].done; | |
431 | } | |
432 | ||
433 | int | |
434 | frvbf_model_fr550_u_integer (SIM_CPU *cpu, const IDESC *idesc, | |
435 | int unit_num, int referenced, | |
436 | INT in_GRi, INT in_GRj, INT out_GRk, | |
437 | INT out_ICCi_1) | |
438 | { | |
439 | int cycles; | |
440 | ||
441 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
442 | if (out_ICCi_1 >= 0) | |
443 | out_ICCi_1 += 4; | |
444 | ||
445 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
446 | { | |
447 | /* The entire VLIW insn must wait if there is a dependency on a register | |
448 | which is not ready yet. */ | |
449 | vliw_wait_for_GR (cpu, in_GRi); | |
450 | vliw_wait_for_GR (cpu, in_GRj); | |
451 | vliw_wait_for_GR (cpu, out_GRk); | |
452 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
453 | handle_resource_wait (cpu); | |
454 | load_wait_for_GR (cpu, in_GRi); | |
455 | load_wait_for_GR (cpu, in_GRj); | |
456 | load_wait_for_GR (cpu, out_GRk); | |
457 | trace_vliw_wait_cycles (cpu); | |
458 | return 0; | |
459 | } | |
460 | ||
461 | fr550_reset_ccr_flags (cpu, out_ICCi_1); | |
462 | ||
463 | /* GRk is available immediately to the next VLIW insn as is ICCi_1. */ | |
464 | cycles = idesc->timing->units[unit_num].done; | |
465 | return cycles; | |
466 | } | |
467 | ||
468 | int | |
469 | frvbf_model_fr550_u_imul (SIM_CPU *cpu, const IDESC *idesc, | |
470 | int unit_num, int referenced, | |
471 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
472 | { | |
473 | int cycles; | |
474 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
475 | if (out_ICCi_1 >= 0) | |
476 | out_ICCi_1 += 4; | |
477 | ||
478 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
479 | { | |
480 | /* The entire VLIW insn must wait if there is a dependency on a register | |
481 | which is not ready yet. */ | |
482 | vliw_wait_for_GR (cpu, in_GRi); | |
483 | vliw_wait_for_GR (cpu, in_GRj); | |
484 | vliw_wait_for_GRdouble (cpu, out_GRk); | |
485 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
486 | handle_resource_wait (cpu); | |
487 | load_wait_for_GR (cpu, in_GRi); | |
488 | load_wait_for_GR (cpu, in_GRj); | |
489 | load_wait_for_GRdouble (cpu, out_GRk); | |
490 | trace_vliw_wait_cycles (cpu); | |
491 | return 0; | |
492 | } | |
493 | ||
494 | /* GRk has a latency of 1 cycles. */ | |
495 | cycles = idesc->timing->units[unit_num].done; | |
496 | update_GRdouble_latency (cpu, out_GRk, cycles + 1); | |
497 | ||
498 | /* ICCi_1 has a latency of 1 cycle. */ | |
499 | update_CCR_latency (cpu, out_ICCi_1, cycles + 1); | |
500 | ||
501 | fr550_reset_ccr_flags (cpu, out_ICCi_1); | |
502 | ||
503 | return cycles; | |
504 | } | |
505 | ||
506 | int | |
507 | frvbf_model_fr550_u_idiv (SIM_CPU *cpu, const IDESC *idesc, | |
508 | int unit_num, int referenced, | |
509 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
510 | { | |
511 | int cycles; | |
512 | FRV_VLIW *vliw; | |
513 | int slot; | |
514 | ||
515 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
516 | if (out_ICCi_1 >= 0) | |
517 | out_ICCi_1 += 4; | |
518 | ||
519 | vliw = CPU_VLIW (cpu); | |
520 | slot = vliw->next_slot - 1; | |
521 | slot = (*vliw->current_vliw)[slot] - UNIT_I0; | |
522 | ||
523 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
524 | { | |
525 | /* The entire VLIW insn must wait if there is a dependency on a register | |
526 | which is not ready yet. */ | |
527 | vliw_wait_for_GR (cpu, in_GRi); | |
528 | vliw_wait_for_GR (cpu, in_GRj); | |
529 | vliw_wait_for_GR (cpu, out_GRk); | |
530 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
531 | vliw_wait_for_idiv_resource (cpu, slot); | |
532 | handle_resource_wait (cpu); | |
533 | load_wait_for_GR (cpu, in_GRi); | |
534 | load_wait_for_GR (cpu, in_GRj); | |
535 | load_wait_for_GR (cpu, out_GRk); | |
536 | trace_vliw_wait_cycles (cpu); | |
537 | return 0; | |
538 | } | |
539 | ||
540 | /* GRk has a latency of 18 cycles! */ | |
541 | cycles = idesc->timing->units[unit_num].done; | |
542 | update_GR_latency (cpu, out_GRk, cycles + 18); | |
543 | ||
544 | /* ICCi_1 has a latency of 18 cycles. */ | |
545 | update_CCR_latency (cpu, out_ICCi_1, cycles + 18); | |
546 | ||
547 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
548 | { | |
549 | /* GNER has a latency of 18 cycles. */ | |
550 | update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18); | |
551 | } | |
552 | ||
553 | /* the idiv resource has a latency of 18 cycles! */ | |
554 | update_idiv_resource_latency (cpu, slot, cycles + 18); | |
555 | ||
556 | fr550_reset_ccr_flags (cpu, out_ICCi_1); | |
557 | ||
558 | return cycles; | |
559 | } | |
560 | ||
561 | int | |
562 | frvbf_model_fr550_u_branch (SIM_CPU *cpu, const IDESC *idesc, | |
563 | int unit_num, int referenced, | |
564 | INT in_GRi, INT in_GRj, | |
565 | INT in_ICCi_2, INT in_FCCi_2) | |
566 | { | |
567 | int cycles; | |
568 | FRV_PROFILE_STATE *ps; | |
569 | ||
570 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
571 | { | |
572 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
573 | if (in_ICCi_2 >= 0) | |
574 | in_ICCi_2 += 4; | |
575 | ||
576 | /* The entire VLIW insn must wait if there is a dependency on a register | |
577 | which is not ready yet. */ | |
578 | vliw_wait_for_GR (cpu, in_GRi); | |
579 | vliw_wait_for_GR (cpu, in_GRj); | |
580 | vliw_wait_for_CCR (cpu, in_ICCi_2); | |
581 | vliw_wait_for_CCR (cpu, in_FCCi_2); | |
582 | handle_resource_wait (cpu); | |
583 | load_wait_for_GR (cpu, in_GRi); | |
584 | load_wait_for_GR (cpu, in_GRj); | |
585 | trace_vliw_wait_cycles (cpu); | |
586 | return 0; | |
587 | } | |
588 | ||
589 | /* When counting branches taken or not taken, don't consider branches after | |
590 | the first taken branch in a vliw insn. */ | |
591 | ps = CPU_PROFILE_STATE (cpu); | |
592 | if (! ps->vliw_branch_taken) | |
593 | { | |
594 | /* (1 << 4): The pc is the 5th element in inputs, outputs. | |
595 | ??? can be cleaned up */ | |
596 | PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); | |
597 | int taken = (referenced & (1 << 4)) != 0; | |
598 | if (taken) | |
599 | { | |
600 | ++PROFILE_MODEL_TAKEN_COUNT (p); | |
601 | ps->vliw_branch_taken = 1; | |
602 | } | |
603 | else | |
604 | ++PROFILE_MODEL_UNTAKEN_COUNT (p); | |
605 | } | |
606 | ||
607 | cycles = idesc->timing->units[unit_num].done; | |
608 | return cycles; | |
609 | } | |
610 | ||
611 | int | |
612 | frvbf_model_fr550_u_trap (SIM_CPU *cpu, const IDESC *idesc, | |
613 | int unit_num, int referenced, | |
614 | INT in_GRi, INT in_GRj, | |
615 | INT in_ICCi_2, INT in_FCCi_2) | |
616 | { | |
617 | int cycles; | |
618 | ||
619 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
620 | { | |
621 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
622 | if (in_ICCi_2 >= 0) | |
623 | in_ICCi_2 += 4; | |
624 | ||
625 | /* The entire VLIW insn must wait if there is a dependency on a register | |
626 | which is not ready yet. */ | |
627 | vliw_wait_for_GR (cpu, in_GRi); | |
628 | vliw_wait_for_GR (cpu, in_GRj); | |
629 | vliw_wait_for_CCR (cpu, in_ICCi_2); | |
630 | vliw_wait_for_CCR (cpu, in_FCCi_2); | |
631 | handle_resource_wait (cpu); | |
632 | load_wait_for_GR (cpu, in_GRi); | |
633 | load_wait_for_GR (cpu, in_GRj); | |
634 | trace_vliw_wait_cycles (cpu); | |
635 | return 0; | |
636 | } | |
637 | ||
638 | cycles = idesc->timing->units[unit_num].done; | |
639 | return cycles; | |
640 | } | |
641 | ||
642 | int | |
643 | frvbf_model_fr550_u_check (SIM_CPU *cpu, const IDESC *idesc, | |
644 | int unit_num, int referenced, | |
645 | INT in_ICCi_3, INT in_FCCi_3) | |
646 | { | |
647 | /* Modelling for this unit is the same as for fr500. */ | |
648 | return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, | |
649 | in_ICCi_3, in_FCCi_3); | |
650 | } | |
651 | ||
652 | int | |
653 | frvbf_model_fr550_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
654 | int unit_num, int referenced, | |
655 | INT out_GRkhi, INT out_GRklo) | |
656 | { | |
657 | int cycles; | |
658 | ||
659 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
660 | { | |
661 | /* The entire VLIW insn must wait if there is a dependency on a GR | |
662 | which is not ready yet. */ | |
663 | vliw_wait_for_GR (cpu, out_GRkhi); | |
664 | vliw_wait_for_GR (cpu, out_GRklo); | |
665 | handle_resource_wait (cpu); | |
666 | load_wait_for_GR (cpu, out_GRkhi); | |
667 | load_wait_for_GR (cpu, out_GRklo); | |
668 | trace_vliw_wait_cycles (cpu); | |
669 | return 0; | |
670 | } | |
671 | ||
672 | /* GRk is available immediately to the next VLIW insn. */ | |
673 | cycles = idesc->timing->units[unit_num].done; | |
674 | ||
675 | return cycles; | |
676 | } | |
677 | ||
678 | int | |
679 | frvbf_model_fr550_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, | |
680 | int unit_num, int referenced, | |
681 | INT in_GRi, INT in_GRj, | |
682 | INT out_GRk, INT out_GRdoublek) | |
683 | { | |
684 | int cycles; | |
685 | ||
686 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
687 | { | |
688 | /* The entire VLIW insn must wait if there is a dependency on a register | |
689 | which is not ready yet. */ | |
690 | vliw_wait_for_GR (cpu, in_GRi); | |
691 | vliw_wait_for_GR (cpu, in_GRj); | |
692 | vliw_wait_for_GR (cpu, out_GRk); | |
693 | vliw_wait_for_GRdouble (cpu, out_GRdoublek); | |
694 | handle_resource_wait (cpu); | |
695 | load_wait_for_GR (cpu, in_GRi); | |
696 | load_wait_for_GR (cpu, in_GRj); | |
697 | load_wait_for_GR (cpu, out_GRk); | |
698 | load_wait_for_GRdouble (cpu, out_GRdoublek); | |
699 | trace_vliw_wait_cycles (cpu); | |
700 | return 0; | |
701 | } | |
702 | ||
703 | cycles = idesc->timing->units[unit_num].done; | |
704 | ||
705 | /* The latency of GRk for a load will depend on how long it takes to retrieve | |
706 | the the data from the cache or memory. */ | |
707 | update_GR_latency_for_load (cpu, out_GRk, cycles); | |
708 | update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); | |
709 | ||
710 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
711 | { | |
712 | /* GNER has a latency of 2 cycles. */ | |
713 | update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); | |
714 | update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); | |
715 | } | |
716 | ||
717 | return cycles; | |
718 | } | |
719 | ||
720 | int | |
721 | frvbf_model_fr550_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, | |
722 | int unit_num, int referenced, | |
723 | INT in_GRi, INT in_GRj, | |
724 | INT in_GRk, INT in_GRdoublek) | |
725 | { | |
726 | int cycles; | |
727 | ||
728 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
729 | { | |
730 | /* The entire VLIW insn must wait if there is a dependency on a register | |
731 | which is not ready yet. */ | |
732 | vliw_wait_for_GR (cpu, in_GRi); | |
733 | vliw_wait_for_GR (cpu, in_GRj); | |
734 | vliw_wait_for_GR (cpu, in_GRk); | |
735 | vliw_wait_for_GRdouble (cpu, in_GRdoublek); | |
736 | handle_resource_wait (cpu); | |
737 | load_wait_for_GR (cpu, in_GRi); | |
738 | load_wait_for_GR (cpu, in_GRj); | |
739 | load_wait_for_GR (cpu, in_GRk); | |
740 | load_wait_for_GRdouble (cpu, in_GRdoublek); | |
741 | trace_vliw_wait_cycles (cpu); | |
742 | return 0; | |
743 | } | |
744 | ||
745 | /* The target register is available immediately. */ | |
746 | cycles = idesc->timing->units[unit_num].done; | |
747 | ||
748 | return cycles; | |
749 | } | |
750 | ||
751 | int | |
752 | frvbf_model_fr550_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, | |
753 | int unit_num, int referenced, | |
754 | INT in_GRi, INT in_GRj, | |
755 | INT out_FRk, INT out_FRdoublek) | |
756 | { | |
757 | int cycles; | |
758 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
759 | { | |
760 | /* The entire VLIW insn must wait if there is a dependency on a register | |
761 | which is not ready yet. | |
762 | The latency of the registers may be less than previously recorded, | |
763 | depending on how they were used previously. | |
764 | See Table 13-8 in the LSI. */ | |
765 | adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRk, 1); | |
766 | adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRdoublek, 2); | |
767 | vliw_wait_for_GR (cpu, in_GRi); | |
768 | vliw_wait_for_GR (cpu, in_GRj); | |
769 | vliw_wait_for_FR (cpu, out_FRk); | |
770 | vliw_wait_for_FRdouble (cpu, out_FRdoublek); | |
771 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
772 | { | |
773 | vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
774 | vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
775 | } | |
776 | handle_resource_wait (cpu); | |
777 | load_wait_for_GR (cpu, in_GRi); | |
778 | load_wait_for_GR (cpu, in_GRj); | |
779 | load_wait_for_FR (cpu, out_FRk); | |
780 | load_wait_for_FRdouble (cpu, out_FRdoublek); | |
781 | trace_vliw_wait_cycles (cpu); | |
782 | return 0; | |
783 | } | |
784 | ||
785 | cycles = idesc->timing->units[unit_num].done; | |
786 | ||
787 | /* The latency of FRk for a load will depend on how long it takes to retrieve | |
788 | the the data from the cache or memory. */ | |
789 | update_FR_latency_for_load (cpu, out_FRk, cycles); | |
790 | update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); | |
791 | ||
792 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
793 | { | |
794 | /* FNER has a latency of 3 cycles. */ | |
795 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3); | |
796 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3); | |
797 | } | |
798 | ||
799 | if (out_FRk >= 0) | |
800 | set_use_is_fr_load (cpu, out_FRk); | |
801 | if (out_FRdoublek >= 0) | |
802 | { | |
803 | set_use_is_fr_load (cpu, out_FRdoublek); | |
804 | set_use_is_fr_load (cpu, out_FRdoublek + 1); | |
805 | } | |
806 | ||
807 | return cycles; | |
808 | } | |
809 | ||
810 | int | |
811 | frvbf_model_fr550_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, | |
812 | int unit_num, int referenced, | |
813 | INT in_GRi, INT in_GRj, | |
814 | INT in_FRk, INT in_FRdoublek) | |
815 | { | |
816 | int cycles; | |
817 | ||
818 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
819 | { | |
820 | /* The entire VLIW insn must wait if there is a dependency on a register | |
821 | which is not ready yet. */ | |
822 | adjust_float_register_busy (cpu, in_FRk, 1, -1, 1, -1, 1); | |
823 | adjust_float_register_busy (cpu, in_FRdoublek, 2, -1, 1, -1, 1); | |
824 | vliw_wait_for_GR (cpu, in_GRi); | |
825 | vliw_wait_for_GR (cpu, in_GRj); | |
826 | vliw_wait_for_FR (cpu, in_FRk); | |
827 | vliw_wait_for_FRdouble (cpu, in_FRdoublek); | |
828 | handle_resource_wait (cpu); | |
829 | load_wait_for_GR (cpu, in_GRi); | |
830 | load_wait_for_GR (cpu, in_GRj); | |
831 | load_wait_for_FR (cpu, in_FRk); | |
832 | load_wait_for_FRdouble (cpu, in_FRdoublek); | |
833 | trace_vliw_wait_cycles (cpu); | |
834 | return 0; | |
835 | } | |
836 | ||
837 | /* The target register is available immediately. */ | |
838 | cycles = idesc->timing->units[unit_num].done; | |
839 | ||
840 | return cycles; | |
841 | } | |
842 | ||
843 | int | |
844 | frvbf_model_fr550_u_ici (SIM_CPU *cpu, const IDESC *idesc, | |
845 | int unit_num, int referenced, | |
846 | INT in_GRi, INT in_GRj) | |
847 | { | |
848 | int cycles; | |
849 | ||
850 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
851 | { | |
852 | /* The entire VLIW insn must wait if there is a dependency on a register | |
853 | which is not ready yet. */ | |
854 | vliw_wait_for_GR (cpu, in_GRi); | |
855 | vliw_wait_for_GR (cpu, in_GRj); | |
856 | handle_resource_wait (cpu); | |
857 | load_wait_for_GR (cpu, in_GRi); | |
858 | load_wait_for_GR (cpu, in_GRj); | |
859 | trace_vliw_wait_cycles (cpu); | |
860 | return 0; | |
861 | } | |
862 | ||
863 | cycles = idesc->timing->units[unit_num].done; | |
864 | request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles); | |
865 | return cycles; | |
866 | } | |
867 | ||
868 | int | |
869 | frvbf_model_fr550_u_dci (SIM_CPU *cpu, const IDESC *idesc, | |
870 | int unit_num, int referenced, | |
871 | INT in_GRi, INT in_GRj) | |
872 | { | |
873 | int cycles; | |
874 | ||
875 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
876 | { | |
877 | /* The entire VLIW insn must wait if there is a dependency on a register | |
878 | which is not ready yet. */ | |
879 | vliw_wait_for_GR (cpu, in_GRi); | |
880 | vliw_wait_for_GR (cpu, in_GRj); | |
881 | handle_resource_wait (cpu); | |
882 | load_wait_for_GR (cpu, in_GRi); | |
883 | load_wait_for_GR (cpu, in_GRj); | |
884 | trace_vliw_wait_cycles (cpu); | |
885 | return 0; | |
886 | } | |
887 | ||
888 | cycles = idesc->timing->units[unit_num].done; | |
889 | request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); | |
890 | return cycles; | |
891 | } | |
892 | ||
893 | int | |
894 | frvbf_model_fr550_u_dcf (SIM_CPU *cpu, const IDESC *idesc, | |
895 | int unit_num, int referenced, | |
896 | INT in_GRi, INT in_GRj) | |
897 | { | |
898 | int cycles; | |
899 | ||
900 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
901 | { | |
902 | /* The entire VLIW insn must wait if there is a dependency on a register | |
903 | which is not ready yet. */ | |
904 | vliw_wait_for_GR (cpu, in_GRi); | |
905 | vliw_wait_for_GR (cpu, in_GRj); | |
906 | handle_resource_wait (cpu); | |
907 | load_wait_for_GR (cpu, in_GRi); | |
908 | load_wait_for_GR (cpu, in_GRj); | |
909 | trace_vliw_wait_cycles (cpu); | |
910 | return 0; | |
911 | } | |
912 | ||
913 | cycles = idesc->timing->units[unit_num].done; | |
914 | request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles); | |
915 | return cycles; | |
916 | } | |
917 | ||
918 | int | |
919 | frvbf_model_fr550_u_icpl (SIM_CPU *cpu, const IDESC *idesc, | |
920 | int unit_num, int referenced, | |
921 | INT in_GRi, INT in_GRj) | |
922 | { | |
923 | int cycles; | |
924 | ||
925 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
926 | { | |
927 | /* The entire VLIW insn must wait if there is a dependency on a register | |
928 | which is not ready yet. */ | |
929 | vliw_wait_for_GR (cpu, in_GRi); | |
930 | vliw_wait_for_GR (cpu, in_GRj); | |
931 | handle_resource_wait (cpu); | |
932 | load_wait_for_GR (cpu, in_GRi); | |
933 | load_wait_for_GR (cpu, in_GRj); | |
934 | trace_vliw_wait_cycles (cpu); | |
935 | return 0; | |
936 | } | |
937 | ||
938 | cycles = idesc->timing->units[unit_num].done; | |
939 | request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles); | |
940 | return cycles; | |
941 | } | |
942 | ||
943 | int | |
944 | frvbf_model_fr550_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, | |
945 | int unit_num, int referenced, | |
946 | INT in_GRi, INT in_GRj) | |
947 | { | |
948 | int cycles; | |
949 | ||
950 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
951 | { | |
952 | /* The entire VLIW insn must wait if there is a dependency on a register | |
953 | which is not ready yet. */ | |
954 | vliw_wait_for_GR (cpu, in_GRi); | |
955 | vliw_wait_for_GR (cpu, in_GRj); | |
956 | handle_resource_wait (cpu); | |
957 | load_wait_for_GR (cpu, in_GRi); | |
958 | load_wait_for_GR (cpu, in_GRj); | |
959 | trace_vliw_wait_cycles (cpu); | |
960 | return 0; | |
961 | } | |
962 | ||
963 | cycles = idesc->timing->units[unit_num].done; | |
964 | request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles); | |
965 | return cycles; | |
966 | } | |
967 | ||
968 | int | |
969 | frvbf_model_fr550_u_icul (SIM_CPU *cpu, const IDESC *idesc, | |
970 | int unit_num, int referenced, | |
971 | INT in_GRi, INT in_GRj) | |
972 | { | |
973 | int cycles; | |
974 | ||
975 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
976 | { | |
977 | /* The entire VLIW insn must wait if there is a dependency on a register | |
978 | which is not ready yet. */ | |
979 | vliw_wait_for_GR (cpu, in_GRi); | |
980 | vliw_wait_for_GR (cpu, in_GRj); | |
981 | handle_resource_wait (cpu); | |
982 | load_wait_for_GR (cpu, in_GRi); | |
983 | load_wait_for_GR (cpu, in_GRj); | |
984 | trace_vliw_wait_cycles (cpu); | |
985 | return 0; | |
986 | } | |
987 | ||
988 | cycles = idesc->timing->units[unit_num].done; | |
989 | request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles); | |
990 | return cycles; | |
991 | } | |
992 | ||
993 | int | |
994 | frvbf_model_fr550_u_dcul (SIM_CPU *cpu, const IDESC *idesc, | |
995 | int unit_num, int referenced, | |
996 | INT in_GRi, INT in_GRj) | |
997 | { | |
998 | int cycles; | |
999 | ||
1000 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1001 | { | |
1002 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1003 | which is not ready yet. */ | |
1004 | vliw_wait_for_GR (cpu, in_GRi); | |
1005 | vliw_wait_for_GR (cpu, in_GRj); | |
1006 | handle_resource_wait (cpu); | |
1007 | load_wait_for_GR (cpu, in_GRi); | |
1008 | load_wait_for_GR (cpu, in_GRj); | |
1009 | trace_vliw_wait_cycles (cpu); | |
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | cycles = idesc->timing->units[unit_num].done; | |
1014 | request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles); | |
1015 | return cycles; | |
1016 | } | |
1017 | ||
1018 | int | |
1019 | frvbf_model_fr550_u_float_arith (SIM_CPU *cpu, const IDESC *idesc, | |
1020 | int unit_num, int referenced, | |
1021 | INT in_FRi, INT in_FRj, | |
1022 | INT in_FRdoublei, INT in_FRdoublej, | |
1023 | INT out_FRk, INT out_FRdoublek) | |
1024 | { | |
1025 | int cycles; | |
1026 | FRV_PROFILE_STATE *ps; | |
1027 | FRV_VLIW *vliw; | |
1028 | int slot; | |
1029 | ||
1030 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1031 | return 0; | |
1032 | ||
1033 | /* The preprocessing can execute right away. */ | |
1034 | cycles = idesc->timing->units[unit_num].done; | |
1035 | ||
1036 | /* The post processing must wait if there is a dependency on a FR | |
1037 | which is not ready yet. */ | |
1038 | adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); | |
1039 | adjust_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, out_FRdoublek, 2); | |
1040 | ps = CPU_PROFILE_STATE (cpu); | |
1041 | ps->post_wait = cycles; | |
1042 | vliw = CPU_VLIW (cpu); | |
1043 | slot = vliw->next_slot - 1; | |
1044 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1045 | post_wait_for_float (cpu, slot); | |
1046 | post_wait_for_FR (cpu, in_FRi); | |
1047 | post_wait_for_FR (cpu, in_FRj); | |
1048 | post_wait_for_FR (cpu, out_FRk); | |
1049 | post_wait_for_FRdouble (cpu, in_FRdoublei); | |
1050 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1051 | post_wait_for_FRdouble (cpu, out_FRdoublek); | |
1052 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1053 | { | |
1054 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
1055 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
1056 | } | |
1057 | restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); | |
1058 | restore_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, out_FRdoublek, 2); | |
1059 | ||
1060 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1061 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1062 | update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); | |
1063 | ||
1064 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1065 | { | |
1066 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1067 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); | |
1068 | } | |
1069 | ||
1070 | /* Once initiated, post-processing will take 2 cycles. */ | |
1071 | update_FR_ptime (cpu, out_FRk, 2); | |
1072 | update_FRdouble_ptime (cpu, out_FRdoublek, 2); | |
1073 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1074 | { | |
1075 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 2); | |
1076 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 2); | |
1077 | } | |
1078 | ||
1079 | /* Mark this use of the register as a floating point op. */ | |
1080 | if (out_FRk >= 0) | |
1081 | set_use_is_fr_complex_2 (cpu, out_FRk); | |
1082 | if (out_FRdoublek >= 0) | |
1083 | { | |
1084 | set_use_is_fr_complex_2 (cpu, out_FRdoublek); | |
1085 | if (out_FRdoublek < 63) | |
1086 | set_use_is_fr_complex_2 (cpu, out_FRdoublek + 1); | |
1087 | } | |
1088 | ||
1089 | /* the media point unit resource has a latency of 4 cycles */ | |
1090 | update_media_resource_latency (cpu, slot, cycles + 4); | |
1091 | ||
1092 | return cycles; | |
1093 | } | |
1094 | ||
1095 | int | |
1096 | frvbf_model_fr550_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc, | |
1097 | int unit_num, int referenced, | |
1098 | INT in_FRi, INT in_FRj, | |
1099 | INT in_FRdoublei, INT in_FRdoublej, | |
1100 | INT out_FRk, INT out_FRdoublek) | |
1101 | { | |
1102 | int cycles; | |
1103 | INT dual_FRi; | |
1104 | INT dual_FRj; | |
1105 | INT dual_FRk; | |
1106 | INT dual_FRdoublei; | |
1107 | INT dual_FRdoublej; | |
1108 | INT dual_FRdoublek; | |
1109 | FRV_PROFILE_STATE *ps; | |
1110 | FRV_VLIW *vliw; | |
1111 | int slot; | |
1112 | ||
1113 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1114 | return 0; | |
1115 | ||
1116 | /* The preprocessing can execute right away. */ | |
1117 | cycles = idesc->timing->units[unit_num].done; | |
1118 | ||
1119 | /* The post processing must wait if there is a dependency on a FR | |
1120 | which is not ready yet. */ | |
1121 | dual_FRi = DUAL_REG (in_FRi); | |
1122 | dual_FRj = DUAL_REG (in_FRj); | |
1123 | dual_FRk = DUAL_REG (out_FRk); | |
1124 | dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei); | |
1125 | dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej); | |
1126 | dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek); | |
1127 | ||
1128 | adjust_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2); | |
1129 | adjust_float_register_busy (cpu, in_FRdoublei, 4, in_FRdoublej, 4, out_FRdoublek, 4); | |
1130 | ps = CPU_PROFILE_STATE (cpu); | |
1131 | ps->post_wait = cycles; | |
1132 | vliw = CPU_VLIW (cpu); | |
1133 | slot = vliw->next_slot - 1; | |
1134 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1135 | post_wait_for_float (cpu, slot); | |
1136 | post_wait_for_FR (cpu, in_FRi); | |
1137 | post_wait_for_FR (cpu, in_FRj); | |
1138 | post_wait_for_FR (cpu, out_FRk); | |
1139 | post_wait_for_FR (cpu, dual_FRi); | |
1140 | post_wait_for_FR (cpu, dual_FRj); | |
1141 | post_wait_for_FR (cpu, dual_FRk); | |
1142 | post_wait_for_FRdouble (cpu, in_FRdoublei); | |
1143 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1144 | post_wait_for_FRdouble (cpu, out_FRdoublek); | |
1145 | post_wait_for_FRdouble (cpu, dual_FRdoublei); | |
1146 | post_wait_for_FRdouble (cpu, dual_FRdoublej); | |
1147 | post_wait_for_FRdouble (cpu, dual_FRdoublek); | |
1148 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1149 | { | |
1150 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
1151 | post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk)); | |
1152 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
1153 | post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek)); | |
1154 | } | |
1155 | restore_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2); | |
1156 | restore_float_register_busy (cpu, in_FRdoublei, 4, in_FRdoublej, 4, out_FRdoublek, 4); | |
1157 | ||
1158 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1159 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1160 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
1161 | update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); | |
1162 | update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait); | |
1163 | ||
1164 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1165 | { | |
1166 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1167 | update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait); | |
1168 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); | |
1169 | update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait); | |
1170 | } | |
1171 | ||
1172 | /* Once initiated, post-processing will take 3 cycles. */ | |
1173 | update_FR_ptime (cpu, out_FRk, 3); | |
1174 | update_FR_ptime (cpu, dual_FRk, 3); | |
1175 | update_FRdouble_ptime (cpu, out_FRdoublek, 3); | |
1176 | update_FRdouble_ptime (cpu, dual_FRdoublek, 3); | |
1177 | ||
1178 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1179 | { | |
1180 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); | |
1181 | update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3); | |
1182 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); | |
1183 | update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3); | |
1184 | } | |
1185 | ||
1186 | /* Mark this use of the register as a floating point op. */ | |
1187 | if (out_FRk >= 0) | |
1188 | fr550_reset_fr_flags (cpu, out_FRk); | |
1189 | if (dual_FRk >= 0) | |
1190 | fr550_reset_fr_flags (cpu, dual_FRk); | |
1191 | if (out_FRdoublek >= 0) | |
1192 | { | |
1193 | fr550_reset_fr_flags (cpu, out_FRdoublek); | |
1194 | if (out_FRdoublek < 63) | |
1195 | fr550_reset_fr_flags (cpu, out_FRdoublek + 1); | |
1196 | } | |
1197 | if (dual_FRdoublek >= 0) | |
1198 | { | |
1199 | fr550_reset_fr_flags (cpu, dual_FRdoublek); | |
1200 | if (dual_FRdoublek < 63) | |
1201 | fr550_reset_fr_flags (cpu, dual_FRdoublek + 1); | |
1202 | } | |
1203 | ||
1204 | /* the media point unit resource has a latency of 5 cycles */ | |
1205 | update_media_resource_latency (cpu, slot, cycles + 5); | |
1206 | ||
1207 | return cycles; | |
1208 | } | |
1209 | ||
1210 | int | |
1211 | frvbf_model_fr550_u_float_div (SIM_CPU *cpu, const IDESC *idesc, | |
1212 | int unit_num, int referenced, | |
1213 | INT in_FRi, INT in_FRj, INT out_FRk) | |
1214 | { | |
1215 | int cycles; | |
1216 | FRV_VLIW *vliw; | |
1217 | int slot; | |
1218 | FRV_PROFILE_STATE *ps; | |
1219 | ||
1220 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1221 | return 0; | |
1222 | ||
1223 | cycles = idesc->timing->units[unit_num].done; | |
1224 | ||
1225 | /* The post processing must wait if there is a dependency on a FR | |
1226 | which is not ready yet. */ | |
1227 | adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); | |
1228 | ps = CPU_PROFILE_STATE (cpu); | |
1229 | ps->post_wait = cycles; | |
1230 | vliw = CPU_VLIW (cpu); | |
1231 | slot = vliw->next_slot - 1; | |
1232 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1233 | post_wait_for_float (cpu, slot); | |
1234 | post_wait_for_fdiv (cpu, slot); | |
1235 | post_wait_for_FR (cpu, in_FRi); | |
1236 | post_wait_for_FR (cpu, in_FRj); | |
1237 | post_wait_for_FR (cpu, out_FRk); | |
1238 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1239 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
1240 | restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); | |
1241 | ||
1242 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1243 | /* Once initiated, post-processing will take 9 cycles. */ | |
1244 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1245 | update_FR_ptime (cpu, out_FRk, 9); | |
1246 | ||
1247 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1248 | { | |
1249 | /* FNER has a latency of 9 cycles. */ | |
1250 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1251 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 9); | |
1252 | } | |
1253 | ||
1254 | /* The latency of the fdiv unit will be at least the latency of the other | |
1255 | inputs. Once initiated, post-processing will take 9 cycles. */ | |
1256 | update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9); | |
1257 | ||
1258 | /* the media point unit resource has a latency of 11 cycles */ | |
1259 | update_media_resource_latency (cpu, slot, cycles + 11); | |
1260 | ||
1261 | fr550_reset_fr_flags (cpu, out_FRk); | |
1262 | ||
1263 | return cycles; | |
1264 | } | |
1265 | ||
1266 | int | |
1267 | frvbf_model_fr550_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc, | |
1268 | int unit_num, int referenced, | |
1269 | INT in_FRj, INT in_FRdoublej, | |
1270 | INT out_FRk, INT out_FRdoublek) | |
1271 | { | |
1272 | int cycles; | |
1273 | FRV_VLIW *vliw; | |
1274 | int slot; | |
1275 | FRV_PROFILE_STATE *ps; | |
1276 | ||
1277 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1278 | return 0; | |
1279 | ||
1280 | cycles = idesc->timing->units[unit_num].done; | |
1281 | ||
1282 | /* The post processing must wait if there is a dependency on a FR | |
1283 | which is not ready yet. */ | |
1284 | adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); | |
1285 | adjust_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2); | |
1286 | ps = CPU_PROFILE_STATE (cpu); | |
1287 | ps->post_wait = cycles; | |
1288 | vliw = CPU_VLIW (cpu); | |
1289 | slot = vliw->next_slot - 1; | |
1290 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1291 | post_wait_for_float (cpu, slot); | |
1292 | post_wait_for_fsqrt (cpu, slot); | |
1293 | post_wait_for_FR (cpu, in_FRj); | |
1294 | post_wait_for_FR (cpu, out_FRk); | |
1295 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1296 | post_wait_for_FRdouble (cpu, out_FRdoublek); | |
1297 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1298 | { | |
1299 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
1300 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
1301 | } | |
1302 | restore_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); | |
1303 | restore_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2); | |
1304 | ||
1305 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1306 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1307 | update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); | |
1308 | ||
1309 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1310 | { | |
1311 | /* FNER has a latency of 14 cycles. */ | |
1312 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1313 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); | |
1314 | } | |
1315 | ||
1316 | /* Once initiated, post-processing will take 14 cycles. */ | |
1317 | update_FR_ptime (cpu, out_FRk, 14); | |
1318 | update_FRdouble_ptime (cpu, out_FRdoublek, 14); | |
1319 | ||
1320 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1321 | { | |
1322 | /* FNER has a latency of 14 cycles. */ | |
1323 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 14); | |
1324 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 14); | |
1325 | } | |
1326 | ||
1327 | /* The latency of the sqrt unit will be the latency of the other | |
1328 | inputs plus 14 cycles. */ | |
1329 | update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); | |
1330 | ||
1331 | fr550_reset_fr_flags (cpu, out_FRk); | |
1332 | if (out_FRdoublek != -1) | |
1333 | { | |
1334 | fr550_reset_fr_flags (cpu, out_FRdoublek); | |
1335 | fr550_reset_fr_flags (cpu, out_FRdoublek + 1); | |
1336 | } | |
1337 | ||
1338 | /* the media point unit resource has a latency of 16 cycles */ | |
1339 | update_media_resource_latency (cpu, slot, cycles + 16); | |
1340 | ||
1341 | return cycles; | |
1342 | } | |
1343 | ||
1344 | int | |
1345 | frvbf_model_fr550_u_float_compare (SIM_CPU *cpu, const IDESC *idesc, | |
1346 | int unit_num, int referenced, | |
1347 | INT in_FRi, INT in_FRj, | |
1348 | INT in_FRdoublei, INT in_FRdoublej, | |
1349 | INT out_FCCi_2) | |
1350 | { | |
1351 | int cycles; | |
1352 | FRV_PROFILE_STATE *ps; | |
1353 | FRV_VLIW *vliw; | |
1354 | int slot; | |
1355 | ||
1356 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1357 | return 0; | |
1358 | ||
1359 | /* The preprocessing can execute right away. */ | |
1360 | cycles = idesc->timing->units[unit_num].done; | |
1361 | ||
1362 | /* The post processing must wait if there is a dependency on a FR | |
1363 | which is not ready yet. */ | |
1364 | adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, -1, 1); | |
1365 | adjust_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, -1, 1); | |
1366 | ps = CPU_PROFILE_STATE (cpu); | |
1367 | ps->post_wait = cycles; | |
1368 | vliw = CPU_VLIW (cpu); | |
1369 | slot = vliw->next_slot - 1; | |
1370 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1371 | post_wait_for_float (cpu, slot); | |
1372 | post_wait_for_FR (cpu, in_FRi); | |
1373 | post_wait_for_FR (cpu, in_FRj); | |
1374 | post_wait_for_FRdouble (cpu, in_FRdoublei); | |
1375 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1376 | post_wait_for_CCR (cpu, out_FCCi_2); | |
1377 | restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, -1, 1); | |
1378 | restore_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, -1, 1); | |
1379 | ||
1380 | /* The latency of FCCi_2 will be the latency of the other inputs plus 2 | |
1381 | cycles. */ | |
1382 | update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 2); | |
1383 | ||
1384 | /* the media point unit resource has a latency of 4 cycles */ | |
1385 | update_media_resource_latency (cpu, slot, cycles + 4); | |
1386 | ||
1387 | set_use_is_ccr_complex (cpu, out_FCCi_2); | |
1388 | ||
1389 | return cycles; | |
1390 | } | |
1391 | ||
1392 | int | |
1393 | frvbf_model_fr550_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc, | |
1394 | int unit_num, int referenced, | |
1395 | INT in_FRi, INT in_FRj, | |
1396 | INT out_FCCi_2) | |
1397 | { | |
1398 | int cycles; | |
1399 | INT dual_FRi; | |
1400 | INT dual_FRj; | |
1401 | INT dual_FCCi_2; | |
1402 | FRV_PROFILE_STATE *ps; | |
1403 | FRV_VLIW *vliw; | |
1404 | int slot; | |
1405 | ||
1406 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1407 | return 0; | |
1408 | ||
1409 | /* The preprocessing can execute right away. */ | |
1410 | cycles = idesc->timing->units[unit_num].done; | |
1411 | ||
1412 | /* The post processing must wait if there is a dependency on a FR | |
1413 | which is not ready yet. */ | |
1414 | ps = CPU_PROFILE_STATE (cpu); | |
1415 | ps->post_wait = cycles; | |
1416 | dual_FRi = DUAL_REG (in_FRi); | |
1417 | dual_FRj = DUAL_REG (in_FRj); | |
1418 | dual_FCCi_2 = out_FCCi_2 + 1; | |
1419 | adjust_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, -1, 1); | |
1420 | vliw = CPU_VLIW (cpu); | |
1421 | slot = vliw->next_slot - 1; | |
1422 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1423 | post_wait_for_float (cpu, slot); | |
1424 | post_wait_for_FR (cpu, in_FRi); | |
1425 | post_wait_for_FR (cpu, in_FRj); | |
1426 | post_wait_for_FR (cpu, dual_FRi); | |
1427 | post_wait_for_FR (cpu, dual_FRj); | |
1428 | post_wait_for_CCR (cpu, out_FCCi_2); | |
1429 | post_wait_for_CCR (cpu, dual_FCCi_2); | |
1430 | restore_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, -1, 1); | |
1431 | ||
1432 | /* The latency of FCCi_2 will be the latency of the other inputs plus 3 | |
1433 | cycles. */ | |
1434 | update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3); | |
1435 | update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3); | |
1436 | ||
1437 | set_use_is_ccr_complex (cpu, out_FCCi_2); | |
1438 | if (dual_FCCi_2 >= 0) | |
1439 | set_use_is_ccr_complex (cpu, dual_FCCi_2); | |
1440 | ||
1441 | /* the media point unit resource has a latency of 5 cycles */ | |
1442 | update_media_resource_latency (cpu, slot, cycles + 5); | |
1443 | ||
1444 | return cycles; | |
1445 | } | |
1446 | ||
1447 | int | |
1448 | frvbf_model_fr550_u_float_convert (SIM_CPU *cpu, const IDESC *idesc, | |
1449 | int unit_num, int referenced, | |
1450 | INT in_FRj, INT in_FRintj, INT in_FRdoublej, | |
1451 | INT out_FRk, INT out_FRintk, | |
1452 | INT out_FRdoublek) | |
1453 | { | |
1454 | int cycles; | |
1455 | FRV_PROFILE_STATE *ps; | |
1456 | FRV_VLIW *vliw; | |
1457 | int slot; | |
1458 | ||
1459 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1460 | return 0; | |
1461 | ||
1462 | /* The preprocessing can execute right away. */ | |
1463 | cycles = idesc->timing->units[unit_num].done; | |
1464 | ||
1465 | /* The post processing must wait if there is a dependency on a FR | |
1466 | which is not ready yet. */ | |
1467 | ps = CPU_PROFILE_STATE (cpu); | |
1468 | ps->post_wait = cycles; | |
1469 | adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); | |
1470 | adjust_float_register_busy (cpu, -1, 1, in_FRintj, 1, out_FRintk, 1); | |
1471 | adjust_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2); | |
1472 | vliw = CPU_VLIW (cpu); | |
1473 | slot = vliw->next_slot - 1; | |
1474 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1475 | post_wait_for_float (cpu, slot); | |
1476 | post_wait_for_FR (cpu, in_FRj); | |
1477 | post_wait_for_FR (cpu, in_FRintj); | |
1478 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1479 | post_wait_for_FR (cpu, out_FRk); | |
1480 | post_wait_for_FR (cpu, out_FRintk); | |
1481 | post_wait_for_FRdouble (cpu, out_FRdoublek); | |
1482 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1483 | { | |
1484 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
1485 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk)); | |
1486 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
1487 | } | |
1488 | restore_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); | |
1489 | restore_float_register_busy (cpu, -1, 1, in_FRintj, 1, out_FRintk, 1); | |
1490 | restore_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2); | |
1491 | ||
1492 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1493 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1494 | update_FR_latency (cpu, out_FRintk, ps->post_wait); | |
1495 | update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); | |
1496 | ||
1497 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1498 | { | |
1499 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1500 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait); | |
1501 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); | |
1502 | } | |
1503 | ||
1504 | /* Once initiated, post-processing will take 2 cycles. */ | |
1505 | update_FR_ptime (cpu, out_FRk, 2); | |
1506 | update_FR_ptime (cpu, out_FRintk, 2); | |
1507 | update_FRdouble_ptime (cpu, out_FRdoublek, 2); | |
1508 | ||
1509 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
1510 | { | |
1511 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 2); | |
1512 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 2); | |
1513 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 2); | |
1514 | } | |
1515 | ||
1516 | /* Mark this use of the register as a floating point op. */ | |
1517 | if (out_FRk >= 0) | |
1518 | set_use_is_fr_complex_2 (cpu, out_FRk); | |
1519 | if (out_FRintk >= 0) | |
1520 | set_use_is_fr_complex_2 (cpu, out_FRintk); | |
1521 | if (out_FRdoublek >= 0) | |
1522 | { | |
1523 | set_use_is_fr_complex_2 (cpu, out_FRdoublek); | |
1524 | set_use_is_fr_complex_2 (cpu, out_FRdoublek + 1); | |
1525 | } | |
1526 | ||
1527 | /* the media point unit resource has a latency of 4 cycles */ | |
1528 | update_media_resource_latency (cpu, slot, cycles + 4); | |
1529 | ||
1530 | return cycles; | |
1531 | } | |
1532 | ||
1533 | int | |
1534 | frvbf_model_fr550_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
1535 | int unit_num, int referenced, | |
1536 | INT in_spr, INT out_GRj) | |
1537 | { | |
1538 | /* Modelling for this unit is the same as for fr500. */ | |
1539 | return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, | |
1540 | in_spr, out_GRj); | |
1541 | } | |
1542 | ||
1543 | int | |
1544 | frvbf_model_fr550_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, | |
1545 | int unit_num, int referenced, | |
1546 | INT in_GRj, INT out_spr) | |
1547 | { | |
1548 | int cycles; | |
1549 | ||
1550 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1551 | { | |
1552 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1553 | which is not ready yet. */ | |
1554 | vliw_wait_for_GR (cpu, in_GRj); | |
1555 | vliw_wait_for_SPR (cpu, out_spr); | |
1556 | handle_resource_wait (cpu); | |
1557 | load_wait_for_GR (cpu, in_GRj); | |
1558 | trace_vliw_wait_cycles (cpu); | |
1559 | return 0; | |
1560 | } | |
1561 | ||
1562 | cycles = idesc->timing->units[unit_num].done; | |
1563 | ||
1564 | #if 0 | |
1565 | /* The latency of spr is ? cycles. */ | |
1566 | update_SPR_latency (cpu, out_spr, cycles + ?); | |
1567 | #endif | |
1568 | ||
1569 | return cycles; | |
1570 | } | |
1571 | ||
1572 | int | |
1573 | frvbf_model_fr550_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, | |
1574 | int unit_num, int referenced, | |
1575 | INT in_GRj, INT out_FRk) | |
1576 | { | |
1577 | int cycles; | |
1578 | ||
1579 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1580 | { | |
1581 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1582 | which is not ready yet. | |
1583 | The latency of the registers may be less than previously recorded, | |
1584 | depending on how they were used previously. | |
1585 | See Table 14-15 in the LSI. */ | |
1586 | adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRk, 1); | |
1587 | vliw_wait_for_GR (cpu, in_GRj); | |
1588 | vliw_wait_for_FR (cpu, out_FRk); | |
1589 | handle_resource_wait (cpu); | |
1590 | load_wait_for_GR (cpu, in_GRj); | |
1591 | load_wait_for_FR (cpu, out_FRk); | |
1592 | trace_vliw_wait_cycles (cpu); | |
1593 | return 0; | |
1594 | } | |
1595 | ||
1596 | /* The latency of FRk is 1 cycles. */ | |
1597 | cycles = idesc->timing->units[unit_num].done; | |
1598 | update_FR_latency (cpu, out_FRk, cycles + 1); | |
1599 | ||
1600 | set_use_is_fr_complex_1 (cpu, out_FRk); | |
1601 | ||
1602 | return cycles; | |
1603 | } | |
1604 | ||
1605 | int | |
1606 | frvbf_model_fr550_u_swap (SIM_CPU *cpu, const IDESC *idesc, | |
1607 | int unit_num, int referenced, | |
1608 | INT in_GRi, INT in_GRj, INT out_GRk) | |
1609 | { | |
1610 | int cycles; | |
1611 | ||
1612 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1613 | { | |
1614 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1615 | which is not ready yet. */ | |
1616 | vliw_wait_for_GR (cpu, in_GRi); | |
1617 | vliw_wait_for_GR (cpu, in_GRj); | |
1618 | vliw_wait_for_GR (cpu, out_GRk); | |
1619 | handle_resource_wait (cpu); | |
1620 | load_wait_for_GR (cpu, in_GRi); | |
1621 | load_wait_for_GR (cpu, in_GRj); | |
1622 | load_wait_for_GR (cpu, out_GRk); | |
1623 | trace_vliw_wait_cycles (cpu); | |
1624 | return 0; | |
1625 | } | |
1626 | ||
1627 | cycles = idesc->timing->units[unit_num].done; | |
1628 | ||
1629 | /* The latency of GRk will depend on how long it takes to swap | |
1630 | the the data from the cache or memory. */ | |
1631 | update_GR_latency_for_swap (cpu, out_GRk, cycles); | |
1632 | ||
1633 | return cycles; | |
1634 | } | |
1635 | ||
1636 | int | |
1637 | frvbf_model_fr550_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc, | |
1638 | int unit_num, int referenced, | |
1639 | INT in_FRj, INT out_FRk) | |
1640 | { | |
1641 | int cycles; | |
1642 | ||
1643 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1644 | { | |
1645 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1646 | which is not ready yet. | |
1647 | The latency of the registers may be less than previously recorded, | |
1648 | depending on how they were used previously. | |
1649 | See Table 14-15 in the LSI. */ | |
1650 | adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); | |
1651 | vliw_wait_for_FR (cpu, in_FRj); | |
1652 | vliw_wait_for_FR (cpu, out_FRk); | |
1653 | handle_resource_wait (cpu); | |
1654 | load_wait_for_FR (cpu, in_FRj); | |
1655 | load_wait_for_FR (cpu, out_FRk); | |
1656 | trace_vliw_wait_cycles (cpu); | |
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | /* The latency of FRj is 2 cycles. */ | |
1661 | cycles = idesc->timing->units[unit_num].done; | |
1662 | update_FR_latency (cpu, out_FRk, cycles + 2); | |
1663 | ||
1664 | set_use_is_fr_complex_2 (cpu, out_FRk); | |
1665 | ||
1666 | return cycles; | |
1667 | } | |
1668 | ||
1669 | int | |
1670 | frvbf_model_fr550_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
1671 | int unit_num, int referenced, | |
1672 | INT in_FRk, INT out_GRj) | |
1673 | { | |
1674 | int cycles; | |
1675 | ||
1676 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1677 | { | |
1678 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1679 | which is not ready yet. | |
1680 | The latency of the registers may be less than previously recorded, | |
1681 | depending on how they were used previously. | |
1682 | See Table 14-15 in the LSI. */ | |
1683 | adjust_float_register_busy (cpu, in_FRk, 1, -1, 1, -1, 1); | |
1684 | vliw_wait_for_FR (cpu, in_FRk); | |
1685 | vliw_wait_for_GR (cpu, out_GRj); | |
1686 | handle_resource_wait (cpu); | |
1687 | load_wait_for_FR (cpu, in_FRk); | |
1688 | load_wait_for_GR (cpu, out_GRj); | |
1689 | trace_vliw_wait_cycles (cpu); | |
1690 | return 0; | |
1691 | } | |
1692 | ||
1693 | /* The latency of GRj is 1 cycle. */ | |
1694 | cycles = idesc->timing->units[unit_num].done; | |
1695 | update_GR_latency (cpu, out_GRj, cycles + 1); | |
1696 | ||
1697 | return cycles; | |
1698 | } | |
1699 | ||
1700 | int | |
1701 | frvbf_model_fr550_u_clrgr (SIM_CPU *cpu, const IDESC *idesc, | |
1702 | int unit_num, int referenced, | |
1703 | INT in_GRk) | |
1704 | { | |
1705 | /* Modelling for this unit is the same as for fr500. */ | |
1706 | return frvbf_model_fr500_u_clrgr (cpu, idesc, unit_num, referenced, in_GRk); | |
1707 | } | |
1708 | ||
1709 | int | |
1710 | frvbf_model_fr550_u_clrfr (SIM_CPU *cpu, const IDESC *idesc, | |
1711 | int unit_num, int referenced, | |
1712 | INT in_FRk) | |
1713 | { | |
1714 | /* Modelling for this unit is the same as for fr500. */ | |
1715 | return frvbf_model_fr500_u_clrfr (cpu, idesc, unit_num, referenced, in_FRk); | |
1716 | } | |
1717 | ||
1718 | int | |
1719 | frvbf_model_fr550_u_commit (SIM_CPU *cpu, const IDESC *idesc, | |
1720 | int unit_num, int referenced, | |
1721 | INT in_GRk, INT in_FRk) | |
1722 | { | |
1723 | /* Modelling for this unit is the same as for fr500. */ | |
1724 | return frvbf_model_fr500_u_commit (cpu, idesc, unit_num, referenced, | |
1725 | in_GRk, in_FRk); | |
1726 | } | |
1727 | ||
1728 | int | |
1729 | frvbf_model_fr550_u_media (SIM_CPU *cpu, const IDESC *idesc, | |
1730 | int unit_num, int referenced, | |
1731 | INT in_FRi, INT in_FRj, INT out_FRk) | |
1732 | { | |
1733 | int cycles; | |
1734 | FRV_PROFILE_STATE *ps; | |
1735 | FRV_VLIW *vliw; | |
1736 | int slot; | |
1737 | ||
1738 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1739 | return 0; | |
1740 | ||
1741 | /* The preprocessing can execute right away. */ | |
1742 | cycles = idesc->timing->units[unit_num].done; | |
1743 | ||
1744 | /* If the previous use of the registers was a media op, | |
1745 | then their latency may be less than previously recorded. | |
1746 | See Table 14-15 in the LSI. */ | |
1747 | adjust_float_register_busy_for_media (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); | |
1748 | ||
1749 | /* The post processing must wait if there is a dependency on a FR | |
1750 | which is not ready yet. */ | |
1751 | ps = CPU_PROFILE_STATE (cpu); | |
1752 | ps->post_wait = cycles; | |
1753 | vliw = CPU_VLIW (cpu); | |
1754 | slot = vliw->next_slot - 1; | |
1755 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1756 | post_wait_for_media (cpu, slot); | |
1757 | post_wait_for_FR (cpu, in_FRi); | |
1758 | post_wait_for_FR (cpu, in_FRj); | |
1759 | post_wait_for_FR (cpu, out_FRk); | |
1760 | ||
1761 | /* Restore the busy cycles of the registers we used. */ | |
1762 | restore_float_register_busy_for_media (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); | |
1763 | ||
1764 | /* The latency of tht output register will be at least the latency of the | |
1765 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1766 | if (out_FRk >= 0) | |
1767 | { | |
1768 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1769 | update_FR_ptime (cpu, out_FRk, 1); | |
1770 | /* Mark this use of the register as a media op. */ | |
1771 | set_use_is_fr_complex_1 (cpu, out_FRk); | |
1772 | } | |
1773 | ||
1774 | /* the floating point unit resource has a latency of 3 cycles */ | |
1775 | update_float_resource_latency (cpu, slot, cycles + 3); | |
1776 | ||
1777 | return cycles; | |
1778 | } | |
1779 | ||
1780 | int | |
1781 | frvbf_model_fr550_u_media_quad (SIM_CPU *cpu, const IDESC *idesc, | |
1782 | int unit_num, int referenced, | |
1783 | INT in_FRi, INT in_FRj, | |
1784 | INT out_FRk) | |
1785 | { | |
1786 | int cycles; | |
1787 | INT dual_FRi; | |
1788 | INT dual_FRj; | |
1789 | INT dual_FRk; | |
1790 | FRV_PROFILE_STATE *ps; | |
1791 | FRV_VLIW *vliw; | |
1792 | int slot; | |
1793 | ||
1794 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1795 | return 0; | |
1796 | ||
1797 | /* The preprocessing can execute right away. */ | |
1798 | cycles = idesc->timing->units[unit_num].done; | |
1799 | ||
1800 | dual_FRi = DUAL_REG (in_FRi); | |
1801 | dual_FRj = DUAL_REG (in_FRj); | |
1802 | dual_FRk = DUAL_REG (out_FRk); | |
1803 | ||
1804 | /* The latency of the registers may be less than previously recorded, | |
1805 | depending on how they were used previously. | |
1806 | See Table 14-15 in the LSI. */ | |
1807 | adjust_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2); | |
1808 | ||
1809 | /* The post processing must wait if there is a dependency on a FR | |
1810 | which is not ready yet. */ | |
1811 | ps = CPU_PROFILE_STATE (cpu); | |
1812 | ps->post_wait = cycles; | |
1813 | vliw = CPU_VLIW (cpu); | |
1814 | slot = vliw->next_slot - 1; | |
1815 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1816 | post_wait_for_media (cpu, slot); | |
1817 | post_wait_for_FR (cpu, in_FRi); | |
1818 | post_wait_for_FR (cpu, dual_FRi); | |
1819 | post_wait_for_FR (cpu, in_FRj); | |
1820 | post_wait_for_FR (cpu, dual_FRj); | |
1821 | post_wait_for_FR (cpu, out_FRk); | |
1822 | post_wait_for_FR (cpu, dual_FRk); | |
1823 | ||
1824 | /* Restore the busy cycles of the registers we used. */ | |
1825 | restore_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2); | |
1826 | ||
1827 | /* The latency of the output register will be at least the latency of the | |
1828 | other inputs. Once initiated, post-processing take 1 cycle. */ | |
1829 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1830 | update_FR_ptime (cpu, out_FRk, 1); | |
1831 | set_use_is_fr_complex_1 (cpu, out_FRk); | |
1832 | ||
1833 | if (dual_FRk >= 0) | |
1834 | { | |
1835 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
1836 | update_FR_ptime (cpu, dual_FRk, 1); | |
1837 | set_use_is_fr_complex_1 (cpu, dual_FRk); | |
1838 | } | |
1839 | ||
1840 | /* the floating point unit resource has a latency of 3 cycles */ | |
1841 | update_float_resource_latency (cpu, slot, cycles + 3); | |
1842 | ||
1843 | return cycles; | |
1844 | } | |
1845 | ||
1846 | int | |
1847 | frvbf_model_fr550_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, | |
1848 | int unit_num, int referenced, | |
1849 | INT in_FRi, INT out_FRk) | |
1850 | { | |
1851 | int cycles; | |
1852 | INT dual_FRk; | |
1853 | FRV_PROFILE_STATE *ps; | |
1854 | FRV_VLIW *vliw; | |
1855 | int slot; | |
1856 | ||
1857 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1858 | return 0; | |
1859 | ||
1860 | /* The preprocessing can execute right away. */ | |
1861 | cycles = idesc->timing->units[unit_num].done; | |
1862 | ||
1863 | /* If the previous use of the registers was a media op, | |
1864 | then their latency will be less than previously recorded. | |
1865 | See Table 14-15 in the LSI. */ | |
1866 | dual_FRk = DUAL_REG (out_FRk); | |
1867 | adjust_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, out_FRk, 2); | |
1868 | ||
1869 | /* The post processing must wait if there is a dependency on a FR | |
1870 | which is not ready yet. */ | |
1871 | ps = CPU_PROFILE_STATE (cpu); | |
1872 | ps->post_wait = cycles; | |
1873 | vliw = CPU_VLIW (cpu); | |
1874 | slot = vliw->next_slot - 1; | |
1875 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1876 | post_wait_for_media (cpu, slot); | |
1877 | post_wait_for_FR (cpu, in_FRi); | |
1878 | post_wait_for_FR (cpu, out_FRk); | |
1879 | post_wait_for_FR (cpu, dual_FRk); | |
1880 | ||
1881 | /* Restore the busy cycles of the registers we used. */ | |
1882 | restore_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, out_FRk, 2); | |
1883 | ||
1884 | /* The latency of the output register will be at least the latency of the | |
1885 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1886 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1887 | update_FR_ptime (cpu, out_FRk, 1); | |
1888 | set_use_is_fr_complex_1 (cpu, out_FRk); | |
1889 | ||
1890 | if (dual_FRk >= 0) | |
1891 | { | |
1892 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
1893 | update_FR_ptime (cpu, dual_FRk, 1); | |
1894 | set_use_is_fr_complex_1 (cpu, dual_FRk); | |
1895 | } | |
1896 | ||
1897 | /* the floating point unit resource has a latency of 3 cycles */ | |
1898 | update_float_resource_latency (cpu, slot, cycles + 3); | |
1899 | ||
1900 | return cycles; | |
1901 | } | |
1902 | ||
1903 | int | |
1904 | frvbf_model_fr550_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1905 | int unit_num, int referenced, | |
1906 | INT in_FRi, INT out_FRk) | |
1907 | { | |
1908 | int cycles; | |
1909 | INT dual_FRi; | |
1910 | FRV_PROFILE_STATE *ps; | |
1911 | FRV_VLIW *vliw; | |
1912 | int slot; | |
1913 | ||
1914 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1915 | return 0; | |
1916 | ||
1917 | /* The preprocessing can execute right away. */ | |
1918 | cycles = idesc->timing->units[unit_num].done; | |
1919 | ||
1920 | dual_FRi = DUAL_REG (in_FRi); | |
1921 | ||
1922 | /* The latency of the registers may be less than previously recorded, | |
1923 | depending on how they were used previously. | |
1924 | See Table 14-15 in the LSI. */ | |
1925 | adjust_float_register_busy_for_media (cpu, in_FRi, 2, -1, 1, out_FRk, 1); | |
1926 | ||
1927 | /* The post processing must wait if there is a dependency on a FR | |
1928 | which is not ready yet. */ | |
1929 | ps = CPU_PROFILE_STATE (cpu); | |
1930 | ps->post_wait = cycles; | |
1931 | vliw = CPU_VLIW (cpu); | |
1932 | slot = vliw->next_slot - 1; | |
1933 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1934 | post_wait_for_media (cpu, slot); | |
1935 | post_wait_for_FR (cpu, in_FRi); | |
1936 | post_wait_for_FR (cpu, dual_FRi); | |
1937 | post_wait_for_FR (cpu, out_FRk); | |
1938 | ||
1939 | /* Restore the busy cycles of the registers we used. */ | |
1940 | restore_float_register_busy_for_media (cpu, in_FRi, 2, -1, 1, out_FRk, 1); | |
1941 | ||
1942 | /* The latency of the output register will be at least the latency of the | |
1943 | other inputs. Once initiated, post-processing takes 1 cycle. */ | |
1944 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1945 | update_FR_ptime (cpu, out_FRk, 1); | |
1946 | ||
1947 | set_use_is_fr_complex_1 (cpu, out_FRk); | |
1948 | ||
1949 | /* the floating point unit resource has a latency of 3 cycles */ | |
1950 | update_float_resource_latency (cpu, slot, cycles + 3); | |
1951 | ||
1952 | return cycles; | |
1953 | } | |
1954 | ||
1955 | int | |
1956 | frvbf_model_fr550_u_media_3_acc (SIM_CPU *cpu, const IDESC *idesc, | |
1957 | int unit_num, int referenced, | |
1958 | INT in_FRj, INT in_ACC40Si, | |
1959 | INT out_FRk) | |
1960 | { | |
1961 | int cycles; | |
1962 | FRV_PROFILE_STATE *ps; | |
1963 | FRV_VLIW *vliw; | |
1964 | int slot; | |
1965 | ||
1966 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1967 | return 0; | |
1968 | ||
1969 | /* The preprocessing can execute right away. */ | |
1970 | cycles = idesc->timing->units[unit_num].done; | |
1971 | ||
1972 | /* If the previous use of the registers was a media op, | |
1973 | then their latency will be less than previously recorded. | |
1974 | See Table 14-15 in the LSI. */ | |
1975 | adjust_float_register_busy_for_media (cpu, -1, 1, in_FRj, 1, out_FRk, 1); | |
1976 | ||
1977 | /* The post processing must wait if there is a dependency on a FR | |
1978 | which is not ready yet. */ | |
1979 | ps = CPU_PROFILE_STATE (cpu); | |
1980 | ps->post_wait = cycles; | |
1981 | vliw = CPU_VLIW (cpu); | |
1982 | slot = vliw->next_slot - 1; | |
1983 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1984 | post_wait_for_media (cpu, slot); | |
1985 | post_wait_for_FR (cpu, in_FRj); | |
1986 | post_wait_for_FR (cpu, out_FRk); | |
1987 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1988 | ||
1989 | /* Restore the busy cycles of the registers we used. */ | |
1990 | restore_float_register_busy_for_media (cpu, -1, 1, in_FRj, 1, out_FRk, 1); | |
1991 | ||
1992 | /* The latency of tht output register will be at least the latency of the | |
1993 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1994 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1995 | update_FR_ptime (cpu, out_FRk, 1); | |
1996 | ||
1997 | set_use_is_fr_complex_1 (cpu, out_FRk); | |
1998 | ||
1999 | /* the floating point unit resource has a latency of 3 cycles */ | |
2000 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2001 | ||
2002 | return cycles; | |
2003 | } | |
2004 | ||
2005 | int | |
2006 | frvbf_model_fr550_u_media_3_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
2007 | int unit_num, int referenced, | |
2008 | INT in_ACC40Si, INT out_FRk) | |
2009 | { | |
2010 | int cycles; | |
2011 | FRV_PROFILE_STATE *ps; | |
2012 | INT ACC40Si_1; | |
2013 | INT dual_FRk; | |
2014 | FRV_VLIW *vliw; | |
2015 | int slot; | |
2016 | ||
2017 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2018 | return 0; | |
2019 | ||
2020 | /* The preprocessing can execute right away. */ | |
2021 | cycles = idesc->timing->units[unit_num].done; | |
2022 | ||
2023 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
2024 | dual_FRk = DUAL_REG (out_FRk); | |
2025 | ||
2026 | /* If the previous use of the registers was a media op, | |
2027 | then their latency will be less than previously recorded. | |
2028 | See Table 14-15 in the LSI. */ | |
2029 | adjust_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 2); | |
2030 | ||
2031 | /* The post processing must wait if there is a dependency on a FR | |
2032 | which is not ready yet. */ | |
2033 | ps = CPU_PROFILE_STATE (cpu); | |
2034 | ps->post_wait = cycles; | |
2035 | vliw = CPU_VLIW (cpu); | |
2036 | slot = vliw->next_slot - 1; | |
2037 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2038 | post_wait_for_media (cpu, slot); | |
2039 | post_wait_for_ACC (cpu, in_ACC40Si); | |
2040 | post_wait_for_ACC (cpu, ACC40Si_1); | |
2041 | post_wait_for_FR (cpu, out_FRk); | |
2042 | post_wait_for_FR (cpu, dual_FRk); | |
2043 | ||
2044 | /* Restore the busy cycles of the registers we used. */ | |
2045 | restore_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 2); | |
2046 | ||
2047 | /* The latency of the output register will be at least the latency of the | |
2048 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2049 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2050 | update_FR_ptime (cpu, out_FRk, 1); | |
2051 | set_use_is_fr_complex_1 (cpu, out_FRk); | |
2052 | if (dual_FRk >= 0) | |
2053 | { | |
2054 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
2055 | update_FR_ptime (cpu, dual_FRk, 1); | |
2056 | set_use_is_fr_complex_1 (cpu, dual_FRk); | |
2057 | } | |
2058 | ||
2059 | /* the floating point unit resource has a latency of 3 cycles */ | |
2060 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2061 | ||
2062 | return cycles; | |
2063 | } | |
2064 | ||
2065 | int | |
2066 | frvbf_model_fr550_u_media_3_wtacc (SIM_CPU *cpu, const IDESC *idesc, | |
2067 | int unit_num, int referenced, | |
2068 | INT in_FRi, INT out_ACC40Sk) | |
2069 | { | |
2070 | int cycles; | |
2071 | FRV_PROFILE_STATE *ps; | |
2072 | FRV_VLIW *vliw; | |
2073 | int slot; | |
2074 | ||
2075 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2076 | return 0; | |
2077 | ||
2078 | /* The preprocessing can execute right away. */ | |
2079 | cycles = idesc->timing->units[unit_num].done; | |
2080 | ||
2081 | ps = CPU_PROFILE_STATE (cpu); | |
2082 | ||
2083 | /* The latency of the registers may be less than previously recorded, | |
2084 | depending on how they were used previously. | |
2085 | See Table 14-15 in the LSI. */ | |
2086 | adjust_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, -1, 1); | |
2087 | ||
2088 | /* The post processing must wait if there is a dependency on a FR | |
2089 | which is not ready yet. */ | |
2090 | ps->post_wait = cycles; | |
2091 | vliw = CPU_VLIW (cpu); | |
2092 | slot = vliw->next_slot - 1; | |
2093 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2094 | post_wait_for_media (cpu, slot); | |
2095 | post_wait_for_FR (cpu, in_FRi); | |
2096 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2097 | ||
2098 | /* Restore the busy cycles of the registers we used. */ | |
2099 | restore_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, -1, 1); | |
2100 | ||
2101 | /* The latency of the output register will be at least the latency of the | |
2102 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2103 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait); | |
2104 | update_ACC_ptime (cpu, out_ACC40Sk, 1); | |
2105 | set_use_is_acc_mmac (cpu, out_ACC40Sk); | |
2106 | ||
2107 | /* the floating point unit resource has a latency of 3 cycles */ | |
2108 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2109 | ||
2110 | return cycles; | |
2111 | } | |
2112 | ||
2113 | int | |
2114 | frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *cpu, const IDESC *idesc, | |
2115 | int unit_num, int referenced) | |
2116 | { | |
2117 | int cycles; | |
2118 | FRV_PROFILE_STATE *ps; | |
2119 | FRV_VLIW *vliw; | |
2120 | int slot; | |
2121 | int i; | |
2122 | ||
2123 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2124 | return 0; | |
2125 | ||
2126 | /* The preprocessing can execute right away. */ | |
2127 | cycles = idesc->timing->units[unit_num].done; | |
2128 | ||
2129 | ps = CPU_PROFILE_STATE (cpu); | |
2130 | ||
2131 | /* The post processing must wait if there is a dependency on a FR | |
2132 | which is not ready yet. */ | |
2133 | ps->post_wait = cycles; | |
2134 | vliw = CPU_VLIW (cpu); | |
2135 | slot = vliw->next_slot - 1; | |
2136 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2137 | post_wait_for_media (cpu, slot); | |
2138 | ||
2139 | /* If A was 1 and the accumulator was ACC0, then we must check all | |
2140 | accumulators. Otherwise just wait for the specified accumulator. */ | |
2141 | if (ps->mclracc_A && ps->mclracc_acc == 0) | |
2142 | { | |
2143 | for (i = 0; i < 8; ++i) | |
2144 | post_wait_for_ACC (cpu, i); | |
2145 | } | |
2146 | else | |
2147 | post_wait_for_ACC (cpu, ps->mclracc_acc); | |
2148 | ||
2149 | /* The latency of the output registers will be at least the latency of the | |
2150 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2151 | if (ps->mclracc_A && ps->mclracc_acc == 0) | |
2152 | { | |
2153 | for (i = 0; i < 8; ++i) | |
2154 | { | |
2155 | update_ACC_latency (cpu, i, ps->post_wait); | |
2156 | update_ACC_ptime (cpu, i, 1); | |
2157 | set_use_is_acc_mmac (cpu, i); | |
2158 | } | |
2159 | } | |
2160 | else | |
2161 | { | |
2162 | update_ACC_latency (cpu, ps->mclracc_acc, ps->post_wait); | |
2163 | update_ACC_ptime (cpu, ps->mclracc_acc, 1); | |
2164 | set_use_is_acc_mmac (cpu, ps->mclracc_acc); | |
2165 | } | |
2166 | ||
2167 | /* the floating point unit resource has a latency of 3 cycles */ | |
2168 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2169 | ||
2170 | return cycles; | |
2171 | } | |
2172 | ||
2173 | int | |
2174 | frvbf_model_fr550_u_media_set (SIM_CPU *cpu, const IDESC *idesc, | |
2175 | int unit_num, int referenced, | |
2176 | INT out_FRk) | |
2177 | { | |
2178 | int cycles; | |
2179 | FRV_PROFILE_STATE *ps; | |
2180 | FRV_VLIW *vliw; | |
2181 | int slot; | |
2182 | ||
2183 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2184 | return 0; | |
2185 | ||
2186 | /* The preprocessing can execute right away. */ | |
2187 | cycles = idesc->timing->units[unit_num].done; | |
2188 | ||
2189 | /* If the previous use of the registers was a media op, | |
2190 | then their latency will be less than previously recorded. | |
2191 | See Table 14-15 in the LSI. */ | |
2192 | adjust_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 1); | |
2193 | ||
2194 | /* The post processing must wait if there is a dependency on a FR | |
2195 | which is not ready yet. */ | |
2196 | ps = CPU_PROFILE_STATE (cpu); | |
2197 | ps->post_wait = cycles; | |
2198 | vliw = CPU_VLIW (cpu); | |
2199 | slot = vliw->next_slot - 1; | |
2200 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2201 | post_wait_for_media (cpu, slot); | |
2202 | post_wait_for_FR (cpu, out_FRk); | |
2203 | ||
2204 | /* Restore the busy cycles of the registers we used. */ | |
2205 | restore_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 1); | |
2206 | ||
2207 | /* The latency of the output register will be at least the latency of the | |
2208 | other inputs. Once initiated, post-processing takes 1 cycle. */ | |
2209 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2210 | update_FR_ptime (cpu, out_FRk, 1); | |
2211 | fr550_reset_acc_flags (cpu, out_FRk); | |
2212 | ||
2213 | /* the floating point unit resource has a latency of 3 cycles */ | |
2214 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2215 | ||
2216 | return cycles; | |
2217 | } | |
2218 | ||
2219 | int | |
2220 | frvbf_model_fr550_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, | |
2221 | int unit_num, int referenced, | |
2222 | INT in_FRi, INT in_FRj, | |
2223 | INT out_ACC40Sk, INT out_ACC40Uk) | |
2224 | { | |
2225 | int cycles; | |
2226 | INT dual_ACC40Sk; | |
2227 | INT dual_ACC40Uk; | |
2228 | FRV_PROFILE_STATE *ps; | |
2229 | FRV_VLIW *vliw; | |
2230 | int slot; | |
2231 | ||
2232 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2233 | return 0; | |
2234 | ||
2235 | /* The preprocessing can execute right away. */ | |
2236 | cycles = idesc->timing->units[unit_num].done; | |
2237 | ||
2238 | ps = CPU_PROFILE_STATE (cpu); | |
2239 | dual_ACC40Sk = DUAL_REG (out_ACC40Sk); | |
2240 | dual_ACC40Uk = DUAL_REG (out_ACC40Uk); | |
2241 | ||
2242 | /* The latency of the registers may be less than previously recorded, | |
2243 | depending on how they were used previously. | |
2244 | See Table 14-15 in the LSI. */ | |
2245 | adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 2); | |
2246 | adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 2); | |
2247 | ||
2248 | /* The post processing must wait if there is a dependency on a FR | |
2249 | which is not ready yet. */ | |
2250 | ps->post_wait = cycles; | |
2251 | vliw = CPU_VLIW (cpu); | |
2252 | slot = vliw->next_slot - 1; | |
2253 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2254 | post_wait_for_media (cpu, slot); | |
2255 | post_wait_for_FR (cpu, in_FRi); | |
2256 | post_wait_for_FR (cpu, in_FRj); | |
2257 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2258 | post_wait_for_ACC (cpu, dual_ACC40Sk); | |
2259 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
2260 | post_wait_for_ACC (cpu, dual_ACC40Uk); | |
2261 | ||
2262 | /* Restore the busy cycles of the registers we used. */ | |
2263 | restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 2); | |
2264 | restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 2); | |
2265 | ||
2266 | /* The latency of the output register will be at least the latency of the | |
2267 | other inputs. Once initiated, post-processing will take 1 cycles. */ | |
2268 | if (out_ACC40Sk >= 0) | |
2269 | { | |
2270 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2271 | set_use_is_acc_mmac (cpu, out_ACC40Sk); | |
2272 | } | |
2273 | if (dual_ACC40Sk >= 0) | |
2274 | { | |
2275 | update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); | |
2276 | set_use_is_acc_mmac (cpu, dual_ACC40Sk); | |
2277 | } | |
2278 | if (out_ACC40Uk >= 0) | |
2279 | { | |
2280 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
2281 | set_use_is_acc_mmac (cpu, out_ACC40Uk); | |
2282 | } | |
2283 | if (dual_ACC40Uk >= 0) | |
2284 | { | |
2285 | update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); | |
2286 | set_use_is_acc_mmac (cpu, dual_ACC40Uk); | |
2287 | } | |
2288 | ||
2289 | /* the floating point unit resource has a latency of 3 cycles */ | |
2290 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2291 | ||
2292 | return cycles; | |
2293 | } | |
2294 | ||
2295 | int | |
2296 | frvbf_model_fr550_u_media_4_acc (SIM_CPU *cpu, const IDESC *idesc, | |
2297 | int unit_num, int referenced, | |
2298 | INT in_ACC40Si, INT out_ACC40Sk) | |
2299 | { | |
2300 | int cycles; | |
2301 | INT ACC40Si_1; | |
2302 | FRV_PROFILE_STATE *ps; | |
2303 | FRV_VLIW *vliw; | |
2304 | int slot; | |
2305 | ||
2306 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2307 | return 0; | |
2308 | ||
2309 | /* The preprocessing can execute right away. */ | |
2310 | cycles = idesc->timing->units[unit_num].done; | |
2311 | ||
2312 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
2313 | ||
2314 | ps = CPU_PROFILE_STATE (cpu); | |
2315 | /* The latency of the registers may be less than previously recorded, | |
2316 | depending on how they were used previously. | |
2317 | See Table 14-15 in the LSI. */ | |
2318 | adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 1); | |
2319 | ||
2320 | /* The post processing must wait if there is a dependency on a register | |
2321 | which is not ready yet. */ | |
2322 | ps->post_wait = cycles; | |
2323 | vliw = CPU_VLIW (cpu); | |
2324 | slot = vliw->next_slot - 1; | |
2325 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2326 | post_wait_for_media (cpu, slot); | |
2327 | post_wait_for_ACC (cpu, in_ACC40Si); | |
2328 | post_wait_for_ACC (cpu, ACC40Si_1); | |
2329 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2330 | ||
2331 | /* Restore the busy cycles of the registers we used. */ | |
2332 | restore_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 1); | |
2333 | ||
2334 | /* The latency of the output register will be at least the latency of the | |
2335 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2336 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2337 | set_use_is_acc_mmac (cpu, out_ACC40Sk); | |
2338 | ||
2339 | /* the floating point unit resource has a latency of 3 cycles */ | |
2340 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2341 | ||
2342 | return cycles; | |
2343 | } | |
2344 | ||
2345 | int | |
2346 | frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
2347 | int unit_num, int referenced, | |
2348 | INT in_ACC40Si, INT out_ACC40Sk) | |
2349 | { | |
2350 | int cycles; | |
2351 | INT ACC40Si_1; | |
2352 | INT ACC40Si_2; | |
2353 | INT ACC40Si_3; | |
2354 | INT ACC40Sk_1; | |
2355 | FRV_PROFILE_STATE *ps; | |
2356 | FRV_VLIW *vliw; | |
2357 | int slot; | |
2358 | ||
2359 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2360 | return 0; | |
2361 | ||
2362 | /* The preprocessing can execute right away. */ | |
2363 | cycles = idesc->timing->units[unit_num].done; | |
2364 | ||
2365 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
2366 | ACC40Si_2 = DUAL_REG (ACC40Si_1); | |
2367 | ACC40Si_3 = DUAL_REG (ACC40Si_2); | |
2368 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
2369 | ||
2370 | ps = CPU_PROFILE_STATE (cpu); | |
2371 | /* The latency of the registers may be less than previously recorded, | |
2372 | depending on how they were used previously. | |
2373 | See Table 14-15 in the LSI. */ | |
2374 | adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 2); | |
2375 | ||
2376 | /* The post processing must wait if there is a dependency on a register | |
2377 | which is not ready yet. */ | |
2378 | ps->post_wait = cycles; | |
2379 | vliw = CPU_VLIW (cpu); | |
2380 | slot = vliw->next_slot - 1; | |
2381 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2382 | post_wait_for_media (cpu, slot); | |
2383 | post_wait_for_ACC (cpu, in_ACC40Si); | |
2384 | post_wait_for_ACC (cpu, ACC40Si_1); | |
2385 | post_wait_for_ACC (cpu, ACC40Si_2); | |
2386 | post_wait_for_ACC (cpu, ACC40Si_3); | |
2387 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2388 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
2389 | ||
2390 | /* Restore the busy cycles of the registers we used. */ | |
2391 | restore_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 2); | |
2392 | ||
2393 | /* The latency of the output register will be at least the latency of the | |
2394 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2395 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2396 | set_use_is_acc_mmac (cpu, out_ACC40Sk); | |
2397 | if (ACC40Sk_1 >= 0) | |
2398 | { | |
2399 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
2400 | set_use_is_acc_mmac (cpu, ACC40Sk_1); | |
2401 | } | |
2402 | ||
2403 | /* the floating point unit resource has a latency of 3 cycles */ | |
2404 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2405 | ||
2406 | return cycles; | |
2407 | } | |
2408 | ||
2409 | int | |
2410 | frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *cpu, const IDESC *idesc, | |
2411 | int unit_num, int referenced, | |
2412 | INT in_ACC40Si, INT out_ACC40Sk) | |
2413 | { | |
2414 | int cycles; | |
2415 | INT ACC40Si_1; | |
2416 | INT ACC40Sk_1; | |
2417 | FRV_PROFILE_STATE *ps; | |
2418 | FRV_VLIW *vliw; | |
2419 | int slot; | |
2420 | ||
2421 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2422 | return 0; | |
2423 | ||
2424 | /* The preprocessing can execute right away. */ | |
2425 | cycles = idesc->timing->units[unit_num].done; | |
2426 | ||
2427 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
2428 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
2429 | ||
2430 | ps = CPU_PROFILE_STATE (cpu); | |
2431 | /* The latency of the registers may be less than previously recorded, | |
2432 | depending on how they were used previously. | |
2433 | See Table 14-15 in the LSI. */ | |
2434 | adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 2); | |
2435 | ||
2436 | /* The post processing must wait if there is a dependency on a register | |
2437 | which is not ready yet. */ | |
2438 | ps->post_wait = cycles; | |
2439 | vliw = CPU_VLIW (cpu); | |
2440 | slot = vliw->next_slot - 1; | |
2441 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2442 | post_wait_for_media (cpu, slot); | |
2443 | post_wait_for_ACC (cpu, in_ACC40Si); | |
2444 | post_wait_for_ACC (cpu, ACC40Si_1); | |
2445 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2446 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
2447 | ||
2448 | /* Restore the busy cycles of the registers we used. */ | |
2449 | restore_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 2); | |
2450 | ||
2451 | /* The latency of the output register will be at least the latency of the | |
2452 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2453 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2454 | set_use_is_acc_mmac (cpu, out_ACC40Sk); | |
2455 | if (ACC40Sk_1 >= 0) | |
2456 | { | |
2457 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
2458 | set_use_is_acc_mmac (cpu, ACC40Sk_1); | |
2459 | } | |
2460 | ||
2461 | /* the floating point unit resource has a latency of 3 cycles */ | |
2462 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2463 | ||
2464 | return cycles; | |
2465 | } | |
2466 | ||
2467 | int | |
2468 | frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, | |
2469 | int unit_num, int referenced, | |
2470 | INT in_ACC40Si, INT out_ACC40Sk) | |
2471 | { | |
2472 | int cycles; | |
2473 | INT ACC40Si_1; | |
2474 | INT ACC40Si_2; | |
2475 | INT ACC40Si_3; | |
2476 | INT ACC40Sk_1; | |
2477 | INT ACC40Sk_2; | |
2478 | INT ACC40Sk_3; | |
2479 | FRV_PROFILE_STATE *ps; | |
2480 | FRV_VLIW *vliw; | |
2481 | int slot; | |
2482 | ||
2483 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2484 | return 0; | |
2485 | ||
2486 | /* The preprocessing can execute right away. */ | |
2487 | cycles = idesc->timing->units[unit_num].done; | |
2488 | ||
2489 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
2490 | ACC40Si_2 = DUAL_REG (ACC40Si_1); | |
2491 | ACC40Si_3 = DUAL_REG (ACC40Si_2); | |
2492 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
2493 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
2494 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
2495 | ||
2496 | ps = CPU_PROFILE_STATE (cpu); | |
2497 | /* The latency of the registers may be less than previously recorded, | |
2498 | depending on how they were used previously. | |
2499 | See Table 14-15 in the LSI. */ | |
2500 | adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 4); | |
2501 | ||
2502 | /* The post processing must wait if there is a dependency on a register | |
2503 | which is not ready yet. */ | |
2504 | ps->post_wait = cycles; | |
2505 | vliw = CPU_VLIW (cpu); | |
2506 | slot = vliw->next_slot - 1; | |
2507 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2508 | post_wait_for_media (cpu, slot); | |
2509 | post_wait_for_ACC (cpu, in_ACC40Si); | |
2510 | post_wait_for_ACC (cpu, ACC40Si_1); | |
2511 | post_wait_for_ACC (cpu, ACC40Si_2); | |
2512 | post_wait_for_ACC (cpu, ACC40Si_3); | |
2513 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2514 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
2515 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
2516 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
2517 | ||
2518 | /* Restore the busy cycles of the registers we used. */ | |
2519 | restore_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 4); | |
2520 | ||
2521 | /* The latency of the output register will be at least the latency of the | |
2522 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2523 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2524 | set_use_is_acc_mmac (cpu, out_ACC40Sk); | |
2525 | if (ACC40Sk_1 >= 0) | |
2526 | { | |
2527 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
2528 | set_use_is_acc_mmac (cpu, ACC40Sk_1); | |
2529 | } | |
2530 | if (ACC40Sk_2 >= 0) | |
2531 | { | |
2532 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
2533 | set_use_is_acc_mmac (cpu, ACC40Sk_2); | |
2534 | } | |
2535 | if (ACC40Sk_3 >= 0) | |
2536 | { | |
2537 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
2538 | set_use_is_acc_mmac (cpu, ACC40Sk_3); | |
2539 | } | |
2540 | ||
2541 | /* the floating point unit resource has a latency of 3 cycles */ | |
2542 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2543 | ||
2544 | return cycles; | |
2545 | } | |
2546 | ||
2547 | int | |
2548 | frvbf_model_fr550_u_media_4_quad (SIM_CPU *cpu, const IDESC *idesc, | |
2549 | int unit_num, int referenced, | |
2550 | INT in_FRi, INT in_FRj, | |
2551 | INT out_ACC40Sk, INT out_ACC40Uk) | |
2552 | { | |
2553 | int cycles; | |
2554 | INT dual_FRi; | |
2555 | INT dual_FRj; | |
2556 | INT ACC40Sk_1; | |
2557 | INT ACC40Sk_2; | |
2558 | INT ACC40Sk_3; | |
2559 | INT ACC40Uk_1; | |
2560 | INT ACC40Uk_2; | |
2561 | INT ACC40Uk_3; | |
2562 | FRV_PROFILE_STATE *ps; | |
2563 | FRV_VLIW *vliw; | |
2564 | int slot; | |
2565 | ||
2566 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2567 | return 0; | |
2568 | ||
2569 | /* The preprocessing can execute right away. */ | |
2570 | cycles = idesc->timing->units[unit_num].done; | |
2571 | ||
2572 | dual_FRi = DUAL_REG (in_FRi); | |
2573 | dual_FRj = DUAL_REG (in_FRj); | |
2574 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
2575 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
2576 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
2577 | ACC40Uk_1 = DUAL_REG (out_ACC40Uk); | |
2578 | ACC40Uk_2 = DUAL_REG (ACC40Uk_1); | |
2579 | ACC40Uk_3 = DUAL_REG (ACC40Uk_2); | |
2580 | ||
2581 | ps = CPU_PROFILE_STATE (cpu); | |
2582 | /* The latency of the registers may be less than previously recorded, | |
2583 | depending on how they were used previously. | |
2584 | See Table 14-15 in the LSI. */ | |
2585 | adjust_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, -1, 1); | |
2586 | adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 4); | |
2587 | adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 4); | |
2588 | ||
2589 | /* The post processing must wait if there is a dependency on a FR | |
2590 | which is not ready yet. */ | |
2591 | ps->post_wait = cycles; | |
2592 | vliw = CPU_VLIW (cpu); | |
2593 | slot = vliw->next_slot - 1; | |
2594 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
2595 | post_wait_for_media (cpu, slot); | |
2596 | post_wait_for_FR (cpu, in_FRi); | |
2597 | post_wait_for_FR (cpu, dual_FRi); | |
2598 | post_wait_for_FR (cpu, in_FRj); | |
2599 | post_wait_for_FR (cpu, dual_FRj); | |
2600 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2601 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
2602 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
2603 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
2604 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
2605 | post_wait_for_ACC (cpu, ACC40Uk_1); | |
2606 | post_wait_for_ACC (cpu, ACC40Uk_2); | |
2607 | post_wait_for_ACC (cpu, ACC40Uk_3); | |
2608 | ||
2609 | /* Restore the busy cycles of the registers we used. */ | |
2610 | restore_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, -1, 1); | |
2611 | restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 4); | |
2612 | restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 4); | |
2613 | ||
2614 | /* The latency of the output register will be at least the latency of the | |
2615 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2616 | if (out_ACC40Sk >= 0) | |
2617 | { | |
2618 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2619 | ||
2620 | set_use_is_acc_mmac (cpu, out_ACC40Sk); | |
2621 | if (ACC40Sk_1 >= 0) | |
2622 | { | |
2623 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
2624 | ||
2625 | set_use_is_acc_mmac (cpu, ACC40Sk_1); | |
2626 | } | |
2627 | if (ACC40Sk_2 >= 0) | |
2628 | { | |
2629 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
2630 | ||
2631 | set_use_is_acc_mmac (cpu, ACC40Sk_2); | |
2632 | } | |
2633 | if (ACC40Sk_3 >= 0) | |
2634 | { | |
2635 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
2636 | ||
2637 | set_use_is_acc_mmac (cpu, ACC40Sk_3); | |
2638 | } | |
2639 | } | |
2640 | else if (out_ACC40Uk >= 0) | |
2641 | { | |
2642 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
2643 | ||
2644 | set_use_is_acc_mmac (cpu, out_ACC40Uk); | |
2645 | if (ACC40Uk_1 >= 0) | |
2646 | { | |
2647 | update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); | |
2648 | ||
2649 | set_use_is_acc_mmac (cpu, ACC40Uk_1); | |
2650 | } | |
2651 | if (ACC40Uk_2 >= 0) | |
2652 | { | |
2653 | update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); | |
2654 | ||
2655 | set_use_is_acc_mmac (cpu, ACC40Uk_2); | |
2656 | } | |
2657 | if (ACC40Uk_3 >= 0) | |
2658 | { | |
2659 | update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); | |
2660 | ||
2661 | set_use_is_acc_mmac (cpu, ACC40Uk_3); | |
2662 | } | |
2663 | } | |
2664 | ||
2665 | /* the floating point unit resource has a latency of 3 cycles */ | |
2666 | update_float_resource_latency (cpu, slot, cycles + 3); | |
2667 | ||
2668 | return cycles; | |
2669 | } | |
2670 | ||
2671 | #endif /* WITH_PROFILE_MODEL_P */ |