]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/frv/sim-main.h
gdb/testsuite: tests for debug lookup within the sysroot
[thirdparty/binutils-gdb.git] / sim / frv / sim-main.h
CommitLineData
b34f6357 1/* frv simulator support code
1d506c26 2 Copyright (C) 1998-2024 Free Software Foundation, Inc.
b34f6357
DB
3 Contributed by Red Hat.
4
5This file is part of the GNU simulators.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
4744ac1b
JB
9the Free Software Foundation; either version 3 of the License, or
10(at your option) any later version.
b34f6357
DB
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
4744ac1b
JB
17You should have received a copy of the GNU General Public License
18along with this program. If not, see <http://www.gnu.org/licenses/>. */
b34f6357 19
a9d20039
MF
20#ifndef FRV_SIM_MAIN_H
21#define FRV_SIM_MAIN_H
22
b34f6357
DB
23/* Main header for the frv. */
24
f0c1b768
MF
25/* This is a global setting. Different cpu families can't mix-n-match -scache
26 and -pbb. However some cpu families may use -simple while others use
27 one of -scache/-pbb. ???? */
28#define WITH_SCACHE_PBB 0
29
b34f6357 30#include "sim-basics.h"
60a10311 31#include "opcodes/frv-desc.h"
6cf3ddd2 32#include <stdbool.h>
60a10311 33#include "opcodes/frv-opc.h"
b34f6357
DB
34#include "arch.h"
35
b34f6357
DB
36#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
37 frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
38
520ca9a7 39#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA)
b34f6357
DB
40
41#include "sim-base.h"
42#include "cgen-sim.h"
43#include "frv-sim.h"
44#include "cache.h"
45#include "registers.h"
46#include "profile.h"
7e83aa92
MF
47
48void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
6e4f085c
MF
49
50extern void frv_sim_close (SIM_DESC sd, int quitting);
51#define SIM_CLOSE_HOOK(...) frv_sim_close (__VA_ARGS__)
b34f6357 52\f
811727ab 53struct frv_sim_cpu {
b34f6357
DB
54 /* CPU specific parts go here.
55 Note that in files that don't need to access these pieces WANT_CPU_FOO
56 won't be defined and thus these parts won't appear. This is ok in the
57 sense that things work. It is a source of bugs though.
58 One has to of course be careful to not take the size of this
59 struct and no structure members accessed in non-cpu specific files can
60 go after here. Oh for a better language. */
61#if defined (WANT_CPU_FRVBF)
62 FRVBF_CPU_DATA cpu_data;
63
64 /* Control information for registers */
65 FRV_REGISTER_CONTROL register_control;
811727ab 66#define CPU_REGISTER_CONTROL(cpu) (& FRV_SIM_CPU (cpu)->register_control)
b34f6357
DB
67
68 FRV_VLIW vliw;
811727ab 69#define CPU_VLIW(cpu) (& FRV_SIM_CPU (cpu)->vliw)
b34f6357
DB
70
71 FRV_CACHE insn_cache;
811727ab 72#define CPU_INSN_CACHE(cpu) (& FRV_SIM_CPU (cpu)->insn_cache)
b34f6357
DB
73
74 FRV_CACHE data_cache;
811727ab 75#define CPU_DATA_CACHE(cpu) (& FRV_SIM_CPU (cpu)->data_cache)
b34f6357
DB
76
77 FRV_PROFILE_STATE profile_state;
811727ab 78#define CPU_PROFILE_STATE(cpu) (& FRV_SIM_CPU (cpu)->profile_state)
b34f6357
DB
79
80 int debug_state;
811727ab 81#define CPU_DEBUG_STATE(cpu) (FRV_SIM_CPU (cpu)->debug_state)
b34f6357
DB
82
83 SI load_address;
811727ab 84#define CPU_LOAD_ADDRESS(cpu) (FRV_SIM_CPU (cpu)->load_address)
b34f6357
DB
85
86 SI load_length;
811727ab 87#define CPU_LOAD_LENGTH(cpu) (FRV_SIM_CPU (cpu)->load_length)
b34f6357
DB
88
89 SI load_flag;
811727ab
MF
90#define CPU_LOAD_SIGNED(cpu) (FRV_SIM_CPU (cpu)->load_flag)
91#define CPU_LOAD_LOCK(cpu) (FRV_SIM_CPU (cpu)->load_flag)
b34f6357
DB
92
93 SI store_flag;
811727ab 94#define CPU_RSTR_INVALIDATE(cpu) (FRV_SIM_CPU (cpu)->store_flag)
b34f6357
DB
95
96 unsigned long elf_flags;
811727ab 97#define CPU_ELF_FLAGS(cpu) (FRV_SIM_CPU (cpu)->elf_flags)
b34f6357
DB
98#endif /* defined (WANT_CPU_FRVBF) */
99};
811727ab 100#define FRV_SIM_CPU(cpu) ((struct frv_sim_cpu *) CPU_ARCH_DATA (cpu))
b34f6357 101\f
b34f6357
DB
102/* Misc. */
103
104/* Catch address exceptions. */
d137b254 105extern SIM_CORE_SIGNAL_FN frv_core_signal ATTRIBUTE_NORETURN;
b34f6357
DB
106#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
107frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
108 (TRANSFER), (ERROR))
109
110/* Default memory size. */
111#define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */
a9d20039
MF
112
113void frvbf_model_branch (SIM_CPU *, PCADDR, int hint);
114void frvbf_perform_writeback (SIM_CPU *);
115
116#endif