]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/ft32/interp.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[thirdparty/binutils-gdb.git] / sim / ft32 / interp.c
CommitLineData
f46e4eb7
JB		 1/* Simulator for the FT32 processor
2
3 Copyright (C) 2008-2015 Free Software Foundation, Inc.
4 Contributed by FTDI <support@ftdichip.com>
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "config.h"
22#include <fcntl.h>
23#include <signal.h>
24#include <stdlib.h>
25#include <stdint.h>
26
27#include "bfd.h"
28#include "gdb/callback.h"
29#include "libiberty.h"
30#include "gdb/remote-sim.h"
31
32#include "sim-main.h"
33#include "sim-options.h"
34
35#include "opcode/ft32.h"
36
37/*
38 * FT32 is a Harvard architecture: RAM and code occupy
39 * different address spaces.
40 *
41 * sim and gdb model FT32 memory by adding 0x800000 to RAM
42 * addresses. This means that sim/gdb can treat all addresses
43 * similarly.
44 *
45 * The address space looks like:
46 *
47 * 00000 start of code memory
48 * 3ffff end of code memory
49 * 800000 start of RAM
50 * 80ffff end of RAM
51 */
52
53#define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */
54
55static unsigned long
56ft32_extract_unsigned_integer (unsigned char *addr, int len)
57{
58 unsigned long retval;
59 unsigned char *p;
60 unsigned char *startaddr = (unsigned char *) addr;
61 unsigned char *endaddr = startaddr + len;
62
63 /* Start at the most significant end of the integer, and work towards
64 the least significant. */
65 retval = 0;
66
67 for (p = endaddr; p > startaddr;)
68 retval = (retval << 8) | * -- p;
69
70 return retval;
71}
72
73static void
74ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
75{
76 unsigned char *p;
77 unsigned char *startaddr = (unsigned char *)addr;
78 unsigned char *endaddr = startaddr + len;
79
80 for (p = startaddr; p < endaddr; p++)
81 {
82 *p = val & 0xff;
83 val >>= 8;
84 }
85}
86
87/*
88 * Align EA according to its size DW.
89 * The FT32 ignores the low bit of a 16-bit addresss,
90 * and the low two bits of a 32-bit address.
91 */
92static uint32_t ft32_align (uint32_t dw, uint32_t ea)
93{
94 switch (dw)
95 {
96 case 1:
97 ea &= ~1;
98 break;
99 case 2:
100 ea &= ~3;
101 break;
102 default:
103 break;
104 }
105 return ea;
106}
107
108/* Read an item from memory address EA, sized DW. */
109static uint32_t
110ft32_read_item (SIM_DESC sd, int dw, uint32_t ea)
111{
112 sim_cpu *cpu = STATE_CPU (sd, 0);
113 address_word cia = CIA_GET (cpu);
114 uint8_t byte[4];
115 uint32_t r;
116
117 ea = ft32_align (dw, ea);
118
119 switch (dw) {
120 case 0:
121 return sim_core_read_aligned_1 (cpu, cia, read_map, ea);
122 case 1:
123 return sim_core_read_aligned_2 (cpu, cia, read_map, ea);
124 case 2:
125 return sim_core_read_aligned_4 (cpu, cia, read_map, ea);
126 default:
127 abort ();
128 }
129}
130
131/* Write item V to memory address EA, sized DW. */
132static void
133ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v)
134{
135 sim_cpu *cpu = STATE_CPU (sd, 0);
136 address_word cia = CIA_GET (cpu);
137 uint8_t byte[4];
138
139 ea = ft32_align (dw, ea);
140
141 switch (dw) {
142 case 0:
143 sim_core_write_aligned_1 (cpu, cia, write_map, ea, v);
144 break;
145 case 1:
146 sim_core_write_aligned_2 (cpu, cia, write_map, ea, v);
147 break;
148 case 2:
149 sim_core_write_aligned_4 (cpu, cia, write_map, ea, v);
150 break;
151 default:
152 abort ();
153 }
154}
155
156#define ILLEGAL() \
157 sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL)
158
159static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea)
160{
161 sim_cpu *cpu = STATE_CPU (sd, 0);
162 uint32_t insnpc = cpu->state.pc;
163 uint32_t r;
164 uint8_t byte[4];
165
166 ea &= 0x1ffff;
167 if (ea & ~0xffff)
168 {
169 /* Simulate some IO devices */
170 switch (ea)
171 {
172 case 0x1fff4:
173 /* Read the simulator cycle timer. */
174 return cpu->state.cycles / 100;
175 default:
176 sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n",
177 ea, insnpc);
178 ILLEGAL ();
179 }
180 }
181 return ft32_read_item (sd, dw, RAM_BIAS + ea);
182}
183
184static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d)
185{
186 sim_cpu *cpu = STATE_CPU (sd, 0);
187 ea &= 0x1ffff;
188 if (ea & 0x10000)
189 {
190 /* Simulate some IO devices */
191 switch (ea)
192 {
193 case 0x10000:
194 /* Console output */
195 putchar (d & 0xff);
196 break;
197 case 0x1fc80:
198 /* Unlock the PM write port */
199 cpu->state.pm_unlock = (d == 0x1337f7d1);
200 break;
201 case 0x1fc84:
202 /* Set the PM write address register */
203 cpu->state.pm_addr = d;
204 break;
205 case 0x1fc88:
206 /* Write to PM */
207 ft32_write_item (sd, dw, cpu->state.pm_addr, d);
208 break;
209 case 0x1fffc:
210 /* Normal exit. */
211 sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.regs[0]);
212 break;
213 case 0x1fff8:
214 sim_io_printf (sd, "Debug write %08x\n", d);
215 break;
216 default:
217 sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea);
218 }
219 }
220 else
221 ft32_write_item (sd, dw, RAM_BIAS + ea, d);
222}
223
224#define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea))
225#define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d))
226
227/* LSBS (n) is a mask of the least significant N bits. */
228#define LSBS(n) ((1U << (n)) - 1)
229
230static void ft32_push (SIM_DESC sd, uint32_t v)
231{
232 sim_cpu *cpu = STATE_CPU (sd, 0);
233 cpu->state.regs[FT32_HARD_SP] -= 4;
234 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
235 cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v);
236}
237
238static uint32_t ft32_pop (SIM_DESC sd)
239{
240 sim_cpu *cpu = STATE_CPU (sd, 0);
241 uint32_t r = cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]);
242 cpu->state.regs[FT32_HARD_SP] += 4;
243 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
244 return r;
245}
246
247/* Extract the low SIZ bits of N as an unsigned number. */
248static int nunsigned (int siz, int n)
249{
250 return n & LSBS (siz);
251}
252
253/* Extract the low SIZ bits of N as a signed number. */
254static int nsigned (int siz, int n)
255{
256 int shift = (sizeof (int) * 8) - siz;
257 return (n << shift) >> shift;
258}
259
260/* Signed division N / D, matching hw behavior for (MIN_INT, -1). */
261static uint32_t ft32sdiv (uint32_t n, uint32_t d)
262{
263 if (n == 0x80000000UL && d == 0xffffffffUL)
264 return 0x80000000UL;
265 else
266 return (uint32_t)((int)n / (int)d);
267}
268
269/* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */
270static uint32_t ft32smod (uint32_t n, uint32_t d)
271{
272 if (n == 0x80000000UL && d == 0xffffffffUL)
273 return 0;
274 else
275 return (uint32_t)((int)n % (int)d);
276}
277
278/* Circular rotate right N by B bits. */
279static uint32_t ror (uint32_t n, uint32_t b)
280{
281 b &= 31;
282 return (n >> b) | (n << (32 - b));
283}
284
285/* Implement the BINS machine instruction.
286 See FT32 Programmer's Reference for details. */
287static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos)
288{
289 uint32_t bitmask = LSBS (len) << pos;
290 return (d & ~bitmask) | ((f << pos) & bitmask);
291}
292
293/* Implement the FLIP machine instruction.
294 See FT32 Programmer's Reference for details. */
295static uint32_t flip (uint32_t x, uint32_t b)
296{
297 if (b & 1)
298 x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1;
299 if (b & 2)
300 x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2;
301 if (b & 4)
302 x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4;
303 if (b & 8)
304 x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8;
305 if (b & 16)
306 x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16;
307 return x;
308}
309
310static void
311step_once (SIM_DESC sd)
312{
313 sim_cpu *cpu = STATE_CPU (sd, 0);
314 address_word cia = CIA_GET (cpu);
315 uint32_t inst;
316 uint32_t dw;
317 uint32_t cb;
318 uint32_t r_d;
319 uint32_t cr;
320 uint32_t cv;
321 uint32_t bt;
322 uint32_t r_1;
323 uint32_t rimm;
324 uint32_t r_2;
325 uint32_t k20;
326 uint32_t pa;
327 uint32_t aa;
328 uint32_t k16;
329 uint32_t k8;
330 uint32_t al;
331 uint32_t r_1v;
332 uint32_t rimmv;
333 uint32_t bit_pos;
334 uint32_t bit_len;
335 uint32_t upper;
336 uint32_t insnpc;
337
338 if (cpu->state.cycles >= cpu->state.next_tick_cycle)
339 {
340 cpu->state.next_tick_cycle += 100000;
341 ft32_push (sd, cpu->state.pc);
342 cpu->state.pc = 12; /* interrupt 1. */
343 }
344 inst = ft32_read_item (sd, 2, cpu->state.pc);
345 cpu->state.cycles += 1;
346
347 /* Handle "call 8" (which is FT32's "break" equivalent) here. */
348 if (inst == 0x00340002)
349 {
350 sim_engine_halt (sd, cpu, NULL,
351 cpu->state.pc,
352 sim_stopped, SIM_SIGTRAP);
353 goto escape;
354 }
355
356 dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ);
357 cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ);
358 r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ);
359 cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ);
360 cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ);
361 bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ);
362 r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ);
363 rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ);
364 r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ);
365 k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ));
366 pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ);
367 aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ);
368 k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ);
369 k8 = nsigned (8, (inst >> FT32_FLD_K8_BIT) & LSBS (FT32_FLD_K8_SIZ));
370 al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ);
371
372 r_1v = cpu->state.regs[r_1];
373 rimmv = (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0x1f];
374
375 bit_pos = rimmv & 31;
376 bit_len = 0xf & (rimmv >> 5);
377 if (bit_len == 0)
378 bit_len = 16;
379
380 upper = (inst >> 27);
381
382 insnpc = cpu->state.pc;
383 cpu->state.pc += 4;
384 switch (upper)
385 {
386 case FT32_PAT_TOC:
387 case FT32_PAT_TOCI:
388 {
389 int take = (cr == 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) == cv);
390 if (take)
391 {
392 cpu->state.cycles += 1;
393 if (bt)
394 ft32_push (sd, cpu->state.pc); /* this is a call. */
395 if (upper == FT32_PAT_TOC)
396 cpu->state.pc = pa << 2;
397 else
398 cpu->state.pc = cpu->state.regs[r_2];
399 if (cpu->state.pc == 0x8)
400 goto escape;
401 }
402 }
403 break;
404
405 case FT32_PAT_ALUOP:
406 case FT32_PAT_CMPOP:
407 {
408 uint32_t result;
409 switch (al)
410 {
411 case 0x0: result = r_1v + rimmv; break;
412 case 0x1: result = ror (r_1v, rimmv); break;
413 case 0x2: result = r_1v - rimmv; break;
414 case 0x3: result = (r_1v << 10) | (1023 & rimmv); break;
415 case 0x4: result = r_1v & rimmv; break;
416 case 0x5: result = r_1v | rimmv; break;
417 case 0x6: result = r_1v ^ rimmv; break;
418 case 0x7: result = ~(r_1v ^ rimmv); break;
419 case 0x8: result = r_1v << rimmv; break;
420 case 0x9: result = r_1v >> rimmv; break;
421 case 0xa: result = (int32_t)r_1v >> rimmv; break;
422 case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break;
423 case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break;
424 case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break;
425 case 0xe: result = flip (r_1v, rimmv); break;
426 default:
427 sim_io_eprintf (sd, "Unhandled alu %#x\n", al);
428 ILLEGAL ();
429 }
430 if (upper == FT32_PAT_ALUOP)
431 cpu->state.regs[r_d] = result;
432 else
433 {
434 uint32_t dwmask = 0;
435 int dwsiz = 0;
436 int zero;
437 int sign;
438 int ahi;
439 int bhi;
440 int overflow;
441 int carry;
442 int bit;
443 uint64_t ra;
444 uint64_t rb;
445 int above;
446 int greater;
447 int greatereq;
448
449 switch (dw)
450 {
451 case 0: dwsiz = 7; dwmask = 0xffU; break;
452 case 1: dwsiz = 15; dwmask = 0xffffU; break;
453 case 2: dwsiz = 31; dwmask = 0xffffffffU; break;
454 }
455
456 zero = (0 == (result & dwmask));
457 sign = 1 & (result >> dwsiz);
458 ahi = 1 & (r_1v >> dwsiz);
459 bhi = 1 & (rimmv >> dwsiz);
460 overflow = (sign != ahi) & (ahi == !bhi);
461 bit = (dwsiz + 1);
462 ra = r_1v & dwmask;
463 rb = rimmv & dwmask;
464 switch (al)
465 {
466 case 0x0: carry = 1 & ((ra + rb) >> bit); break;
467 case 0x2: carry = 1 & ((ra - rb) >> bit); break;
468 default: carry = 0; break;
469 }
470 above = (!carry & !zero);
471 greater = (sign == overflow) & !zero;
472 greatereq = (sign == overflow);
473
474 cpu->state.regs[r_d] = (
475 (above << 6) |
476 (greater << 5) |
477 (greatereq << 4) |
478 (sign << 3) |
479 (overflow << 2) |
480 (carry << 1) |
481 (zero << 0));
482 }
483 }
484 break;
485
486 case FT32_PAT_LDK:
487 cpu->state.regs[r_d] = k20;
488 break;
489
490 case FT32_PAT_LPM:
491 cpu->state.regs[r_d] = ft32_read_item (sd, dw, pa << 2);
492 cpu->state.cycles += 1;
493 break;
494
495 case FT32_PAT_LPMI:
496 cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k8);
497 cpu->state.cycles += 1;
498 break;
499
500 case FT32_PAT_STA:
501 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
502 break;
503
504 case FT32_PAT_STI:
505 cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k8, cpu->state.regs[r_1]);
506 break;
507
508 case FT32_PAT_LDA:
509 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, aa);
510 cpu->state.cycles += 1;
511 break;
512
513 case FT32_PAT_LDI:
514 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k8);
515 cpu->state.cycles += 1;
516 break;
517
518 case FT32_PAT_EXA:
519 {
520 uint32_t tmp;
521 tmp = cpu_mem_read (sd, dw, aa);
522 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
523 cpu->state.regs[r_d] = tmp;
524 cpu->state.cycles += 1;
525 }
526 break;
527
528 case FT32_PAT_EXI:
529 {
530 uint32_t tmp;
531 tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k8);
532 cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k8, cpu->state.regs[r_d]);
533 cpu->state.regs[r_d] = tmp;
534 cpu->state.cycles += 1;
535 }
536 break;
537
538 case FT32_PAT_PUSH:
539 ft32_push (sd, r_1v);
540 break;
541
542 case FT32_PAT_LINK:
543 ft32_push (sd, cpu->state.regs[r_d]);
544 cpu->state.regs[r_d] = cpu->state.regs[FT32_HARD_SP];
545 cpu->state.regs[FT32_HARD_SP] -= k16;
546 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
547 break;
548
549 case FT32_PAT_UNLINK:
550 cpu->state.regs[FT32_HARD_SP] = cpu->state.regs[r_d];
551 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
552 cpu->state.regs[r_d] = ft32_pop (sd);
553 break;
554
555 case FT32_PAT_POP:
556 cpu->state.cycles += 1;
557 cpu->state.regs[r_d] = ft32_pop (sd);
558 break;
559
560 case FT32_PAT_RETURN:
561 cpu->state.pc = ft32_pop (sd);
562 break;
563
564 case FT32_PAT_FFUOP:
565 switch (al)
566 {
567 case 0x0:
568 cpu->state.regs[r_d] = r_1v / rimmv;
569 break;
570 case 0x1:
571 cpu->state.regs[r_d] = r_1v % rimmv;
572 break;
573 case 0x2:
574 cpu->state.regs[r_d] = ft32sdiv (r_1v, rimmv);
575 break;
576 case 0x3:
577 cpu->state.regs[r_d] = ft32smod (r_1v, rimmv);
578 break;
579
580 case 0x4:
581 {
582 /* strcmp instruction. */
583 uint32_t a = r_1v;
584 uint32_t b = rimmv;
585 uint32_t i = 0;
586 while ((GET_BYTE (a + i) != 0) &&
587 (GET_BYTE (a + i) == GET_BYTE (b + i)))
588 i++;
589 cpu->state.regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i);
590 }
591 break;
592
593 case 0x5:
594 {
595 /* memcpy instruction. */
596 uint32_t src = r_1v;
597 uint32_t dst = cpu->state.regs[r_d];
598 uint32_t i;
599 for (i = 0; i < rimmv; i++)
600 PUT_BYTE (dst + i, GET_BYTE (src + i));
601 }
602 break;
603 case 0x6:
604 {
605 /* strlen instruction. */
606 uint32_t src = r_1v;
607 uint32_t i;
608 for (i = 0; GET_BYTE (src + i) != 0; i++)
609 ;
610 cpu->state.regs[r_d] = i;
611 }
612 break;
613 case 0x7:
614 {
615 /* memset instruction. */
616 uint32_t dst = cpu->state.regs[r_d];
617 uint32_t i;
618 for (i = 0; i < rimmv; i++)
619 PUT_BYTE (dst + i, r_1v);
620 }
621 break;
622 case 0x8:
623 cpu->state.regs[r_d] = r_1v * rimmv;
624 break;
625 case 0x9:
626 cpu->state.regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32;
627 break;
628 case 0xa:
629 {
630 /* stpcpy instruction. */
631 uint32_t src = r_1v;
632 uint32_t dst = cpu->state.regs[r_d];
633 uint32_t i;
634 for (i = 0; GET_BYTE (src + i) != 0; i++)
635 PUT_BYTE (dst + i, GET_BYTE (src + i));
636 PUT_BYTE (dst + i, 0);
637 cpu->state.regs[r_d] = dst + i;
638 }
639 break;
640 case 0xe:
641 {
642 /* streamout instruction. */
643 uint32_t i;
644 uint32_t src = cpu->state.regs[r_1];
645 for (i = 0; i < rimmv; i += (1 << dw))
646 {
647 cpu_mem_write (sd,
648 dw,
649 cpu->state.regs[r_d],
650 cpu_mem_read (sd, dw, src));
651 src += (1 << dw);
652 }
653 }
654 break;
655 default:
656 sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc);
657 ILLEGAL ();
658 }
659 break;
660
661 default:
662 sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc);
663 ILLEGAL ();
664 }
665 cpu->state.num_i++;
666
667escape:
668 ;
669}
670
671void
672sim_engine_run (SIM_DESC sd,
673 int next_cpu_nr, /* ignore */
674 int nr_cpus, /* ignore */
675 int siggnal) /* ignore */
676{
677 sim_cpu *cpu;
678
679 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
680
681 cpu = STATE_CPU (sd, 0);
682
683 while (1)
684 {
685 step_once (sd);
686 if (sim_events_tick (sd))
687 sim_events_process (sd);
688 }
689}
690
f46e4eb7
JB		 691static uint32_t *
692ft32_lookup_register (SIM_CPU *cpu, int nr)
693{
694 /* Handle the register number translation here.
695 * Sim registers are 0-31.
696 * Other tools (gcc, gdb) use:
697 * 0 - fp
698 * 1 - sp
699 * 2 - r0
700 * 31 - cc
701 */
702
703 if ((nr < 0) || (nr > 32))
704 {
705 sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr);
706 abort ();
707 }
708
709 switch (nr)
710 {
711 case FT32_FP_REGNUM:
712 return &cpu->state.regs[FT32_HARD_FP];
713 case FT32_SP_REGNUM:
714 return &cpu->state.regs[FT32_HARD_SP];
715 case FT32_CC_REGNUM:
716 return &cpu->state.regs[FT32_HARD_CC];
717 case FT32_PC_REGNUM:
718 return &cpu->state.pc;
719 default:
720 return &cpu->state.regs[nr - 2];
721 }
722}
723
724static int
725ft32_reg_store (SIM_CPU *cpu,
726 int rn,
727 unsigned char *memory,
728 int length)
729{
730 if (0 <= rn && rn <= 32)
731 {
732 if (length == 4)
733 *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4);
734
735 return 4;
736 }
737 else
738 return 0;
739}
740
741static int
742ft32_reg_fetch (SIM_CPU *cpu,
743 int rn,
744 unsigned char *memory,
745 int length)
746{
747 if (0 <= rn && rn <= 32)
748 {
749 if (length == 4)
750 ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn));
751
752 return 4;
753 }
754 else
755 return 0;
756}
757
758static sim_cia
759ft32_pc_get (SIM_CPU *cpu)
760{
761 return 32;
762}
763
764static void
765ft32_pc_set (SIM_CPU *cpu, sim_cia newpc)
766{
767 cpu->state.pc = newpc;
768}
769
770/* Cover function of sim_state_free to free the cpu buffers as well. */
771
772static void
773free_state (SIM_DESC sd)
774{
775 if (STATE_MODULES (sd) != NULL)
776 sim_module_uninstall (sd);
777 sim_cpu_free_all (sd);
778 sim_state_free (sd);
779}
780
781SIM_DESC
782sim_open (SIM_OPEN_KIND kind,
783 host_callback *cb,
784 struct bfd *abfd,
785 char **argv)
786{
787 char c;
788 size_t i;
789 SIM_DESC sd = sim_state_alloc (kind, cb);
790
791 /* The cpu data is kept in a separately allocated chunk of memory. */
792 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
793 {
794 free_state (sd);
795 return 0;
796 }
797
798 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
799 {
800 free_state (sd);
801 return 0;
802 }
803
804 /* getopt will print the error message so we just have to exit if this fails.
805 FIXME: Hmmm... in the case of gdb we need getopt to call
806 print_filtered. */
807 if (sim_parse_args (sd, argv) != SIM_RC_OK)
808 {
809 free_state (sd);
810 return 0;
811 }
812
813 /* Allocate external memory if none specified by user.
814 Use address 4 here in case the user wanted address 0 unmapped. */
815 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
816 {
817 sim_do_command (sd, "memory region 0x00000000,0x40000");
818 sim_do_command (sd, "memory region 0x800000,0x10000");
819 }
820
821 /* Check for/establish the reference program image. */
822 if (sim_analyze_program (sd,
823 (STATE_PROG_ARGV (sd) != NULL
824 ? *STATE_PROG_ARGV (sd)
825 : NULL), abfd) != SIM_RC_OK)
826 {
827 free_state (sd);
828 return 0;
829 }
830
831 /* Configure/verify the target byte order and other runtime
832 configuration options. */
833 if (sim_config (sd) != SIM_RC_OK)
834 {
835 free_state (sd);
836 return 0;
837 }
838
839 if (sim_post_argv_init (sd) != SIM_RC_OK)
840 {
841 free_state (sd);
842 return 0;
843 }
844
845 /* CPU specific initialization. */
846 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
847 {
848 SIM_CPU *cpu = STATE_CPU (sd, i);
849
850 CPU_REG_FETCH (cpu) = ft32_reg_fetch;
851 CPU_REG_STORE (cpu) = ft32_reg_store;
852 CPU_PC_FETCH (cpu) = ft32_pc_get;
853 CPU_PC_STORE (cpu) = ft32_pc_set;
854 }
855
856 return sd;
857}
858
859void
860sim_close (SIM_DESC sd, int quitting)
861{
862 sim_module_uninstall (sd);
863}
864
865SIM_RC
866sim_create_inferior (SIM_DESC sd,
867 struct bfd *abfd,
868 char **argv,
869 char **env)
870{
871 uint32_t addr;
872 sim_cpu *cpu = STATE_CPU (sd, 0);
873
874 /* Set the PC. */
875 if (abfd != NULL)
876 addr = bfd_get_start_address (abfd);
877 else
878 addr = 0;
879
880 if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
881 {
882 freeargv (STATE_PROG_ARGV (sd));
883 STATE_PROG_ARGV (sd) = dupargv (argv);
884 }
885 cpu->state.regs[FT32_HARD_SP] = addr;
886 cpu->state.num_i = 0;
887 cpu->state.cycles = 0;
888 cpu->state.next_tick_cycle = 100000;
889
890 return SIM_RC_OK;
891}
A mirror of the official binutils-gdb repository