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Regenerate cgen-derived files.
[thirdparty/binutils-gdb.git] / sim / lm32 / sem-switch.c
CommitLineData
c28c63d8
JB		 1/* Simulator instruction semantics for lm32bf.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
0f51e9bf 5Copyright 1996-2010 Free Software Foundation, Inc.
c28c63d8
JB		 6
7This file is part of the GNU simulators.
8
fb067cad
DE		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
c28c63d8 13
fb067cad
DE		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
c28c63d8 18
fb067cad
DE		 19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
c28c63d8
JB		 22
23*/
24
25#ifdef DEFINE_LABELS
26
27 /* The labels have the case they have because the enum of insn types
28 is all uppercase and in the non-stdc case the insn symbol is built
29 into the enum name. */
30
31 static struct {
32 int index;
33 void *label;
34 } labels[] = {
35 { LM32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
36 { LM32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
37 { LM32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
38 { LM32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
39 { LM32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
40 { LM32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
41 { LM32BF_INSN_ADD, && case_sem_INSN_ADD },
42 { LM32BF_INSN_ADDI, && case_sem_INSN_ADDI },
43 { LM32BF_INSN_AND, && case_sem_INSN_AND },
44 { LM32BF_INSN_ANDI, && case_sem_INSN_ANDI },
45 { LM32BF_INSN_ANDHII, && case_sem_INSN_ANDHII },
46 { LM32BF_INSN_B, && case_sem_INSN_B },
47 { LM32BF_INSN_BI, && case_sem_INSN_BI },
48 { LM32BF_INSN_BE, && case_sem_INSN_BE },
49 { LM32BF_INSN_BG, && case_sem_INSN_BG },
50 { LM32BF_INSN_BGE, && case_sem_INSN_BGE },
51 { LM32BF_INSN_BGEU, && case_sem_INSN_BGEU },
52 { LM32BF_INSN_BGU, && case_sem_INSN_BGU },
53 { LM32BF_INSN_BNE, && case_sem_INSN_BNE },
54 { LM32BF_INSN_CALL, && case_sem_INSN_CALL },
55 { LM32BF_INSN_CALLI, && case_sem_INSN_CALLI },
56 { LM32BF_INSN_CMPE, && case_sem_INSN_CMPE },
57 { LM32BF_INSN_CMPEI, && case_sem_INSN_CMPEI },
58 { LM32BF_INSN_CMPG, && case_sem_INSN_CMPG },
59 { LM32BF_INSN_CMPGI, && case_sem_INSN_CMPGI },
60 { LM32BF_INSN_CMPGE, && case_sem_INSN_CMPGE },
61 { LM32BF_INSN_CMPGEI, && case_sem_INSN_CMPGEI },
62 { LM32BF_INSN_CMPGEU, && case_sem_INSN_CMPGEU },
63 { LM32BF_INSN_CMPGEUI, && case_sem_INSN_CMPGEUI },
64 { LM32BF_INSN_CMPGU, && case_sem_INSN_CMPGU },
65 { LM32BF_INSN_CMPGUI, && case_sem_INSN_CMPGUI },
66 { LM32BF_INSN_CMPNE, && case_sem_INSN_CMPNE },
67 { LM32BF_INSN_CMPNEI, && case_sem_INSN_CMPNEI },
68 { LM32BF_INSN_DIVU, && case_sem_INSN_DIVU },
69 { LM32BF_INSN_LB, && case_sem_INSN_LB },
70 { LM32BF_INSN_LBU, && case_sem_INSN_LBU },
71 { LM32BF_INSN_LH, && case_sem_INSN_LH },
72 { LM32BF_INSN_LHU, && case_sem_INSN_LHU },
73 { LM32BF_INSN_LW, && case_sem_INSN_LW },
74 { LM32BF_INSN_MODU, && case_sem_INSN_MODU },
75 { LM32BF_INSN_MUL, && case_sem_INSN_MUL },
76 { LM32BF_INSN_MULI, && case_sem_INSN_MULI },
77 { LM32BF_INSN_NOR, && case_sem_INSN_NOR },
78 { LM32BF_INSN_NORI, && case_sem_INSN_NORI },
79 { LM32BF_INSN_OR, && case_sem_INSN_OR },
80 { LM32BF_INSN_ORI, && case_sem_INSN_ORI },
81 { LM32BF_INSN_ORHII, && case_sem_INSN_ORHII },
82 { LM32BF_INSN_RCSR, && case_sem_INSN_RCSR },
83 { LM32BF_INSN_SB, && case_sem_INSN_SB },
84 { LM32BF_INSN_SEXTB, && case_sem_INSN_SEXTB },
85 { LM32BF_INSN_SEXTH, && case_sem_INSN_SEXTH },
86 { LM32BF_INSN_SH, && case_sem_INSN_SH },
87 { LM32BF_INSN_SL, && case_sem_INSN_SL },
88 { LM32BF_INSN_SLI, && case_sem_INSN_SLI },
89 { LM32BF_INSN_SR, && case_sem_INSN_SR },
90 { LM32BF_INSN_SRI, && case_sem_INSN_SRI },
91 { LM32BF_INSN_SRU, && case_sem_INSN_SRU },
92 { LM32BF_INSN_SRUI, && case_sem_INSN_SRUI },
93 { LM32BF_INSN_SUB, && case_sem_INSN_SUB },
94 { LM32BF_INSN_SW, && case_sem_INSN_SW },
95 { LM32BF_INSN_USER, && case_sem_INSN_USER },
96 { LM32BF_INSN_WCSR, && case_sem_INSN_WCSR },
97 { LM32BF_INSN_XOR, && case_sem_INSN_XOR },
98 { LM32BF_INSN_XORI, && case_sem_INSN_XORI },
99 { LM32BF_INSN_XNOR, && case_sem_INSN_XNOR },
100 { LM32BF_INSN_XNORI, && case_sem_INSN_XNORI },
101 { LM32BF_INSN_BREAK, && case_sem_INSN_BREAK },
102 { LM32BF_INSN_SCALL, && case_sem_INSN_SCALL },
103 { 0, 0 }
104 };
105 int i;
106
107 for (i = 0; labels[i].label != 0; ++i)
108 {
109#if FAST_P
110 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
111#else
112 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
113#endif
114 }
115
116#undef DEFINE_LABELS
117#endif /* DEFINE_LABELS */
118
119#ifdef DEFINE_SWITCH
120
121/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
122 off frills like tracing and profiling. */
123/* FIXME: A better way would be to have TRACE_RESULT check for something
124 that can cause it to be optimized out. Another way would be to emit
125 special handlers into the instruction "stream". */
126
127#if FAST_P
128#undef TRACE_RESULT
129#define TRACE_RESULT(cpu, abuf, name, type, val)
130#endif
131
132#undef GET_ATTR
c28c63d8 133#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
c28c63d8
JB		 134
135{
136
137#if WITH_SCACHE_PBB
138
139/* Branch to next handler without going around main loop. */
140#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
141SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
142
143#else /* ! WITH_SCACHE_PBB */
144
145#define NEXT(vpc) BREAK (sem)
146#ifdef __GNUC__
147#if FAST_P
148 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
149#else
150 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
151#endif
152#else
153 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
154#endif
155
156#endif /* ! WITH_SCACHE_PBB */
157
158 {
159
160 CASE (sem, INSN_X_INVALID) : /* --invalid-- */
161{
162 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
163 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2310652a 164#define FLD(f) abuf->fields.sfmt_empty.f
c28c63d8
JB		 165 int UNUSED written = 0;
166 IADDR UNUSED pc = abuf->addr;
167 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
168
169 {
170 /* Update the recorded pc in the cpu state struct.
171 Only necessary for WITH_SCACHE case, but to avoid the
172 conditional compilation .... */
173 SET_H_PC (pc);
174 /* Virtual insns have zero size. Overwrite vpc with address of next insn
175 using the default-insn-bitsize spec. When executing insns in parallel
176 we may want to queue the fault and continue execution. */
177 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
178 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
179 }
180
181#undef FLD
182}
183 NEXT (vpc);
184
185 CASE (sem, INSN_X_AFTER) : /* --after-- */
186{
187 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
188 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2310652a 189#define FLD(f) abuf->fields.sfmt_empty.f
c28c63d8
JB		 190 int UNUSED written = 0;
191 IADDR UNUSED pc = abuf->addr;
192 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
193
194 {
195#if WITH_SCACHE_PBB_LM32BF
196 lm32bf_pbb_after (current_cpu, sem_arg);
197#endif
198 }
199
200#undef FLD
201}
202 NEXT (vpc);
203
204 CASE (sem, INSN_X_BEFORE) : /* --before-- */
205{
206 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
207 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2310652a 208#define FLD(f) abuf->fields.sfmt_empty.f
c28c63d8
JB		 209 int UNUSED written = 0;
210 IADDR UNUSED pc = abuf->addr;
211 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
212
213 {
214#if WITH_SCACHE_PBB_LM32BF
215 lm32bf_pbb_before (current_cpu, sem_arg);
216#endif
217 }
218
219#undef FLD
220}
221 NEXT (vpc);
222
223 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
224{
225 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
226 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2310652a 227#define FLD(f) abuf->fields.sfmt_empty.f
c28c63d8
JB		 228 int UNUSED written = 0;
229 IADDR UNUSED pc = abuf->addr;
230 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
231
232 {
233#if WITH_SCACHE_PBB_LM32BF
234#ifdef DEFINE_SWITCH
235 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
236 pbb_br_type, pbb_br_npc);
237 BREAK (sem);
238#else
239 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
240 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
241 CPU_PBB_BR_TYPE (current_cpu),
242 CPU_PBB_BR_NPC (current_cpu));
243#endif
244#endif
245 }
246
247#undef FLD
248}
249 NEXT (vpc);
250
251 CASE (sem, INSN_X_CHAIN) : /* --chain-- */
252{
253 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
254 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2310652a 255#define FLD(f) abuf->fields.sfmt_empty.f
c28c63d8
JB		 256 int UNUSED written = 0;
257 IADDR UNUSED pc = abuf->addr;
258 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
259
260 {
261#if WITH_SCACHE_PBB_LM32BF
262 vpc = lm32bf_pbb_chain (current_cpu, sem_arg);
263#ifdef DEFINE_SWITCH
264 BREAK (sem);
265#endif
266#endif
267 }
268
269#undef FLD
270}
271 NEXT (vpc);
272
273 CASE (sem, INSN_X_BEGIN) : /* --begin-- */
274{
275 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
276 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2310652a 277#define FLD(f) abuf->fields.sfmt_empty.f
c28c63d8
JB		 278 int UNUSED written = 0;
279 IADDR UNUSED pc = abuf->addr;
280 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
281
282 {
283#if WITH_SCACHE_PBB_LM32BF
284#if defined DEFINE_SWITCH || defined FAST_P
285 /* In the switch case FAST_P is a constant, allowing several optimizations
286 in any called inline functions. */
287 vpc = lm32bf_pbb_begin (current_cpu, FAST_P);
288#else
289#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
290 vpc = lm32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
291#else
292 vpc = lm32bf_pbb_begin (current_cpu, 0);
293#endif
294#endif
295#endif
296 }
297
298#undef FLD
299}
300 NEXT (vpc);
301
302 CASE (sem, INSN_ADD) : /* add $r2,$r0,$r1 */
303{
304 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
305 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
306#define FLD(f) abuf->fields.sfmt_user.f
307 int UNUSED written = 0;
308 IADDR UNUSED pc = abuf->addr;
309 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
310
311 {
312 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
313 CPU (h_gr[FLD (f_r2)]) = opval;
314 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
315 }
316
317#undef FLD
318}
319 NEXT (vpc);
320
321 CASE (sem, INSN_ADDI) : /* addi $r1,$r0,$imm */
322{
323 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
324 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
325#define FLD(f) abuf->fields.sfmt_addi.f
326 int UNUSED written = 0;
327 IADDR UNUSED pc = abuf->addr;
328 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
329
330 {
331 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
332 CPU (h_gr[FLD (f_r1)]) = opval;
333 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
334 }
335
336#undef FLD
337}
338 NEXT (vpc);
339
340 CASE (sem, INSN_AND) : /* and $r2,$r0,$r1 */
341{
342 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
343 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
344#define FLD(f) abuf->fields.sfmt_user.f
345 int UNUSED written = 0;
346 IADDR UNUSED pc = abuf->addr;
347 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
348
349 {
350 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
351 CPU (h_gr[FLD (f_r2)]) = opval;
352 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
353 }
354
355#undef FLD
356}
357 NEXT (vpc);
358
359 CASE (sem, INSN_ANDI) : /* andi $r1,$r0,$uimm */
360{
361 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
362 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
363#define FLD(f) abuf->fields.sfmt_andi.f
364 int UNUSED written = 0;
365 IADDR UNUSED pc = abuf->addr;
366 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
367
368 {
369 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
370 CPU (h_gr[FLD (f_r1)]) = opval;
371 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
372 }
373
374#undef FLD
375}
376 NEXT (vpc);
377
378 CASE (sem, INSN_ANDHII) : /* andhi $r1,$r0,$hi16 */
379{
380 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
381 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
382#define FLD(f) abuf->fields.sfmt_andi.f
383 int UNUSED written = 0;
384 IADDR UNUSED pc = abuf->addr;
385 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
386
387 {
388 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));
389 CPU (h_gr[FLD (f_r1)]) = opval;
390 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
391 }
392
393#undef FLD
394}
395 NEXT (vpc);
396
397 CASE (sem, INSN_B) : /* b $r0 */
398{
399 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
400 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
401#define FLD(f) abuf->fields.sfmt_be.f
402 int UNUSED written = 0;
403 IADDR UNUSED pc = abuf->addr;
404 SEM_BRANCH_INIT
405 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
406
407 {
408 USI opval = lm32bf_b_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), FLD (f_r0));
409 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
410 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
411 }
412
413 SEM_BRANCH_FINI (vpc);
414#undef FLD
415}
416 NEXT (vpc);
417
418 CASE (sem, INSN_BI) : /* bi $call */
419{
420 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
421 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
422#define FLD(f) abuf->fields.sfmt_bi.f
423 int UNUSED written = 0;
424 IADDR UNUSED pc = abuf->addr;
425 SEM_BRANCH_INIT
426 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
427
428 {
429 USI opval = EXTSISI (FLD (i_call));
430 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
431 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
432 }
433
434 SEM_BRANCH_FINI (vpc);
435#undef FLD
436}
437 NEXT (vpc);
438
439 CASE (sem, INSN_BE) : /* be $r0,$r1,$branch */
440{
441 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
442 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
443#define FLD(f) abuf->fields.sfmt_be.f
444 int UNUSED written = 0;
445 IADDR UNUSED pc = abuf->addr;
446 SEM_BRANCH_INIT
447 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
448
449if (EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
450 {
451 USI opval = FLD (i_branch);
452 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
453 written |= (1 << 3);
454 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
455 }
456}
457
458 abuf->written = written;
459 SEM_BRANCH_FINI (vpc);
460#undef FLD
461}
462 NEXT (vpc);
463
464 CASE (sem, INSN_BG) : /* bg $r0,$r1,$branch */
465{
466 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
467 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
468#define FLD(f) abuf->fields.sfmt_be.f
469 int UNUSED written = 0;
470 IADDR UNUSED pc = abuf->addr;
471 SEM_BRANCH_INIT
472 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
473
474if (GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
475 {
476 USI opval = FLD (i_branch);
477 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
478 written |= (1 << 3);
479 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
480 }
481}
482
483 abuf->written = written;
484 SEM_BRANCH_FINI (vpc);
485#undef FLD
486}
487 NEXT (vpc);
488
489 CASE (sem, INSN_BGE) : /* bge $r0,$r1,$branch */
490{
491 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
492 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
493#define FLD(f) abuf->fields.sfmt_be.f
494 int UNUSED written = 0;
495 IADDR UNUSED pc = abuf->addr;
496 SEM_BRANCH_INIT
497 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
498
499if (GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
500 {
501 USI opval = FLD (i_branch);
502 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
503 written |= (1 << 3);
504 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
505 }
506}
507
508 abuf->written = written;
509 SEM_BRANCH_FINI (vpc);
510#undef FLD
511}
512 NEXT (vpc);
513
514 CASE (sem, INSN_BGEU) : /* bgeu $r0,$r1,$branch */
515{
516 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
517 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
518#define FLD(f) abuf->fields.sfmt_be.f
519 int UNUSED written = 0;
520 IADDR UNUSED pc = abuf->addr;
521 SEM_BRANCH_INIT
522 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
523
524if (GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
525 {
526 USI opval = FLD (i_branch);
527 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
528 written |= (1 << 3);
529 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
530 }
531}
532
533 abuf->written = written;
534 SEM_BRANCH_FINI (vpc);
535#undef FLD
536}
537 NEXT (vpc);
538
539 CASE (sem, INSN_BGU) : /* bgu $r0,$r1,$branch */
540{
541 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
542 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
543#define FLD(f) abuf->fields.sfmt_be.f
544 int UNUSED written = 0;
545 IADDR UNUSED pc = abuf->addr;
546 SEM_BRANCH_INIT
547 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
548
549if (GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
550 {
551 USI opval = FLD (i_branch);
552 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
553 written |= (1 << 3);
554 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
555 }
556}
557
558 abuf->written = written;
559 SEM_BRANCH_FINI (vpc);
560#undef FLD
561}
562 NEXT (vpc);
563
564 CASE (sem, INSN_BNE) : /* bne $r0,$r1,$branch */
565{
566 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
567 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
568#define FLD(f) abuf->fields.sfmt_be.f
569 int UNUSED written = 0;
570 IADDR UNUSED pc = abuf->addr;
571 SEM_BRANCH_INIT
572 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
573
574if (NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
575 {
576 USI opval = FLD (i_branch);
577 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
578 written |= (1 << 3);
579 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
580 }
581}
582
583 abuf->written = written;
584 SEM_BRANCH_FINI (vpc);
585#undef FLD
586}
587 NEXT (vpc);
588
589 CASE (sem, INSN_CALL) : /* call $r0 */
590{
591 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
592 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
593#define FLD(f) abuf->fields.sfmt_be.f
594 int UNUSED written = 0;
595 IADDR UNUSED pc = abuf->addr;
596 SEM_BRANCH_INIT
597 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
598
599{
600 {
601 SI opval = ADDSI (pc, 4);
602 CPU (h_gr[((UINT) 29)]) = opval;
603 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
604 }
605 {
606 USI opval = CPU (h_gr[FLD (f_r0)]);
607 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
608 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
609 }
610}
611
612 SEM_BRANCH_FINI (vpc);
613#undef FLD
614}
615 NEXT (vpc);
616
617 CASE (sem, INSN_CALLI) : /* calli $call */
618{
619 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
620 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
621#define FLD(f) abuf->fields.sfmt_bi.f
622 int UNUSED written = 0;
623 IADDR UNUSED pc = abuf->addr;
624 SEM_BRANCH_INIT
625 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
626
627{
628 {
629 SI opval = ADDSI (pc, 4);
630 CPU (h_gr[((UINT) 29)]) = opval;
631 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
632 }
633 {
634 USI opval = EXTSISI (FLD (i_call));
635 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
636 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
637 }
638}
639
640 SEM_BRANCH_FINI (vpc);
641#undef FLD
642}
643 NEXT (vpc);
644
645 CASE (sem, INSN_CMPE) : /* cmpe $r2,$r0,$r1 */
646{
647 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
648 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
649#define FLD(f) abuf->fields.sfmt_user.f
650 int UNUSED written = 0;
651 IADDR UNUSED pc = abuf->addr;
652 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
653
654 {
655 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
656 CPU (h_gr[FLD (f_r2)]) = opval;
657 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
658 }
659
660#undef FLD
661}
662 NEXT (vpc);
663
664 CASE (sem, INSN_CMPEI) : /* cmpei $r1,$r0,$imm */
665{
666 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
667 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
668#define FLD(f) abuf->fields.sfmt_addi.f
669 int UNUSED written = 0;
670 IADDR UNUSED pc = abuf->addr;
671 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
672
673 {
674 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
675 CPU (h_gr[FLD (f_r1)]) = opval;
676 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
677 }
678
679#undef FLD
680}
681 NEXT (vpc);
682
683 CASE (sem, INSN_CMPG) : /* cmpg $r2,$r0,$r1 */
684{
685 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
686 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
687#define FLD(f) abuf->fields.sfmt_user.f
688 int UNUSED written = 0;
689 IADDR UNUSED pc = abuf->addr;
690 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
691
692 {
693 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
694 CPU (h_gr[FLD (f_r2)]) = opval;
695 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
696 }
697
698#undef FLD
699}
700 NEXT (vpc);
701
702 CASE (sem, INSN_CMPGI) : /* cmpgi $r1,$r0,$imm */
703{
704 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
705 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
706#define FLD(f) abuf->fields.sfmt_addi.f
707 int UNUSED written = 0;
708 IADDR UNUSED pc = abuf->addr;
709 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
710
711 {
712 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
713 CPU (h_gr[FLD (f_r1)]) = opval;
714 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
715 }
716
717#undef FLD
718}
719 NEXT (vpc);
720
721 CASE (sem, INSN_CMPGE) : /* cmpge $r2,$r0,$r1 */
722{
723 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
724 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
725#define FLD(f) abuf->fields.sfmt_user.f
726 int UNUSED written = 0;
727 IADDR UNUSED pc = abuf->addr;
728 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
729
730 {
731 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
732 CPU (h_gr[FLD (f_r2)]) = opval;
733 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
734 }
735
736#undef FLD
737}
738 NEXT (vpc);
739
740 CASE (sem, INSN_CMPGEI) : /* cmpgei $r1,$r0,$imm */
741{
742 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
743 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
744#define FLD(f) abuf->fields.sfmt_addi.f
745 int UNUSED written = 0;
746 IADDR UNUSED pc = abuf->addr;
747 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
748
749 {
750 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
751 CPU (h_gr[FLD (f_r1)]) = opval;
752 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
753 }
754
755#undef FLD
756}
757 NEXT (vpc);
758
759 CASE (sem, INSN_CMPGEU) : /* cmpgeu $r2,$r0,$r1 */
760{
761 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
762 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
763#define FLD(f) abuf->fields.sfmt_user.f
764 int UNUSED written = 0;
765 IADDR UNUSED pc = abuf->addr;
766 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
767
768 {
769 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
770 CPU (h_gr[FLD (f_r2)]) = opval;
771 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
772 }
773
774#undef FLD
775}
776 NEXT (vpc);
777
778 CASE (sem, INSN_CMPGEUI) : /* cmpgeui $r1,$r0,$uimm */
779{
780 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
781 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
782#define FLD(f) abuf->fields.sfmt_andi.f
783 int UNUSED written = 0;
784 IADDR UNUSED pc = abuf->addr;
785 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
786
787 {
788 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
789 CPU (h_gr[FLD (f_r1)]) = opval;
790 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
791 }
792
793#undef FLD
794}
795 NEXT (vpc);
796
797 CASE (sem, INSN_CMPGU) : /* cmpgu $r2,$r0,$r1 */
798{
799 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
800 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
801#define FLD(f) abuf->fields.sfmt_user.f
802 int UNUSED written = 0;
803 IADDR UNUSED pc = abuf->addr;
804 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
805
806 {
807 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
808 CPU (h_gr[FLD (f_r2)]) = opval;
809 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
810 }
811
812#undef FLD
813}
814 NEXT (vpc);
815
816 CASE (sem, INSN_CMPGUI) : /* cmpgui $r1,$r0,$uimm */
817{
818 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
819 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
820#define FLD(f) abuf->fields.sfmt_andi.f
821 int UNUSED written = 0;
822 IADDR UNUSED pc = abuf->addr;
823 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
824
825 {
826 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
827 CPU (h_gr[FLD (f_r1)]) = opval;
828 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
829 }
830
831#undef FLD
832}
833 NEXT (vpc);
834
835 CASE (sem, INSN_CMPNE) : /* cmpne $r2,$r0,$r1 */
836{
837 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
838 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
839#define FLD(f) abuf->fields.sfmt_user.f
840 int UNUSED written = 0;
841 IADDR UNUSED pc = abuf->addr;
842 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
843
844 {
845 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
846 CPU (h_gr[FLD (f_r2)]) = opval;
847 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
848 }
849
850#undef FLD
851}
852 NEXT (vpc);
853
854 CASE (sem, INSN_CMPNEI) : /* cmpnei $r1,$r0,$imm */
855{
856 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
857 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
858#define FLD(f) abuf->fields.sfmt_addi.f
859 int UNUSED written = 0;
860 IADDR UNUSED pc = abuf->addr;
861 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
862
863 {
864 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
865 CPU (h_gr[FLD (f_r1)]) = opval;
866 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
867 }
868
869#undef FLD
870}
871 NEXT (vpc);
872
873 CASE (sem, INSN_DIVU) : /* divu $r2,$r0,$r1 */
874{
875 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
876 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
877#define FLD(f) abuf->fields.sfmt_user.f
878 int UNUSED written = 0;
879 IADDR UNUSED pc = abuf->addr;
880 SEM_BRANCH_INIT
881 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
882
883 {
884 USI opval = lm32bf_divu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
885 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
886 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
887 }
888
889 SEM_BRANCH_FINI (vpc);
890#undef FLD
891}
892 NEXT (vpc);
893
894 CASE (sem, INSN_LB) : /* lb $r1,($r0+$imm) */
895{
896 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
897 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
898#define FLD(f) abuf->fields.sfmt_addi.f
899 int UNUSED written = 0;
900 IADDR UNUSED pc = abuf->addr;
901 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
902
903 {
904 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
905 CPU (h_gr[FLD (f_r1)]) = opval;
906 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
907 }
908
909#undef FLD
910}
911 NEXT (vpc);
912
913 CASE (sem, INSN_LBU) : /* lbu $r1,($r0+$imm) */
914{
915 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
916 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
917#define FLD(f) abuf->fields.sfmt_addi.f
918 int UNUSED written = 0;
919 IADDR UNUSED pc = abuf->addr;
920 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
921
922 {
923 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
924 CPU (h_gr[FLD (f_r1)]) = opval;
925 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
926 }
927
928#undef FLD
929}
930 NEXT (vpc);
931
932 CASE (sem, INSN_LH) : /* lh $r1,($r0+$imm) */
933{
934 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
935 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
936#define FLD(f) abuf->fields.sfmt_addi.f
937 int UNUSED written = 0;
938 IADDR UNUSED pc = abuf->addr;
939 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
940
941 {
942 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
943 CPU (h_gr[FLD (f_r1)]) = opval;
944 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
945 }
946
947#undef FLD
948}
949 NEXT (vpc);
950
951 CASE (sem, INSN_LHU) : /* lhu $r1,($r0+$imm) */
952{
953 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
954 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
955#define FLD(f) abuf->fields.sfmt_addi.f
956 int UNUSED written = 0;
957 IADDR UNUSED pc = abuf->addr;
958 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
959
960 {
961 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
962 CPU (h_gr[FLD (f_r1)]) = opval;
963 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
964 }
965
966#undef FLD
967}
968 NEXT (vpc);
969
970 CASE (sem, INSN_LW) : /* lw $r1,($r0+$imm) */
971{
972 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
973 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
974#define FLD(f) abuf->fields.sfmt_addi.f
975 int UNUSED written = 0;
976 IADDR UNUSED pc = abuf->addr;
977 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
978
979 {
980 SI opval = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))));
981 CPU (h_gr[FLD (f_r1)]) = opval;
982 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
983 }
984
985#undef FLD
986}
987 NEXT (vpc);
988
989 CASE (sem, INSN_MODU) : /* modu $r2,$r0,$r1 */
990{
991 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
992 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
993#define FLD(f) abuf->fields.sfmt_user.f
994 int UNUSED written = 0;
995 IADDR UNUSED pc = abuf->addr;
996 SEM_BRANCH_INIT
997 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
998
999 {
1000 USI opval = lm32bf_modu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
1001 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1002 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1003 }
1004
1005 SEM_BRANCH_FINI (vpc);
1006#undef FLD
1007}
1008 NEXT (vpc);
1009
1010 CASE (sem, INSN_MUL) : /* mul $r2,$r0,$r1 */
1011{
1012 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1013 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1014#define FLD(f) abuf->fields.sfmt_user.f
1015 int UNUSED written = 0;
1016 IADDR UNUSED pc = abuf->addr;
1017 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1018
1019 {
1020 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1021 CPU (h_gr[FLD (f_r2)]) = opval;
1022 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1023 }
1024
1025#undef FLD
1026}
1027 NEXT (vpc);
1028
1029 CASE (sem, INSN_MULI) : /* muli $r1,$r0,$imm */
1030{
1031 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1032 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1033#define FLD(f) abuf->fields.sfmt_addi.f
1034 int UNUSED written = 0;
1035 IADDR UNUSED pc = abuf->addr;
1036 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1037
1038 {
1039 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
1040 CPU (h_gr[FLD (f_r1)]) = opval;
1041 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1042 }
1043
1044#undef FLD
1045}
1046 NEXT (vpc);
1047
1048 CASE (sem, INSN_NOR) : /* nor $r2,$r0,$r1 */
1049{
1050 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1051 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1052#define FLD(f) abuf->fields.sfmt_user.f
1053 int UNUSED written = 0;
1054 IADDR UNUSED pc = abuf->addr;
1055 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1056
1057 {
1058 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])));
1059 CPU (h_gr[FLD (f_r2)]) = opval;
1060 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1061 }
1062
1063#undef FLD
1064}
1065 NEXT (vpc);
1066
1067 CASE (sem, INSN_NORI) : /* nori $r1,$r0,$uimm */
1068{
1069 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1070 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1071#define FLD(f) abuf->fields.sfmt_andi.f
1072 int UNUSED written = 0;
1073 IADDR UNUSED pc = abuf->addr;
1074 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1075
1076 {
1077 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
1078 CPU (h_gr[FLD (f_r1)]) = opval;
1079 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1080 }
1081
1082#undef FLD
1083}
1084 NEXT (vpc);
1085
1086 CASE (sem, INSN_OR) : /* or $r2,$r0,$r1 */
1087{
1088 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1089 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1090#define FLD(f) abuf->fields.sfmt_user.f
1091 int UNUSED written = 0;
1092 IADDR UNUSED pc = abuf->addr;
1093 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1094
1095 {
1096 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1097 CPU (h_gr[FLD (f_r2)]) = opval;
1098 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1099 }
1100
1101#undef FLD
1102}
1103 NEXT (vpc);
1104
1105 CASE (sem, INSN_ORI) : /* ori $r1,$r0,$lo16 */
1106{
1107 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1108 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1109#define FLD(f) abuf->fields.sfmt_andi.f
1110 int UNUSED written = 0;
1111 IADDR UNUSED pc = abuf->addr;
1112 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1113
1114 {
1115 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
1116 CPU (h_gr[FLD (f_r1)]) = opval;
1117 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1118 }
1119
1120#undef FLD
1121}
1122 NEXT (vpc);
1123
1124 CASE (sem, INSN_ORHII) : /* orhi $r1,$r0,$hi16 */
1125{
1126 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1127 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1128#define FLD(f) abuf->fields.sfmt_andi.f
1129 int UNUSED written = 0;
1130 IADDR UNUSED pc = abuf->addr;
1131 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1132
1133 {
1134 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));
1135 CPU (h_gr[FLD (f_r1)]) = opval;
1136 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1137 }
1138
1139#undef FLD
1140}
1141 NEXT (vpc);
1142
1143 CASE (sem, INSN_RCSR) : /* rcsr $r2,$csr */
1144{
1145 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1146 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1147#define FLD(f) abuf->fields.sfmt_rcsr.f
1148 int UNUSED written = 0;
1149 IADDR UNUSED pc = abuf->addr;
1150 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1151
1152 {
1153 SI opval = CPU (h_csr[FLD (f_csr)]);
1154 CPU (h_gr[FLD (f_r2)]) = opval;
1155 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1156 }
1157
1158#undef FLD
1159}
1160 NEXT (vpc);
1161
1162 CASE (sem, INSN_SB) : /* sb ($r0+$imm),$r1 */
1163{
1164 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1165 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1166#define FLD(f) abuf->fields.sfmt_addi.f
1167 int UNUSED written = 0;
1168 IADDR UNUSED pc = abuf->addr;
1169 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1170
1171 {
1172 QI opval = CPU (h_gr[FLD (f_r1)]);
1173 SETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1174 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1175 }
1176
1177#undef FLD
1178}
1179 NEXT (vpc);
1180
1181 CASE (sem, INSN_SEXTB) : /* sextb $r2,$r0 */
1182{
1183 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1184 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1185#define FLD(f) abuf->fields.sfmt_user.f
1186 int UNUSED written = 0;
1187 IADDR UNUSED pc = abuf->addr;
1188 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1189
1190 {
1191 SI opval = EXTQISI (TRUNCSIQI (CPU (h_gr[FLD (f_r0)])));
1192 CPU (h_gr[FLD (f_r2)]) = opval;
1193 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1194 }
1195
1196#undef FLD
1197}
1198 NEXT (vpc);
1199
1200 CASE (sem, INSN_SEXTH) : /* sexth $r2,$r0 */
1201{
1202 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1203 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1204#define FLD(f) abuf->fields.sfmt_user.f
1205 int UNUSED written = 0;
1206 IADDR UNUSED pc = abuf->addr;
1207 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1208
1209 {
1210 SI opval = EXTHISI (TRUNCSIHI (CPU (h_gr[FLD (f_r0)])));
1211 CPU (h_gr[FLD (f_r2)]) = opval;
1212 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1213 }
1214
1215#undef FLD
1216}
1217 NEXT (vpc);
1218
1219 CASE (sem, INSN_SH) : /* sh ($r0+$imm),$r1 */
1220{
1221 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1222 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1223#define FLD(f) abuf->fields.sfmt_addi.f
1224 int UNUSED written = 0;
1225 IADDR UNUSED pc = abuf->addr;
1226 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1227
1228 {
1229 HI opval = CPU (h_gr[FLD (f_r1)]);
1230 SETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1231 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1232 }
1233
1234#undef FLD
1235}
1236 NEXT (vpc);
1237
1238 CASE (sem, INSN_SL) : /* sl $r2,$r0,$r1 */
1239{
1240 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1241 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1242#define FLD(f) abuf->fields.sfmt_user.f
1243 int UNUSED written = 0;
1244 IADDR UNUSED pc = abuf->addr;
1245 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1246
1247 {
1248 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1249 CPU (h_gr[FLD (f_r2)]) = opval;
1250 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1251 }
1252
1253#undef FLD
1254}
1255 NEXT (vpc);
1256
1257 CASE (sem, INSN_SLI) : /* sli $r1,$r0,$imm */
1258{
1259 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1260 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1261#define FLD(f) abuf->fields.sfmt_addi.f
1262 int UNUSED written = 0;
1263 IADDR UNUSED pc = abuf->addr;
1264 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1265
1266 {
1267 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1268 CPU (h_gr[FLD (f_r1)]) = opval;
1269 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1270 }
1271
1272#undef FLD
1273}
1274 NEXT (vpc);
1275
1276 CASE (sem, INSN_SR) : /* sr $r2,$r0,$r1 */
1277{
1278 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1279 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1280#define FLD(f) abuf->fields.sfmt_user.f
1281 int UNUSED written = 0;
1282 IADDR UNUSED pc = abuf->addr;
1283 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1284
1285 {
1286 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1287 CPU (h_gr[FLD (f_r2)]) = opval;
1288 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1289 }
1290
1291#undef FLD
1292}
1293 NEXT (vpc);
1294
1295 CASE (sem, INSN_SRI) : /* sri $r1,$r0,$imm */
1296{
1297 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1298 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1299#define FLD(f) abuf->fields.sfmt_addi.f
1300 int UNUSED written = 0;
1301 IADDR UNUSED pc = abuf->addr;
1302 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1303
1304 {
1305 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1306 CPU (h_gr[FLD (f_r1)]) = opval;
1307 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1308 }
1309
1310#undef FLD
1311}
1312 NEXT (vpc);
1313
1314 CASE (sem, INSN_SRU) : /* sru $r2,$r0,$r1 */
1315{
1316 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1317 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1318#define FLD(f) abuf->fields.sfmt_user.f
1319 int UNUSED written = 0;
1320 IADDR UNUSED pc = abuf->addr;
1321 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1322
1323 {
1324 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1325 CPU (h_gr[FLD (f_r2)]) = opval;
1326 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1327 }
1328
1329#undef FLD
1330}
1331 NEXT (vpc);
1332
1333 CASE (sem, INSN_SRUI) : /* srui $r1,$r0,$imm */
1334{
1335 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1336 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1337#define FLD(f) abuf->fields.sfmt_addi.f
1338 int UNUSED written = 0;
1339 IADDR UNUSED pc = abuf->addr;
1340 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1341
1342 {
1343 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1344 CPU (h_gr[FLD (f_r1)]) = opval;
1345 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1346 }
1347
1348#undef FLD
1349}
1350 NEXT (vpc);
1351
1352 CASE (sem, INSN_SUB) : /* sub $r2,$r0,$r1 */
1353{
1354 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1355 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1356#define FLD(f) abuf->fields.sfmt_user.f
1357 int UNUSED written = 0;
1358 IADDR UNUSED pc = abuf->addr;
1359 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1360
1361 {
1362 SI opval = SUBSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1363 CPU (h_gr[FLD (f_r2)]) = opval;
1364 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1365 }
1366
1367#undef FLD
1368}
1369 NEXT (vpc);
1370
1371 CASE (sem, INSN_SW) : /* sw ($r0+$imm),$r1 */
1372{
1373 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1374 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1375#define FLD(f) abuf->fields.sfmt_addi.f
1376 int UNUSED written = 0;
1377 IADDR UNUSED pc = abuf->addr;
1378 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1379
1380 {
1381 SI opval = CPU (h_gr[FLD (f_r1)]);
1382 SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1383 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1384 }
1385
1386#undef FLD
1387}
1388 NEXT (vpc);
1389
1390 CASE (sem, INSN_USER) : /* user $r2,$r0,$r1,$user */
1391{
1392 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1393 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1394#define FLD(f) abuf->fields.sfmt_user.f
1395 int UNUSED written = 0;
1396 IADDR UNUSED pc = abuf->addr;
1397 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1398
1399 {
1400 SI opval = lm32bf_user_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]), FLD (f_user));
1401 CPU (h_gr[FLD (f_r2)]) = opval;
1402 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1403 }
1404
1405#undef FLD
1406}
1407 NEXT (vpc);
1408
1409 CASE (sem, INSN_WCSR) : /* wcsr $csr,$r1 */
1410{
1411 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1412 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1413#define FLD(f) abuf->fields.sfmt_wcsr.f
1414 int UNUSED written = 0;
1415 IADDR UNUSED pc = abuf->addr;
1416 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1417
1418lm32bf_wcsr_insn (current_cpu, FLD (f_csr), CPU (h_gr[FLD (f_r1)]));
1419
1420#undef FLD
1421}
1422 NEXT (vpc);
1423
1424 CASE (sem, INSN_XOR) : /* xor $r2,$r0,$r1 */
1425{
1426 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1427 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1428#define FLD(f) abuf->fields.sfmt_user.f
1429 int UNUSED written = 0;
1430 IADDR UNUSED pc = abuf->addr;
1431 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1432
1433 {
1434 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1435 CPU (h_gr[FLD (f_r2)]) = opval;
1436 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1437 }
1438
1439#undef FLD
1440}
1441 NEXT (vpc);
1442
1443 CASE (sem, INSN_XORI) : /* xori $r1,$r0,$uimm */
1444{
1445 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1446 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1447#define FLD(f) abuf->fields.sfmt_andi.f
1448 int UNUSED written = 0;
1449 IADDR UNUSED pc = abuf->addr;
1450 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1451
1452 {
1453 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
1454 CPU (h_gr[FLD (f_r1)]) = opval;
1455 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1456 }
1457
1458#undef FLD
1459}
1460 NEXT (vpc);
1461
1462 CASE (sem, INSN_XNOR) : /* xnor $r2,$r0,$r1 */
1463{
1464 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1465 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1466#define FLD(f) abuf->fields.sfmt_user.f
1467 int UNUSED written = 0;
1468 IADDR UNUSED pc = abuf->addr;
1469 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1470
1471 {
1472 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])));
1473 CPU (h_gr[FLD (f_r2)]) = opval;
1474 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1475 }
1476
1477#undef FLD
1478}
1479 NEXT (vpc);
1480
1481 CASE (sem, INSN_XNORI) : /* xnori $r1,$r0,$uimm */
1482{
1483 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1484 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1485#define FLD(f) abuf->fields.sfmt_andi.f
1486 int UNUSED written = 0;
1487 IADDR UNUSED pc = abuf->addr;
1488 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1489
1490 {
1491 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
1492 CPU (h_gr[FLD (f_r1)]) = opval;
1493 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1494 }
1495
1496#undef FLD
1497}
1498 NEXT (vpc);
1499
1500 CASE (sem, INSN_BREAK) : /* break */
1501{
1502 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1503 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2310652a 1504#define FLD(f) abuf->fields.sfmt_empty.f
c28c63d8
JB		 1505 int UNUSED written = 0;
1506 IADDR UNUSED pc = abuf->addr;
1507 SEM_BRANCH_INIT
1508 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1509
1510 {
1511 USI opval = lm32bf_break_insn (current_cpu, pc);
1512 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1513 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1514 }
1515
1516 SEM_BRANCH_FINI (vpc);
1517#undef FLD
1518}
1519 NEXT (vpc);
1520
1521 CASE (sem, INSN_SCALL) : /* scall */
1522{
1523 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1524 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2310652a 1525#define FLD(f) abuf->fields.sfmt_empty.f
c28c63d8
JB		 1526 int UNUSED written = 0;
1527 IADDR UNUSED pc = abuf->addr;
1528 SEM_BRANCH_INIT
1529 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1530
1531 {
1532 USI opval = lm32bf_scall_insn (current_cpu, pc);
1533 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1534 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1535 }
1536
1537 SEM_BRANCH_FINI (vpc);
1538#undef FLD
1539}
1540 NEXT (vpc);
1541
1542
1543 }
1544 ENDSWITCH (sem) /* End of semantic switch. */
1545
1546 /* At this point `vpc' contains the next insn to execute. */
1547}
1548
1549#undef DEFINE_SWITCH
1550#endif /* DEFINE_SWITCH */
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