]>
Commit | Line | Data |
---|---|---|
16b47b25 NC |
1 | /* Simulator instruction decoder for m32r2f. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
1d506c26 | 5 | Copyright (C) 1996-2024 Free Software Foundation, Inc. |
16b47b25 NC |
6 | |
7 | This file is part of the GNU simulators. | |
8 | ||
e9c60591 DE |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
16b47b25 | 13 | |
e9c60591 DE |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
16b47b25 | 18 | |
e9c60591 | 19 | You should have received a copy of the GNU General Public License along |
9d4f3616 AM |
20 | with this program; if not, write to the Free Software Foundation, Inc., |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
16b47b25 NC |
22 | |
23 | */ | |
24 | ||
25 | #define WANT_CPU m32r2f | |
26 | #define WANT_CPU_M32R2F | |
27 | ||
28 | #include "sim-main.h" | |
29 | #include "sim-assert.h" | |
9d4f3616 AM |
30 | #include "cgen-mem.h" |
31 | #include "cgen-ops.h" | |
16b47b25 NC |
32 | |
33 | /* Insn can't be executed in parallel. | |
34 | Or is that "do NOt Pass to Air defense Radar"? :-) */ | |
35 | #define NOPAR (-1) | |
36 | ||
37 | /* The instruction descriptor array. | |
38 | This is computed at runtime. Space for it is not malloc'd to save a | |
39 | teensy bit of cpu in the decoder. Moving it to malloc space is trivial | |
40 | but won't be done until necessary (we don't currently support the runtime | |
41 | addition of instructions nor an SMP machine with different cpus). */ | |
42 | static IDESC m32r2f_insn_data[M32R2F_INSN__MAX]; | |
43 | ||
44 | /* Commas between elements are contained in the macros. | |
45 | Some of these are conditionally compiled out. */ | |
46 | ||
47 | static const struct insn_sem m32r2f_insn_sem[] = | |
48 | { | |
49 | { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
50 | { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
51 | { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
52 | { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
53 | { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
54 | { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
55 | { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD }, | |
56 | { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR }, | |
57 | { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND }, | |
58 | { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR }, | |
59 | { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R2F_INSN_WRITE_OR }, | |
60 | { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR }, | |
61 | { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR }, | |
62 | { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR }, | |
63 | { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADDI, M32R2F_INSN_WRITE_ADDI }, | |
64 | { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV }, | |
65 | { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR }, | |
66 | { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADDX, M32R2F_INSN_WRITE_ADDX }, | |
67 | { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8 }, | |
68 | { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR }, | |
69 | { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR }, | |
70 | { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
71 | { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
72 | { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
73 | { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
74 | { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
75 | { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
76 | { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M32R2F_INSN_WRITE_BL8 }, | |
77 | { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR }, | |
78 | { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8 }, | |
79 | { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR }, | |
80 | { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8, M32R2F_INSN_WRITE_BNC8 }, | |
81 | { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR }, | |
82 | { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR }, | |
83 | { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8 }, | |
84 | { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR }, | |
85 | { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BNCL8, M32R2F_INSN_WRITE_BNCL8 }, | |
86 | { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR }, | |
87 | { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP }, | |
88 | { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR }, | |
89 | { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU, M32R2F_INSN_WRITE_CMPU }, | |
90 | { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR }, | |
91 | { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ }, | |
92 | { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMPZ, M32R2F_INSN_WRITE_CMPZ }, | |
93 | { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
94 | { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
95 | { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
96 | { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
97 | { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
98 | { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
99 | { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
100 | { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
101 | { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
102 | { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
103 | { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
104 | { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
105 | { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC }, | |
106 | { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M32R2F_INSN_WRITE_JNC }, | |
107 | { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL }, | |
108 | { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M32R2F_INSN_WRITE_JMP }, | |
109 | { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD }, | |
110 | { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR }, | |
111 | { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M32R2F_INSN_WRITE_LDB }, | |
112 | { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR }, | |
113 | { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH }, | |
114 | { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR }, | |
115 | { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB, M32R2F_INSN_WRITE_LDUB }, | |
116 | { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR }, | |
117 | { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH }, | |
118 | { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR }, | |
119 | { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INSN_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS }, | |
120 | { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR }, | |
121 | { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8 }, | |
122 | { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR }, | |
123 | { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOCK, M32R2F_INSN_WRITE_LOCK }, | |
124 | { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A }, | |
125 | { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A }, | |
126 | { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A }, | |
127 | { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A }, | |
128 | { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL }, | |
129 | { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A }, | |
130 | { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A }, | |
131 | { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A }, | |
132 | { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A }, | |
133 | { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2F_INSN_WRITE_MV }, | |
134 | { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A }, | |
135 | { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A }, | |
136 | { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A }, | |
137 | { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVFC, M32R2F_INSN_WRITE_MVFC }, | |
138 | { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A }, | |
139 | { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A }, | |
140 | { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC }, | |
141 | { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M32R2F_INSN_WRITE_NEG }, | |
142 | { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP }, | |
143 | { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M32R2F_INSN_WRITE_NOT }, | |
144 | { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI }, | |
145 | { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI }, | |
146 | { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE }, | |
147 | { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR }, | |
148 | { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M32R2F_INSN_WRITE_SLL }, | |
149 | { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, | |
150 | { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI }, | |
151 | { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M32R2F_INSN_WRITE_SRA }, | |
152 | { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, | |
153 | { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI }, | |
154 | { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M32R2F_INSN_WRITE_SRL }, | |
155 | { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, | |
156 | { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI }, | |
157 | { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2F_INSN_WRITE_ST }, | |
158 | { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR }, | |
159 | { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB }, | |
160 | { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR }, | |
161 | { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M32R2F_INSN_WRITE_STH }, | |
162 | { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR }, | |
163 | { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS }, | |
164 | { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS }, | |
165 | { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS }, | |
166 | { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS }, | |
167 | { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB }, | |
168 | { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUBV, M32R2F_INSN_WRITE_SUBV }, | |
169 | { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX }, | |
170 | { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRAP, M32R2F_INSN_WRITE_TRAP }, | |
171 | { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK }, | |
172 | { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR }, | |
173 | { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR }, | |
174 | { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR }, | |
175 | { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ }, | |
176 | { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD }, | |
177 | { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACWU1, M32R2F_INSN_WRITE_MACWU1 }, | |
178 | { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO }, | |
179 | { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_PAR_MULWU1, M32R2F_INSN_WRITE_MULWU1 }, | |
180 | { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1 }, | |
181 | { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2F_INSN_WRITE_SC }, | |
182 | { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC }, | |
183 | { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_PAR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW }, | |
184 | { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW }, | |
185 | { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR }, | |
186 | { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR }, | |
187 | { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTST, M32R2F_INSN_WRITE_BTST }, | |
188 | }; | |
189 | ||
2310652a DE |
190 | static const struct insn_sem m32r2f_insn_sem_invalid = |
191 | { | |
16b47b25 NC |
192 | VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR |
193 | }; | |
194 | ||
195 | /* Initialize an IDESC from the compile-time computable parts. */ | |
196 | ||
197 | static INLINE void | |
198 | init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) | |
199 | { | |
200 | const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; | |
201 | ||
202 | id->num = t->index; | |
203 | id->sfmt = t->sfmt; | |
204 | if ((int) t->type <= 0) | |
205 | id->idata = & cgen_virtual_insn_table[- (int) t->type]; | |
206 | else | |
207 | id->idata = & insn_table[t->type]; | |
208 | id->attrs = CGEN_INSN_ATTRS (id->idata); | |
209 | /* Oh my god, a magic number. */ | |
210 | id->length = CGEN_INSN_BITSIZE (id->idata) / 8; | |
211 | ||
212 | #if WITH_PROFILE_MODEL_P | |
213 | id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; | |
214 | { | |
215 | SIM_DESC sd = CPU_STATE (cpu); | |
216 | SIM_ASSERT (t->index == id->timing->num); | |
217 | } | |
218 | #endif | |
219 | ||
220 | /* Semantic pointers are initialized elsewhere. */ | |
221 | } | |
222 | ||
223 | /* Initialize the instruction descriptor table. */ | |
224 | ||
225 | void | |
226 | m32r2f_init_idesc_table (SIM_CPU *cpu) | |
227 | { | |
228 | IDESC *id,*tabend; | |
229 | const struct insn_sem *t,*tend; | |
230 | int tabsize = M32R2F_INSN__MAX; | |
231 | IDESC *table = m32r2f_insn_data; | |
232 | ||
233 | memset (table, 0, tabsize * sizeof (IDESC)); | |
234 | ||
235 | /* First set all entries to the `invalid insn'. */ | |
236 | t = & m32r2f_insn_sem_invalid; | |
237 | for (id = table, tabend = table + tabsize; id < tabend; ++id) | |
238 | init_idesc (cpu, id, t); | |
239 | ||
240 | /* Now fill in the values for the chosen cpu. */ | |
13a590ca | 241 | for (t = m32r2f_insn_sem, tend = t + ARRAY_SIZE (m32r2f_insn_sem); |
16b47b25 NC |
242 | t != tend; ++t) |
243 | { | |
244 | init_idesc (cpu, & table[t->index], t); | |
245 | if (t->par_index != NOPAR) | |
246 | { | |
247 | init_idesc (cpu, &table[t->par_index], t); | |
248 | table[t->index].par_idesc = &table[t->par_index]; | |
249 | } | |
250 | if (t->par_index != NOPAR) | |
251 | { | |
252 | init_idesc (cpu, &table[t->write_index], t); | |
253 | table[t->par_index].par_idesc = &table[t->write_index]; | |
254 | } | |
255 | } | |
256 | ||
257 | /* Link the IDESC table into the cpu. */ | |
258 | CPU_IDESC (cpu) = table; | |
259 | } | |
260 | ||
261 | /* Given an instruction, return a pointer to its IDESC entry. */ | |
262 | ||
263 | const IDESC * | |
264 | m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, | |
197fa1aa | 265 | CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, |
16b47b25 NC |
266 | ARGBUF *abuf) |
267 | { | |
268 | /* Result of decoder. */ | |
269 | M32R2F_INSN_TYPE itype; | |
270 | ||
271 | { | |
197fa1aa | 272 | CGEN_INSN_WORD insn = base_insn; |
16b47b25 NC |
273 | |
274 | { | |
401b5b00 MF |
275 | unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); |
276 | switch (val0) | |
16b47b25 | 277 | { |
aea0b946 MF |
278 | case 0: itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv; |
279 | case 1: itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx; | |
280 | case 2: itype = M32R2F_INSN_SUB; goto extract_sfmt_add; | |
281 | case 3: itype = M32R2F_INSN_NEG; goto extract_sfmt_mv; | |
282 | case 4: itype = M32R2F_INSN_CMP; goto extract_sfmt_cmp; | |
283 | case 5: itype = M32R2F_INSN_CMPU; goto extract_sfmt_cmp; | |
284 | case 6: itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp; | |
285 | case 7: | |
16b47b25 | 286 | { |
401b5b00 MF |
287 | unsigned int val1 = (((insn >> 8) & (3 << 0))); |
288 | switch (val1) | |
16b47b25 | 289 | { |
aea0b946 | 290 | case 0: |
e9c60591 DE |
291 | if ((entire_insn & 0xfff0) == 0x70) |
292 | { itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz; } | |
293 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 294 | case 3: |
e9c60591 DE |
295 | if ((entire_insn & 0xfff0) == 0x370) |
296 | { itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz; } | |
297 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 298 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
299 | } |
300 | } | |
aea0b946 MF |
301 | case 8: itype = M32R2F_INSN_ADDV; goto extract_sfmt_addv; |
302 | case 9: itype = M32R2F_INSN_ADDX; goto extract_sfmt_addx; | |
303 | case 10: itype = M32R2F_INSN_ADD; goto extract_sfmt_add; | |
304 | case 11: itype = M32R2F_INSN_NOT; goto extract_sfmt_mv; | |
305 | case 12: itype = M32R2F_INSN_AND; goto extract_sfmt_add; | |
306 | case 13: itype = M32R2F_INSN_XOR; goto extract_sfmt_add; | |
307 | case 14: itype = M32R2F_INSN_OR; goto extract_sfmt_add; | |
308 | case 15: | |
e9c60591 DE |
309 | if ((entire_insn & 0xf8f0) == 0xf0) |
310 | { itype = M32R2F_INSN_BTST; goto extract_sfmt_btst; } | |
311 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 MF |
312 | case 16: itype = M32R2F_INSN_SRL; goto extract_sfmt_add; |
313 | case 18: itype = M32R2F_INSN_SRA; goto extract_sfmt_add; | |
314 | case 20: itype = M32R2F_INSN_SLL; goto extract_sfmt_add; | |
315 | case 22: itype = M32R2F_INSN_MUL; goto extract_sfmt_add; | |
316 | case 24: itype = M32R2F_INSN_MV; goto extract_sfmt_mv; | |
317 | case 25: itype = M32R2F_INSN_MVFC; goto extract_sfmt_mvfc; | |
318 | case 26: itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc; | |
319 | case 28: | |
16b47b25 | 320 | { |
401b5b00 MF |
321 | unsigned int val1 = (((insn >> 8) & (3 << 0))); |
322 | switch (val1) | |
16b47b25 | 323 | { |
aea0b946 | 324 | case 0: |
e9c60591 DE |
325 | if ((entire_insn & 0xfff0) == 0x1cc0) |
326 | { itype = M32R2F_INSN_JC; goto extract_sfmt_jc; } | |
327 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 328 | case 1: |
e9c60591 DE |
329 | if ((entire_insn & 0xfff0) == 0x1dc0) |
330 | { itype = M32R2F_INSN_JNC; goto extract_sfmt_jc; } | |
331 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 332 | case 2: |
e9c60591 DE |
333 | if ((entire_insn & 0xfff0) == 0x1ec0) |
334 | { itype = M32R2F_INSN_JL; goto extract_sfmt_jl; } | |
335 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 336 | case 3: |
e9c60591 DE |
337 | if ((entire_insn & 0xfff0) == 0x1fc0) |
338 | { itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp; } | |
339 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 340 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
341 | } |
342 | } | |
aea0b946 | 343 | case 29: |
e9c60591 DE |
344 | if ((entire_insn & 0xffff) == 0x10d6) |
345 | { itype = M32R2F_INSN_RTE; goto extract_sfmt_rte; } | |
346 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 347 | case 31: |
e9c60591 DE |
348 | if ((entire_insn & 0xfff0) == 0x10f0) |
349 | { itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap; } | |
350 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 MF |
351 | case 32: itype = M32R2F_INSN_STB; goto extract_sfmt_stb; |
352 | case 33: itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus; | |
353 | case 34: itype = M32R2F_INSN_STH; goto extract_sfmt_sth; | |
354 | case 35: itype = M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus; | |
355 | case 36: itype = M32R2F_INSN_ST; goto extract_sfmt_st; | |
356 | case 37: itype = M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock; | |
357 | case 38: itype = M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus; | |
358 | case 39: itype = M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus; | |
359 | case 40: itype = M32R2F_INSN_LDB; goto extract_sfmt_ldb; | |
360 | case 41: itype = M32R2F_INSN_LDUB; goto extract_sfmt_ldb; | |
361 | case 42: itype = M32R2F_INSN_LDH; goto extract_sfmt_ldh; | |
362 | case 43: itype = M32R2F_INSN_LDUH; goto extract_sfmt_ldh; | |
363 | case 44: itype = M32R2F_INSN_LD; goto extract_sfmt_ld; | |
364 | case 45: itype = M32R2F_INSN_LOCK; goto extract_sfmt_lock; | |
365 | case 46: itype = M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus; | |
366 | case 48: | |
367 | case 56: itype = M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a; | |
368 | case 49: | |
369 | case 57: itype = M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a; | |
370 | case 50: | |
371 | case 58: itype = M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a; | |
372 | case 51: | |
373 | case 59: itype = M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a; | |
374 | case 52: | |
375 | case 60: itype = M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a; | |
376 | case 53: | |
377 | case 61: itype = M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a; | |
378 | case 54: | |
379 | case 62: itype = M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a; | |
380 | case 55: | |
381 | case 63: itype = M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a; | |
382 | case 64: | |
383 | case 65: | |
384 | case 66: | |
385 | case 67: | |
386 | case 68: | |
387 | case 69: | |
388 | case 70: | |
389 | case 71: | |
390 | case 72: | |
391 | case 73: | |
392 | case 74: | |
393 | case 75: | |
394 | case 76: | |
395 | case 77: | |
396 | case 78: | |
397 | case 79: itype = M32R2F_INSN_ADDI; goto extract_sfmt_addi; | |
398 | case 80: | |
399 | case 81: itype = M32R2F_INSN_SRLI; goto extract_sfmt_slli; | |
400 | case 82: | |
401 | case 83: itype = M32R2F_INSN_SRAI; goto extract_sfmt_slli; | |
402 | case 84: | |
403 | case 85: itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli; | |
404 | case 87: | |
16b47b25 | 405 | { |
401b5b00 MF |
406 | unsigned int val1 = (((insn >> 0) & (1 << 0))); |
407 | switch (val1) | |
16b47b25 | 408 | { |
aea0b946 | 409 | case 0: |
e9c60591 DE |
410 | if ((entire_insn & 0xf0f3) == 0x5070) |
411 | { itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; } | |
412 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 413 | case 1: |
e9c60591 DE |
414 | if ((entire_insn & 0xf0f3) == 0x5071) |
415 | { itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; } | |
416 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 417 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
418 | } |
419 | } | |
aea0b946 | 420 | case 88: |
e9c60591 DE |
421 | if ((entire_insn & 0xf3f2) == 0x5080) |
422 | { itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; } | |
423 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 424 | case 89: |
e9c60591 DE |
425 | if ((entire_insn & 0xf3f2) == 0x5090) |
426 | { itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; } | |
427 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 MF |
428 | case 90: itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1; |
429 | case 91: itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1; | |
430 | case 92: itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1; | |
431 | case 93: itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo; | |
432 | case 94: | |
e9c60591 DE |
433 | if ((entire_insn & 0xffff) == 0x50e4) |
434 | { itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd; } | |
435 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 436 | case 95: |
16b47b25 | 437 | { |
401b5b00 MF |
438 | unsigned int val1 = (((insn >> 0) & (3 << 0))); |
439 | switch (val1) | |
16b47b25 | 440 | { |
aea0b946 MF |
441 | case 0: itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; |
442 | case 1: itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; | |
443 | case 2: itype = M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a; | |
444 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
445 | } |
446 | } | |
aea0b946 MF |
447 | case 96: |
448 | case 97: | |
449 | case 98: | |
450 | case 99: | |
451 | case 100: | |
452 | case 101: | |
453 | case 102: | |
454 | case 103: | |
455 | case 104: | |
456 | case 105: | |
457 | case 106: | |
458 | case 107: | |
459 | case 108: | |
460 | case 109: | |
461 | case 110: | |
462 | case 111: itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8; | |
463 | case 112: | |
16b47b25 | 464 | { |
401b5b00 MF |
465 | unsigned int val1 = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); |
466 | switch (val1) | |
16b47b25 | 467 | { |
aea0b946 | 468 | case 0: |
e9c60591 DE |
469 | if ((entire_insn & 0xffff) == 0x7000) |
470 | { itype = M32R2F_INSN_NOP; goto extract_sfmt_nop; } | |
471 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 MF |
472 | case 2: |
473 | case 3: itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; | |
474 | case 4: | |
475 | case 5: itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; | |
476 | case 9: | |
e9c60591 DE |
477 | if ((entire_insn & 0xffff) == 0x7401) |
478 | { itype = M32R2F_INSN_SC; goto extract_sfmt_sc; } | |
479 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 480 | case 11: |
e9c60591 DE |
481 | if ((entire_insn & 0xffff) == 0x7501) |
482 | { itype = M32R2F_INSN_SNC; goto extract_sfmt_sc; } | |
483 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 MF |
484 | case 16: |
485 | case 17: itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8; | |
486 | case 18: | |
487 | case 19: itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8; | |
488 | case 24: | |
489 | case 25: itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8; | |
490 | case 26: | |
491 | case 27: itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8; | |
492 | case 28: | |
493 | case 29: itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8; | |
494 | case 30: | |
495 | case 31: itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8; | |
496 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
497 | } |
498 | } | |
aea0b946 MF |
499 | case 113: |
500 | case 114: | |
501 | case 115: | |
502 | case 116: | |
503 | case 117: | |
504 | case 118: | |
505 | case 119: | |
506 | case 120: | |
507 | case 121: | |
508 | case 122: | |
509 | case 123: | |
510 | case 124: | |
511 | case 125: | |
512 | case 126: | |
513 | case 127: | |
16b47b25 | 514 | { |
401b5b00 MF |
515 | unsigned int val1 = (((insn >> 8) & (15 << 0))); |
516 | switch (val1) | |
16b47b25 | 517 | { |
aea0b946 MF |
518 | case 1: itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; |
519 | case 2: itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; | |
520 | case 8: itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8; | |
521 | case 9: itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8; | |
522 | case 12: itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8; | |
523 | case 13: itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8; | |
524 | case 14: itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8; | |
525 | case 15: itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8; | |
526 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
527 | } |
528 | } | |
aea0b946 | 529 | case 132: |
e9c60591 DE |
530 | if ((entire_insn & 0xfff00000) == 0x80400000) |
531 | { itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi; } | |
532 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 533 | case 133: |
e9c60591 DE |
534 | if ((entire_insn & 0xfff00000) == 0x80500000) |
535 | { itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi; } | |
536 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 537 | case 134: |
16b47b25 | 538 | { |
401b5b00 MF |
539 | unsigned int val1 = (((entire_insn >> 8) & (3 << 0))); |
540 | switch (val1) | |
16b47b25 | 541 | { |
aea0b946 | 542 | case 0: |
e9c60591 DE |
543 | if ((entire_insn & 0xf0f0ffff) == 0x80600000) |
544 | { itype = M32R2F_INSN_SAT; goto extract_sfmt_sat; } | |
545 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 546 | case 2: |
e9c60591 DE |
547 | if ((entire_insn & 0xf0f0ffff) == 0x80600200) |
548 | { itype = M32R2F_INSN_SATH; goto extract_sfmt_satb; } | |
549 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 550 | case 3: |
e9c60591 DE |
551 | if ((entire_insn & 0xf0f0ffff) == 0x80600300) |
552 | { itype = M32R2F_INSN_SATB; goto extract_sfmt_satb; } | |
553 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 554 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
555 | } |
556 | } | |
aea0b946 MF |
557 | case 136: itype = M32R2F_INSN_ADDV3; goto extract_sfmt_addv3; |
558 | case 138: itype = M32R2F_INSN_ADD3; goto extract_sfmt_add3; | |
559 | case 140: itype = M32R2F_INSN_AND3; goto extract_sfmt_and3; | |
560 | case 141: itype = M32R2F_INSN_XOR3; goto extract_sfmt_and3; | |
561 | case 142: itype = M32R2F_INSN_OR3; goto extract_sfmt_or3; | |
562 | case 144: | |
16b47b25 | 563 | { |
401b5b00 MF |
564 | unsigned int val1 = (((entire_insn >> 3) & (3 << 0))); |
565 | switch (val1) | |
16b47b25 | 566 | { |
aea0b946 | 567 | case 0: |
e9c60591 DE |
568 | if ((entire_insn & 0xf0f0ffff) == 0x90000000) |
569 | { itype = M32R2F_INSN_DIV; goto extract_sfmt_div; } | |
570 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 571 | case 2: |
e9c60591 DE |
572 | if ((entire_insn & 0xf0f0ffff) == 0x90000010) |
573 | { itype = M32R2F_INSN_DIVH; goto extract_sfmt_div; } | |
574 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 575 | case 3: |
e9c60591 DE |
576 | if ((entire_insn & 0xf0f0ffff) == 0x90000018) |
577 | { itype = M32R2F_INSN_DIVB; goto extract_sfmt_div; } | |
578 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 579 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
580 | } |
581 | } | |
aea0b946 | 582 | case 145: |
16b47b25 | 583 | { |
401b5b00 MF |
584 | unsigned int val1 = (((entire_insn >> 3) & (3 << 0))); |
585 | switch (val1) | |
16b47b25 | 586 | { |
aea0b946 | 587 | case 0: |
e9c60591 DE |
588 | if ((entire_insn & 0xf0f0ffff) == 0x90100000) |
589 | { itype = M32R2F_INSN_DIVU; goto extract_sfmt_div; } | |
590 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 591 | case 2: |
e9c60591 DE |
592 | if ((entire_insn & 0xf0f0ffff) == 0x90100010) |
593 | { itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; } | |
594 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 595 | case 3: |
e9c60591 DE |
596 | if ((entire_insn & 0xf0f0ffff) == 0x90100018) |
597 | { itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div; } | |
598 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 599 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
600 | } |
601 | } | |
aea0b946 | 602 | case 146: |
16b47b25 | 603 | { |
401b5b00 MF |
604 | unsigned int val1 = (((entire_insn >> 3) & (3 << 0))); |
605 | switch (val1) | |
16b47b25 | 606 | { |
aea0b946 | 607 | case 0: |
e9c60591 DE |
608 | if ((entire_insn & 0xf0f0ffff) == 0x90200000) |
609 | { itype = M32R2F_INSN_REM; goto extract_sfmt_div; } | |
610 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 611 | case 2: |
e9c60591 DE |
612 | if ((entire_insn & 0xf0f0ffff) == 0x90200010) |
613 | { itype = M32R2F_INSN_REMH; goto extract_sfmt_div; } | |
614 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 615 | case 3: |
e9c60591 DE |
616 | if ((entire_insn & 0xf0f0ffff) == 0x90200018) |
617 | { itype = M32R2F_INSN_REMB; goto extract_sfmt_div; } | |
618 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 619 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
620 | } |
621 | } | |
aea0b946 | 622 | case 147: |
16b47b25 | 623 | { |
401b5b00 MF |
624 | unsigned int val1 = (((entire_insn >> 3) & (3 << 0))); |
625 | switch (val1) | |
16b47b25 | 626 | { |
aea0b946 | 627 | case 0: |
e9c60591 DE |
628 | if ((entire_insn & 0xf0f0ffff) == 0x90300000) |
629 | { itype = M32R2F_INSN_REMU; goto extract_sfmt_div; } | |
630 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 631 | case 2: |
e9c60591 DE |
632 | if ((entire_insn & 0xf0f0ffff) == 0x90300010) |
633 | { itype = M32R2F_INSN_REMUH; goto extract_sfmt_div; } | |
634 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 635 | case 3: |
e9c60591 DE |
636 | if ((entire_insn & 0xf0f0ffff) == 0x90300018) |
637 | { itype = M32R2F_INSN_REMUB; goto extract_sfmt_div; } | |
638 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 639 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
640 | } |
641 | } | |
aea0b946 MF |
642 | case 152: itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3; |
643 | case 154: itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3; | |
644 | case 156: itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3; | |
645 | case 159: | |
e9c60591 DE |
646 | if ((entire_insn & 0xf0ff0000) == 0x90f00000) |
647 | { itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16; } | |
648 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 MF |
649 | case 160: itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d; |
650 | case 162: itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d; | |
651 | case 164: itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d; | |
652 | case 166: | |
e9c60591 DE |
653 | if ((entire_insn & 0xf8f00000) == 0xa0600000) |
654 | { itype = M32R2F_INSN_BSET; goto extract_sfmt_bset; } | |
655 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 656 | case 167: |
e9c60591 DE |
657 | if ((entire_insn & 0xf8f00000) == 0xa0700000) |
658 | { itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset; } | |
659 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 MF |
660 | case 168: itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d; |
661 | case 169: itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d; | |
662 | case 170: itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d; | |
663 | case 171: itype = M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d; | |
664 | case 172: itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d; | |
665 | case 176: itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq; | |
666 | case 177: itype = M32R2F_INSN_BNE; goto extract_sfmt_beq; | |
667 | case 184: | |
e9c60591 DE |
668 | if ((entire_insn & 0xfff00000) == 0xb0800000) |
669 | { itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz; } | |
670 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 671 | case 185: |
e9c60591 DE |
672 | if ((entire_insn & 0xfff00000) == 0xb0900000) |
673 | { itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz; } | |
674 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 675 | case 186: |
e9c60591 DE |
676 | if ((entire_insn & 0xfff00000) == 0xb0a00000) |
677 | { itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz; } | |
678 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 679 | case 187: |
e9c60591 DE |
680 | if ((entire_insn & 0xfff00000) == 0xb0b00000) |
681 | { itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz; } | |
682 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 683 | case 188: |
e9c60591 DE |
684 | if ((entire_insn & 0xfff00000) == 0xb0c00000) |
685 | { itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz; } | |
686 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 687 | case 189: |
e9c60591 DE |
688 | if ((entire_insn & 0xfff00000) == 0xb0d00000) |
689 | { itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz; } | |
690 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 691 | case 220: |
e9c60591 DE |
692 | if ((entire_insn & 0xf0ff0000) == 0xd0c00000) |
693 | { itype = M32R2F_INSN_SETH; goto extract_sfmt_seth; } | |
694 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 MF |
695 | case 224: |
696 | case 225: | |
697 | case 226: | |
698 | case 227: | |
699 | case 228: | |
700 | case 229: | |
701 | case 230: | |
702 | case 231: | |
703 | case 232: | |
704 | case 233: | |
705 | case 234: | |
706 | case 235: | |
707 | case 236: | |
708 | case 237: | |
709 | case 238: | |
710 | case 239: itype = M32R2F_INSN_LD24; goto extract_sfmt_ld24; | |
711 | case 240: | |
712 | case 241: | |
713 | case 242: | |
714 | case 243: | |
715 | case 244: | |
716 | case 245: | |
717 | case 246: | |
718 | case 247: | |
719 | case 248: | |
720 | case 249: | |
721 | case 250: | |
722 | case 251: | |
723 | case 252: | |
724 | case 253: | |
725 | case 254: | |
726 | case 255: | |
16b47b25 | 727 | { |
401b5b00 MF |
728 | unsigned int val1 = (((insn >> 8) & (7 << 0))); |
729 | switch (val1) | |
16b47b25 | 730 | { |
aea0b946 | 731 | case 0: |
e9c60591 DE |
732 | if ((entire_insn & 0xff000000) == 0xf8000000) |
733 | { itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24; } | |
734 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 735 | case 1: |
e9c60591 DE |
736 | if ((entire_insn & 0xff000000) == 0xf9000000) |
737 | { itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24; } | |
738 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 739 | case 4: |
e9c60591 DE |
740 | if ((entire_insn & 0xff000000) == 0xfc000000) |
741 | { itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24; } | |
742 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 743 | case 5: |
e9c60591 DE |
744 | if ((entire_insn & 0xff000000) == 0xfd000000) |
745 | { itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24; } | |
746 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 747 | case 6: |
e9c60591 DE |
748 | if ((entire_insn & 0xff000000) == 0xfe000000) |
749 | { itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24; } | |
750 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 751 | case 7: |
e9c60591 DE |
752 | if ((entire_insn & 0xff000000) == 0xff000000) |
753 | { itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24; } | |
754 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
aea0b946 | 755 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
756 | } |
757 | } | |
aea0b946 | 758 | default: itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
16b47b25 NC |
759 | } |
760 | } | |
761 | } | |
762 | ||
763 | /* The instruction has been decoded, now extract the fields. */ | |
764 | ||
765 | extract_sfmt_empty: | |
766 | { | |
767 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 768 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
769 | |
770 | ||
771 | /* Record the fields for the semantic handler. */ | |
db7858e2 | 772 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); |
16b47b25 NC |
773 | |
774 | #undef FLD | |
775 | return idesc; | |
776 | } | |
777 | ||
778 | extract_sfmt_add: | |
779 | { | |
780 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 781 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
782 | #define FLD(f) abuf->fields.sfmt_add.f |
783 | UINT f_r1; | |
784 | UINT f_r2; | |
785 | ||
786 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
787 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
788 | ||
789 | /* Record the fields for the semantic handler. */ | |
790 | FLD (f_r1) = f_r1; | |
791 | FLD (f_r2) = f_r2; | |
792 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
793 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 794 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
795 | |
796 | #if WITH_PROFILE_MODEL_P | |
797 | /* Record the fields for profiling. */ | |
798 | if (PROFILE_MODEL_P (current_cpu)) | |
799 | { | |
800 | FLD (in_dr) = f_r1; | |
801 | FLD (in_sr) = f_r2; | |
802 | FLD (out_dr) = f_r1; | |
803 | } | |
804 | #endif | |
805 | #undef FLD | |
806 | return idesc; | |
807 | } | |
808 | ||
809 | extract_sfmt_add3: | |
810 | { | |
811 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 812 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
813 | #define FLD(f) abuf->fields.sfmt_add3.f |
814 | UINT f_r1; | |
815 | UINT f_r2; | |
816 | INT f_simm16; | |
817 | ||
818 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
819 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 820 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
821 | |
822 | /* Record the fields for the semantic handler. */ | |
823 | FLD (f_simm16) = f_simm16; | |
824 | FLD (f_r2) = f_r2; | |
825 | FLD (f_r1) = f_r1; | |
826 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
827 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 828 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
829 | |
830 | #if WITH_PROFILE_MODEL_P | |
831 | /* Record the fields for profiling. */ | |
832 | if (PROFILE_MODEL_P (current_cpu)) | |
833 | { | |
834 | FLD (in_sr) = f_r2; | |
835 | FLD (out_dr) = f_r1; | |
836 | } | |
837 | #endif | |
838 | #undef FLD | |
839 | return idesc; | |
840 | } | |
841 | ||
842 | extract_sfmt_and3: | |
843 | { | |
844 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 845 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
846 | #define FLD(f) abuf->fields.sfmt_and3.f |
847 | UINT f_r1; | |
848 | UINT f_r2; | |
849 | UINT f_uimm16; | |
850 | ||
851 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
852 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
853 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
854 | ||
855 | /* Record the fields for the semantic handler. */ | |
856 | FLD (f_r2) = f_r2; | |
857 | FLD (f_uimm16) = f_uimm16; | |
858 | FLD (f_r1) = f_r1; | |
859 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
860 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 861 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
862 | |
863 | #if WITH_PROFILE_MODEL_P | |
864 | /* Record the fields for profiling. */ | |
865 | if (PROFILE_MODEL_P (current_cpu)) | |
866 | { | |
867 | FLD (in_sr) = f_r2; | |
868 | FLD (out_dr) = f_r1; | |
869 | } | |
870 | #endif | |
871 | #undef FLD | |
872 | return idesc; | |
873 | } | |
874 | ||
875 | extract_sfmt_or3: | |
876 | { | |
877 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 878 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
879 | #define FLD(f) abuf->fields.sfmt_and3.f |
880 | UINT f_r1; | |
881 | UINT f_r2; | |
882 | UINT f_uimm16; | |
883 | ||
884 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
885 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
886 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
887 | ||
888 | /* Record the fields for the semantic handler. */ | |
889 | FLD (f_r2) = f_r2; | |
890 | FLD (f_uimm16) = f_uimm16; | |
891 | FLD (f_r1) = f_r1; | |
892 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
893 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 894 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
895 | |
896 | #if WITH_PROFILE_MODEL_P | |
897 | /* Record the fields for profiling. */ | |
898 | if (PROFILE_MODEL_P (current_cpu)) | |
899 | { | |
900 | FLD (in_sr) = f_r2; | |
901 | FLD (out_dr) = f_r1; | |
902 | } | |
903 | #endif | |
904 | #undef FLD | |
905 | return idesc; | |
906 | } | |
907 | ||
908 | extract_sfmt_addi: | |
909 | { | |
910 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 911 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
912 | #define FLD(f) abuf->fields.sfmt_addi.f |
913 | UINT f_r1; | |
914 | INT f_simm8; | |
915 | ||
916 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
62836bf4 | 917 | f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); |
16b47b25 NC |
918 | |
919 | /* Record the fields for the semantic handler. */ | |
920 | FLD (f_r1) = f_r1; | |
921 | FLD (f_simm8) = f_simm8; | |
922 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 923 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
924 | |
925 | #if WITH_PROFILE_MODEL_P | |
926 | /* Record the fields for profiling. */ | |
927 | if (PROFILE_MODEL_P (current_cpu)) | |
928 | { | |
929 | FLD (in_dr) = f_r1; | |
930 | FLD (out_dr) = f_r1; | |
931 | } | |
932 | #endif | |
933 | #undef FLD | |
934 | return idesc; | |
935 | } | |
936 | ||
937 | extract_sfmt_addv: | |
938 | { | |
939 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 940 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
941 | #define FLD(f) abuf->fields.sfmt_add.f |
942 | UINT f_r1; | |
943 | UINT f_r2; | |
944 | ||
945 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
946 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
947 | ||
948 | /* Record the fields for the semantic handler. */ | |
949 | FLD (f_r1) = f_r1; | |
950 | FLD (f_r2) = f_r2; | |
951 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
952 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 953 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
954 | |
955 | #if WITH_PROFILE_MODEL_P | |
956 | /* Record the fields for profiling. */ | |
957 | if (PROFILE_MODEL_P (current_cpu)) | |
958 | { | |
959 | FLD (in_dr) = f_r1; | |
960 | FLD (in_sr) = f_r2; | |
961 | FLD (out_dr) = f_r1; | |
962 | } | |
963 | #endif | |
964 | #undef FLD | |
965 | return idesc; | |
966 | } | |
967 | ||
968 | extract_sfmt_addv3: | |
969 | { | |
970 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 971 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
972 | #define FLD(f) abuf->fields.sfmt_add3.f |
973 | UINT f_r1; | |
974 | UINT f_r2; | |
975 | INT f_simm16; | |
976 | ||
977 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
978 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 979 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
980 | |
981 | /* Record the fields for the semantic handler. */ | |
982 | FLD (f_simm16) = f_simm16; | |
983 | FLD (f_r2) = f_r2; | |
984 | FLD (f_r1) = f_r1; | |
985 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
986 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 987 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
988 | |
989 | #if WITH_PROFILE_MODEL_P | |
990 | /* Record the fields for profiling. */ | |
991 | if (PROFILE_MODEL_P (current_cpu)) | |
992 | { | |
993 | FLD (in_sr) = f_r2; | |
994 | FLD (out_dr) = f_r1; | |
995 | } | |
996 | #endif | |
997 | #undef FLD | |
998 | return idesc; | |
999 | } | |
1000 | ||
1001 | extract_sfmt_addx: | |
1002 | { | |
1003 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1004 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1005 | #define FLD(f) abuf->fields.sfmt_add.f |
1006 | UINT f_r1; | |
1007 | UINT f_r2; | |
1008 | ||
1009 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1010 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1011 | ||
1012 | /* Record the fields for the semantic handler. */ | |
1013 | FLD (f_r1) = f_r1; | |
1014 | FLD (f_r2) = f_r2; | |
1015 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1016 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1017 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1018 | |
1019 | #if WITH_PROFILE_MODEL_P | |
1020 | /* Record the fields for profiling. */ | |
1021 | if (PROFILE_MODEL_P (current_cpu)) | |
1022 | { | |
1023 | FLD (in_dr) = f_r1; | |
1024 | FLD (in_sr) = f_r2; | |
1025 | FLD (out_dr) = f_r1; | |
1026 | } | |
1027 | #endif | |
1028 | #undef FLD | |
1029 | return idesc; | |
1030 | } | |
1031 | ||
1032 | extract_sfmt_bc8: | |
1033 | { | |
1034 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1035 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1036 | #define FLD(f) abuf->fields.sfmt_bl8.f |
1037 | SI f_disp8; | |
1038 | ||
9d4f3616 | 1039 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); |
16b47b25 NC |
1040 | |
1041 | /* Record the fields for the semantic handler. */ | |
1042 | FLD (i_disp8) = f_disp8; | |
db7858e2 | 1043 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); |
16b47b25 NC |
1044 | |
1045 | #if WITH_PROFILE_MODEL_P | |
1046 | /* Record the fields for profiling. */ | |
1047 | if (PROFILE_MODEL_P (current_cpu)) | |
1048 | { | |
1049 | } | |
1050 | #endif | |
1051 | #undef FLD | |
1052 | return idesc; | |
1053 | } | |
1054 | ||
1055 | extract_sfmt_bc24: | |
1056 | { | |
1057 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1058 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1059 | #define FLD(f) abuf->fields.sfmt_bl24.f |
1060 | SI f_disp24; | |
1061 | ||
9d4f3616 | 1062 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); |
16b47b25 NC |
1063 | |
1064 | /* Record the fields for the semantic handler. */ | |
1065 | FLD (i_disp24) = f_disp24; | |
db7858e2 | 1066 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); |
16b47b25 NC |
1067 | |
1068 | #if WITH_PROFILE_MODEL_P | |
1069 | /* Record the fields for profiling. */ | |
1070 | if (PROFILE_MODEL_P (current_cpu)) | |
1071 | { | |
1072 | } | |
1073 | #endif | |
1074 | #undef FLD | |
1075 | return idesc; | |
1076 | } | |
1077 | ||
1078 | extract_sfmt_beq: | |
1079 | { | |
1080 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1081 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1082 | #define FLD(f) abuf->fields.sfmt_beq.f |
1083 | UINT f_r1; | |
1084 | UINT f_r2; | |
1085 | SI f_disp16; | |
1086 | ||
1087 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1088 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
9d4f3616 | 1089 | f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); |
16b47b25 NC |
1090 | |
1091 | /* Record the fields for the semantic handler. */ | |
1092 | FLD (f_r1) = f_r1; | |
1093 | FLD (f_r2) = f_r2; | |
1094 | FLD (i_disp16) = f_disp16; | |
1095 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1096 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1097 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1098 | |
1099 | #if WITH_PROFILE_MODEL_P | |
1100 | /* Record the fields for profiling. */ | |
1101 | if (PROFILE_MODEL_P (current_cpu)) | |
1102 | { | |
1103 | FLD (in_src1) = f_r1; | |
1104 | FLD (in_src2) = f_r2; | |
1105 | } | |
1106 | #endif | |
1107 | #undef FLD | |
1108 | return idesc; | |
1109 | } | |
1110 | ||
1111 | extract_sfmt_beqz: | |
1112 | { | |
1113 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1114 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1115 | #define FLD(f) abuf->fields.sfmt_beq.f |
1116 | UINT f_r2; | |
1117 | SI f_disp16; | |
1118 | ||
1119 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
9d4f3616 | 1120 | f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); |
16b47b25 NC |
1121 | |
1122 | /* Record the fields for the semantic handler. */ | |
1123 | FLD (f_r2) = f_r2; | |
1124 | FLD (i_disp16) = f_disp16; | |
1125 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1126 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1127 | |
1128 | #if WITH_PROFILE_MODEL_P | |
1129 | /* Record the fields for profiling. */ | |
1130 | if (PROFILE_MODEL_P (current_cpu)) | |
1131 | { | |
1132 | FLD (in_src2) = f_r2; | |
1133 | } | |
1134 | #endif | |
1135 | #undef FLD | |
1136 | return idesc; | |
1137 | } | |
1138 | ||
1139 | extract_sfmt_bl8: | |
1140 | { | |
1141 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1142 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1143 | #define FLD(f) abuf->fields.sfmt_bl8.f |
1144 | SI f_disp8; | |
1145 | ||
9d4f3616 | 1146 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); |
16b47b25 NC |
1147 | |
1148 | /* Record the fields for the semantic handler. */ | |
1149 | FLD (i_disp8) = f_disp8; | |
db7858e2 | 1150 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); |
16b47b25 NC |
1151 | |
1152 | #if WITH_PROFILE_MODEL_P | |
1153 | /* Record the fields for profiling. */ | |
1154 | if (PROFILE_MODEL_P (current_cpu)) | |
1155 | { | |
1156 | FLD (out_h_gr_SI_14) = 14; | |
1157 | } | |
1158 | #endif | |
1159 | #undef FLD | |
1160 | return idesc; | |
1161 | } | |
1162 | ||
1163 | extract_sfmt_bl24: | |
1164 | { | |
1165 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1166 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1167 | #define FLD(f) abuf->fields.sfmt_bl24.f |
1168 | SI f_disp24; | |
1169 | ||
9d4f3616 | 1170 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); |
16b47b25 NC |
1171 | |
1172 | /* Record the fields for the semantic handler. */ | |
1173 | FLD (i_disp24) = f_disp24; | |
db7858e2 | 1174 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); |
16b47b25 NC |
1175 | |
1176 | #if WITH_PROFILE_MODEL_P | |
1177 | /* Record the fields for profiling. */ | |
1178 | if (PROFILE_MODEL_P (current_cpu)) | |
1179 | { | |
1180 | FLD (out_h_gr_SI_14) = 14; | |
1181 | } | |
1182 | #endif | |
1183 | #undef FLD | |
1184 | return idesc; | |
1185 | } | |
1186 | ||
1187 | extract_sfmt_bcl8: | |
1188 | { | |
1189 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1190 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1191 | #define FLD(f) abuf->fields.sfmt_bl8.f |
1192 | SI f_disp8; | |
1193 | ||
9d4f3616 | 1194 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); |
16b47b25 NC |
1195 | |
1196 | /* Record the fields for the semantic handler. */ | |
1197 | FLD (i_disp8) = f_disp8; | |
db7858e2 | 1198 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); |
16b47b25 NC |
1199 | |
1200 | #if WITH_PROFILE_MODEL_P | |
1201 | /* Record the fields for profiling. */ | |
1202 | if (PROFILE_MODEL_P (current_cpu)) | |
1203 | { | |
1204 | FLD (out_h_gr_SI_14) = 14; | |
1205 | } | |
1206 | #endif | |
1207 | #undef FLD | |
1208 | return idesc; | |
1209 | } | |
1210 | ||
1211 | extract_sfmt_bcl24: | |
1212 | { | |
1213 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1214 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1215 | #define FLD(f) abuf->fields.sfmt_bl24.f |
1216 | SI f_disp24; | |
1217 | ||
9d4f3616 | 1218 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); |
16b47b25 NC |
1219 | |
1220 | /* Record the fields for the semantic handler. */ | |
1221 | FLD (i_disp24) = f_disp24; | |
db7858e2 | 1222 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); |
16b47b25 NC |
1223 | |
1224 | #if WITH_PROFILE_MODEL_P | |
1225 | /* Record the fields for profiling. */ | |
1226 | if (PROFILE_MODEL_P (current_cpu)) | |
1227 | { | |
1228 | FLD (out_h_gr_SI_14) = 14; | |
1229 | } | |
1230 | #endif | |
1231 | #undef FLD | |
1232 | return idesc; | |
1233 | } | |
1234 | ||
1235 | extract_sfmt_bra8: | |
1236 | { | |
1237 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1238 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1239 | #define FLD(f) abuf->fields.sfmt_bl8.f |
1240 | SI f_disp8; | |
1241 | ||
9d4f3616 | 1242 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); |
16b47b25 NC |
1243 | |
1244 | /* Record the fields for the semantic handler. */ | |
1245 | FLD (i_disp8) = f_disp8; | |
db7858e2 | 1246 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); |
16b47b25 NC |
1247 | |
1248 | #if WITH_PROFILE_MODEL_P | |
1249 | /* Record the fields for profiling. */ | |
1250 | if (PROFILE_MODEL_P (current_cpu)) | |
1251 | { | |
1252 | } | |
1253 | #endif | |
1254 | #undef FLD | |
1255 | return idesc; | |
1256 | } | |
1257 | ||
1258 | extract_sfmt_bra24: | |
1259 | { | |
1260 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1261 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1262 | #define FLD(f) abuf->fields.sfmt_bl24.f |
1263 | SI f_disp24; | |
1264 | ||
9d4f3616 | 1265 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); |
16b47b25 NC |
1266 | |
1267 | /* Record the fields for the semantic handler. */ | |
1268 | FLD (i_disp24) = f_disp24; | |
db7858e2 | 1269 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); |
16b47b25 NC |
1270 | |
1271 | #if WITH_PROFILE_MODEL_P | |
1272 | /* Record the fields for profiling. */ | |
1273 | if (PROFILE_MODEL_P (current_cpu)) | |
1274 | { | |
1275 | } | |
1276 | #endif | |
1277 | #undef FLD | |
1278 | return idesc; | |
1279 | } | |
1280 | ||
1281 | extract_sfmt_cmp: | |
1282 | { | |
1283 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1284 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1285 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
1286 | UINT f_r1; | |
1287 | UINT f_r2; | |
1288 | ||
1289 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1290 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1291 | ||
1292 | /* Record the fields for the semantic handler. */ | |
1293 | FLD (f_r1) = f_r1; | |
1294 | FLD (f_r2) = f_r2; | |
1295 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1296 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1297 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1298 | |
1299 | #if WITH_PROFILE_MODEL_P | |
1300 | /* Record the fields for profiling. */ | |
1301 | if (PROFILE_MODEL_P (current_cpu)) | |
1302 | { | |
1303 | FLD (in_src1) = f_r1; | |
1304 | FLD (in_src2) = f_r2; | |
1305 | } | |
1306 | #endif | |
1307 | #undef FLD | |
1308 | return idesc; | |
1309 | } | |
1310 | ||
1311 | extract_sfmt_cmpi: | |
1312 | { | |
1313 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1314 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1315 | #define FLD(f) abuf->fields.sfmt_st_d.f |
1316 | UINT f_r2; | |
1317 | INT f_simm16; | |
1318 | ||
1319 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1320 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1321 | |
1322 | /* Record the fields for the semantic handler. */ | |
1323 | FLD (f_simm16) = f_simm16; | |
1324 | FLD (f_r2) = f_r2; | |
1325 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1326 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1327 | |
1328 | #if WITH_PROFILE_MODEL_P | |
1329 | /* Record the fields for profiling. */ | |
1330 | if (PROFILE_MODEL_P (current_cpu)) | |
1331 | { | |
1332 | FLD (in_src2) = f_r2; | |
1333 | } | |
1334 | #endif | |
1335 | #undef FLD | |
1336 | return idesc; | |
1337 | } | |
1338 | ||
1339 | extract_sfmt_cmpz: | |
1340 | { | |
1341 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1342 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1343 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
1344 | UINT f_r2; | |
1345 | ||
1346 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1347 | ||
1348 | /* Record the fields for the semantic handler. */ | |
1349 | FLD (f_r2) = f_r2; | |
1350 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1351 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1352 | |
1353 | #if WITH_PROFILE_MODEL_P | |
1354 | /* Record the fields for profiling. */ | |
1355 | if (PROFILE_MODEL_P (current_cpu)) | |
1356 | { | |
1357 | FLD (in_src2) = f_r2; | |
1358 | } | |
1359 | #endif | |
1360 | #undef FLD | |
1361 | return idesc; | |
1362 | } | |
1363 | ||
1364 | extract_sfmt_div: | |
1365 | { | |
1366 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1367 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1368 | #define FLD(f) abuf->fields.sfmt_add.f |
1369 | UINT f_r1; | |
1370 | UINT f_r2; | |
1371 | ||
1372 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1373 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1374 | ||
1375 | /* Record the fields for the semantic handler. */ | |
1376 | FLD (f_r1) = f_r1; | |
1377 | FLD (f_r2) = f_r2; | |
1378 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1379 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1380 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1381 | |
1382 | #if WITH_PROFILE_MODEL_P | |
1383 | /* Record the fields for profiling. */ | |
1384 | if (PROFILE_MODEL_P (current_cpu)) | |
1385 | { | |
1386 | FLD (in_dr) = f_r1; | |
1387 | FLD (in_sr) = f_r2; | |
1388 | FLD (out_dr) = f_r1; | |
1389 | } | |
1390 | #endif | |
1391 | #undef FLD | |
1392 | return idesc; | |
1393 | } | |
1394 | ||
1395 | extract_sfmt_jc: | |
1396 | { | |
1397 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1398 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1399 | #define FLD(f) abuf->fields.sfmt_jl.f |
1400 | UINT f_r2; | |
1401 | ||
1402 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1403 | ||
1404 | /* Record the fields for the semantic handler. */ | |
1405 | FLD (f_r2) = f_r2; | |
1406 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1407 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1408 | |
1409 | #if WITH_PROFILE_MODEL_P | |
1410 | /* Record the fields for profiling. */ | |
1411 | if (PROFILE_MODEL_P (current_cpu)) | |
1412 | { | |
1413 | FLD (in_sr) = f_r2; | |
1414 | } | |
1415 | #endif | |
1416 | #undef FLD | |
1417 | return idesc; | |
1418 | } | |
1419 | ||
1420 | extract_sfmt_jl: | |
1421 | { | |
1422 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1423 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1424 | #define FLD(f) abuf->fields.sfmt_jl.f |
1425 | UINT f_r2; | |
1426 | ||
1427 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1428 | ||
1429 | /* Record the fields for the semantic handler. */ | |
1430 | FLD (f_r2) = f_r2; | |
1431 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1432 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1433 | |
1434 | #if WITH_PROFILE_MODEL_P | |
1435 | /* Record the fields for profiling. */ | |
1436 | if (PROFILE_MODEL_P (current_cpu)) | |
1437 | { | |
1438 | FLD (in_sr) = f_r2; | |
1439 | FLD (out_h_gr_SI_14) = 14; | |
1440 | } | |
1441 | #endif | |
1442 | #undef FLD | |
1443 | return idesc; | |
1444 | } | |
1445 | ||
1446 | extract_sfmt_jmp: | |
1447 | { | |
1448 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1449 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1450 | #define FLD(f) abuf->fields.sfmt_jl.f |
1451 | UINT f_r2; | |
1452 | ||
1453 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1454 | ||
1455 | /* Record the fields for the semantic handler. */ | |
1456 | FLD (f_r2) = f_r2; | |
1457 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1458 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1459 | |
1460 | #if WITH_PROFILE_MODEL_P | |
1461 | /* Record the fields for profiling. */ | |
1462 | if (PROFILE_MODEL_P (current_cpu)) | |
1463 | { | |
1464 | FLD (in_sr) = f_r2; | |
1465 | } | |
1466 | #endif | |
1467 | #undef FLD | |
1468 | return idesc; | |
1469 | } | |
1470 | ||
1471 | extract_sfmt_ld: | |
1472 | { | |
1473 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1474 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1475 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1476 | UINT f_r1; | |
1477 | UINT f_r2; | |
1478 | ||
1479 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1480 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1481 | ||
1482 | /* Record the fields for the semantic handler. */ | |
1483 | FLD (f_r2) = f_r2; | |
1484 | FLD (f_r1) = f_r1; | |
1485 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1486 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1487 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1488 | |
1489 | #if WITH_PROFILE_MODEL_P | |
1490 | /* Record the fields for profiling. */ | |
1491 | if (PROFILE_MODEL_P (current_cpu)) | |
1492 | { | |
1493 | FLD (in_sr) = f_r2; | |
1494 | FLD (out_dr) = f_r1; | |
1495 | } | |
1496 | #endif | |
1497 | #undef FLD | |
1498 | return idesc; | |
1499 | } | |
1500 | ||
1501 | extract_sfmt_ld_d: | |
1502 | { | |
1503 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1504 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1505 | #define FLD(f) abuf->fields.sfmt_add3.f |
1506 | UINT f_r1; | |
1507 | UINT f_r2; | |
1508 | INT f_simm16; | |
1509 | ||
1510 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1511 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1512 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1513 | |
1514 | /* Record the fields for the semantic handler. */ | |
1515 | FLD (f_simm16) = f_simm16; | |
1516 | FLD (f_r2) = f_r2; | |
1517 | FLD (f_r1) = f_r1; | |
1518 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1519 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1520 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1521 | |
1522 | #if WITH_PROFILE_MODEL_P | |
1523 | /* Record the fields for profiling. */ | |
1524 | if (PROFILE_MODEL_P (current_cpu)) | |
1525 | { | |
1526 | FLD (in_sr) = f_r2; | |
1527 | FLD (out_dr) = f_r1; | |
1528 | } | |
1529 | #endif | |
1530 | #undef FLD | |
1531 | return idesc; | |
1532 | } | |
1533 | ||
1534 | extract_sfmt_ldb: | |
1535 | { | |
1536 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1537 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1538 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1539 | UINT f_r1; | |
1540 | UINT f_r2; | |
1541 | ||
1542 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1543 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1544 | ||
1545 | /* Record the fields for the semantic handler. */ | |
1546 | FLD (f_r2) = f_r2; | |
1547 | FLD (f_r1) = f_r1; | |
1548 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1549 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1550 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1551 | |
1552 | #if WITH_PROFILE_MODEL_P | |
1553 | /* Record the fields for profiling. */ | |
1554 | if (PROFILE_MODEL_P (current_cpu)) | |
1555 | { | |
1556 | FLD (in_sr) = f_r2; | |
1557 | FLD (out_dr) = f_r1; | |
1558 | } | |
1559 | #endif | |
1560 | #undef FLD | |
1561 | return idesc; | |
1562 | } | |
1563 | ||
1564 | extract_sfmt_ldb_d: | |
1565 | { | |
1566 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1567 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1568 | #define FLD(f) abuf->fields.sfmt_add3.f |
1569 | UINT f_r1; | |
1570 | UINT f_r2; | |
1571 | INT f_simm16; | |
1572 | ||
1573 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1574 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1575 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1576 | |
1577 | /* Record the fields for the semantic handler. */ | |
1578 | FLD (f_simm16) = f_simm16; | |
1579 | FLD (f_r2) = f_r2; | |
1580 | FLD (f_r1) = f_r1; | |
1581 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1582 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1583 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1584 | |
1585 | #if WITH_PROFILE_MODEL_P | |
1586 | /* Record the fields for profiling. */ | |
1587 | if (PROFILE_MODEL_P (current_cpu)) | |
1588 | { | |
1589 | FLD (in_sr) = f_r2; | |
1590 | FLD (out_dr) = f_r1; | |
1591 | } | |
1592 | #endif | |
1593 | #undef FLD | |
1594 | return idesc; | |
1595 | } | |
1596 | ||
1597 | extract_sfmt_ldh: | |
1598 | { | |
1599 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1600 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1601 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1602 | UINT f_r1; | |
1603 | UINT f_r2; | |
1604 | ||
1605 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1606 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1607 | ||
1608 | /* Record the fields for the semantic handler. */ | |
1609 | FLD (f_r2) = f_r2; | |
1610 | FLD (f_r1) = f_r1; | |
1611 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1612 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1613 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1614 | |
1615 | #if WITH_PROFILE_MODEL_P | |
1616 | /* Record the fields for profiling. */ | |
1617 | if (PROFILE_MODEL_P (current_cpu)) | |
1618 | { | |
1619 | FLD (in_sr) = f_r2; | |
1620 | FLD (out_dr) = f_r1; | |
1621 | } | |
1622 | #endif | |
1623 | #undef FLD | |
1624 | return idesc; | |
1625 | } | |
1626 | ||
1627 | extract_sfmt_ldh_d: | |
1628 | { | |
1629 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1630 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1631 | #define FLD(f) abuf->fields.sfmt_add3.f |
1632 | UINT f_r1; | |
1633 | UINT f_r2; | |
1634 | INT f_simm16; | |
1635 | ||
1636 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1637 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1638 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1639 | |
1640 | /* Record the fields for the semantic handler. */ | |
1641 | FLD (f_simm16) = f_simm16; | |
1642 | FLD (f_r2) = f_r2; | |
1643 | FLD (f_r1) = f_r1; | |
1644 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1645 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1646 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1647 | |
1648 | #if WITH_PROFILE_MODEL_P | |
1649 | /* Record the fields for profiling. */ | |
1650 | if (PROFILE_MODEL_P (current_cpu)) | |
1651 | { | |
1652 | FLD (in_sr) = f_r2; | |
1653 | FLD (out_dr) = f_r1; | |
1654 | } | |
1655 | #endif | |
1656 | #undef FLD | |
1657 | return idesc; | |
1658 | } | |
1659 | ||
1660 | extract_sfmt_ld_plus: | |
1661 | { | |
1662 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1663 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1664 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1665 | UINT f_r1; | |
1666 | UINT f_r2; | |
1667 | ||
1668 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1669 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1670 | ||
1671 | /* Record the fields for the semantic handler. */ | |
1672 | FLD (f_r2) = f_r2; | |
1673 | FLD (f_r1) = f_r1; | |
1674 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1675 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1676 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1677 | |
1678 | #if WITH_PROFILE_MODEL_P | |
1679 | /* Record the fields for profiling. */ | |
1680 | if (PROFILE_MODEL_P (current_cpu)) | |
1681 | { | |
1682 | FLD (in_sr) = f_r2; | |
1683 | FLD (out_dr) = f_r1; | |
1684 | FLD (out_sr) = f_r2; | |
1685 | } | |
1686 | #endif | |
1687 | #undef FLD | |
1688 | return idesc; | |
1689 | } | |
1690 | ||
1691 | extract_sfmt_ld24: | |
1692 | { | |
1693 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1694 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1695 | #define FLD(f) abuf->fields.sfmt_ld24.f |
1696 | UINT f_r1; | |
1697 | UINT f_uimm24; | |
1698 | ||
1699 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1700 | f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); | |
1701 | ||
1702 | /* Record the fields for the semantic handler. */ | |
1703 | FLD (f_r1) = f_r1; | |
1704 | FLD (i_uimm24) = f_uimm24; | |
1705 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1706 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1707 | |
1708 | #if WITH_PROFILE_MODEL_P | |
1709 | /* Record the fields for profiling. */ | |
1710 | if (PROFILE_MODEL_P (current_cpu)) | |
1711 | { | |
1712 | FLD (out_dr) = f_r1; | |
1713 | } | |
1714 | #endif | |
1715 | #undef FLD | |
1716 | return idesc; | |
1717 | } | |
1718 | ||
1719 | extract_sfmt_ldi8: | |
1720 | { | |
1721 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1722 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1723 | #define FLD(f) abuf->fields.sfmt_addi.f |
1724 | UINT f_r1; | |
1725 | INT f_simm8; | |
1726 | ||
1727 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
62836bf4 | 1728 | f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); |
16b47b25 NC |
1729 | |
1730 | /* Record the fields for the semantic handler. */ | |
1731 | FLD (f_simm8) = f_simm8; | |
1732 | FLD (f_r1) = f_r1; | |
1733 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1734 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1735 | |
1736 | #if WITH_PROFILE_MODEL_P | |
1737 | /* Record the fields for profiling. */ | |
1738 | if (PROFILE_MODEL_P (current_cpu)) | |
1739 | { | |
1740 | FLD (out_dr) = f_r1; | |
1741 | } | |
1742 | #endif | |
1743 | #undef FLD | |
1744 | return idesc; | |
1745 | } | |
1746 | ||
1747 | extract_sfmt_ldi16: | |
1748 | { | |
1749 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1750 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1751 | #define FLD(f) abuf->fields.sfmt_add3.f |
1752 | UINT f_r1; | |
1753 | INT f_simm16; | |
1754 | ||
1755 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
62836bf4 | 1756 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1757 | |
1758 | /* Record the fields for the semantic handler. */ | |
1759 | FLD (f_simm16) = f_simm16; | |
1760 | FLD (f_r1) = f_r1; | |
1761 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1762 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1763 | |
1764 | #if WITH_PROFILE_MODEL_P | |
1765 | /* Record the fields for profiling. */ | |
1766 | if (PROFILE_MODEL_P (current_cpu)) | |
1767 | { | |
1768 | FLD (out_dr) = f_r1; | |
1769 | } | |
1770 | #endif | |
1771 | #undef FLD | |
1772 | return idesc; | |
1773 | } | |
1774 | ||
1775 | extract_sfmt_lock: | |
1776 | { | |
1777 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1778 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1779 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1780 | UINT f_r1; | |
1781 | UINT f_r2; | |
1782 | ||
1783 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1784 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1785 | ||
1786 | /* Record the fields for the semantic handler. */ | |
1787 | FLD (f_r2) = f_r2; | |
1788 | FLD (f_r1) = f_r1; | |
1789 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1790 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1791 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1792 | |
1793 | #if WITH_PROFILE_MODEL_P | |
1794 | /* Record the fields for profiling. */ | |
1795 | if (PROFILE_MODEL_P (current_cpu)) | |
1796 | { | |
1797 | FLD (in_sr) = f_r2; | |
1798 | FLD (out_dr) = f_r1; | |
1799 | } | |
1800 | #endif | |
1801 | #undef FLD | |
1802 | return idesc; | |
1803 | } | |
1804 | ||
1805 | extract_sfmt_machi_a: | |
1806 | { | |
1807 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1808 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1809 | #define FLD(f) abuf->fields.sfmt_machi_a.f |
1810 | UINT f_r1; | |
1811 | UINT f_acc; | |
1812 | UINT f_r2; | |
1813 | ||
1814 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1815 | f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); | |
1816 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1817 | ||
1818 | /* Record the fields for the semantic handler. */ | |
1819 | FLD (f_acc) = f_acc; | |
1820 | FLD (f_r1) = f_r1; | |
1821 | FLD (f_r2) = f_r2; | |
1822 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1823 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1824 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1825 | |
1826 | #if WITH_PROFILE_MODEL_P | |
1827 | /* Record the fields for profiling. */ | |
1828 | if (PROFILE_MODEL_P (current_cpu)) | |
1829 | { | |
1830 | FLD (in_src1) = f_r1; | |
1831 | FLD (in_src2) = f_r2; | |
1832 | } | |
1833 | #endif | |
1834 | #undef FLD | |
1835 | return idesc; | |
1836 | } | |
1837 | ||
1838 | extract_sfmt_mulhi_a: | |
1839 | { | |
1840 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1841 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1842 | #define FLD(f) abuf->fields.sfmt_machi_a.f |
1843 | UINT f_r1; | |
1844 | UINT f_acc; | |
1845 | UINT f_r2; | |
1846 | ||
1847 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1848 | f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); | |
1849 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1850 | ||
1851 | /* Record the fields for the semantic handler. */ | |
1852 | FLD (f_r1) = f_r1; | |
1853 | FLD (f_r2) = f_r2; | |
1854 | FLD (f_acc) = f_acc; | |
1855 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1856 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 1857 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
1858 | |
1859 | #if WITH_PROFILE_MODEL_P | |
1860 | /* Record the fields for profiling. */ | |
1861 | if (PROFILE_MODEL_P (current_cpu)) | |
1862 | { | |
1863 | FLD (in_src1) = f_r1; | |
1864 | FLD (in_src2) = f_r2; | |
1865 | } | |
1866 | #endif | |
1867 | #undef FLD | |
1868 | return idesc; | |
1869 | } | |
1870 | ||
1871 | extract_sfmt_mv: | |
1872 | { | |
1873 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1874 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1875 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1876 | UINT f_r1; | |
1877 | UINT f_r2; | |
1878 | ||
1879 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1880 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1881 | ||
1882 | /* Record the fields for the semantic handler. */ | |
1883 | FLD (f_r2) = f_r2; | |
1884 | FLD (f_r1) = f_r1; | |
1885 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1886 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1887 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1888 | |
1889 | #if WITH_PROFILE_MODEL_P | |
1890 | /* Record the fields for profiling. */ | |
1891 | if (PROFILE_MODEL_P (current_cpu)) | |
1892 | { | |
1893 | FLD (in_sr) = f_r2; | |
1894 | FLD (out_dr) = f_r1; | |
1895 | } | |
1896 | #endif | |
1897 | #undef FLD | |
1898 | return idesc; | |
1899 | } | |
1900 | ||
1901 | extract_sfmt_mvfachi_a: | |
1902 | { | |
1903 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1904 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1905 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f |
1906 | UINT f_r1; | |
1907 | UINT f_accs; | |
1908 | ||
1909 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1910 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1911 | ||
1912 | /* Record the fields for the semantic handler. */ | |
1913 | FLD (f_accs) = f_accs; | |
1914 | FLD (f_r1) = f_r1; | |
1915 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1916 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1917 | |
1918 | #if WITH_PROFILE_MODEL_P | |
1919 | /* Record the fields for profiling. */ | |
1920 | if (PROFILE_MODEL_P (current_cpu)) | |
1921 | { | |
1922 | FLD (out_dr) = f_r1; | |
1923 | } | |
1924 | #endif | |
1925 | #undef FLD | |
1926 | return idesc; | |
1927 | } | |
1928 | ||
1929 | extract_sfmt_mvfc: | |
1930 | { | |
1931 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1932 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1933 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1934 | UINT f_r1; | |
1935 | UINT f_r2; | |
1936 | ||
1937 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1938 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1939 | ||
1940 | /* Record the fields for the semantic handler. */ | |
1941 | FLD (f_r2) = f_r2; | |
1942 | FLD (f_r1) = f_r1; | |
1943 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1944 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1945 | |
1946 | #if WITH_PROFILE_MODEL_P | |
1947 | /* Record the fields for profiling. */ | |
1948 | if (PROFILE_MODEL_P (current_cpu)) | |
1949 | { | |
1950 | FLD (out_dr) = f_r1; | |
1951 | } | |
1952 | #endif | |
1953 | #undef FLD | |
1954 | return idesc; | |
1955 | } | |
1956 | ||
1957 | extract_sfmt_mvtachi_a: | |
1958 | { | |
1959 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1960 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1961 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f |
1962 | UINT f_r1; | |
1963 | UINT f_accs; | |
1964 | ||
1965 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1966 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1967 | ||
1968 | /* Record the fields for the semantic handler. */ | |
1969 | FLD (f_accs) = f_accs; | |
1970 | FLD (f_r1) = f_r1; | |
1971 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 1972 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
1973 | |
1974 | #if WITH_PROFILE_MODEL_P | |
1975 | /* Record the fields for profiling. */ | |
1976 | if (PROFILE_MODEL_P (current_cpu)) | |
1977 | { | |
1978 | FLD (in_src1) = f_r1; | |
1979 | } | |
1980 | #endif | |
1981 | #undef FLD | |
1982 | return idesc; | |
1983 | } | |
1984 | ||
1985 | extract_sfmt_mvtc: | |
1986 | { | |
1987 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1988 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1989 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1990 | UINT f_r1; | |
1991 | UINT f_r2; | |
1992 | ||
1993 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1994 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1995 | ||
1996 | /* Record the fields for the semantic handler. */ | |
1997 | FLD (f_r2) = f_r2; | |
1998 | FLD (f_r1) = f_r1; | |
1999 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2000 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2001 | |
2002 | #if WITH_PROFILE_MODEL_P | |
2003 | /* Record the fields for profiling. */ | |
2004 | if (PROFILE_MODEL_P (current_cpu)) | |
2005 | { | |
2006 | FLD (in_sr) = f_r2; | |
2007 | } | |
2008 | #endif | |
2009 | #undef FLD | |
2010 | return idesc; | |
2011 | } | |
2012 | ||
2013 | extract_sfmt_nop: | |
2014 | { | |
2015 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 2016 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2017 | |
2018 | ||
2019 | /* Record the fields for the semantic handler. */ | |
db7858e2 | 2020 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); |
16b47b25 NC |
2021 | |
2022 | #undef FLD | |
2023 | return idesc; | |
2024 | } | |
2025 | ||
2026 | extract_sfmt_rac_dsi: | |
2027 | { | |
2028 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2029 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2030 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f |
2031 | UINT f_accd; | |
2032 | UINT f_accs; | |
2033 | SI f_imm1; | |
2034 | ||
2035 | f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); | |
2036 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
2037 | f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); | |
2038 | ||
2039 | /* Record the fields for the semantic handler. */ | |
2040 | FLD (f_accs) = f_accs; | |
2041 | FLD (f_imm1) = f_imm1; | |
2042 | FLD (f_accd) = f_accd; | |
db7858e2 | 2043 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0)); |
16b47b25 NC |
2044 | |
2045 | #undef FLD | |
2046 | return idesc; | |
2047 | } | |
2048 | ||
2049 | extract_sfmt_rte: | |
2050 | { | |
2051 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 2052 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2053 | |
2054 | ||
2055 | /* Record the fields for the semantic handler. */ | |
db7858e2 | 2056 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); |
16b47b25 NC |
2057 | |
2058 | #if WITH_PROFILE_MODEL_P | |
2059 | /* Record the fields for profiling. */ | |
2060 | if (PROFILE_MODEL_P (current_cpu)) | |
2061 | { | |
2062 | } | |
2063 | #endif | |
2064 | #undef FLD | |
2065 | return idesc; | |
2066 | } | |
2067 | ||
2068 | extract_sfmt_seth: | |
2069 | { | |
2070 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2071 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2072 | #define FLD(f) abuf->fields.sfmt_seth.f |
2073 | UINT f_r1; | |
2074 | UINT f_hi16; | |
2075 | ||
2076 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2077 | f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
2078 | ||
2079 | /* Record the fields for the semantic handler. */ | |
2080 | FLD (f_hi16) = f_hi16; | |
2081 | FLD (f_r1) = f_r1; | |
2082 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 2083 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
2084 | |
2085 | #if WITH_PROFILE_MODEL_P | |
2086 | /* Record the fields for profiling. */ | |
2087 | if (PROFILE_MODEL_P (current_cpu)) | |
2088 | { | |
2089 | FLD (out_dr) = f_r1; | |
2090 | } | |
2091 | #endif | |
2092 | #undef FLD | |
2093 | return idesc; | |
2094 | } | |
2095 | ||
2096 | extract_sfmt_sll3: | |
2097 | { | |
2098 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2099 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2100 | #define FLD(f) abuf->fields.sfmt_add3.f |
2101 | UINT f_r1; | |
2102 | UINT f_r2; | |
2103 | INT f_simm16; | |
2104 | ||
2105 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2106 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2107 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2108 | |
2109 | /* Record the fields for the semantic handler. */ | |
2110 | FLD (f_simm16) = f_simm16; | |
2111 | FLD (f_r2) = f_r2; | |
2112 | FLD (f_r1) = f_r1; | |
2113 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2114 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 2115 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
2116 | |
2117 | #if WITH_PROFILE_MODEL_P | |
2118 | /* Record the fields for profiling. */ | |
2119 | if (PROFILE_MODEL_P (current_cpu)) | |
2120 | { | |
2121 | FLD (in_sr) = f_r2; | |
2122 | FLD (out_dr) = f_r1; | |
2123 | } | |
2124 | #endif | |
2125 | #undef FLD | |
2126 | return idesc; | |
2127 | } | |
2128 | ||
2129 | extract_sfmt_slli: | |
2130 | { | |
2131 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2132 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2133 | #define FLD(f) abuf->fields.sfmt_slli.f |
2134 | UINT f_r1; | |
2135 | UINT f_uimm5; | |
2136 | ||
2137 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2138 | f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); | |
2139 | ||
2140 | /* Record the fields for the semantic handler. */ | |
2141 | FLD (f_r1) = f_r1; | |
2142 | FLD (f_uimm5) = f_uimm5; | |
2143 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 2144 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
2145 | |
2146 | #if WITH_PROFILE_MODEL_P | |
2147 | /* Record the fields for profiling. */ | |
2148 | if (PROFILE_MODEL_P (current_cpu)) | |
2149 | { | |
2150 | FLD (in_dr) = f_r1; | |
2151 | FLD (out_dr) = f_r1; | |
2152 | } | |
2153 | #endif | |
2154 | #undef FLD | |
2155 | return idesc; | |
2156 | } | |
2157 | ||
2158 | extract_sfmt_st: | |
2159 | { | |
2160 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2161 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2162 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2163 | UINT f_r1; | |
2164 | UINT f_r2; | |
2165 | ||
2166 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2167 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2168 | ||
2169 | /* Record the fields for the semantic handler. */ | |
2170 | FLD (f_r1) = f_r1; | |
2171 | FLD (f_r2) = f_r2; | |
2172 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2173 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2174 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2175 | |
2176 | #if WITH_PROFILE_MODEL_P | |
2177 | /* Record the fields for profiling. */ | |
2178 | if (PROFILE_MODEL_P (current_cpu)) | |
2179 | { | |
2180 | FLD (in_src1) = f_r1; | |
2181 | FLD (in_src2) = f_r2; | |
2182 | } | |
2183 | #endif | |
2184 | #undef FLD | |
2185 | return idesc; | |
2186 | } | |
2187 | ||
2188 | extract_sfmt_st_d: | |
2189 | { | |
2190 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2191 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2192 | #define FLD(f) abuf->fields.sfmt_st_d.f |
2193 | UINT f_r1; | |
2194 | UINT f_r2; | |
2195 | INT f_simm16; | |
2196 | ||
2197 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2198 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2199 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2200 | |
2201 | /* Record the fields for the semantic handler. */ | |
2202 | FLD (f_simm16) = f_simm16; | |
2203 | FLD (f_r1) = f_r1; | |
2204 | FLD (f_r2) = f_r2; | |
2205 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2206 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2207 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2208 | |
2209 | #if WITH_PROFILE_MODEL_P | |
2210 | /* Record the fields for profiling. */ | |
2211 | if (PROFILE_MODEL_P (current_cpu)) | |
2212 | { | |
2213 | FLD (in_src1) = f_r1; | |
2214 | FLD (in_src2) = f_r2; | |
2215 | } | |
2216 | #endif | |
2217 | #undef FLD | |
2218 | return idesc; | |
2219 | } | |
2220 | ||
2221 | extract_sfmt_stb: | |
2222 | { | |
2223 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2224 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2225 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2226 | UINT f_r1; | |
2227 | UINT f_r2; | |
2228 | ||
2229 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2230 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2231 | ||
2232 | /* Record the fields for the semantic handler. */ | |
2233 | FLD (f_r1) = f_r1; | |
2234 | FLD (f_r2) = f_r2; | |
2235 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2236 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2237 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2238 | |
2239 | #if WITH_PROFILE_MODEL_P | |
2240 | /* Record the fields for profiling. */ | |
2241 | if (PROFILE_MODEL_P (current_cpu)) | |
2242 | { | |
2243 | FLD (in_src1) = f_r1; | |
2244 | FLD (in_src2) = f_r2; | |
2245 | } | |
2246 | #endif | |
2247 | #undef FLD | |
2248 | return idesc; | |
2249 | } | |
2250 | ||
2251 | extract_sfmt_stb_d: | |
2252 | { | |
2253 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2254 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2255 | #define FLD(f) abuf->fields.sfmt_st_d.f |
2256 | UINT f_r1; | |
2257 | UINT f_r2; | |
2258 | INT f_simm16; | |
2259 | ||
2260 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2261 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2262 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2263 | |
2264 | /* Record the fields for the semantic handler. */ | |
2265 | FLD (f_simm16) = f_simm16; | |
2266 | FLD (f_r1) = f_r1; | |
2267 | FLD (f_r2) = f_r2; | |
2268 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2269 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2270 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2271 | |
2272 | #if WITH_PROFILE_MODEL_P | |
2273 | /* Record the fields for profiling. */ | |
2274 | if (PROFILE_MODEL_P (current_cpu)) | |
2275 | { | |
2276 | FLD (in_src1) = f_r1; | |
2277 | FLD (in_src2) = f_r2; | |
2278 | } | |
2279 | #endif | |
2280 | #undef FLD | |
2281 | return idesc; | |
2282 | } | |
2283 | ||
2284 | extract_sfmt_sth: | |
2285 | { | |
2286 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2287 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2288 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2289 | UINT f_r1; | |
2290 | UINT f_r2; | |
2291 | ||
2292 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2293 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2294 | ||
2295 | /* Record the fields for the semantic handler. */ | |
2296 | FLD (f_r1) = f_r1; | |
2297 | FLD (f_r2) = f_r2; | |
2298 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2299 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2300 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2301 | |
2302 | #if WITH_PROFILE_MODEL_P | |
2303 | /* Record the fields for profiling. */ | |
2304 | if (PROFILE_MODEL_P (current_cpu)) | |
2305 | { | |
2306 | FLD (in_src1) = f_r1; | |
2307 | FLD (in_src2) = f_r2; | |
2308 | } | |
2309 | #endif | |
2310 | #undef FLD | |
2311 | return idesc; | |
2312 | } | |
2313 | ||
2314 | extract_sfmt_sth_d: | |
2315 | { | |
2316 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2317 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2318 | #define FLD(f) abuf->fields.sfmt_st_d.f |
2319 | UINT f_r1; | |
2320 | UINT f_r2; | |
2321 | INT f_simm16; | |
2322 | ||
2323 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2324 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2325 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2326 | |
2327 | /* Record the fields for the semantic handler. */ | |
2328 | FLD (f_simm16) = f_simm16; | |
2329 | FLD (f_r1) = f_r1; | |
2330 | FLD (f_r2) = f_r2; | |
2331 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2332 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2333 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2334 | |
2335 | #if WITH_PROFILE_MODEL_P | |
2336 | /* Record the fields for profiling. */ | |
2337 | if (PROFILE_MODEL_P (current_cpu)) | |
2338 | { | |
2339 | FLD (in_src1) = f_r1; | |
2340 | FLD (in_src2) = f_r2; | |
2341 | } | |
2342 | #endif | |
2343 | #undef FLD | |
2344 | return idesc; | |
2345 | } | |
2346 | ||
2347 | extract_sfmt_st_plus: | |
2348 | { | |
2349 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2350 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2351 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2352 | UINT f_r1; | |
2353 | UINT f_r2; | |
2354 | ||
2355 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2356 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2357 | ||
2358 | /* Record the fields for the semantic handler. */ | |
2359 | FLD (f_r1) = f_r1; | |
2360 | FLD (f_r2) = f_r2; | |
2361 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2362 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2363 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2364 | |
2365 | #if WITH_PROFILE_MODEL_P | |
2366 | /* Record the fields for profiling. */ | |
2367 | if (PROFILE_MODEL_P (current_cpu)) | |
2368 | { | |
2369 | FLD (in_src1) = f_r1; | |
2370 | FLD (in_src2) = f_r2; | |
2371 | FLD (out_src2) = f_r2; | |
2372 | } | |
2373 | #endif | |
2374 | #undef FLD | |
2375 | return idesc; | |
2376 | } | |
2377 | ||
2378 | extract_sfmt_sth_plus: | |
2379 | { | |
2380 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2381 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2382 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2383 | UINT f_r1; | |
2384 | UINT f_r2; | |
2385 | ||
2386 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2387 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2388 | ||
2389 | /* Record the fields for the semantic handler. */ | |
2390 | FLD (f_r1) = f_r1; | |
2391 | FLD (f_r2) = f_r2; | |
2392 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2393 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2394 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2395 | |
2396 | #if WITH_PROFILE_MODEL_P | |
2397 | /* Record the fields for profiling. */ | |
2398 | if (PROFILE_MODEL_P (current_cpu)) | |
2399 | { | |
2400 | FLD (in_src1) = f_r1; | |
2401 | FLD (in_src2) = f_r2; | |
2402 | FLD (out_src2) = f_r2; | |
2403 | } | |
2404 | #endif | |
2405 | #undef FLD | |
2406 | return idesc; | |
2407 | } | |
2408 | ||
2409 | extract_sfmt_stb_plus: | |
2410 | { | |
2411 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2412 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2413 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2414 | UINT f_r1; | |
2415 | UINT f_r2; | |
2416 | ||
2417 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2418 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2419 | ||
2420 | /* Record the fields for the semantic handler. */ | |
2421 | FLD (f_r1) = f_r1; | |
2422 | FLD (f_r2) = f_r2; | |
2423 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2424 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2425 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2426 | |
2427 | #if WITH_PROFILE_MODEL_P | |
2428 | /* Record the fields for profiling. */ | |
2429 | if (PROFILE_MODEL_P (current_cpu)) | |
2430 | { | |
2431 | FLD (in_src1) = f_r1; | |
2432 | FLD (in_src2) = f_r2; | |
2433 | FLD (out_src2) = f_r2; | |
2434 | } | |
2435 | #endif | |
2436 | #undef FLD | |
2437 | return idesc; | |
2438 | } | |
2439 | ||
2440 | extract_sfmt_trap: | |
2441 | { | |
2442 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2443 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2444 | #define FLD(f) abuf->fields.sfmt_trap.f |
2445 | UINT f_uimm4; | |
2446 | ||
2447 | f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2448 | ||
2449 | /* Record the fields for the semantic handler. */ | |
2450 | FLD (f_uimm4) = f_uimm4; | |
db7858e2 | 2451 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); |
16b47b25 NC |
2452 | |
2453 | #if WITH_PROFILE_MODEL_P | |
2454 | /* Record the fields for profiling. */ | |
2455 | if (PROFILE_MODEL_P (current_cpu)) | |
2456 | { | |
2457 | } | |
2458 | #endif | |
2459 | #undef FLD | |
2460 | return idesc; | |
2461 | } | |
2462 | ||
2463 | extract_sfmt_unlock: | |
2464 | { | |
2465 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2466 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2467 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2468 | UINT f_r1; | |
2469 | UINT f_r2; | |
2470 | ||
2471 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2472 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2473 | ||
2474 | /* Record the fields for the semantic handler. */ | |
2475 | FLD (f_r1) = f_r1; | |
2476 | FLD (f_r2) = f_r2; | |
2477 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2478 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2479 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2480 | |
2481 | #if WITH_PROFILE_MODEL_P | |
2482 | /* Record the fields for profiling. */ | |
2483 | if (PROFILE_MODEL_P (current_cpu)) | |
2484 | { | |
2485 | FLD (in_src1) = f_r1; | |
2486 | FLD (in_src2) = f_r2; | |
2487 | } | |
2488 | #endif | |
2489 | #undef FLD | |
2490 | return idesc; | |
2491 | } | |
2492 | ||
2493 | extract_sfmt_satb: | |
2494 | { | |
2495 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2496 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2497 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
2498 | UINT f_r1; | |
2499 | UINT f_r2; | |
2500 | ||
2501 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2502 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2503 | ||
2504 | /* Record the fields for the semantic handler. */ | |
2505 | FLD (f_r2) = f_r2; | |
2506 | FLD (f_r1) = f_r1; | |
2507 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2508 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 2509 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
2510 | |
2511 | #if WITH_PROFILE_MODEL_P | |
2512 | /* Record the fields for profiling. */ | |
2513 | if (PROFILE_MODEL_P (current_cpu)) | |
2514 | { | |
2515 | FLD (in_sr) = f_r2; | |
2516 | FLD (out_dr) = f_r1; | |
2517 | } | |
2518 | #endif | |
2519 | #undef FLD | |
2520 | return idesc; | |
2521 | } | |
2522 | ||
2523 | extract_sfmt_sat: | |
2524 | { | |
2525 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2526 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2527 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
2528 | UINT f_r1; | |
2529 | UINT f_r2; | |
2530 | ||
2531 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2532 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2533 | ||
2534 | /* Record the fields for the semantic handler. */ | |
2535 | FLD (f_r2) = f_r2; | |
2536 | FLD (f_r1) = f_r1; | |
2537 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2538 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
db7858e2 | 2539 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
16b47b25 NC |
2540 | |
2541 | #if WITH_PROFILE_MODEL_P | |
2542 | /* Record the fields for profiling. */ | |
2543 | if (PROFILE_MODEL_P (current_cpu)) | |
2544 | { | |
2545 | FLD (in_sr) = f_r2; | |
2546 | FLD (out_dr) = f_r1; | |
2547 | } | |
2548 | #endif | |
2549 | #undef FLD | |
2550 | return idesc; | |
2551 | } | |
2552 | ||
2553 | extract_sfmt_sadd: | |
2554 | { | |
2555 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 2556 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2557 | |
2558 | ||
2559 | /* Record the fields for the semantic handler. */ | |
db7858e2 | 2560 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0)); |
16b47b25 NC |
2561 | |
2562 | #undef FLD | |
2563 | return idesc; | |
2564 | } | |
2565 | ||
2566 | extract_sfmt_macwu1: | |
2567 | { | |
2568 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2569 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2570 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2571 | UINT f_r1; | |
2572 | UINT f_r2; | |
2573 | ||
2574 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2575 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2576 | ||
2577 | /* Record the fields for the semantic handler. */ | |
2578 | FLD (f_r1) = f_r1; | |
2579 | FLD (f_r2) = f_r2; | |
2580 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2581 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2582 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2583 | |
2584 | #if WITH_PROFILE_MODEL_P | |
2585 | /* Record the fields for profiling. */ | |
2586 | if (PROFILE_MODEL_P (current_cpu)) | |
2587 | { | |
2588 | FLD (in_src1) = f_r1; | |
2589 | FLD (in_src2) = f_r2; | |
2590 | } | |
2591 | #endif | |
2592 | #undef FLD | |
2593 | return idesc; | |
2594 | } | |
2595 | ||
2596 | extract_sfmt_msblo: | |
2597 | { | |
2598 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2599 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2600 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2601 | UINT f_r1; | |
2602 | UINT f_r2; | |
2603 | ||
2604 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2605 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2606 | ||
2607 | /* Record the fields for the semantic handler. */ | |
2608 | FLD (f_r1) = f_r1; | |
2609 | FLD (f_r2) = f_r2; | |
2610 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2611 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2612 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2613 | |
2614 | #if WITH_PROFILE_MODEL_P | |
2615 | /* Record the fields for profiling. */ | |
2616 | if (PROFILE_MODEL_P (current_cpu)) | |
2617 | { | |
2618 | FLD (in_src1) = f_r1; | |
2619 | FLD (in_src2) = f_r2; | |
2620 | } | |
2621 | #endif | |
2622 | #undef FLD | |
2623 | return idesc; | |
2624 | } | |
2625 | ||
2626 | extract_sfmt_mulwu1: | |
2627 | { | |
2628 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2629 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2630 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2631 | UINT f_r1; | |
2632 | UINT f_r2; | |
2633 | ||
2634 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2635 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2636 | ||
2637 | /* Record the fields for the semantic handler. */ | |
2638 | FLD (f_r1) = f_r1; | |
2639 | FLD (f_r2) = f_r2; | |
2640 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2641 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2642 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2643 | |
2644 | #if WITH_PROFILE_MODEL_P | |
2645 | /* Record the fields for profiling. */ | |
2646 | if (PROFILE_MODEL_P (current_cpu)) | |
2647 | { | |
2648 | FLD (in_src1) = f_r1; | |
2649 | FLD (in_src2) = f_r2; | |
2650 | } | |
2651 | #endif | |
2652 | #undef FLD | |
2653 | return idesc; | |
2654 | } | |
2655 | ||
2656 | extract_sfmt_sc: | |
2657 | { | |
2658 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 2659 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2660 | |
2661 | ||
2662 | /* Record the fields for the semantic handler. */ | |
db7858e2 | 2663 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0)); |
16b47b25 NC |
2664 | |
2665 | #undef FLD | |
2666 | return idesc; | |
2667 | } | |
2668 | ||
2669 | extract_sfmt_clrpsw: | |
2670 | { | |
2671 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2672 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2673 | #define FLD(f) abuf->fields.sfmt_clrpsw.f |
2674 | UINT f_uimm8; | |
2675 | ||
2676 | f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); | |
2677 | ||
2678 | /* Record the fields for the semantic handler. */ | |
2679 | FLD (f_uimm8) = f_uimm8; | |
db7858e2 | 2680 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); |
16b47b25 NC |
2681 | |
2682 | #undef FLD | |
2683 | return idesc; | |
2684 | } | |
2685 | ||
2686 | extract_sfmt_setpsw: | |
2687 | { | |
2688 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2689 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2690 | #define FLD(f) abuf->fields.sfmt_clrpsw.f |
2691 | UINT f_uimm8; | |
2692 | ||
2693 | f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); | |
2694 | ||
2695 | /* Record the fields for the semantic handler. */ | |
2696 | FLD (f_uimm8) = f_uimm8; | |
db7858e2 | 2697 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); |
16b47b25 NC |
2698 | |
2699 | #undef FLD | |
2700 | return idesc; | |
2701 | } | |
2702 | ||
2703 | extract_sfmt_bset: | |
2704 | { | |
2705 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2706 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2707 | #define FLD(f) abuf->fields.sfmt_bset.f |
2708 | UINT f_uimm3; | |
2709 | UINT f_r2; | |
2710 | INT f_simm16; | |
2711 | ||
2712 | f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); | |
2713 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2714 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2715 | |
2716 | /* Record the fields for the semantic handler. */ | |
2717 | FLD (f_simm16) = f_simm16; | |
2718 | FLD (f_r2) = f_r2; | |
2719 | FLD (f_uimm3) = f_uimm3; | |
2720 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2721 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2722 | |
2723 | #if WITH_PROFILE_MODEL_P | |
2724 | /* Record the fields for profiling. */ | |
2725 | if (PROFILE_MODEL_P (current_cpu)) | |
2726 | { | |
2727 | FLD (in_sr) = f_r2; | |
2728 | } | |
2729 | #endif | |
2730 | #undef FLD | |
2731 | return idesc; | |
2732 | } | |
2733 | ||
2734 | extract_sfmt_btst: | |
2735 | { | |
2736 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2737 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2738 | #define FLD(f) abuf->fields.sfmt_bset.f |
2739 | UINT f_uimm3; | |
2740 | UINT f_r2; | |
2741 | ||
2742 | f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); | |
2743 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2744 | ||
2745 | /* Record the fields for the semantic handler. */ | |
2746 | FLD (f_r2) = f_r2; | |
2747 | FLD (f_uimm3) = f_uimm3; | |
2748 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
db7858e2 | 2749 | CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); |
16b47b25 NC |
2750 | |
2751 | #if WITH_PROFILE_MODEL_P | |
2752 | /* Record the fields for profiling. */ | |
2753 | if (PROFILE_MODEL_P (current_cpu)) | |
2754 | { | |
2755 | FLD (in_sr) = f_r2; | |
2756 | } | |
2757 | #endif | |
2758 | #undef FLD | |
2759 | return idesc; | |
2760 | } | |
2761 | ||
2762 | } |