[thirdparty/binutils-gdb.git] / sim / m32r / m32r-sim.h

/* collection of junk waiting time to sort out
   Copyright (C) 1996-2023 Free Software Foundation, Inc.
   Contributed by Cygnus Support.

   This file is part of GDB, the GNU debugger.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef M32R_SIM_H
#define M32R_SIM_H

#include "symcat.h"

/* GDB register numbers.  */
#define PSW_REGNUM	16
#define CBR_REGNUM	17
#define SPI_REGNUM	18
#define SPU_REGNUM	19
#define BPC_REGNUM	20
#define PC_REGNUM	21
#define ACCL_REGNUM	22
#define ACCH_REGNUM	23
#define ACC1L_REGNUM	24
#define ACC1H_REGNUM	25
#define BBPSW_REGNUM	26
#define BBPC_REGNUM	27
#define EVB_REGNUM	28

extern int m32r_decode_gdb_ctrl_regnum (int);

/* Cover macros for hardware accesses.
   FIXME: Eventually move to cgen.  */
#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)

#ifndef GET_H_CR
extern USI  m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);

#define GET_H_CR(regno) \
  XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
#define SET_H_CR(regno, val) \
  XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
#endif

#ifndef  GET_H_PSW
extern UQI  m32rbf_h_psw_get_handler (SIM_CPU *);
extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);

#define GET_H_PSW() \
  XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
#define SET_H_PSW(val) \
  XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
#endif

/* FIXME: These prototypes are necessary because the cgen generated
   cpu.h, cpux.h and cpu2.h headers do not provide them, and functions
   which take or return parameters that are larger than an int must be
   prototyed in order for them to work correctly.

   The correct solution is to fix the code in cgen/sim.scm to generate
   prototypes for each of the functions it generates.  */
extern DI   m32rbf_h_accum_get_handler (SIM_CPU *);
extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
extern DI   m32r2f_h_accums_get_handler (SIM_CPU *, UINT);
extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI);

#ifndef  GET_H_ACCUM
#define GET_H_ACCUM() \
  XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
#define SET_H_ACCUM(val) \
  XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
#endif
\f
/* Misc. profile data.  */

typedef struct {
  /* nop insn slot filler count */
  unsigned int fillnop_count;
  /* number of parallel insns */
  unsigned int parallel_count;

  /* FIXME: generalize this to handle all insn lengths, move to common.  */
  /* number of short insns, not including parallel ones */
  unsigned int short_count;
  /* number of long insns */
  unsigned int long_count;

  /* Working area for computing cycle counts.  */
  unsigned long insn_cycles; /* FIXME: delete */
  unsigned long cti_stall;
  unsigned long load_stall;
  unsigned long biggest_cycles;

  /* Bitmask of registers loaded by previous insn.  */
  unsigned int load_regs;
  /* Bitmask of registers loaded by current insn.  */
  unsigned int load_regs_pending;
} M32R_MISC_PROFILE;

/* Initialize the working area.  */
void m32r_init_insn_cycles (SIM_CPU *, int);
/* Update the totals for the insn.  */
void m32r_record_insn_cycles (SIM_CPU *, int);

/* This is invoked by the nop pattern in the .cpu file.  */
#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
do { \
  if (PROFILE_INSN_P (cpu) \
      && (addr & 3) != 0) \
    ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
} while (0)

/* This is invoked by the execute section of mloop{,x}.in.  */
#define PROFILE_COUNT_PARINSNS(cpu) \
do { \
  if (PROFILE_INSN_P (cpu)) \
    ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
} while (0)

/* This is invoked by the execute section of mloop{,x}.in.  */
#define PROFILE_COUNT_SHORTINSNS(cpu) \
do { \
  if (PROFILE_INSN_P (cpu)) \
    ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
} while (0)

/* This is invoked by the execute section of mloop{,x}.in.  */
#define PROFILE_COUNT_LONGINSNS(cpu) \
do { \
  if (PROFILE_INSN_P (cpu)) \
    ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
} while (0)
\f
#define GETTWI GETTSI
#define SETTWI SETTSI
\f
/* Additional execution support.  */

\f
/* Hardware/device support.
   ??? Will eventually want to move device stuff to config files.  */

/* Exception, Interrupt, and Trap addresses */
#define EIT_SYSBREAK_ADDR	0x10
#define EIT_RSVD_INSN_ADDR	0x20
#define EIT_ADDR_EXCP_ADDR	0x30
#define EIT_TRAP_BASE_ADDR	0x40
#define EIT_EXTERN_ADDR		0x80
#define EIT_RESET_ADDR		0x7ffffff0
#define EIT_WAKEUP_ADDR		0x7ffffff0

/* Special purpose traps.  */
#define TRAP_SYSCALL	0
#define TRAP_BREAKPOINT	1

/* Handle the trap insn.  */
USI m32r_trap (SIM_CPU *, PCADDR, int);
\f
struct m32r_sim_cpu {
  M32R_MISC_PROFILE m32r_misc_profile;
#define CPU_M32R_MISC_PROFILE(cpu) (& M32R_SIM_CPU (cpu)->m32r_misc_profile)

  /* CPU specific parts go here.
     Note that in files that don't need to access these pieces WANT_CPU_FOO
     won't be defined and thus these parts won't appear.  This is ok in the
     sense that things work.  It is a source of bugs though.
     One has to of course be careful to not take the size of this
     struct and no structure members accessed in non-cpu specific files can
     go after here.  Oh for a better language.  */
#if defined (WANT_CPU_M32RBF)
  M32RBF_CPU_DATA cpu_data;
#endif
#if defined (WANT_CPU_M32RXF)
  M32RXF_CPU_DATA cpu_data;
#elif defined (WANT_CPU_M32R2F)
  M32R2F_CPU_DATA cpu_data;
#endif
};
#define M32R_SIM_CPU(cpu) ((struct m32r_sim_cpu *) CPU_ARCH_DATA (cpu))

#endif /* M32R_SIM_H */
Commit	Line	Data
c906108c	1	/* collection of junk waiting time to sort out
213516ef	2	Copyright (C) 1996-2023 Free Software Foundation, Inc.
c906108c SS	3	Contributed by Cygnus Support.
c906108c SS	4
16b47b25	5	This file is part of GDB, the GNU debugger.
c906108c	6
16b47b25 NC	7	This program is free software; you can redistribute it and/or modify
16b47b25 NC	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
c906108c	11
16b47b25 NC	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
c906108c	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c SS	19
	20	#ifndef M32R_SIM_H
	21	#define M32R_SIM_H
	22
3eaecff5 MF	23	#include "symcat.h"
3eaecff5 MF	24
16b47b25	25	/* GDB register numbers. */
c906108c SS	26	#define PSW_REGNUM 16
	27	#define CBR_REGNUM 17
	28	#define SPI_REGNUM 18
	29	#define SPU_REGNUM 19
	30	#define BPC_REGNUM 20
	31	#define PC_REGNUM 21
	32	#define ACCL_REGNUM 22
	33	#define ACCH_REGNUM 23
	34	#define ACC1L_REGNUM 24
	35	#define ACC1H_REGNUM 25
	36	#define BBPSW_REGNUM 26
	37	#define BBPC_REGNUM 27
16b47b25	38	#define EVB_REGNUM 28
c906108c SS	39
	40	extern int m32r_decode_gdb_ctrl_regnum (int);
	41
	42	/* Cover macros for hardware accesses.
	43	FIXME: Eventually move to cgen. */
	44	#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
	45
16b47b25 NC	46	#ifndef GET_H_CR
16b47b25 NC	47	extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
c906108c	48	extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
16b47b25	49
0b2e03b4 AC	50	#define GET_H_CR(regno) \
	51	XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
	52	#define SET_H_CR(regno, val) \
	53	XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
16b47b25	54	#endif
c906108c	55
16b47b25 NC	56	#ifndef GET_H_PSW
16b47b25 NC	57	extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
c906108c	58	extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
16b47b25	59
0b2e03b4 AC	60	#define GET_H_PSW() \
	61	XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
	62	#define SET_H_PSW(val) \
	63	XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
16b47b25	64	#endif
c906108c	65
94cde56a NC	66	/* FIXME: These prototypes are necessary because the cgen generated
	67	cpu.h, cpux.h and cpu2.h headers do not provide them, and functions
	68	which take or return parameters that are larger than an int must be
	69	prototyed in order for them to work correctly.
	70
	71	The correct solution is to fix the code in cgen/sim.scm to generate
	72	prototypes for each of the functions it generates. */
16b47b25	73	extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
c906108c	74	extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
94cde56a NC	75	extern DI m32r2f_h_accums_get_handler (SIM_CPU *, UINT);
94cde56a NC	76	extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI);
16b47b25	77
94cde56a	78	#ifndef GET_H_ACCUM
0b2e03b4 AC	79	#define GET_H_ACCUM() \
	80	XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
	81	#define SET_H_ACCUM(val) \
	82	XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
16b47b25	83	#endif
c906108c SS	84	\f
	85	/* Misc. profile data. */
	86
	87	typedef struct {
	88	/* nop insn slot filler count */
	89	unsigned int fillnop_count;
	90	/* number of parallel insns */
	91	unsigned int parallel_count;
	92
	93	/* FIXME: generalize this to handle all insn lengths, move to common. */
	94	/* number of short insns, not including parallel ones */
	95	unsigned int short_count;
	96	/* number of long insns */
	97	unsigned int long_count;
	98
	99	/* Working area for computing cycle counts. */
	100	unsigned long insn_cycles; /* FIXME: delete */
	101	unsigned long cti_stall;
	102	unsigned long load_stall;
	103	unsigned long biggest_cycles;
	104
	105	/* Bitmask of registers loaded by previous insn. */
	106	unsigned int load_regs;
	107	/* Bitmask of registers loaded by current insn. */
	108	unsigned int load_regs_pending;
	109	} M32R_MISC_PROFILE;
	110
	111	/* Initialize the working area. */
	112	void m32r_init_insn_cycles (SIM_CPU *, int);
	113	/* Update the totals for the insn. */
	114	void m32r_record_insn_cycles (SIM_CPU *, int);
	115
	116	/* This is invoked by the nop pattern in the .cpu file. */
	117	#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
	118	do { \
	119	if (PROFILE_INSN_P (cpu) \
	120	&& (addr & 3) != 0) \
	121	++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
	122	} while (0)
	123
	124	/* This is invoked by the execute section of mloop{,x}.in. */
	125	#define PROFILE_COUNT_PARINSNS(cpu) \
	126	do { \
	127	if (PROFILE_INSN_P (cpu)) \
	128	++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
	129	} while (0)
	130
	131	/* This is invoked by the execute section of mloop{,x}.in. */
	132	#define PROFILE_COUNT_SHORTINSNS(cpu) \
	133	do { \
	134	if (PROFILE_INSN_P (cpu)) \
	135	++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
	136	} while (0)
	137
	138	/* This is invoked by the execute section of mloop{,x}.in. */
	139	#define PROFILE_COUNT_LONGINSNS(cpu) \
	140	do { \
	141	if (PROFILE_INSN_P (cpu)) \
	142	++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
	143	} while (0)
	144	\f
	145	#define GETTWI GETTSI
	146	#define SETTWI SETTSI
	147	\f
148	/* Additional execution support. */
149
150	\f
151	/* Hardware/device support.
152	??? Will eventually want to move device stuff to config files. */
153
154	/* Exception, Interrupt, and Trap addresses */
155	#define EIT_SYSBREAK_ADDR 0x10
156	#define EIT_RSVD_INSN_ADDR 0x20
157	#define EIT_ADDR_EXCP_ADDR 0x30
158	#define EIT_TRAP_BASE_ADDR 0x40
159	#define EIT_EXTERN_ADDR 0x80
160	#define EIT_RESET_ADDR 0x7ffffff0
161	#define EIT_WAKEUP_ADDR 0x7ffffff0
162
163	/* Special purpose traps. */
164	#define TRAP_SYSCALL 0
165	#define TRAP_BREAKPOINT 1
166
c906108c SS	167	/* Handle the trap insn. */
c906108c SS	168	USI m32r_trap (SIM_CPU *, PCADDR, int);
f51d9c6a MF	169	\f
	170	struct m32r_sim_cpu {
	171	M32R_MISC_PROFILE m32r_misc_profile;
	172	#define CPU_M32R_MISC_PROFILE(cpu) (& M32R_SIM_CPU (cpu)->m32r_misc_profile)
	173
	174	/* CPU specific parts go here.
	175	Note that in files that don't need to access these pieces WANT_CPU_FOO
	176	won't be defined and thus these parts won't appear. This is ok in the
	177	sense that things work. It is a source of bugs though.
	178	One has to of course be careful to not take the size of this
	179	struct and no structure members accessed in non-cpu specific files can
	180	go after here. Oh for a better language. */
	181	#if defined (WANT_CPU_M32RBF)
	182	M32RBF_CPU_DATA cpu_data;
	183	#endif
	184	#if defined (WANT_CPU_M32RXF)
	185	M32RXF_CPU_DATA cpu_data;
	186	#elif defined (WANT_CPU_M32R2F)
	187	M32R2F_CPU_DATA cpu_data;
	188	#endif
	189	};
	190	#define M32R_SIM_CPU(cpu) ((struct m32r_sim_cpu *) CPU_ARCH_DATA (cpu))
c906108c SS	191
c906108c SS	192	#endif /* M32R_SIM_H */